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authorGeert Uytterhoeven <geert+renesas@linux-m68k.org>2014-01-12 05:27:37 -0500
committerMark Brown <broonie@linaro.org>2014-01-13 07:10:01 -0500
commit6ab4865b7e34e707857107ca76c0b98d87a992dd (patch)
treeadc9e67cb9e5a26a0404a23b606926dd6a94b5a7
parente2e5ed79fed3a9be3846651ca5b463658f8ff6c9 (diff)
spi: rspi: Add more RSPI register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat
-rw-r--r--drivers/spi/spi-rspi.c185
1 files changed, 99 insertions, 86 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 627126ae2571..1f69343689f9 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -37,27 +37,29 @@
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 38#include <linux/spi/rspi.h>
39 39
40#define RSPI_SPCR 0x00 40#define RSPI_SPCR 0x00 /* Control Register */
41#define RSPI_SSLP 0x01 41#define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
42#define RSPI_SPPCR 0x02 42#define RSPI_SPPCR 0x02 /* Pin Control Register */
43#define RSPI_SPSR 0x03 43#define RSPI_SPSR 0x03 /* Status Register */
44#define RSPI_SPDR 0x04 44#define RSPI_SPDR 0x04 /* Data Register */
45#define RSPI_SPSCR 0x08 45#define RSPI_SPSCR 0x08 /* Sequence Control Register */
46#define RSPI_SPSSR 0x09 46#define RSPI_SPSSR 0x09 /* Sequence Status Register */
47#define RSPI_SPBR 0x0a 47#define RSPI_SPBR 0x0a /* Bit Rate Register */
48#define RSPI_SPDCR 0x0b 48#define RSPI_SPDCR 0x0b /* Data Control Register */
49#define RSPI_SPCKD 0x0c 49#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d 50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e 51#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f 52#define RSPI_SPCR2 0x0f /* Control Register 2 */
53#define RSPI_SPCMD0 0x10 53#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 54#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 55#define RSPI_SPCMD2 0x14 /* Command Register 2 */
56#define RSPI_SPCMD3 0x16 56#define RSPI_SPCMD3 0x16 /* Command Register 3 */
57#define RSPI_SPCMD4 0x18 57#define RSPI_SPCMD4 0x18 /* Command Register 4 */
58#define RSPI_SPCMD5 0x1a 58#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c 59#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e 60#define RSPI_SPCMD7 0x1e /* Command Register 7 */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
61 63
62/*qspi only */ 64/*qspi only */
63#define QSPI_SPBFCR 0x18 65#define QSPI_SPBFCR 0x18
@@ -67,87 +69,98 @@
67#define QSPI_SPBMUL2 0x24 69#define QSPI_SPBMUL2 0x24
68#define QSPI_SPBMUL3 0x28 70#define QSPI_SPBMUL3 0x28
69 71
70/* SPCR */ 72/* SPCR - Control Register */
71#define SPCR_SPRIE 0x80 73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
72#define SPCR_SPE 0x40 74#define SPCR_SPE 0x40 /* Function Enable */
73#define SPCR_SPTIE 0x20 75#define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
74#define SPCR_SPEIE 0x10 76#define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
75#define SPCR_MSTR 0x08 77#define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
76#define SPCR_MODFEN 0x04 78#define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
77#define SPCR_TXMD 0x02 79/* RSPI on SH only */
78#define SPCR_SPMS 0x01 80#define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
79 81#define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
80/* SSLP */ 82
81#define SSLP_SSL1P 0x02 83/* SSLP - Slave Select Polarity Register */
82#define SSLP_SSL0P 0x01 84#define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
83 85#define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
84/* SPPCR */ 86
85#define SPPCR_MOIFE 0x20 87/* SPPCR - Pin Control Register */
86#define SPPCR_MOIFV 0x10 88#define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
89#define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
87#define SPPCR_SPOM 0x04 90#define SPPCR_SPOM 0x04
88#define SPPCR_SPLP2 0x02 91#define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
89#define SPPCR_SPLP 0x01 92#define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
90 93
91/* SPSR */ 94/* SPSR - Status Register */
92#define SPSR_SPRF 0x80 95#define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
93#define SPSR_SPTEF 0x20 96#define SPSR_TEND 0x40 /* Transmit End */
94#define SPSR_PERF 0x08 97#define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
95#define SPSR_MODF 0x04 98#define SPSR_PERF 0x08 /* Parity Error Flag */
96#define SPSR_IDLNF 0x02 99#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
97#define SPSR_OVRF 0x01 100#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
98 101#define SPSR_OVRF 0x01 /* Overrun Error Flag */
99/* SPSCR */ 102
100#define SPSCR_SPSLN_MASK 0x07 103/* SPSCR - Sequence Control Register */
101 104#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
102/* SPSSR */ 105
103#define SPSSR_SPECM_MASK 0x70 106/* SPSSR - Sequence Status Register */
104#define SPSSR_SPCP_MASK 0x07 107#define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
105 108#define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
106/* SPDCR */ 109
107#define SPDCR_SPLW 0x20 110/* SPDCR - Data Control Register */
108#define SPDCR_SPRDTD 0x10 111#define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
112#define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
113#define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
114#define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
115#define SPDCR_SPLWORD SPDCR_SPLW1
116#define SPDCR_SPLBYTE SPDCR_SPLW0
117#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
118#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */
109#define SPDCR_SLSEL1 0x08 119#define SPDCR_SLSEL1 0x08
110#define SPDCR_SLSEL0 0x04 120#define SPDCR_SLSEL0 0x04
111#define SPDCR_SLSEL_MASK 0x0c 121#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */
112#define SPDCR_SPFC1 0x02 122#define SPDCR_SPFC1 0x02
113#define SPDCR_SPFC0 0x01 123#define SPDCR_SPFC0 0x01
124#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */
114 125
115/* SPCKD */ 126/* SPCKD - Clock Delay Register */
116#define SPCKD_SCKDL_MASK 0x07 127#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
117 128
118/* SSLND */ 129/* SSLND - Slave Select Negation Delay Register */
119#define SSLND_SLNDL_MASK 0x07 130#define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
120 131
121/* SPND */ 132/* SPND - Next-Access Delay Register */
122#define SPND_SPNDL_MASK 0x07 133#define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
123 134
124/* SPCR2 */ 135/* SPCR2 - Control Register 2 */
125#define SPCR2_PTE 0x08 136#define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
126#define SPCR2_SPIE 0x04 137#define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
127#define SPCR2_SPOE 0x02 138#define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
128#define SPCR2_SPPE 0x01 139#define SPCR2_SPPE 0x01 /* Parity Enable */
129 140
130/* SPCMDn */ 141/* SPCMDn - Command Registers */
131#define SPCMD_SCKDEN 0x8000 142#define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
132#define SPCMD_SLNDEN 0x4000 143#define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
133#define SPCMD_SPNDEN 0x2000 144#define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
134#define SPCMD_LSBF 0x1000 145#define SPCMD_LSBF 0x1000 /* LSB First */
135#define SPCMD_SPB_MASK 0x0f00 146#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
136#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 147#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
137#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 148#define SPCMD_SPB_8BIT 0x0000 /* qspi only */
138#define SPCMD_SPB_16BIT 0x0100 149#define SPCMD_SPB_16BIT 0x0100
139#define SPCMD_SPB_20BIT 0x0000 150#define SPCMD_SPB_20BIT 0x0000
140#define SPCMD_SPB_24BIT 0x0100 151#define SPCMD_SPB_24BIT 0x0100
141#define SPCMD_SPB_32BIT 0x0200 152#define SPCMD_SPB_32BIT 0x0200
142#define SPCMD_SSLKP 0x0080 153#define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
143#define SPCMD_SSLA_MASK 0x0030 154#define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
144#define SPCMD_BRDV_MASK 0x000c 155#define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
145#define SPCMD_CPOL 0x0002 156#define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
146#define SPCMD_CPHA 0x0001 157#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
147 158
148/* SPBFCR */ 159/* SPBFCR - Buffer Control Register */
149#define SPBFCR_TXRST 0x80 /* qspi only */ 160#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */
150#define SPBFCR_RXRST 0x40 /* qspi only */ 161#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */
162#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
163#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
151 164
152#define DUMMY_DATA 0x00 165#define DUMMY_DATA 0x00
153 166
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 12:36:15 -0400