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authorKiran AVND <avnd.kiran@samsung.com>2014-05-19 08:33:05 -0400
committerMauro Carvalho Chehab <m.chehab@samsung.com>2014-05-23 14:30:38 -0400
commit6a9c6f681257985468e4835bf9f911ec56482f02 (patch)
treea4a56ee741e6e4e77715f97e579620e36778af10
parent1c6f33acd31738c82985375e27043b71aa3229fb (diff)
[media] s5p-mfc: Add variants to access mfc registers
This patch is needed in preparation to add MFC V8 where the register offsets are changed w.r.t MFC V6/V7. This patch adds variants of MFC V6 and V7 while accessing MFC registers. Registers are kept in mfc context and are initialized to a particular MFC variant during probe, which is used instead of macros. This avoids duplication of the code for MFC variants V6 & V7, and reduces the if_else checks while accessing registers of different MFC variants. Signed-off-by: Kiran AVND <avnd.kiran@samsung.com> Signed-off-by: Pawel Osciak <posciak@chromium.org> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc.c1
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_common.h1
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_opr.c6
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_opr.h254
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c693
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h7
6 files changed, 707 insertions, 255 deletions
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index 297d6819741e..2ab90dda1629 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -1193,6 +1193,7 @@ static int s5p_mfc_probe(struct platform_device *pdev)
1193 /* Initialize HW ops and commands based on MFC version */ 1193 /* Initialize HW ops and commands based on MFC version */
1194 s5p_mfc_init_hw_ops(dev); 1194 s5p_mfc_init_hw_ops(dev);
1195 s5p_mfc_init_hw_cmds(dev); 1195 s5p_mfc_init_hw_cmds(dev);
1196 s5p_mfc_init_regs(dev);
1196 1197
1197 pr_debug("%s--\n", __func__); 1198 pr_debug("%s--\n", __func__);
1198 return 0; 1199 return 0;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index 5c28cc3e699b..662fcefb64e4 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -330,6 +330,7 @@ struct s5p_mfc_dev {
330 int warn_start; 330 int warn_start;
331 struct s5p_mfc_hw_ops *mfc_ops; 331 struct s5p_mfc_hw_ops *mfc_ops;
332 struct s5p_mfc_hw_cmds *mfc_cmds; 332 struct s5p_mfc_hw_cmds *mfc_cmds;
333 const struct s5p_mfc_regs *mfc_regs;
333}; 334};
334 335
335/** 336/**
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c
index 3c01c339d696..c9a227428e6a 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c
@@ -31,6 +31,12 @@ void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev)
31 dev->mfc_ops = s5p_mfc_ops; 31 dev->mfc_ops = s5p_mfc_ops;
32} 32}
33 33
34void s5p_mfc_init_regs(struct s5p_mfc_dev *dev)
35{
36 if (IS_MFCV6_PLUS(dev))
37 dev->mfc_regs = s5p_mfc_init_regs_v6_plus(dev);
38}
39
34int s5p_mfc_alloc_priv_buf(struct device *dev, 40int s5p_mfc_alloc_priv_buf(struct device *dev,
35 struct s5p_mfc_priv_buf *b) 41 struct s5p_mfc_priv_buf *b)
36{ 42{
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
index 754c540e7a7e..7a7ad32ee608 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
@@ -17,6 +17,259 @@
17 17
18#include "s5p_mfc_common.h" 18#include "s5p_mfc_common.h"
19 19
20struct s5p_mfc_regs {
21
22 /* codec common registers */
23 void *risc_on;
24 void *risc2host_int;
25 void *host2risc_int;
26 void *risc_base_address;
27 void *mfc_reset;
28 void *host2risc_command;
29 void *risc2host_command;
30 void *mfc_bus_reset_ctrl;
31 void *firmware_version;
32 void *instance_id;
33 void *codec_type;
34 void *context_mem_addr;
35 void *context_mem_size;
36 void *pixel_format;
37 void *metadata_enable;
38 void *mfc_version;
39 void *dbg_info_enable;
40 void *dbg_buffer_addr;
41 void *dbg_buffer_size;
42 void *hed_control;
43 void *mfc_timeout_value;
44 void *hed_shared_mem_addr;
45 void *dis_shared_mem_addr;/* only v7 */
46 void *ret_instance_id;
47 void *error_code;
48 void *dbg_buffer_output_size;
49 void *metadata_status;
50 void *metadata_addr_mb_info;
51 void *metadata_size_mb_info;
52 void *dbg_info_stage_counter;
53
54 /* decoder registers */
55 void *d_crc_ctrl;
56 void *d_dec_options;
57 void *d_display_delay;
58 void *d_set_frame_width;
59 void *d_set_frame_height;
60 void *d_sei_enable;
61 void *d_min_num_dpb;
62 void *d_min_first_plane_dpb_size;
63 void *d_min_second_plane_dpb_size;
64 void *d_min_third_plane_dpb_size;/* only v8 */
65 void *d_min_num_mv;
66 void *d_mvc_num_views;
67 void *d_min_num_dis;/* only v7 */
68 void *d_min_first_dis_size;/* only v7 */
69 void *d_min_second_dis_size;/* only v7 */
70 void *d_min_third_dis_size;/* only v7 */
71 void *d_post_filter_luma_dpb0;/* v7 and v8 */
72 void *d_post_filter_luma_dpb1;/* v7 and v8 */
73 void *d_post_filter_luma_dpb2;/* only v7 */
74 void *d_post_filter_chroma_dpb0;/* v7 and v8 */
75 void *d_post_filter_chroma_dpb1;/* v7 and v8 */
76 void *d_post_filter_chroma_dpb2;/* only v7 */
77 void *d_num_dpb;
78 void *d_num_mv;
79 void *d_init_buffer_options;
80 void *d_first_plane_dpb_stride_size;/* only v8 */
81 void *d_second_plane_dpb_stride_size;/* only v8 */
82 void *d_third_plane_dpb_stride_size;/* only v8 */
83 void *d_first_plane_dpb_size;
84 void *d_second_plane_dpb_size;
85 void *d_third_plane_dpb_size;/* only v8 */
86 void *d_mv_buffer_size;
87 void *d_first_plane_dpb;
88 void *d_second_plane_dpb;
89 void *d_third_plane_dpb;
90 void *d_mv_buffer;
91 void *d_scratch_buffer_addr;
92 void *d_scratch_buffer_size;
93 void *d_metadata_buffer_addr;
94 void *d_metadata_buffer_size;
95 void *d_nal_start_options;/* v7 and v8 */
96 void *d_cpb_buffer_addr;
97 void *d_cpb_buffer_size;
98 void *d_available_dpb_flag_upper;
99 void *d_available_dpb_flag_lower;
100 void *d_cpb_buffer_offset;
101 void *d_slice_if_enable;
102 void *d_picture_tag;
103 void *d_stream_data_size;
104 void *d_dynamic_dpb_flag_upper;/* v7 and v8 */
105 void *d_dynamic_dpb_flag_lower;/* v7 and v8 */
106 void *d_display_frame_width;
107 void *d_display_frame_height;
108 void *d_display_status;
109 void *d_display_first_plane_addr;
110 void *d_display_second_plane_addr;
111 void *d_display_third_plane_addr;/* only v8 */
112 void *d_display_frame_type;
113 void *d_display_crop_info1;
114 void *d_display_crop_info2;
115 void *d_display_picture_profile;
116 void *d_display_luma_crc;/* v7 and v8 */
117 void *d_display_chroma0_crc;/* v7 and v8 */
118 void *d_display_chroma1_crc;/* only v8 */
119 void *d_display_luma_crc_top;/* only v6 */
120 void *d_display_chroma_crc_top;/* only v6 */
121 void *d_display_luma_crc_bot;/* only v6 */
122 void *d_display_chroma_crc_bot;/* only v6 */
123 void *d_display_aspect_ratio;
124 void *d_display_extended_ar;
125 void *d_decoded_frame_width;
126 void *d_decoded_frame_height;
127 void *d_decoded_status;
128 void *d_decoded_first_plane_addr;
129 void *d_decoded_second_plane_addr;
130 void *d_decoded_third_plane_addr;/* only v8 */
131 void *d_decoded_frame_type;
132 void *d_decoded_crop_info1;
133 void *d_decoded_crop_info2;
134 void *d_decoded_picture_profile;
135 void *d_decoded_nal_size;
136 void *d_decoded_luma_crc;
137 void *d_decoded_chroma0_crc;
138 void *d_decoded_chroma1_crc;/* only v8 */
139 void *d_ret_picture_tag_top;
140 void *d_ret_picture_tag_bot;
141 void *d_ret_picture_time_top;
142 void *d_ret_picture_time_bot;
143 void *d_chroma_format;
144 void *d_vc1_info;/* v7 and v8 */
145 void *d_mpeg4_info;
146 void *d_h264_info;
147 void *d_metadata_addr_concealed_mb;
148 void *d_metadata_size_concealed_mb;
149 void *d_metadata_addr_vc1_param;
150 void *d_metadata_size_vc1_param;
151 void *d_metadata_addr_sei_nal;
152 void *d_metadata_size_sei_nal;
153 void *d_metadata_addr_vui;
154 void *d_metadata_size_vui;
155 void *d_metadata_addr_mvcvui;/* v7 and v8 */
156 void *d_metadata_size_mvcvui;/* v7 and v8 */
157 void *d_mvc_view_id;
158 void *d_frame_pack_sei_avail;
159 void *d_frame_pack_arrgment_id;
160 void *d_frame_pack_sei_info;
161 void *d_frame_pack_grid_pos;
162 void *d_display_recovery_sei_info;/* v7 and v8 */
163 void *d_decoded_recovery_sei_info;/* v7 and v8 */
164 void *d_display_first_addr;/* only v7 */
165 void *d_display_second_addr;/* only v7 */
166 void *d_display_third_addr;/* only v7 */
167 void *d_decoded_first_addr;/* only v7 */
168 void *d_decoded_second_addr;/* only v7 */
169 void *d_decoded_third_addr;/* only v7 */
170 void *d_used_dpb_flag_upper;/* v7 and v8 */
171 void *d_used_dpb_flag_lower;/* v7 and v8 */
172
173 /* encoder registers */
174 void *e_frame_width;
175 void *e_frame_height;
176 void *e_cropped_frame_width;
177 void *e_cropped_frame_height;
178 void *e_frame_crop_offset;
179 void *e_enc_options;
180 void *e_picture_profile;
181 void *e_vbv_buffer_size;
182 void *e_vbv_init_delay;
183 void *e_fixed_picture_qp;
184 void *e_rc_config;
185 void *e_rc_qp_bound;
186 void *e_rc_qp_bound_pb;/* v7 and v8 */
187 void *e_rc_mode;
188 void *e_mb_rc_config;
189 void *e_padding_ctrl;
190 void *e_air_threshold;
191 void *e_mv_hor_range;
192 void *e_mv_ver_range;
193 void *e_num_dpb;
194 void *e_luma_dpb;
195 void *e_chroma_dpb;
196 void *e_me_buffer;
197 void *e_scratch_buffer_addr;
198 void *e_scratch_buffer_size;
199 void *e_tmv_buffer0;
200 void *e_tmv_buffer1;
201 void *e_ir_buffer_addr;/* v7 and v8 */
202 void *e_source_first_plane_addr;
203 void *e_source_second_plane_addr;
204 void *e_source_third_plane_addr;/* v7 and v8 */
205 void *e_source_first_plane_stride;/* v7 and v8 */
206 void *e_source_second_plane_stride;/* v7 and v8 */
207 void *e_source_third_plane_stride;/* v7 and v8 */
208 void *e_stream_buffer_addr;
209 void *e_stream_buffer_size;
210 void *e_roi_buffer_addr;
211 void *e_param_change;
212 void *e_ir_size;
213 void *e_gop_config;
214 void *e_mslice_mode;
215 void *e_mslice_size_mb;
216 void *e_mslice_size_bits;
217 void *e_frame_insertion;
218 void *e_rc_frame_rate;
219 void *e_rc_bit_rate;
220 void *e_rc_roi_ctrl;
221 void *e_picture_tag;
222 void *e_bit_count_enable;
223 void *e_max_bit_count;
224 void *e_min_bit_count;
225 void *e_metadata_buffer_addr;
226 void *e_metadata_buffer_size;
227 void *e_encoded_source_first_plane_addr;
228 void *e_encoded_source_second_plane_addr;
229 void *e_encoded_source_third_plane_addr;/* v7 and v8 */
230 void *e_stream_size;
231 void *e_slice_type;
232 void *e_picture_count;
233 void *e_ret_picture_tag;
234 void *e_stream_buffer_write_pointer; /* only v6 */
235 void *e_recon_luma_dpb_addr;
236 void *e_recon_chroma_dpb_addr;
237 void *e_metadata_addr_enc_slice;
238 void *e_metadata_size_enc_slice;
239 void *e_mpeg4_options;
240 void *e_mpeg4_hec_period;
241 void *e_aspect_ratio;
242 void *e_extended_sar;
243 void *e_h264_options;
244 void *e_h264_options_2;/* v7 and v8 */
245 void *e_h264_lf_alpha_offset;
246 void *e_h264_lf_beta_offset;
247 void *e_h264_i_period;
248 void *e_h264_fmo_slice_grp_map_type;
249 void *e_h264_fmo_num_slice_grp_minus1;
250 void *e_h264_fmo_slice_grp_change_dir;
251 void *e_h264_fmo_slice_grp_change_rate_minus1;
252 void *e_h264_fmo_run_length_minus1_0;
253 void *e_h264_aso_slice_order_0;
254 void *e_h264_chroma_qp_offset;
255 void *e_h264_num_t_layer;
256 void *e_h264_hierarchical_qp_layer0;
257 void *e_h264_frame_packing_sei_info;
258 void *e_h264_nal_control;/* v7 and v8 */
259 void *e_mvc_frame_qp_view1;
260 void *e_mvc_rc_bit_rate_view1;
261 void *e_mvc_rc_qbound_view1;
262 void *e_mvc_rc_mode_view1;
263 void *e_mvc_inter_view_prediction_on;
264 void *e_vp8_options;/* v7 and v8 */
265 void *e_vp8_filter_options;/* v7 and v8 */
266 void *e_vp8_golden_frame_option;/* v7 and v8 */
267 void *e_vp8_num_t_layer;/* v7 and v8 */
268 void *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */
269 void *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
270 void *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
271};
272
20struct s5p_mfc_hw_ops { 273struct s5p_mfc_hw_ops {
21 int (*alloc_dec_temp_buffers)(struct s5p_mfc_ctx *ctx); 274 int (*alloc_dec_temp_buffers)(struct s5p_mfc_ctx *ctx);
22 void (*release_dec_desc_buffer)(struct s5p_mfc_ctx *ctx); 275 void (*release_dec_desc_buffer)(struct s5p_mfc_ctx *ctx);
@@ -80,6 +333,7 @@ struct s5p_mfc_hw_ops {
80}; 333};
81 334
82void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev); 335void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev);
336void s5p_mfc_init_regs(struct s5p_mfc_dev *dev);
83int s5p_mfc_alloc_priv_buf(struct device *dev, 337int s5p_mfc_alloc_priv_buf(struct device *dev,
84 struct s5p_mfc_priv_buf *b); 338 struct s5p_mfc_priv_buf *b);
85void s5p_mfc_release_priv_buf(struct device *dev, 339void s5p_mfc_release_priv_buf(struct device *dev,
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index 518d9a0aaaf6..37a054a714a8 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -43,10 +43,10 @@
43 } while (0) 43 } while (0)
44#endif /* S5P_MFC_DEBUG_REGWRITE */ 44#endif /* S5P_MFC_DEBUG_REGWRITE */
45 45
46#define READL(offset) readl(dev->regs_base + (offset)) 46#define READL(reg) \
47#define WRITEL(data, offset) writel((data), dev->regs_base + (offset)) 47 (WARN_ON_ONCE(!(reg)) ? 0 : readl(reg))
48#define OFFSETA(x) (((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET) 48#define WRITEL(data, reg) \
49#define OFFSETB(x) (((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET) 49 (WARN_ON_ONCE(!(reg)) ? 0 : writel((data), (reg)))
50 50
51/* Allocate temporary buffers for decoding */ 51/* Allocate temporary buffers for decoding */
52static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx) 52static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
@@ -366,16 +366,17 @@ static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
366 unsigned int strm_size) 366 unsigned int strm_size)
367{ 367{
368 struct s5p_mfc_dev *dev = ctx->dev; 368 struct s5p_mfc_dev *dev = ctx->dev;
369 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
369 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size; 370 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
370 371
371 mfc_debug_enter(); 372 mfc_debug_enter();
372 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n" 373 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
373 "buf_size: 0x%08x (%d)\n", 374 "buf_size: 0x%08x (%d)\n",
374 ctx->inst_no, buf_addr, strm_size, strm_size); 375 ctx->inst_no, buf_addr, strm_size, strm_size);
375 WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6); 376 WRITEL(strm_size, mfc_regs->d_stream_data_size);
376 WRITEL(buf_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6); 377 WRITEL(buf_addr, mfc_regs->d_cpb_buffer_addr);
377 WRITEL(buf_size->cpb, S5P_FIMV_D_CPB_BUFFER_SIZE_V6); 378 WRITEL(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
378 WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6); 379 WRITEL(start_num_byte, mfc_regs->d_cpb_buffer_offset);
379 380
380 mfc_debug_leave(); 381 mfc_debug_leave();
381 return 0; 382 return 0;
@@ -387,6 +388,7 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
387 unsigned int frame_size, i; 388 unsigned int frame_size, i;
388 unsigned int frame_size_ch, frame_size_mv; 389 unsigned int frame_size_ch, frame_size_mv;
389 struct s5p_mfc_dev *dev = ctx->dev; 390 struct s5p_mfc_dev *dev = ctx->dev;
391 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
390 size_t buf_addr1; 392 size_t buf_addr1;
391 int buf_size1; 393 int buf_size1;
392 int align_gap; 394 int align_gap;
@@ -398,19 +400,19 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
398 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count); 400 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
399 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay); 401 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
400 402
401 WRITEL(ctx->total_dpb_count, S5P_FIMV_D_NUM_DPB_V6); 403 WRITEL(ctx->total_dpb_count, mfc_regs->d_num_dpb);
402 WRITEL(ctx->luma_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6); 404 WRITEL(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
403 WRITEL(ctx->chroma_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6); 405 WRITEL(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
404 406
405 WRITEL(buf_addr1, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6); 407 WRITEL(buf_addr1, mfc_regs->d_scratch_buffer_addr);
406 WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6); 408 WRITEL(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
407 buf_addr1 += ctx->scratch_buf_size; 409 buf_addr1 += ctx->scratch_buf_size;
408 buf_size1 -= ctx->scratch_buf_size; 410 buf_size1 -= ctx->scratch_buf_size;
409 411
410 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC || 412 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
411 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){ 413 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
412 WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6); 414 WRITEL(ctx->mv_size, mfc_regs->d_mv_buffer_size);
413 WRITEL(ctx->mv_count, S5P_FIMV_D_NUM_MV_V6); 415 WRITEL(ctx->mv_count, mfc_regs->d_num_mv);
414 } 416 }
415 417
416 frame_size = ctx->luma_size; 418 frame_size = ctx->luma_size;
@@ -424,11 +426,11 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
424 mfc_debug(2, "Luma %d: %x\n", i, 426 mfc_debug(2, "Luma %d: %x\n", i,
425 ctx->dst_bufs[i].cookie.raw.luma); 427 ctx->dst_bufs[i].cookie.raw.luma);
426 WRITEL(ctx->dst_bufs[i].cookie.raw.luma, 428 WRITEL(ctx->dst_bufs[i].cookie.raw.luma,
427 S5P_FIMV_D_LUMA_DPB_V6 + i * 4); 429 mfc_regs->d_first_plane_dpb + i * 4);
428 mfc_debug(2, "\tChroma %d: %x\n", i, 430 mfc_debug(2, "\tChroma %d: %x\n", i,
429 ctx->dst_bufs[i].cookie.raw.chroma); 431 ctx->dst_bufs[i].cookie.raw.chroma);
430 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma, 432 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma,
431 S5P_FIMV_D_CHROMA_DPB_V6 + i * 4); 433 mfc_regs->d_second_plane_dpb + i * 4);
432 } 434 }
433 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 435 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
434 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { 436 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
@@ -441,7 +443,7 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
441 443
442 mfc_debug(2, "\tBuf1: %x, size: %d\n", 444 mfc_debug(2, "\tBuf1: %x, size: %d\n",
443 buf_addr1, buf_size1); 445 buf_addr1, buf_size1);
444 WRITEL(buf_addr1, S5P_FIMV_D_MV_BUFFER_V6 + i * 4); 446 WRITEL(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
445 buf_addr1 += frame_size_mv; 447 buf_addr1 += frame_size_mv;
446 buf_size1 -= frame_size_mv; 448 buf_size1 -= frame_size_mv;
447 } 449 }
@@ -454,7 +456,7 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
454 return -ENOMEM; 456 return -ENOMEM;
455 } 457 }
456 458
457 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 459 WRITEL(ctx->inst_no, mfc_regs->instance_id);
458 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 460 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
459 S5P_FIMV_CH_INIT_BUFS_V6, NULL); 461 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
460 462
@@ -467,9 +469,10 @@ static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
467 unsigned long addr, unsigned int size) 469 unsigned long addr, unsigned int size)
468{ 470{
469 struct s5p_mfc_dev *dev = ctx->dev; 471 struct s5p_mfc_dev *dev = ctx->dev;
472 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
470 473
471 WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6); /* 16B align */ 474 WRITEL(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
472 WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6); 475 WRITEL(size, mfc_regs->e_stream_buffer_size);
473 476
474 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n", 477 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n",
475 addr, size); 478 addr, size);
@@ -481,14 +484,10 @@ static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
481 unsigned long y_addr, unsigned long c_addr) 484 unsigned long y_addr, unsigned long c_addr)
482{ 485{
483 struct s5p_mfc_dev *dev = ctx->dev; 486 struct s5p_mfc_dev *dev = ctx->dev;
487 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
484 488
485 if (IS_MFCV7(dev)) { 489 WRITEL(y_addr, mfc_regs->e_source_first_plane_addr);
486 WRITEL(y_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7); 490 WRITEL(c_addr, mfc_regs->e_source_second_plane_addr);
487 WRITEL(c_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
488 } else {
489 WRITEL(y_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
490 WRITEL(c_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
491 }
492 491
493 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr); 492 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
494 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr); 493 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
@@ -498,18 +497,14 @@ static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
498 unsigned long *y_addr, unsigned long *c_addr) 497 unsigned long *y_addr, unsigned long *c_addr)
499{ 498{
500 struct s5p_mfc_dev *dev = ctx->dev; 499 struct s5p_mfc_dev *dev = ctx->dev;
500 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
501 unsigned long enc_recon_y_addr, enc_recon_c_addr; 501 unsigned long enc_recon_y_addr, enc_recon_c_addr;
502 502
503 if (IS_MFCV7(dev)) { 503 *y_addr = READL(mfc_regs->e_encoded_source_first_plane_addr);
504 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7); 504 *c_addr = READL(mfc_regs->e_encoded_source_second_plane_addr);
505 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
506 } else {
507 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
508 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
509 }
510 505
511 enc_recon_y_addr = READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6); 506 enc_recon_y_addr = READL(mfc_regs->e_recon_luma_dpb_addr);
512 enc_recon_c_addr = READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6); 507 enc_recon_c_addr = READL(mfc_regs->e_recon_chroma_dpb_addr);
513 508
514 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr); 509 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr);
515 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr); 510 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
@@ -519,6 +514,7 @@ static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
519static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) 514static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
520{ 515{
521 struct s5p_mfc_dev *dev = ctx->dev; 516 struct s5p_mfc_dev *dev = ctx->dev;
517 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
522 size_t buf_addr1; 518 size_t buf_addr1;
523 int i, buf_size1; 519 int i, buf_size1;
524 520
@@ -530,24 +526,24 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
530 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); 526 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
531 527
532 for (i = 0; i < ctx->pb_count; i++) { 528 for (i = 0; i < ctx->pb_count; i++) {
533 WRITEL(buf_addr1, S5P_FIMV_E_LUMA_DPB_V6 + (4 * i)); 529 WRITEL(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
534 buf_addr1 += ctx->luma_dpb_size; 530 buf_addr1 += ctx->luma_dpb_size;
535 WRITEL(buf_addr1, S5P_FIMV_E_CHROMA_DPB_V6 + (4 * i)); 531 WRITEL(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
536 buf_addr1 += ctx->chroma_dpb_size; 532 buf_addr1 += ctx->chroma_dpb_size;
537 WRITEL(buf_addr1, S5P_FIMV_E_ME_BUFFER_V6 + (4 * i)); 533 WRITEL(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
538 buf_addr1 += ctx->me_buffer_size; 534 buf_addr1 += ctx->me_buffer_size;
539 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + 535 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
540 ctx->me_buffer_size); 536 ctx->me_buffer_size);
541 } 537 }
542 538
543 WRITEL(buf_addr1, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6); 539 WRITEL(buf_addr1, mfc_regs->e_scratch_buffer_addr);
544 WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6); 540 WRITEL(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
545 buf_addr1 += ctx->scratch_buf_size; 541 buf_addr1 += ctx->scratch_buf_size;
546 buf_size1 -= ctx->scratch_buf_size; 542 buf_size1 -= ctx->scratch_buf_size;
547 543
548 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER0_V6); 544 WRITEL(buf_addr1, mfc_regs->e_tmv_buffer0);
549 buf_addr1 += ctx->tmv_buffer_size >> 1; 545 buf_addr1 += ctx->tmv_buffer_size >> 1;
550 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER1_V6); 546 WRITEL(buf_addr1, mfc_regs->e_tmv_buffer1);
551 buf_addr1 += ctx->tmv_buffer_size >> 1; 547 buf_addr1 += ctx->tmv_buffer_size >> 1;
552 buf_size1 -= ctx->tmv_buffer_size; 548 buf_size1 -= ctx->tmv_buffer_size;
553 549
@@ -558,7 +554,7 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
558 return -ENOMEM; 554 return -ENOMEM;
559 } 555 }
560 556
561 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 557 WRITEL(ctx->inst_no, mfc_regs->instance_id);
562 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 558 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
563 S5P_FIMV_CH_INIT_BUFS_V6, NULL); 559 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
564 560
@@ -570,18 +566,19 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
570static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx) 566static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
571{ 567{
572 struct s5p_mfc_dev *dev = ctx->dev; 568 struct s5p_mfc_dev *dev = ctx->dev;
569 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
573 570
574 /* multi-slice control */ 571 /* multi-slice control */
575 /* multi-slice MB number or bit size */ 572 /* multi-slice MB number or bit size */
576 WRITEL(ctx->slice_mode, S5P_FIMV_E_MSLICE_MODE_V6); 573 WRITEL(ctx->slice_mode, mfc_regs->e_mslice_mode);
577 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 574 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
578 WRITEL(ctx->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6); 575 WRITEL(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
579 } else if (ctx->slice_mode == 576 } else if (ctx->slice_mode ==
580 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 577 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
581 WRITEL(ctx->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6); 578 WRITEL(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
582 } else { 579 } else {
583 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB_V6); 580 WRITEL(0x0, mfc_regs->e_mslice_size_mb);
584 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS_V6); 581 WRITEL(0x0, mfc_regs->e_mslice_size_bits);
585 } 582 }
586 583
587 return 0; 584 return 0;
@@ -590,27 +587,28 @@ static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
590static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) 587static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
591{ 588{
592 struct s5p_mfc_dev *dev = ctx->dev; 589 struct s5p_mfc_dev *dev = ctx->dev;
590 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
593 struct s5p_mfc_enc_params *p = &ctx->enc_params; 591 struct s5p_mfc_enc_params *p = &ctx->enc_params;
594 unsigned int reg = 0; 592 unsigned int reg = 0;
595 593
596 mfc_debug_enter(); 594 mfc_debug_enter();
597 595
598 /* width */ 596 /* width */
599 WRITEL(ctx->img_width, S5P_FIMV_E_FRAME_WIDTH_V6); /* 16 align */ 597 WRITEL(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
600 /* height */ 598 /* height */
601 WRITEL(ctx->img_height, S5P_FIMV_E_FRAME_HEIGHT_V6); /* 16 align */ 599 WRITEL(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
602 600
603 /* cropped width */ 601 /* cropped width */
604 WRITEL(ctx->img_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6); 602 WRITEL(ctx->img_width, mfc_regs->e_cropped_frame_width);
605 /* cropped height */ 603 /* cropped height */
606 WRITEL(ctx->img_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6); 604 WRITEL(ctx->img_height, mfc_regs->e_cropped_frame_height);
607 /* cropped offset */ 605 /* cropped offset */
608 WRITEL(0x0, S5P_FIMV_E_FRAME_CROP_OFFSET_V6); 606 WRITEL(0x0, mfc_regs->e_frame_crop_offset);
609 607
610 /* pictype : IDR period */ 608 /* pictype : IDR period */
611 reg = 0; 609 reg = 0;
612 reg |= p->gop_size & 0xFFFF; 610 reg |= p->gop_size & 0xFFFF;
613 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6); 611 WRITEL(reg, mfc_regs->e_gop_config);
614 612
615 /* multi-slice control */ 613 /* multi-slice control */
616 /* multi-slice MB number or bit size */ 614 /* multi-slice MB number or bit size */
@@ -618,65 +616,65 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
618 reg = 0; 616 reg = 0;
619 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 617 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
620 reg |= (0x1 << 3); 618 reg |= (0x1 << 3);
621 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 619 WRITEL(reg, mfc_regs->e_enc_options);
622 ctx->slice_size.mb = p->slice_mb; 620 ctx->slice_size.mb = p->slice_mb;
623 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 621 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
624 reg |= (0x1 << 3); 622 reg |= (0x1 << 3);
625 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 623 WRITEL(reg, mfc_regs->e_enc_options);
626 ctx->slice_size.bits = p->slice_bit; 624 ctx->slice_size.bits = p->slice_bit;
627 } else { 625 } else {
628 reg &= ~(0x1 << 3); 626 reg &= ~(0x1 << 3);
629 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 627 WRITEL(reg, mfc_regs->e_enc_options);
630 } 628 }
631 629
632 s5p_mfc_set_slice_mode(ctx); 630 s5p_mfc_set_slice_mode(ctx);
633 631
634 /* cyclic intra refresh */ 632 /* cyclic intra refresh */
635 WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE_V6); 633 WRITEL(p->intra_refresh_mb, mfc_regs->e_ir_size);
636 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); 634 reg = READL(mfc_regs->e_enc_options);
637 if (p->intra_refresh_mb == 0) 635 if (p->intra_refresh_mb == 0)
638 reg &= ~(0x1 << 4); 636 reg &= ~(0x1 << 4);
639 else 637 else
640 reg |= (0x1 << 4); 638 reg |= (0x1 << 4);
641 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 639 WRITEL(reg, mfc_regs->e_enc_options);
642 640
643 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */ 641 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
644 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); 642 reg = READL(mfc_regs->e_enc_options);
645 reg &= ~(0x1 << 9); 643 reg &= ~(0x1 << 9);
646 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 644 WRITEL(reg, mfc_regs->e_enc_options);
647 645
648 /* memory structure cur. frame */ 646 /* memory structure cur. frame */
649 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { 647 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
650 /* 0: Linear, 1: 2D tiled*/ 648 /* 0: Linear, 1: 2D tiled*/
651 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); 649 reg = READL(mfc_regs->e_enc_options);
652 reg &= ~(0x1 << 7); 650 reg &= ~(0x1 << 7);
653 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 651 WRITEL(reg, mfc_regs->e_enc_options);
654 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 652 /* 0: NV12(CbCr), 1: NV21(CrCb) */
655 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6); 653 WRITEL(0x0, mfc_regs->pixel_format);
656 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) { 654 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
657 /* 0: Linear, 1: 2D tiled*/ 655 /* 0: Linear, 1: 2D tiled*/
658 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); 656 reg = READL(mfc_regs->e_enc_options);
659 reg &= ~(0x1 << 7); 657 reg &= ~(0x1 << 7);
660 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 658 WRITEL(reg, mfc_regs->e_enc_options);
661 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 659 /* 0: NV12(CbCr), 1: NV21(CrCb) */
662 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6); 660 WRITEL(0x1, mfc_regs->pixel_format);
663 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) { 661 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
664 /* 0: Linear, 1: 2D tiled*/ 662 /* 0: Linear, 1: 2D tiled*/
665 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); 663 reg = READL(mfc_regs->e_enc_options);
666 reg |= (0x1 << 7); 664 reg |= (0x1 << 7);
667 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 665 WRITEL(reg, mfc_regs->e_enc_options);
668 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 666 /* 0: NV12(CbCr), 1: NV21(CrCb) */
669 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6); 667 WRITEL(0x0, mfc_regs->pixel_format);
670 } 668 }
671 669
672 /* memory structure recon. frame */ 670 /* memory structure recon. frame */
673 /* 0: Linear, 1: 2D tiled */ 671 /* 0: Linear, 1: 2D tiled */
674 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); 672 reg = READL(mfc_regs->e_enc_options);
675 reg |= (0x1 << 8); 673 reg |= (0x1 << 8);
676 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 674 WRITEL(reg, mfc_regs->e_enc_options);
677 675
678 /* padding control & value */ 676 /* padding control & value */
679 WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL_V6); 677 WRITEL(0x0, mfc_regs->e_padding_ctrl);
680 if (p->pad) { 678 if (p->pad) {
681 reg = 0; 679 reg = 0;
682 /** enable */ 680 /** enable */
@@ -687,64 +685,64 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
687 reg |= ((p->pad_cb & 0xFF) << 8); 685 reg |= ((p->pad_cb & 0xFF) << 8);
688 /** y value */ 686 /** y value */
689 reg |= p->pad_luma & 0xFF; 687 reg |= p->pad_luma & 0xFF;
690 WRITEL(reg, S5P_FIMV_E_PADDING_CTRL_V6); 688 WRITEL(reg, mfc_regs->e_padding_ctrl);
691 } 689 }
692 690
693 /* rate control config. */ 691 /* rate control config. */
694 reg = 0; 692 reg = 0;
695 /* frame-level rate control */ 693 /* frame-level rate control */
696 reg |= ((p->rc_frame & 0x1) << 9); 694 reg |= ((p->rc_frame & 0x1) << 9);
697 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 695 WRITEL(reg, mfc_regs->e_rc_config);
698 696
699 /* bit rate */ 697 /* bit rate */
700 if (p->rc_frame) 698 if (p->rc_frame)
701 WRITEL(p->rc_bitrate, 699 WRITEL(p->rc_bitrate,
702 S5P_FIMV_E_RC_BIT_RATE_V6); 700 mfc_regs->e_rc_bit_rate);
703 else 701 else
704 WRITEL(1, S5P_FIMV_E_RC_BIT_RATE_V6); 702 WRITEL(1, mfc_regs->e_rc_bit_rate);
705 703
706 /* reaction coefficient */ 704 /* reaction coefficient */
707 if (p->rc_frame) { 705 if (p->rc_frame) {
708 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */ 706 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
709 WRITEL(1, S5P_FIMV_E_RC_RPARAM_V6); 707 WRITEL(1, mfc_regs->e_rc_mode);
710 else /* loose CBR */ 708 else /* loose CBR */
711 WRITEL(2, S5P_FIMV_E_RC_RPARAM_V6); 709 WRITEL(2, mfc_regs->e_rc_mode);
712 } 710 }
713 711
714 /* seq header ctrl */ 712 /* seq header ctrl */
715 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); 713 reg = READL(mfc_regs->e_enc_options);
716 reg &= ~(0x1 << 2); 714 reg &= ~(0x1 << 2);
717 reg |= ((p->seq_hdr_mode & 0x1) << 2); 715 reg |= ((p->seq_hdr_mode & 0x1) << 2);
718 716
719 /* frame skip mode */ 717 /* frame skip mode */
720 reg &= ~(0x3); 718 reg &= ~(0x3);
721 reg |= (p->frame_skip_mode & 0x3); 719 reg |= (p->frame_skip_mode & 0x3);
722 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); 720 WRITEL(reg, mfc_regs->e_enc_options);
723 721
724 /* 'DROP_CONTROL_ENABLE', disable */ 722 /* 'DROP_CONTROL_ENABLE', disable */
725 reg = READL(S5P_FIMV_E_RC_CONFIG_V6); 723 reg = READL(mfc_regs->e_rc_config);
726 reg &= ~(0x1 << 10); 724 reg &= ~(0x1 << 10);
727 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 725 WRITEL(reg, mfc_regs->e_rc_config);
728 726
729 /* setting for MV range [16, 256] */ 727 /* setting for MV range [16, 256] */
730 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); 728 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
731 WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6); 729 WRITEL(reg, mfc_regs->e_mv_hor_range);
732 730
733 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); 731 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
734 WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6); 732 WRITEL(reg, mfc_regs->e_mv_ver_range);
735 733
736 WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6); 734 WRITEL(0x0, mfc_regs->e_frame_insertion);
737 WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR_V6); 735 WRITEL(0x0, mfc_regs->e_roi_buffer_addr);
738 WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE_V6); 736 WRITEL(0x0, mfc_regs->e_param_change);
739 WRITEL(0x0, S5P_FIMV_E_RC_ROI_CTRL_V6); 737 WRITEL(0x0, mfc_regs->e_rc_roi_ctrl);
740 WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG_V6); 738 WRITEL(0x0, mfc_regs->e_picture_tag);
741 739
742 WRITEL(0x0, S5P_FIMV_E_BIT_COUNT_ENABLE_V6); 740 WRITEL(0x0, mfc_regs->e_bit_count_enable);
743 WRITEL(0x0, S5P_FIMV_E_MAX_BIT_COUNT_V6); 741 WRITEL(0x0, mfc_regs->e_max_bit_count);
744 WRITEL(0x0, S5P_FIMV_E_MIN_BIT_COUNT_V6); 742 WRITEL(0x0, mfc_regs->e_min_bit_count);
745 743
746 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6); 744 WRITEL(0x0, mfc_regs->e_metadata_buffer_addr);
747 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6); 745 WRITEL(0x0, mfc_regs->e_metadata_buffer_size);
748 746
749 mfc_debug_leave(); 747 mfc_debug_leave();
750 748
@@ -754,6 +752,7 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
754static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 752static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
755{ 753{
756 struct s5p_mfc_dev *dev = ctx->dev; 754 struct s5p_mfc_dev *dev = ctx->dev;
755 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
757 struct s5p_mfc_enc_params *p = &ctx->enc_params; 756 struct s5p_mfc_enc_params *p = &ctx->enc_params;
758 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264; 757 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
759 unsigned int reg = 0; 758 unsigned int reg = 0;
@@ -764,10 +763,10 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
764 s5p_mfc_set_enc_params(ctx); 763 s5p_mfc_set_enc_params(ctx);
765 764
766 /* pictype : number of B */ 765 /* pictype : number of B */
767 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6); 766 reg = READL(mfc_regs->e_gop_config);
768 reg &= ~(0x3 << 16); 767 reg &= ~(0x3 << 16);
769 reg |= ((p->num_b_frame & 0x3) << 16); 768 reg |= ((p->num_b_frame & 0x3) << 16);
770 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6); 769 WRITEL(reg, mfc_regs->e_gop_config);
771 770
772 /* profile & level */ 771 /* profile & level */
773 reg = 0; 772 reg = 0;
@@ -775,18 +774,19 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
775 reg |= ((p_h264->level & 0xFF) << 8); 774 reg |= ((p_h264->level & 0xFF) << 8);
776 /** profile - 0 ~ 3 */ 775 /** profile - 0 ~ 3 */
777 reg |= p_h264->profile & 0x3F; 776 reg |= p_h264->profile & 0x3F;
778 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6); 777 WRITEL(reg, mfc_regs->e_picture_profile);
779 778
780 /* rate control config. */ 779 /* rate control config. */
781 reg = READL(S5P_FIMV_E_RC_CONFIG_V6); 780 reg = READL(mfc_regs->e_rc_config);
782 /** macroblock level rate control */ 781 /** macroblock level rate control */
783 reg &= ~(0x1 << 8); 782 reg &= ~(0x1 << 8);
784 reg |= ((p->rc_mb & 0x1) << 8); 783 reg |= ((p->rc_mb & 0x1) << 8);
785 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 784 WRITEL(reg, mfc_regs->e_rc_config);
785
786 /** frame QP */ 786 /** frame QP */
787 reg &= ~(0x3F); 787 reg &= ~(0x3F);
788 reg |= p_h264->rc_frame_qp & 0x3F; 788 reg |= p_h264->rc_frame_qp & 0x3F;
789 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 789 WRITEL(reg, mfc_regs->e_rc_config);
790 790
791 /* max & min value of QP */ 791 /* max & min value of QP */
792 reg = 0; 792 reg = 0;
@@ -794,16 +794,16 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
794 reg |= ((p_h264->rc_max_qp & 0x3F) << 8); 794 reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
795 /** min QP */ 795 /** min QP */
796 reg |= p_h264->rc_min_qp & 0x3F; 796 reg |= p_h264->rc_min_qp & 0x3F;
797 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6); 797 WRITEL(reg, mfc_regs->e_rc_qp_bound);
798 798
799 /* other QPs */ 799 /* other QPs */
800 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 800 WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
801 if (!p->rc_frame && !p->rc_mb) { 801 if (!p->rc_frame && !p->rc_mb) {
802 reg = 0; 802 reg = 0;
803 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16); 803 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
804 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8); 804 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
805 reg |= p_h264->rc_frame_qp & 0x3F; 805 reg |= p_h264->rc_frame_qp & 0x3F;
806 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 806 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
807 } 807 }
808 808
809 /* frame rate */ 809 /* frame rate */
@@ -811,38 +811,38 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
811 reg = 0; 811 reg = 0;
812 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 812 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
813 reg |= p->rc_framerate_denom & 0xFFFF; 813 reg |= p->rc_framerate_denom & 0xFFFF;
814 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6); 814 WRITEL(reg, mfc_regs->e_rc_frame_rate);
815 } 815 }
816 816
817 /* vbv buffer size */ 817 /* vbv buffer size */
818 if (p->frame_skip_mode == 818 if (p->frame_skip_mode ==
819 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 819 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
820 WRITEL(p_h264->cpb_size & 0xFFFF, 820 WRITEL(p_h264->cpb_size & 0xFFFF,
821 S5P_FIMV_E_VBV_BUFFER_SIZE_V6); 821 mfc_regs->e_vbv_buffer_size);
822 822
823 if (p->rc_frame) 823 if (p->rc_frame)
824 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); 824 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
825 } 825 }
826 826
827 /* interlace */ 827 /* interlace */
828 reg = 0; 828 reg = 0;
829 reg |= ((p_h264->interlace & 0x1) << 3); 829 reg |= ((p_h264->interlace & 0x1) << 3);
830 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 830 WRITEL(reg, mfc_regs->e_h264_options);
831 831
832 /* height */ 832 /* height */
833 if (p_h264->interlace) { 833 if (p_h264->interlace) {
834 WRITEL(ctx->img_height >> 1, 834 WRITEL(ctx->img_height >> 1,
835 S5P_FIMV_E_FRAME_HEIGHT_V6); /* 32 align */ 835 mfc_regs->e_frame_height); /* 32 align */
836 /* cropped height */ 836 /* cropped height */
837 WRITEL(ctx->img_height >> 1, 837 WRITEL(ctx->img_height >> 1,
838 S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6); 838 mfc_regs->e_cropped_frame_height);
839 } 839 }
840 840
841 /* loop filter ctrl */ 841 /* loop filter ctrl */
842 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 842 reg = READL(mfc_regs->e_h264_options);
843 reg &= ~(0x3 << 1); 843 reg &= ~(0x3 << 1);
844 reg |= ((p_h264->loop_filter_mode & 0x3) << 1); 844 reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
845 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 845 WRITEL(reg, mfc_regs->e_h264_options);
846 846
847 /* loopfilter alpha offset */ 847 /* loopfilter alpha offset */
848 if (p_h264->loop_filter_alpha < 0) { 848 if (p_h264->loop_filter_alpha < 0) {
@@ -852,7 +852,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
852 reg = 0x00; 852 reg = 0x00;
853 reg |= (p_h264->loop_filter_alpha & 0xF); 853 reg |= (p_h264->loop_filter_alpha & 0xF);
854 } 854 }
855 WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6); 855 WRITEL(reg, mfc_regs->e_h264_lf_alpha_offset);
856 856
857 /* loopfilter beta offset */ 857 /* loopfilter beta offset */
858 if (p_h264->loop_filter_beta < 0) { 858 if (p_h264->loop_filter_beta < 0) {
@@ -862,28 +862,28 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
862 reg = 0x00; 862 reg = 0x00;
863 reg |= (p_h264->loop_filter_beta & 0xF); 863 reg |= (p_h264->loop_filter_beta & 0xF);
864 } 864 }
865 WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6); 865 WRITEL(reg, mfc_regs->e_h264_lf_beta_offset);
866 866
867 /* entropy coding mode */ 867 /* entropy coding mode */
868 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 868 reg = READL(mfc_regs->e_h264_options);
869 reg &= ~(0x1); 869 reg &= ~(0x1);
870 reg |= p_h264->entropy_mode & 0x1; 870 reg |= p_h264->entropy_mode & 0x1;
871 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 871 WRITEL(reg, mfc_regs->e_h264_options);
872 872
873 /* number of ref. picture */ 873 /* number of ref. picture */
874 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 874 reg = READL(mfc_regs->e_h264_options);
875 reg &= ~(0x1 << 7); 875 reg &= ~(0x1 << 7);
876 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7); 876 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
877 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 877 WRITEL(reg, mfc_regs->e_h264_options);
878 878
879 /* 8x8 transform enable */ 879 /* 8x8 transform enable */
880 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 880 reg = READL(mfc_regs->e_h264_options);
881 reg &= ~(0x3 << 12); 881 reg &= ~(0x3 << 12);
882 reg |= ((p_h264->_8x8_transform & 0x3) << 12); 882 reg |= ((p_h264->_8x8_transform & 0x3) << 12);
883 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 883 WRITEL(reg, mfc_regs->e_h264_options);
884 884
885 /* macroblock adaptive scaling features */ 885 /* macroblock adaptive scaling features */
886 WRITEL(0x0, S5P_FIMV_E_MB_RC_CONFIG_V6); 886 WRITEL(0x0, mfc_regs->e_mb_rc_config);
887 if (p->rc_mb) { 887 if (p->rc_mb) {
888 reg = 0; 888 reg = 0;
889 /** dark region */ 889 /** dark region */
@@ -894,92 +894,95 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
894 reg |= ((p_h264->rc_mb_static & 0x1) << 1); 894 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
895 /** high activity region */ 895 /** high activity region */
896 reg |= p_h264->rc_mb_activity & 0x1; 896 reg |= p_h264->rc_mb_activity & 0x1;
897 WRITEL(reg, S5P_FIMV_E_MB_RC_CONFIG_V6); 897 WRITEL(reg, mfc_regs->e_mb_rc_config);
898 } 898 }
899 899
900 /* aspect ratio VUI */ 900 /* aspect ratio VUI */
901 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 901 READL(mfc_regs->e_h264_options);
902 reg &= ~(0x1 << 5); 902 reg &= ~(0x1 << 5);
903 reg |= ((p_h264->vui_sar & 0x1) << 5); 903 reg |= ((p_h264->vui_sar & 0x1) << 5);
904 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 904 WRITEL(reg, mfc_regs->e_h264_options);
905 905
906 WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO_V6); 906 WRITEL(0x0, mfc_regs->e_aspect_ratio);
907 WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR_V6); 907 WRITEL(0x0, mfc_regs->e_extended_sar);
908 if (p_h264->vui_sar) { 908 if (p_h264->vui_sar) {
909 /* aspect ration IDC */ 909 /* aspect ration IDC */
910 reg = 0; 910 reg = 0;
911 reg |= p_h264->vui_sar_idc & 0xFF; 911 reg |= p_h264->vui_sar_idc & 0xFF;
912 WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO_V6); 912 WRITEL(reg, mfc_regs->e_aspect_ratio);
913 if (p_h264->vui_sar_idc == 0xFF) { 913 if (p_h264->vui_sar_idc == 0xFF) {
914 /* extended SAR */ 914 /* extended SAR */
915 reg = 0; 915 reg = 0;
916 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16; 916 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
917 reg |= p_h264->vui_ext_sar_height & 0xFFFF; 917 reg |= p_h264->vui_ext_sar_height & 0xFFFF;
918 WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR_V6); 918 WRITEL(reg, mfc_regs->e_extended_sar);
919 } 919 }
920 } 920 }
921 921
922 /* intra picture period for H.264 open GOP */ 922 /* intra picture period for H.264 open GOP */
923 /* control */ 923 /* control */
924 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 924 READL(mfc_regs->e_h264_options);
925 reg &= ~(0x1 << 4); 925 reg &= ~(0x1 << 4);
926 reg |= ((p_h264->open_gop & 0x1) << 4); 926 reg |= ((p_h264->open_gop & 0x1) << 4);
927 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 927 WRITEL(reg, mfc_regs->e_h264_options);
928
928 /* value */ 929 /* value */
929 WRITEL(0x0, S5P_FIMV_E_H264_I_PERIOD_V6); 930 WRITEL(0x0, mfc_regs->e_h264_i_period);
930 if (p_h264->open_gop) { 931 if (p_h264->open_gop) {
931 reg = 0; 932 reg = 0;
932 reg |= p_h264->open_gop_size & 0xFFFF; 933 reg |= p_h264->open_gop_size & 0xFFFF;
933 WRITEL(reg, S5P_FIMV_E_H264_I_PERIOD_V6); 934 WRITEL(reg, mfc_regs->e_h264_i_period);
934 } 935 }
935 936
936 /* 'WEIGHTED_BI_PREDICTION' for B is disable */ 937 /* 'WEIGHTED_BI_PREDICTION' for B is disable */
937 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 938 READL(mfc_regs->e_h264_options);
938 reg &= ~(0x3 << 9); 939 reg &= ~(0x3 << 9);
939 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 940 WRITEL(reg, mfc_regs->e_h264_options);
940 941
941 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */ 942 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
942 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 943 READL(mfc_regs->e_h264_options);
943 reg &= ~(0x1 << 14); 944 reg &= ~(0x1 << 14);
944 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 945 WRITEL(reg, mfc_regs->e_h264_options);
945 946
946 /* ASO */ 947 /* ASO */
947 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 948 READL(mfc_regs->e_h264_options);
948 reg &= ~(0x1 << 6); 949 reg &= ~(0x1 << 6);
949 reg |= ((p_h264->aso & 0x1) << 6); 950 reg |= ((p_h264->aso & 0x1) << 6);
950 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 951 WRITEL(reg, mfc_regs->e_h264_options);
951 952
952 /* hier qp enable */ 953 /* hier qp enable */
953 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 954 READL(mfc_regs->e_h264_options);
954 reg &= ~(0x1 << 8); 955 reg &= ~(0x1 << 8);
955 reg |= ((p_h264->open_gop & 0x1) << 8); 956 reg |= ((p_h264->open_gop & 0x1) << 8);
956 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 957 WRITEL(reg, mfc_regs->e_h264_options);
957 reg = 0; 958 reg = 0;
958 if (p_h264->hier_qp && p_h264->hier_qp_layer) { 959 if (p_h264->hier_qp && p_h264->hier_qp_layer) {
959 reg |= (p_h264->hier_qp_type & 0x1) << 0x3; 960 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
960 reg |= p_h264->hier_qp_layer & 0x7; 961 reg |= p_h264->hier_qp_layer & 0x7;
961 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6); 962 WRITEL(reg, mfc_regs->e_h264_num_t_layer);
962 /* QP value for each layer */ 963 /* QP value for each layer */
963 for (i = 0; i < (p_h264->hier_qp_layer & 0x7); i++) 964 for (i = 0; i < p_h264->hier_qp_layer &&
965 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
964 WRITEL(p_h264->hier_qp_layer_qp[i], 966 WRITEL(p_h264->hier_qp_layer_qp[i],
965 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 + 967 mfc_regs->e_h264_hierarchical_qp_layer0
966 i * 4); 968 + i * 4);
969 }
967 } 970 }
968 /* number of coding layer should be zero when hierarchical is disable */ 971 /* number of coding layer should be zero when hierarchical is disable */
969 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6); 972 WRITEL(reg, mfc_regs->e_h264_num_t_layer);
970 973
971 /* frame packing SEI generation */ 974 /* frame packing SEI generation */
972 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); 975 READL(mfc_regs->e_h264_options);
973 reg &= ~(0x1 << 25); 976 reg &= ~(0x1 << 25);
974 reg |= ((p_h264->sei_frame_packing & 0x1) << 25); 977 reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
975 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); 978 WRITEL(reg, mfc_regs->e_h264_options);
976 if (p_h264->sei_frame_packing) { 979 if (p_h264->sei_frame_packing) {
977 reg = 0; 980 reg = 0;
978 /** current frame0 flag */ 981 /** current frame0 flag */
979 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2); 982 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
980 /** arrangement type */ 983 /** arrangement type */
981 reg |= p_h264->sei_fp_arrangement_type & 0x3; 984 reg |= p_h264->sei_fp_arrangement_type & 0x3;
982 WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6); 985 WRITEL(reg, mfc_regs->e_h264_frame_packing_sei_info);
983 } 986 }
984 987
985 if (p_h264->fmo) { 988 if (p_h264->fmo) {
@@ -989,8 +992,8 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
989 p_h264->fmo_slice_grp = 4; 992 p_h264->fmo_slice_grp = 4;
990 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++) 993 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
991 WRITEL(p_h264->fmo_run_len[i] - 1, 994 WRITEL(p_h264->fmo_run_len[i] - 1,
992 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 + 995 mfc_regs->e_h264_fmo_run_length_minus1_0
993 i * 4); 996 + i * 4);
994 break; 997 break;
995 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES: 998 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
996 if (p_h264->fmo_slice_grp > 4) 999 if (p_h264->fmo_slice_grp > 4)
@@ -1001,10 +1004,10 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1001 if (p_h264->fmo_slice_grp > 2) 1004 if (p_h264->fmo_slice_grp > 2)
1002 p_h264->fmo_slice_grp = 2; 1005 p_h264->fmo_slice_grp = 2;
1003 WRITEL(p_h264->fmo_chg_dir & 0x1, 1006 WRITEL(p_h264->fmo_chg_dir & 0x1,
1004 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6); 1007 mfc_regs->e_h264_fmo_slice_grp_change_dir);
1005 /* the valid range is 0 ~ number of macroblocks -1 */ 1008 /* the valid range is 0 ~ number of macroblocks -1 */
1006 WRITEL(p_h264->fmo_chg_rate, 1009 WRITEL(p_h264->fmo_chg_rate,
1007 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6); 1010 mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1008 break; 1011 break;
1009 default: 1012 default:
1010 mfc_err("Unsupported map type for FMO: %d\n", 1013 mfc_err("Unsupported map type for FMO: %d\n",
@@ -1015,11 +1018,11 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1015 } 1018 }
1016 1019
1017 WRITEL(p_h264->fmo_map_type, 1020 WRITEL(p_h264->fmo_map_type,
1018 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6); 1021 mfc_regs->e_h264_fmo_slice_grp_map_type);
1019 WRITEL(p_h264->fmo_slice_grp - 1, 1022 WRITEL(p_h264->fmo_slice_grp - 1,
1020 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6); 1023 mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1021 } else { 1024 } else {
1022 WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6); 1025 WRITEL(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1023 } 1026 }
1024 1027
1025 mfc_debug_leave(); 1028 mfc_debug_leave();
@@ -1030,6 +1033,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1030static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) 1033static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1031{ 1034{
1032 struct s5p_mfc_dev *dev = ctx->dev; 1035 struct s5p_mfc_dev *dev = ctx->dev;
1036 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1033 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1037 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1034 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; 1038 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1035 unsigned int reg = 0; 1039 unsigned int reg = 0;
@@ -1039,10 +1043,10 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1039 s5p_mfc_set_enc_params(ctx); 1043 s5p_mfc_set_enc_params(ctx);
1040 1044
1041 /* pictype : number of B */ 1045 /* pictype : number of B */
1042 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6); 1046 reg = READL(mfc_regs->e_gop_config);
1043 reg &= ~(0x3 << 16); 1047 reg &= ~(0x3 << 16);
1044 reg |= ((p->num_b_frame & 0x3) << 16); 1048 reg |= ((p->num_b_frame & 0x3) << 16);
1045 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6); 1049 WRITEL(reg, mfc_regs->e_gop_config);
1046 1050
1047 /* profile & level */ 1051 /* profile & level */
1048 reg = 0; 1052 reg = 0;
@@ -1050,18 +1054,19 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1050 reg |= ((p_mpeg4->level & 0xFF) << 8); 1054 reg |= ((p_mpeg4->level & 0xFF) << 8);
1051 /** profile - 0 ~ 1 */ 1055 /** profile - 0 ~ 1 */
1052 reg |= p_mpeg4->profile & 0x3F; 1056 reg |= p_mpeg4->profile & 0x3F;
1053 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6); 1057 WRITEL(reg, mfc_regs->e_picture_profile);
1054 1058
1055 /* rate control config. */ 1059 /* rate control config. */
1056 reg = READL(S5P_FIMV_E_RC_CONFIG_V6); 1060 reg = READL(mfc_regs->e_rc_config);
1057 /** macroblock level rate control */ 1061 /** macroblock level rate control */
1058 reg &= ~(0x1 << 8); 1062 reg &= ~(0x1 << 8);
1059 reg |= ((p->rc_mb & 0x1) << 8); 1063 reg |= ((p->rc_mb & 0x1) << 8);
1060 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 1064 WRITEL(reg, mfc_regs->e_rc_config);
1065
1061 /** frame QP */ 1066 /** frame QP */
1062 reg &= ~(0x3F); 1067 reg &= ~(0x3F);
1063 reg |= p_mpeg4->rc_frame_qp & 0x3F; 1068 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1064 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 1069 WRITEL(reg, mfc_regs->e_rc_config);
1065 1070
1066 /* max & min value of QP */ 1071 /* max & min value of QP */
1067 reg = 0; 1072 reg = 0;
@@ -1069,16 +1074,16 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1069 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8); 1074 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1070 /** min QP */ 1075 /** min QP */
1071 reg |= p_mpeg4->rc_min_qp & 0x3F; 1076 reg |= p_mpeg4->rc_min_qp & 0x3F;
1072 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6); 1077 WRITEL(reg, mfc_regs->e_rc_qp_bound);
1073 1078
1074 /* other QPs */ 1079 /* other QPs */
1075 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 1080 WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1076 if (!p->rc_frame && !p->rc_mb) { 1081 if (!p->rc_frame && !p->rc_mb) {
1077 reg = 0; 1082 reg = 0;
1078 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16); 1083 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1079 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8); 1084 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1080 reg |= p_mpeg4->rc_frame_qp & 0x3F; 1085 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1081 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 1086 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1082 } 1087 }
1083 1088
1084 /* frame rate */ 1089 /* frame rate */
@@ -1086,21 +1091,21 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1086 reg = 0; 1091 reg = 0;
1087 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1092 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1088 reg |= p->rc_framerate_denom & 0xFFFF; 1093 reg |= p->rc_framerate_denom & 0xFFFF;
1089 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6); 1094 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1090 } 1095 }
1091 1096
1092 /* vbv buffer size */ 1097 /* vbv buffer size */
1093 if (p->frame_skip_mode == 1098 if (p->frame_skip_mode ==
1094 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1099 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1095 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6); 1100 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1096 1101
1097 if (p->rc_frame) 1102 if (p->rc_frame)
1098 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); 1103 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1099 } 1104 }
1100 1105
1101 /* Disable HEC */ 1106 /* Disable HEC */
1102 WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS_V6); 1107 WRITEL(0x0, mfc_regs->e_mpeg4_options);
1103 WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6); 1108 WRITEL(0x0, mfc_regs->e_mpeg4_hec_period);
1104 1109
1105 mfc_debug_leave(); 1110 mfc_debug_leave();
1106 1111
@@ -1110,6 +1115,7 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1110static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) 1115static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1111{ 1116{
1112 struct s5p_mfc_dev *dev = ctx->dev; 1117 struct s5p_mfc_dev *dev = ctx->dev;
1118 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1113 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1119 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1114 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; 1120 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1115 unsigned int reg = 0; 1121 unsigned int reg = 0;
@@ -1122,18 +1128,19 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1122 reg = 0; 1128 reg = 0;
1123 /** profile */ 1129 /** profile */
1124 reg |= (0x1 << 4); 1130 reg |= (0x1 << 4);
1125 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6); 1131 WRITEL(reg, mfc_regs->e_picture_profile);
1126 1132
1127 /* rate control config. */ 1133 /* rate control config. */
1128 reg = READL(S5P_FIMV_E_RC_CONFIG_V6); 1134 reg = READL(mfc_regs->e_rc_config);
1129 /** macroblock level rate control */ 1135 /** macroblock level rate control */
1130 reg &= ~(0x1 << 8); 1136 reg &= ~(0x1 << 8);
1131 reg |= ((p->rc_mb & 0x1) << 8); 1137 reg |= ((p->rc_mb & 0x1) << 8);
1132 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 1138 WRITEL(reg, mfc_regs->e_rc_config);
1139
1133 /** frame QP */ 1140 /** frame QP */
1134 reg &= ~(0x3F); 1141 reg &= ~(0x3F);
1135 reg |= p_h263->rc_frame_qp & 0x3F; 1142 reg |= p_h263->rc_frame_qp & 0x3F;
1136 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 1143 WRITEL(reg, mfc_regs->e_rc_config);
1137 1144
1138 /* max & min value of QP */ 1145 /* max & min value of QP */
1139 reg = 0; 1146 reg = 0;
@@ -1141,16 +1148,16 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1141 reg |= ((p_h263->rc_max_qp & 0x3F) << 8); 1148 reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1142 /** min QP */ 1149 /** min QP */
1143 reg |= p_h263->rc_min_qp & 0x3F; 1150 reg |= p_h263->rc_min_qp & 0x3F;
1144 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6); 1151 WRITEL(reg, mfc_regs->e_rc_qp_bound);
1145 1152
1146 /* other QPs */ 1153 /* other QPs */
1147 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 1154 WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1148 if (!p->rc_frame && !p->rc_mb) { 1155 if (!p->rc_frame && !p->rc_mb) {
1149 reg = 0; 1156 reg = 0;
1150 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16); 1157 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1151 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8); 1158 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1152 reg |= p_h263->rc_frame_qp & 0x3F; 1159 reg |= p_h263->rc_frame_qp & 0x3F;
1153 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 1160 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1154 } 1161 }
1155 1162
1156 /* frame rate */ 1163 /* frame rate */
@@ -1158,16 +1165,16 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1158 reg = 0; 1165 reg = 0;
1159 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1166 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1160 reg |= p->rc_framerate_denom & 0xFFFF; 1167 reg |= p->rc_framerate_denom & 0xFFFF;
1161 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6); 1168 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1162 } 1169 }
1163 1170
1164 /* vbv buffer size */ 1171 /* vbv buffer size */
1165 if (p->frame_skip_mode == 1172 if (p->frame_skip_mode ==
1166 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1173 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1167 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6); 1174 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1168 1175
1169 if (p->rc_frame) 1176 if (p->rc_frame)
1170 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); 1177 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1171 } 1178 }
1172 1179
1173 mfc_debug_leave(); 1180 mfc_debug_leave();
@@ -1178,6 +1185,7 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1178static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx) 1185static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1179{ 1186{
1180 struct s5p_mfc_dev *dev = ctx->dev; 1187 struct s5p_mfc_dev *dev = ctx->dev;
1188 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1181 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1189 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1182 struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8; 1190 struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1183 unsigned int reg = 0; 1191 unsigned int reg = 0;
@@ -1188,57 +1196,57 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1188 s5p_mfc_set_enc_params(ctx); 1196 s5p_mfc_set_enc_params(ctx);
1189 1197
1190 /* pictype : number of B */ 1198 /* pictype : number of B */
1191 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6); 1199 reg = READL(mfc_regs->e_gop_config);
1192 reg &= ~(0x3 << 16); 1200 reg &= ~(0x3 << 16);
1193 reg |= ((p->num_b_frame & 0x3) << 16); 1201 reg |= ((p->num_b_frame & 0x3) << 16);
1194 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6); 1202 WRITEL(reg, mfc_regs->e_gop_config);
1195 1203
1196 /* profile - 0 ~ 3 */ 1204 /* profile - 0 ~ 3 */
1197 reg = p_vp8->profile & 0x3; 1205 reg = p_vp8->profile & 0x3;
1198 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6); 1206 WRITEL(reg, mfc_regs->e_picture_profile);
1199 1207
1200 /* rate control config. */ 1208 /* rate control config. */
1201 reg = READL(S5P_FIMV_E_RC_CONFIG_V6); 1209 reg = READL(mfc_regs->e_rc_config);
1202 /** macroblock level rate control */ 1210 /** macroblock level rate control */
1203 reg &= ~(0x1 << 8); 1211 reg &= ~(0x1 << 8);
1204 reg |= ((p->rc_mb & 0x1) << 8); 1212 reg |= ((p->rc_mb & 0x1) << 8);
1205 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 1213 WRITEL(reg, mfc_regs->e_rc_config);
1206 1214
1207 /* frame rate */ 1215 /* frame rate */
1208 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { 1216 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1209 reg = 0; 1217 reg = 0;
1210 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1218 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1211 reg |= p->rc_framerate_denom & 0xFFFF; 1219 reg |= p->rc_framerate_denom & 0xFFFF;
1212 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6); 1220 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1213 } 1221 }
1214 1222
1215 /* frame QP */ 1223 /* frame QP */
1216 reg &= ~(0x7F); 1224 reg &= ~(0x7F);
1217 reg |= p_vp8->rc_frame_qp & 0x7F; 1225 reg |= p_vp8->rc_frame_qp & 0x7F;
1218 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); 1226 WRITEL(reg, mfc_regs->e_rc_config);
1219 1227
1220 /* other QPs */ 1228 /* other QPs */
1221 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 1229 WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1222 if (!p->rc_frame && !p->rc_mb) { 1230 if (!p->rc_frame && !p->rc_mb) {
1223 reg = 0; 1231 reg = 0;
1224 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8); 1232 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1225 reg |= p_vp8->rc_frame_qp & 0x7F; 1233 reg |= p_vp8->rc_frame_qp & 0x7F;
1226 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 1234 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1227 } 1235 }
1228 1236
1229 /* max QP */ 1237 /* max QP */
1230 reg = ((p_vp8->rc_max_qp & 0x7F) << 8); 1238 reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1231 /* min QP */ 1239 /* min QP */
1232 reg |= p_vp8->rc_min_qp & 0x7F; 1240 reg |= p_vp8->rc_min_qp & 0x7F;
1233 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6); 1241 WRITEL(reg, mfc_regs->e_rc_qp_bound);
1234 1242
1235 /* vbv buffer size */ 1243 /* vbv buffer size */
1236 if (p->frame_skip_mode == 1244 if (p->frame_skip_mode ==
1237 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1245 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1238 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6); 1246 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1239 1247
1240 if (p->rc_frame) 1248 if (p->rc_frame)
1241 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); 1249 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1242 } 1250 }
1243 1251
1244 /* VP8 specific params */ 1252 /* VP8 specific params */
@@ -1260,7 +1268,7 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1260 } 1268 }
1261 reg |= (val & 0xF) << 3; 1269 reg |= (val & 0xF) << 3;
1262 reg |= (p_vp8->num_ref & 0x2); 1270 reg |= (p_vp8->num_ref & 0x2);
1263 WRITEL(reg, S5P_FIMV_E_VP8_OPTIONS_V7); 1271 WRITEL(reg, mfc_regs->e_vp8_options);
1264 1272
1265 mfc_debug_leave(); 1273 mfc_debug_leave();
1266 1274
@@ -1271,6 +1279,7 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1271static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) 1279static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1272{ 1280{
1273 struct s5p_mfc_dev *dev = ctx->dev; 1281 struct s5p_mfc_dev *dev = ctx->dev;
1282 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1274 unsigned int reg = 0; 1283 unsigned int reg = 0;
1275 int fmo_aso_ctrl = 0; 1284 int fmo_aso_ctrl = 0;
1276 1285
@@ -1278,9 +1287,9 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1278 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, 1287 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1279 S5P_FIMV_CH_SEQ_HEADER_V6); 1288 S5P_FIMV_CH_SEQ_HEADER_V6);
1280 mfc_debug(2, "BUFs: %08x %08x %08x\n", 1289 mfc_debug(2, "BUFs: %08x %08x %08x\n",
1281 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6), 1290 READL(mfc_regs->d_cpb_buffer_addr),
1282 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6), 1291 READL(mfc_regs->d_cpb_buffer_addr),
1283 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6)); 1292 READL(mfc_regs->d_cpb_buffer_addr));
1284 1293
1285 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ 1294 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1286 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); 1295 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
@@ -1291,11 +1300,11 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1291 * set to negative value. */ 1300 * set to negative value. */
1292 if (ctx->display_delay >= 0) { 1301 if (ctx->display_delay >= 0) {
1293 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); 1302 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1294 WRITEL(ctx->display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6); 1303 WRITEL(ctx->display_delay, mfc_regs->d_display_delay);
1295 } 1304 }
1296 1305
1297 if (IS_MFCV7(dev)) { 1306 if (IS_MFCV7(dev)) {
1298 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6); 1307 WRITEL(reg, mfc_regs->d_dec_options);
1299 reg = 0; 1308 reg = 0;
1300 } 1309 }
1301 1310
@@ -1310,21 +1319,21 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1310 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6); 1319 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1311 1320
1312 if (IS_MFCV7(dev)) 1321 if (IS_MFCV7(dev))
1313 WRITEL(reg, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6); 1322 WRITEL(reg, mfc_regs->d_init_buffer_options);
1314 else 1323 else
1315 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6); 1324 WRITEL(reg, mfc_regs->d_dec_options);
1316 1325
1317 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 1326 /* 0: NV12(CbCr), 1: NV21(CrCb) */
1318 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M) 1327 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1319 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6); 1328 WRITEL(0x1, mfc_regs->pixel_format);
1320 else 1329 else
1321 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6); 1330 WRITEL(0x0, mfc_regs->pixel_format);
1322 1331
1323 1332
1324 /* sei parse */ 1333 /* sei parse */
1325 WRITEL(ctx->sei_fp_parse & 0x1, S5P_FIMV_D_SEI_ENABLE_V6); 1334 WRITEL(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1326 1335
1327 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 1336 WRITEL(ctx->inst_no, mfc_regs->instance_id);
1328 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1337 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1329 S5P_FIMV_CH_SEQ_HEADER_V6, NULL); 1338 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1330 1339
@@ -1335,11 +1344,12 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1335static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) 1344static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1336{ 1345{
1337 struct s5p_mfc_dev *dev = ctx->dev; 1346 struct s5p_mfc_dev *dev = ctx->dev;
1347 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1338 1348
1339 if (flush) { 1349 if (flush) {
1340 dev->curr_ctx = ctx->num; 1350 dev->curr_ctx = ctx->num;
1341 s5p_mfc_clean_ctx_int_flags(ctx); 1351 s5p_mfc_clean_ctx_int_flags(ctx);
1342 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 1352 WRITEL(ctx->inst_no, mfc_regs->instance_id);
1343 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1353 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1344 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL); 1354 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1345 } 1355 }
@@ -1350,11 +1360,12 @@ static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1350 enum s5p_mfc_decode_arg last_frame) 1360 enum s5p_mfc_decode_arg last_frame)
1351{ 1361{
1352 struct s5p_mfc_dev *dev = ctx->dev; 1362 struct s5p_mfc_dev *dev = ctx->dev;
1363 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1353 1364
1354 WRITEL(ctx->dec_dst_flag, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6); 1365 WRITEL(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1355 WRITEL(ctx->slice_interface & 0x1, S5P_FIMV_D_SLICE_IF_ENABLE_V6); 1366 WRITEL(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1356 1367
1357 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 1368 WRITEL(ctx->inst_no, mfc_regs->instance_id);
1358 /* Issue different commands to instance basing on whether it 1369 /* Issue different commands to instance basing on whether it
1359 * is the last frame or not. */ 1370 * is the last frame or not. */
1360 switch (last_frame) { 1371 switch (last_frame) {
@@ -1378,6 +1389,7 @@ static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1378static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx) 1389static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1379{ 1390{
1380 struct s5p_mfc_dev *dev = ctx->dev; 1391 struct s5p_mfc_dev *dev = ctx->dev;
1392 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1381 1393
1382 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) 1394 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1383 s5p_mfc_set_enc_params_h264(ctx); 1395 s5p_mfc_set_enc_params_h264(ctx);
@@ -1393,13 +1405,13 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1393 return -EINVAL; 1405 return -EINVAL;
1394 } 1406 }
1395 1407
1396 /* Set stride lengths */ 1408 /* Set stride lengths for v7 & above */
1397 if (IS_MFCV7(dev)) { 1409 if (IS_MFCV7(dev)) {
1398 WRITEL(ctx->img_width, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7); 1410 WRITEL(ctx->img_width, mfc_regs->e_source_first_plane_stride);
1399 WRITEL(ctx->img_width, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7); 1411 WRITEL(ctx->img_width, mfc_regs->e_source_second_plane_stride);
1400 } 1412 }
1401 1413
1402 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 1414 WRITEL(ctx->inst_no, mfc_regs->instance_id);
1403 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1415 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1404 S5P_FIMV_CH_SEQ_HEADER_V6, NULL); 1416 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1405 1417
@@ -1409,14 +1421,16 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1409static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx) 1421static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1410{ 1422{
1411 struct s5p_mfc_dev *dev = ctx->dev; 1423 struct s5p_mfc_dev *dev = ctx->dev;
1424 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1412 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1425 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1413 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264; 1426 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1414 int i; 1427 int i;
1415 1428
1416 if (p_h264->aso) { 1429 if (p_h264->aso) {
1417 for (i = 0; i < 8; i++) 1430 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1418 WRITEL(p_h264->aso_slice_order[i], 1431 WRITEL(p_h264->aso_slice_order[i],
1419 S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 + i * 4); 1432 mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1433 }
1420 } 1434 }
1421 return 0; 1435 return 0;
1422} 1436}
@@ -1425,6 +1439,7 @@ static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1425static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx) 1439static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1426{ 1440{
1427 struct s5p_mfc_dev *dev = ctx->dev; 1441 struct s5p_mfc_dev *dev = ctx->dev;
1442 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1428 1443
1429 mfc_debug(2, "++\n"); 1444 mfc_debug(2, "++\n");
1430 1445
@@ -1435,7 +1450,7 @@ static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1435 1450
1436 s5p_mfc_set_slice_mode(ctx); 1451 s5p_mfc_set_slice_mode(ctx);
1437 1452
1438 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 1453 WRITEL(ctx->inst_no, mfc_regs->instance_id);
1439 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1454 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1440 S5P_FIMV_CH_FRAME_START_V6, NULL); 1455 S5P_FIMV_CH_FRAME_START_V6, NULL);
1441 1456
@@ -1810,28 +1825,26 @@ static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1810 1825
1811static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev) 1826static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1812{ 1827{
1813 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6); 1828 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1814 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_INT_V6); 1829 WRITEL(0, mfc_regs->risc2host_command);
1830 WRITEL(0, mfc_regs->risc2host_int);
1815} 1831}
1816 1832
1817static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data, 1833static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1818 unsigned int ofs) 1834 unsigned int ofs)
1819{ 1835{
1820 struct s5p_mfc_dev *dev = ctx->dev;
1821
1822 s5p_mfc_clock_on(); 1836 s5p_mfc_clock_on();
1823 WRITEL(data, ofs); 1837 WRITEL(data, (void *)ofs);
1824 s5p_mfc_clock_off(); 1838 s5p_mfc_clock_off();
1825} 1839}
1826 1840
1827static unsigned int 1841static unsigned int
1828s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs) 1842s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1829{ 1843{
1830 struct s5p_mfc_dev *dev = ctx->dev;
1831 int ret; 1844 int ret;
1832 1845
1833 s5p_mfc_clock_on(); 1846 s5p_mfc_clock_on();
1834 ret = READL(ofs); 1847 ret = READL((void *)ofs);
1835 s5p_mfc_clock_off(); 1848 s5p_mfc_clock_off();
1836 1849
1837 return ret; 1850 return ret;
@@ -1839,50 +1852,51 @@ s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1839 1852
1840static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev) 1853static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1841{ 1854{
1842 return mfc_read(dev, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6); 1855 return READL(dev->mfc_regs->d_display_first_plane_addr);
1843} 1856}
1844 1857
1845static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev) 1858static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1846{ 1859{
1847 return mfc_read(dev, S5P_FIMV_D_DECODED_LUMA_ADDR_V6); 1860 return READL(dev->mfc_regs->d_decoded_first_plane_addr);
1848} 1861}
1849 1862
1850static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev) 1863static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1851{ 1864{
1852 return mfc_read(dev, S5P_FIMV_D_DISPLAY_STATUS_V6); 1865 return READL(dev->mfc_regs->d_display_status);
1853} 1866}
1854 1867
1855static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev) 1868static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
1856{ 1869{
1857 return mfc_read(dev, S5P_FIMV_D_DECODED_STATUS_V6); 1870 return READL(dev->mfc_regs->d_decoded_status);
1858} 1871}
1859 1872
1860static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev) 1873static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1861{ 1874{
1862 return mfc_read(dev, S5P_FIMV_D_DECODED_FRAME_TYPE_V6) & 1875 return READL(dev->mfc_regs->d_decoded_frame_type) &
1863 S5P_FIMV_DECODE_FRAME_MASK_V6; 1876 S5P_FIMV_DECODE_FRAME_MASK_V6;
1864} 1877}
1865 1878
1866static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx) 1879static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1867{ 1880{
1868 return mfc_read(ctx->dev, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6) & 1881 struct s5p_mfc_dev *dev = ctx->dev;
1882 return READL(dev->mfc_regs->d_display_frame_type) &
1869 S5P_FIMV_DECODE_FRAME_MASK_V6; 1883 S5P_FIMV_DECODE_FRAME_MASK_V6;
1870} 1884}
1871 1885
1872static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev) 1886static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1873{ 1887{
1874 return mfc_read(dev, S5P_FIMV_D_DECODED_NAL_SIZE_V6); 1888 return READL(dev->mfc_regs->d_decoded_nal_size);
1875} 1889}
1876 1890
1877static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev) 1891static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1878{ 1892{
1879 return mfc_read(dev, S5P_FIMV_RISC2HOST_CMD_V6) & 1893 return READL(dev->mfc_regs->risc2host_command) &
1880 S5P_FIMV_RISC2HOST_CMD_MASK; 1894 S5P_FIMV_RISC2HOST_CMD_MASK;
1881} 1895}
1882 1896
1883static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev) 1897static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1884{ 1898{
1885 return mfc_read(dev, S5P_FIMV_ERROR_CODE_V6); 1899 return READL(dev->mfc_regs->error_code);
1886} 1900}
1887 1901
1888static int s5p_mfc_err_dec_v6(unsigned int err) 1902static int s5p_mfc_err_dec_v6(unsigned int err)
@@ -1897,82 +1911,263 @@ static int s5p_mfc_err_dspl_v6(unsigned int err)
1897 1911
1898static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev) 1912static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1899{ 1913{
1900 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6); 1914 return READL(dev->mfc_regs->d_display_frame_width);
1901} 1915}
1902 1916
1903static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev) 1917static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1904{ 1918{
1905 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6); 1919 return READL(dev->mfc_regs->d_display_frame_height);
1906} 1920}
1907 1921
1908static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev) 1922static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1909{ 1923{
1910 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_DPB_V6); 1924 return READL(dev->mfc_regs->d_min_num_dpb);
1911} 1925}
1912 1926
1913static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev) 1927static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1914{ 1928{
1915 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_MV_V6); 1929 return READL(dev->mfc_regs->d_min_num_mv);
1916} 1930}
1917 1931
1918static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev) 1932static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1919{ 1933{
1920 return mfc_read(dev, S5P_FIMV_RET_INSTANCE_ID_V6); 1934 return READL(dev->mfc_regs->ret_instance_id);
1921} 1935}
1922 1936
1923static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev) 1937static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1924{ 1938{
1925 return mfc_read(dev, S5P_FIMV_E_NUM_DPB_V6); 1939 return READL(dev->mfc_regs->e_num_dpb);
1926} 1940}
1927 1941
1928static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev) 1942static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1929{ 1943{
1930 return mfc_read(dev, S5P_FIMV_E_STREAM_SIZE_V6); 1944 return READL(dev->mfc_regs->e_stream_size);
1931} 1945}
1932 1946
1933static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev) 1947static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1934{ 1948{
1935 return mfc_read(dev, S5P_FIMV_E_SLICE_TYPE_V6); 1949 return READL(dev->mfc_regs->e_slice_type);
1936} 1950}
1937 1951
1938static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev) 1952static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
1939{ 1953{
1940 return mfc_read(dev, S5P_FIMV_E_PICTURE_COUNT_V6); 1954 return READL(dev->mfc_regs->e_picture_count);
1941} 1955}
1942 1956
1943static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx) 1957static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
1944{ 1958{
1945 return mfc_read(ctx->dev, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6); 1959 struct s5p_mfc_dev *dev = ctx->dev;
1960 return READL(dev->mfc_regs->d_frame_pack_sei_avail);
1946} 1961}
1947 1962
1948static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev) 1963static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
1949{ 1964{
1950 return mfc_read(dev, S5P_FIMV_D_MVC_NUM_VIEWS_V6); 1965 return READL(dev->mfc_regs->d_mvc_num_views);
1951} 1966}
1952 1967
1953static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev) 1968static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
1954{ 1969{
1955 return mfc_read(dev, S5P_FIMV_D_MVC_VIEW_ID_V6); 1970 return READL(dev->mfc_regs->d_mvc_view_id);
1956} 1971}
1957 1972
1958static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx) 1973static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
1959{ 1974{
1960 return s5p_mfc_read_info_v6(ctx, PIC_TIME_TOP_V6); 1975 return s5p_mfc_read_info_v6(ctx,
1976 (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_top);
1961} 1977}
1962 1978
1963static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx) 1979static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
1964{ 1980{
1965 return s5p_mfc_read_info_v6(ctx, PIC_TIME_BOT_V6); 1981 return s5p_mfc_read_info_v6(ctx,
1982 (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
1966} 1983}
1967 1984
1968static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx) 1985static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
1969{ 1986{
1970 return s5p_mfc_read_info_v6(ctx, CROP_INFO_H_V6); 1987 return s5p_mfc_read_info_v6(ctx,
1988 (unsigned int) ctx->dev->mfc_regs->d_display_crop_info1);
1971} 1989}
1972 1990
1973static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx) 1991static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
1974{ 1992{
1975 return s5p_mfc_read_info_v6(ctx, CROP_INFO_V_V6); 1993 return s5p_mfc_read_info_v6(ctx,
1994 (unsigned int) ctx->dev->mfc_regs->d_display_crop_info2);
1995}
1996
1997static struct s5p_mfc_regs mfc_regs;
1998
1999/* Initialize registers for MFC v6 onwards */
2000const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
2001{
2002 memset(&mfc_regs, 0, sizeof(mfc_regs));
2003
2004#define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))
2005#define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)
2006 /* codec common registers */
2007 R(risc_on, S5P_FIMV_RISC_ON_V6);
2008 R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);
2009 R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);
2010 R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);
2011 R(mfc_reset, S5P_FIMV_MFC_RESET_V6);
2012 R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);
2013 R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);
2014 R(firmware_version, S5P_FIMV_FW_VERSION_V6);
2015 R(instance_id, S5P_FIMV_INSTANCE_ID_V6);
2016 R(codec_type, S5P_FIMV_CODEC_TYPE_V6);
2017 R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
2018 R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
2019 R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);
2020 R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);
2021 R(error_code, S5P_FIMV_ERROR_CODE_V6);
2022
2023 /* decoder registers */
2024 R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);
2025 R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);
2026 R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
2027 R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);
2028 R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);
2029 R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);
2030 R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
2031 R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);
2032 R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);
2033 R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);
2034 R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
2035 R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
2036 R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
2037 R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);
2038 R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);
2039 R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);
2040 R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
2041 R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
2042 R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
2043 R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
2044 R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
2045 R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
2046 R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
2047 R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
2048 R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
2049 R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
2050 R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);
2051 R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
2052 R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);
2053 R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);
2054 R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);
2055 R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);
2056 R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);
2057 R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);
2058 R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);
2059 R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
2060 R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);
2061 R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);
2062 R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
2063 R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);
2064 R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);
2065 R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);
2066 R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);
2067 R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
2068
2069 /* encoder registers */
2070 R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);
2071 R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);
2072 R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
2073 R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
2074 R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
2075 R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);
2076 R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);
2077 R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
2078 R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
2079 R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
2080 R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);
2081 R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);
2082 R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);
2083 R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);
2084 R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);
2085 R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);
2086 R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);
2087 R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);
2088 R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);
2089 R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);
2090 R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);
2091 R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
2092 R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
2093 R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);
2094 R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);
2095 R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
2096 R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
2097 R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);
2098 R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
2099 R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
2100 R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);
2101 R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);
2102 R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);
2103 R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
2104 R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
2105 R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
2106 R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);
2107 R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);
2108 R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);
2109 R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);
2110 R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);
2111 R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
2112 R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);
2113 R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);
2114 R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
2115 R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
2116 R(e_encoded_source_first_plane_addr,
2117 S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
2118 R(e_encoded_source_second_plane_addr,
2119 S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
2120 R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);
2121 R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);
2122 R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);
2123 R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);
2124 R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
2125 R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
2126 R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);
2127 R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
2128 R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);
2129 R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);
2130 R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);
2131 R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
2132 R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
2133 R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);
2134 R(e_h264_fmo_slice_grp_map_type,
2135 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
2136 R(e_h264_fmo_num_slice_grp_minus1,
2137 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
2138 R(e_h264_fmo_slice_grp_change_dir,
2139 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
2140 R(e_h264_fmo_slice_grp_change_rate_minus1,
2141 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
2142 R(e_h264_fmo_run_length_minus1_0,
2143 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);
2144 R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);
2145 R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
2146 R(e_h264_hierarchical_qp_layer0,
2147 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);
2148 R(e_h264_frame_packing_sei_info,
2149 S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
2150
2151 if (!IS_MFCV7(dev))
2152 goto done;
2153
2154 /* Initialize registers used in MFC v7 */
2155 R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
2156 R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
2157 R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);
2158 R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
2159 R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
2160 R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);
2161 R(e_encoded_source_first_plane_addr,
2162 S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
2163 R(e_encoded_source_second_plane_addr,
2164 S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
2165 R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
2166
2167done:
2168 return &mfc_regs;
2169#undef S5P_MFC_REG_ADDR
2170#undef R
1976} 2171}
1977 2172
1978/* Initialize opr function pointers for MFC v6 */ 2173/* Initialize opr function pointers for MFC v6 */
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
index ab164efa127e..80558484bb40 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
@@ -40,11 +40,6 @@
40#define FRAME_DELTA_H264_H263 1 40#define FRAME_DELTA_H264_H263 1
41#define TIGHT_CBR_MAX 10 41#define TIGHT_CBR_MAX 10
42 42
43/* Definitions for shared memory compatibility */
44#define PIC_TIME_TOP_V6 S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6
45#define PIC_TIME_BOT_V6 S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6
46#define CROP_INFO_H_V6 S5P_FIMV_D_DISPLAY_CROP_INFO1_V6
47#define CROP_INFO_V_V6 S5P_FIMV_D_DISPLAY_CROP_INFO2_V6
48
49struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void); 43struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void);
44const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev);
50#endif /* S5P_MFC_OPR_V6_H_ */ 45#endif /* S5P_MFC_OPR_V6_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 17:51:22 -0400