[POWERPC] 85xx: Add v1 device tree source for Wind River SBC8560 board

This adds a v1 device tree source for the Wind River SBC8560 board. The biggest difference between this and the MPC8560ADS reference platform dts is the use of an external 16550 compatible UART instead of the CPM2. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
author: Paul Gortmaker <paul.gortmaker@windriver.com> 2008-01-24 18:41:24 -0500
committer: Kumar Gala <galak@kernel.crashing.org> 2008-01-28 09:30:47 -0500
commit: 6a35b6f09b8ef19ac99342951e49e3b242b5093b (patch)
tree: 310cd9bc6b185c7c54ac8951219656e5b8532dc7
parent: 2c19806122832a5fd83253ba8321308a531051da (diff)
1 files changed, 330 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
new file mode 100644
index 000000000000..0476802fba60
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -0,0 +1,330 @@
+/*
+ * SBC8560 Device Tree Source
+ *
+ * Copyright 2007 Wind River Systems Inc.
+ *
+ * Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/ {
+        model = "SBC8560";
+        compatible = "SBC8560";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8560@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <0x20>;     // 32 bytes
+                        i-cache-line-size = <0x20>;     // 32 bytes
+                        d-cache-size = <0x8000>;        // L1, 32K
+                        i-cache-size = <0x8000>;        // L1, 32K
+                        timebase-frequency = <0>;       // From uboot
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        soc@ff700000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                ranges = <0x0 0xff700000 0x00100000>;
+                reg = <0xff700000 0x00100000>;
+                clock-frequency = <0>;
+                memory-controller@2000 {
+                        compatible = "fsl,8560-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0x12 0x2>;
+                };
+                l2-cache-controller@20000 {
+                        compatible = "fsl,8560-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <0x20>;       // 32 bytes
+                        cache-size = <0x40000>;         // L2, 256K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0x10 0x2>;
+                };
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <0x2b 0x2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <0x2b 0x2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+                mdio@24520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-mdio";
+                        reg = <0x24520 0x20>;
+                        phy0: ethernet-phy@19 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <0x6 0x1>;
+                                reg = <0x19>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy1: ethernet-phy@1a {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <0x7 0x1>;
+                                reg = <0x1a>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy2: ethernet-phy@1b {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <0x8 0x1>;
+                                reg = <0x1b>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy3: ethernet-phy@1c {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <0x8 0x1>;
+                                reg = <0x1c>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+                enet0: ethernet@24000 {
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy0>;
+                };
+                enet1: ethernet@25000 {
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy1>;
+                };
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        device_type = "open-pic";
+                };
+                cpm@919c0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
+                        reg = <0x919c0 0x30>;
+                        ranges;
+                        muram@80000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x0 0x80000 0x10000>;
+                                data@0 {
+                                        compatible = "fsl,cpm-muram-data";
+                                        reg = <0x0 0x4000 0x9000 0x2000>;
+                                };
+                        };
+                        brg@919f0 {
+                                compatible = "fsl,mpc8560-brg",
+                                             "fsl,cpm2-brg",
+                                             "fsl,cpm-brg";
+                                reg = <0x919f0 0x10 0x915f0 0x10>;
+                                clock-frequency = <165000000>;
+                        };
+                        cpmpic: pic@90c00 {
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <2>;
+                                interrupts = <0x2e 0x2>;
+                                interrupt-parent = <&mpic>;
+                                reg = <0x90c00 0x80>;
+                                compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
+                        };
+                        enet2: ethernet@91320 {
+                                device_type = "network";
+                                compatible = "fsl,mpc8560-fcc-enet",
+                                             "fsl,cpm2-fcc-enet";
+                                reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
+                                local-mac-address = [ 00 00 00 00 00 00 ];
+                                fsl,cpm-command = <0x16200300>;
+                                interrupts = <0x21 0x8>;
+                                interrupt-parent = <&cpmpic>;
+                                phy-handle = <&phy2>;
+                        };
+                        enet3: ethernet@91340 {
+                                device_type = "network";
+                                compatible = "fsl,mpc8560-fcc-enet",
+                                             "fsl,cpm2-fcc-enet";
+                                reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
+                                local-mac-address = [ 00 00 00 00 00 00 ];
+                                fsl,cpm-command = <0x1a400300>;
+                                interrupts = <0x22 0x8>;
+                                interrupt-parent = <&cpmpic>;
+                                phy-handle = <&phy3>;
+                        };
+                };
+                global-utilities@e0000 {
+                        compatible = "fsl,mpc8560-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+        pci0: pci@ff708000 {
+                cell-index = <0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+                device_type = "pci";
+                reg = <0xff708000 0x1000>;
+                clock-frequency = <66666666>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x02 */
+                        0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
+                interrupt-parent = <&mpic>;
+                interrupts = <0x18 0x2>;
+                bus-range = <0x0 0x0>;
+                ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
+        };
+        localbus@ff705000 {
+                compatible = "fsl,mpc8560-localbus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0xff705000 0x100>;       // BRx, ORx, etc.
+                ranges = <
+                        0x0 0x0 0xff800000 0x0800000    // 8MB boot flash
+                        0x1 0x0 0xe4000000 0x4000000    // 64MB flash
+                        0x3 0x0 0x20000000 0x4000000    // 64MB SDRAM
+                        0x4 0x0 0x24000000 0x4000000    // 64MB SDRAM
+                        0x5 0x0 0xfc000000 0x0c00000    // EPLD
+                        0x6 0x0 0xe0000000 0x4000000    // 64MB flash
+                        0x7 0x0 0x80000000 0x0200000    // ATM1,2
+                >;
+                epld@5,0 {
+                        compatible = "wrs,epld-localbus";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        reg = <0x5 0x0 0xc00000>;
+                        ranges = <
+                                0x0 0x0 0x5 0x000000 0x1fff     // LED disp.
+                                0x1 0x0 0x5 0x100000 0x1fff     // switches
+                                0x2 0x0 0x5 0x200000 0x1fff     // ID reg.
+                                0x3 0x0 0x5 0x300000 0x1fff     // status reg.
+                                0x4 0x0 0x5 0x400000 0x1fff     // reset reg.
+                                0x5 0x0 0x5 0x500000 0x1fff     // Wind port
+                                0x7 0x0 0x5 0x700000 0x1fff     // UART #1
+                                0x8 0x0 0x5 0x800000 0x1fff     // UART #2
+                                0x9 0x0 0x5 0x900000 0x1fff     // RTC
+                                0xb 0x0 0x5 0xb00000 0x1fff     // EEPROM
+                        >;
+                        bidr@2,0 {
+                                compatible = "wrs,sbc8560-bidr";
+                                reg = <0x2 0x0 0x10>;
+                        };
+                        bcsr@3,0 {
+                                compatible = "wrs,sbc8560-bcsr";
+                                reg = <0x3 0x0 0x10>;
+                        };
+                        brstcr@4,0 {
+                                compatible = "wrs,sbc8560-brstcr";
+                                reg = <0x4 0x0 0x10>;
+                        };
+                        serial0: serial@7,0 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0x7 0x0 0x100>;
+                                clock-frequency = <1843200>;
+                                interrupts = <0x9 0x2>;
+                                interrupt-parent = <&mpic>;
+                        };
+                        serial1: serial@8,0 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0x8 0x0 0x100>;
+                                clock-frequency = <1843200>;
+                                interrupts = <0xa 0x2>;
+                                interrupt-parent = <&mpic>;
+                        };
+                        rtc@9,0 {
+                                compatible = "m48t59";
+                                reg = <0x9 0x0 0x1fff>;
+                        };
+                };
+        };
+};
author	Paul Gortmaker <paul.gortmaker@windriver.com>	2008-01-24 18:41:24 -0500
committer	Kumar Gala <galak@kernel.crashing.org>	2008-01-28 09:30:47 -0500
commit	6a35b6f09b8ef19ac99342951e49e3b242b5093b (patch)
tree	310cd9bc6b185c7c54ac8951219656e5b8532dc7
parent	2c19806122832a5fd83253ba8321308a531051da (diff)

diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts new file mode 100644 index 000000000000..0476802fba60 --- /dev/null +++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -0,0 +1,330 @@
	1	/*
	2	* SBC8560 Device Tree Source
	3	*
	4	* Copyright 2007 Wind River Systems Inc.
	5	*
	6	* Paul Gortmaker (see MAINTAINERS for contact information)
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	/dts-v1/;
	15
	16	/ {
	17	model = "SBC8560";
	18	compatible = "SBC8560";
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21
	22	aliases {
	23	ethernet0 = &enet0;
	24	ethernet1 = &enet1;
	25	ethernet2 = &enet2;
	26	ethernet3 = &enet3;
	27	serial0 = &serial0;
	28	serial1 = &serial1;
	29	pci0 = &pci0;
	30	};
	31
	32	cpus {
	33	#address-cells = <1>;
	34	#size-cells = <0>;
	35
	36	PowerPC,8560@0 {
	37	device_type = "cpu";
	38	reg = <0>;
	39	d-cache-line-size = <0x20>; // 32 bytes
	40	i-cache-line-size = <0x20>; // 32 bytes
	41	d-cache-size = <0x8000>; // L1, 32K
	42	i-cache-size = <0x8000>; // L1, 32K
	43	timebase-frequency = <0>; // From uboot
	44	bus-frequency = <0>;
	45	clock-frequency = <0>;
	46	};
	47	};
	48
	49	memory {
	50	device_type = "memory";
	51	reg = <0x00000000 0x20000000>;
	52	};
	53
	54	soc@ff700000 {
	55	#address-cells = <1>;
	56	#size-cells = <1>;
	57	device_type = "soc";
	58	ranges = <0x0 0xff700000 0x00100000>;
	59	reg = <0xff700000 0x00100000>;
	60	clock-frequency = <0>;
	61
	62	memory-controller@2000 {
	63	compatible = "fsl,8560-memory-controller";
	64	reg = <0x2000 0x1000>;
	65	interrupt-parent = <&mpic>;
	66	interrupts = <0x12 0x2>;
	67	};
	68
	69	l2-cache-controller@20000 {
	70	compatible = "fsl,8560-l2-cache-controller";
	71	reg = <0x20000 0x1000>;
	72	cache-line-size = <0x20>; // 32 bytes
	73	cache-size = <0x40000>; // L2, 256K
	74	interrupt-parent = <&mpic>;
	75	interrupts = <0x10 0x2>;
	76	};
	77
	78	i2c@3000 {
	79	#address-cells = <1>;
	80	#size-cells = <0>;
	81	cell-index = <0>;
	82	compatible = "fsl-i2c";
	83	reg = <0x3000 0x100>;
	84	interrupts = <0x2b 0x2>;
	85	interrupt-parent = <&mpic>;
	86	dfsrr;
	87	};
	88
	89	i2c@3100 {
	90	#address-cells = <1>;
	91	#size-cells = <0>;
	92	cell-index = <1>;
	93	compatible = "fsl-i2c";
	94	reg = <0x3100 0x100>;
	95	interrupts = <0x2b 0x2>;
	96	interrupt-parent = <&mpic>;
	97	dfsrr;
	98	};
	99
	100	mdio@24520 {
	101	#address-cells = <1>;
	102	#size-cells = <0>;
	103	compatible = "fsl,gianfar-mdio";
	104	reg = <0x24520 0x20>;
	105	phy0: ethernet-phy@19 {
	106	interrupt-parent = <&mpic>;
	107	interrupts = <0x6 0x1>;
	108	reg = <0x19>;
	109	device_type = "ethernet-phy";
	110	};
	111	phy1: ethernet-phy@1a {
	112	interrupt-parent = <&mpic>;
	113	interrupts = <0x7 0x1>;
	114	reg = <0x1a>;
	115	device_type = "ethernet-phy";
	116	};
	117	phy2: ethernet-phy@1b {
	118	interrupt-parent = <&mpic>;
	119	interrupts = <0x8 0x1>;
	120	reg = <0x1b>;
	121	device_type = "ethernet-phy";
	122	};
	123	phy3: ethernet-phy@1c {
	124	interrupt-parent = <&mpic>;
	125	interrupts = <0x8 0x1>;
	126	reg = <0x1c>;
	127	device_type = "ethernet-phy";
	128	};
	129	};
	130
	131	enet0: ethernet@24000 {
	132	cell-index = <0>;
	133	device_type = "network";
	134	model = "TSEC";
	135	compatible = "gianfar";
	136	reg = <0x24000 0x1000>;
	137	local-mac-address = [ 00 00 00 00 00 00 ];
	138	interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
	139	interrupt-parent = <&mpic>;
	140	phy-handle = <&phy0>;
	141	};
	142
	143	enet1: ethernet@25000 {
	144	cell-index = <1>;
	145	device_type = "network";
	146	model = "TSEC";
	147	compatible = "gianfar";
	148	reg = <0x25000 0x1000>;
	149	local-mac-address = [ 00 00 00 00 00 00 ];
	150	interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
	151	interrupt-parent = <&mpic>;
	152	phy-handle = <&phy1>;
	153	};
	154
	155	mpic: pic@40000 {
	156	interrupt-controller;
	157	#address-cells = <0>;
	158	#size-cells = <0>;
	159	#interrupt-cells = <2>;
	160	reg = <0x40000 0x40000>;
	161	device_type = "open-pic";
	162	};
	163
	164	cpm@919c0 {
	165	#address-cells = <1>;
	166	#size-cells = <1>;
	167	compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
	168	reg = <0x919c0 0x30>;
	169	ranges;
	170
	171	muram@80000 {
	172	#address-cells = <1>;
	173	#size-cells = <1>;
	174	ranges = <0x0 0x80000 0x10000>;
	175
	176	data@0 {
	177	compatible = "fsl,cpm-muram-data";
	178	reg = <0x0 0x4000 0x9000 0x2000>;
	179	};
	180	};
	181
	182	brg@919f0 {
	183	compatible = "fsl,mpc8560-brg",
	184	"fsl,cpm2-brg",
	185	"fsl,cpm-brg";
	186	reg = <0x919f0 0x10 0x915f0 0x10>;
	187	clock-frequency = <165000000>;
	188	};
	189
	190	cpmpic: pic@90c00 {
	191	interrupt-controller;
	192	#address-cells = <0>;
	193	#interrupt-cells = <2>;
	194	interrupts = <0x2e 0x2>;
	195	interrupt-parent = <&mpic>;
	196	reg = <0x90c00 0x80>;
	197	compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
	198	};
	199
	200	enet2: ethernet@91320 {
	201	device_type = "network";
	202	compatible = "fsl,mpc8560-fcc-enet",
	203	"fsl,cpm2-fcc-enet";
	204	reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
	205	local-mac-address = [ 00 00 00 00 00 00 ];
	206	fsl,cpm-command = <0x16200300>;
	207	interrupts = <0x21 0x8>;
	208	interrupt-parent = <&cpmpic>;
	209	phy-handle = <&phy2>;
	210	};
	211
	212	enet3: ethernet@91340 {
	213	device_type = "network";
	214	compatible = "fsl,mpc8560-fcc-enet",
	215	"fsl,cpm2-fcc-enet";
	216	reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
	217	local-mac-address = [ 00 00 00 00 00 00 ];
	218	fsl,cpm-command = <0x1a400300>;
	219	interrupts = <0x22 0x8>;
	220	interrupt-parent = <&cpmpic>;
	221	phy-handle = <&phy3>;
	222	};
	223	};
	224
	225	global-utilities@e0000 {
	226	compatible = "fsl,mpc8560-guts";
	227	reg = <0xe0000 0x1000>;
	228	fsl,has-rstcr;
	229	};
	230	};
	231
	232	pci0: pci@ff708000 {
	233	cell-index = <0>;
	234	#interrupt-cells = <1>;
	235	#size-cells = <2>;
	236	#address-cells = <3>;
	237	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	238	device_type = "pci";
	239	reg = <0xff708000 0x1000>;
	240	clock-frequency = <66666666>;
	241	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	242	interrupt-map = <
	243
	244	/* IDSEL 0x02 */
	245	0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
	246	0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
	247	0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
	248	0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
	249
	250	interrupt-parent = <&mpic>;
	251	interrupts = <0x18 0x2>;
	252	bus-range = <0x0 0x0>;
	253	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	254	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	255	};
	256
	257	localbus@ff705000 {
	258	compatible = "fsl,mpc8560-localbus";
	259	#address-cells = <2>;
	260	#size-cells = <1>;
	261	reg = <0xff705000 0x100>; // BRx, ORx, etc.
	262
	263	ranges = <
	264	0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
	265	0x1 0x0 0xe4000000 0x4000000 // 64MB flash
	266	0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
	267	0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
	268	0x5 0x0 0xfc000000 0x0c00000 // EPLD
	269	0x6 0x0 0xe0000000 0x4000000 // 64MB flash
	270	0x7 0x0 0x80000000 0x0200000 // ATM1,2
	271	>;
	272
	273	epld@5,0 {
	274	compatible = "wrs,epld-localbus";
	275	#address-cells = <2>;
	276	#size-cells = <1>;
	277	reg = <0x5 0x0 0xc00000>;
	278	ranges = <
	279	0x0 0x0 0x5 0x000000 0x1fff // LED disp.
	280	0x1 0x0 0x5 0x100000 0x1fff // switches
	281	0x2 0x0 0x5 0x200000 0x1fff // ID reg.
	282	0x3 0x0 0x5 0x300000 0x1fff // status reg.
	283	0x4 0x0 0x5 0x400000 0x1fff // reset reg.
	284	0x5 0x0 0x5 0x500000 0x1fff // Wind port
	285	0x7 0x0 0x5 0x700000 0x1fff // UART #1
	286	0x8 0x0 0x5 0x800000 0x1fff // UART #2
	287	0x9 0x0 0x5 0x900000 0x1fff // RTC
	288	0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
	289	>;
	290
	291	bidr@2,0 {
	292	compatible = "wrs,sbc8560-bidr";
	293	reg = <0x2 0x0 0x10>;
	294	};
	295
	296	bcsr@3,0 {
	297	compatible = "wrs,sbc8560-bcsr";
	298	reg = <0x3 0x0 0x10>;
	299	};
	300
	301	brstcr@4,0 {
	302	compatible = "wrs,sbc8560-brstcr";
	303	reg = <0x4 0x0 0x10>;
	304	};
	305
	306	serial0: serial@7,0 {
	307	device_type = "serial";
	308	compatible = "ns16550";
	309	reg = <0x7 0x0 0x100>;
	310	clock-frequency = <1843200>;
	311	interrupts = <0x9 0x2>;
	312	interrupt-parent = <&mpic>;
	313	};
	314
	315	serial1: serial@8,0 {
	316	device_type = "serial";
	317	compatible = "ns16550";
	318	reg = <0x8 0x0 0x100>;
	319	clock-frequency = <1843200>;
	320	interrupts = <0xa 0x2>;
	321	interrupt-parent = <&mpic>;
	322	};
	323
	324	rtc@9,0 {
	325	compatible = "m48t59";
	326	reg = <0x9 0x0 0x1fff>;
	327	};
	328	};
	329	};
	330	};