aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLaxman Dewangan <ldewangan@nvidia.com>2013-01-11 08:33:03 -0500
committerStephen Warren <swarren@nvidia.com>2013-01-28 13:24:08 -0500
commit699ed4b94c6278ab0f629fde261af78cd1458f73 (patch)
tree7d17a2c8ec60cfba49b4ce8a45a0de24def25097
parentbb2c1de9ffadc0e1cca1925a89cc04204b247f5b (diff)
ARM: tegra: add DT entry for KBC controller
NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi8
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi8
2 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c4c0bb76dd6c..47534d9970bd 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -404,6 +404,14 @@
404 status = "disabled"; 404 status = "disabled";
405 }; 405 };
406 406
407 kbc {
408 compatible = "nvidia,tegra20-kbc";
409 reg = <0x7000e200 0x100>;
410 interrupts = <0 85 0x04>;
411 clocks = <&tegra_car 36>;
412 status = "disabled";
413 };
414
407 pmc { 415 pmc {
408 compatible = "nvidia,tegra20-pmc"; 416 compatible = "nvidia,tegra20-pmc";
409 reg = <0x7000e400 0x400>; 417 reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index a67fc13ec36d..ff4a0ca45983 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -413,6 +413,14 @@
413 status = "disabled"; 413 status = "disabled";
414 }; 414 };
415 415
416 kbc {
417 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
418 reg = <0x7000e200 0x100>;
419 interrupts = <0 85 0x04>;
420 clocks = <&tegra_car 36>;
421 status = "disabled";
422 };
423
416 pmc { 424 pmc {
417 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; 425 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
418 reg = <0x7000e400 0x400>; 426 reg = <0x7000e400 0x400>;