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authorRob Clark <robdclark@gmail.com>2014-11-07 18:10:04 -0500
committerRob Clark <robdclark@gmail.com>2014-11-16 14:27:35 -0500
commit69193e5060dd1c8f7cd614bad05f33f3e042ae6d (patch)
tree94f8c5ab7e2847e8955cbd6323c7365dbf83e918
parenta8cecf33249b80d8a3c2ca5df1c45eb3b5231b28 (diff)
drm/msm: small fence cleanup
Give ourselves a way to wait for certain fence #.. makes it easier to wait on a set of bo's, which we'll need for atomic. Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r--drivers/gpu/drm/msm/msm_drv.c20
-rw-r--r--drivers/gpu/drm/msm/msm_drv.h2
-rw-r--r--drivers/gpu/drm/msm/msm_gem.c25
-rw-r--r--drivers/gpu/drm/msm/msm_gem.h13
4 files changed, 39 insertions, 21 deletions
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 5717d4ec1a2c..1456b1c3e890 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -619,6 +619,26 @@ int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
619 return ret; 619 return ret;
620} 620}
621 621
622int msm_queue_fence_cb(struct drm_device *dev,
623 struct msm_fence_cb *cb, uint32_t fence)
624{
625 struct msm_drm_private *priv = dev->dev_private;
626 int ret = 0;
627
628 mutex_lock(&dev->struct_mutex);
629 if (!list_empty(&cb->work.entry)) {
630 ret = -EINVAL;
631 } else if (fence > priv->completed_fence) {
632 cb->fence = fence;
633 list_add_tail(&cb->work.entry, &priv->fence_cbs);
634 } else {
635 queue_work(priv->wq, &cb->work);
636 }
637 mutex_unlock(&dev->struct_mutex);
638
639 return ret;
640}
641
622/* called from workqueue */ 642/* called from workqueue */
623void msm_update_fence(struct drm_device *dev, uint32_t fence) 643void msm_update_fence(struct drm_device *dev, uint32_t fence)
624{ 644{
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index c763c19405de..5901be444777 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -154,6 +154,8 @@ int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
154 154
155int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, 155int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
156 struct timespec *timeout); 156 struct timespec *timeout);
157int msm_queue_fence_cb(struct drm_device *dev,
158 struct msm_fence_cb *cb, uint32_t fence);
157void msm_update_fence(struct drm_device *dev, uint32_t fence); 159void msm_update_fence(struct drm_device *dev, uint32_t fence);
158 160
159int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 161int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 4b1b82adabde..8207862b70d1 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -397,23 +397,10 @@ void *msm_gem_vaddr(struct drm_gem_object *obj)
397int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, 397int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
398 struct msm_fence_cb *cb) 398 struct msm_fence_cb *cb)
399{ 399{
400 struct drm_device *dev = obj->dev;
401 struct msm_drm_private *priv = dev->dev_private;
402 struct msm_gem_object *msm_obj = to_msm_bo(obj); 400 struct msm_gem_object *msm_obj = to_msm_bo(obj);
403 int ret = 0; 401 uint32_t fence = msm_gem_fence(msm_obj,
404 402 MSM_PREP_READ | MSM_PREP_WRITE);
405 mutex_lock(&dev->struct_mutex); 403 return msm_queue_fence_cb(obj->dev, cb, fence);
406 if (!list_empty(&cb->work.entry)) {
407 ret = -EINVAL;
408 } else if (is_active(msm_obj)) {
409 cb->fence = max(msm_obj->read_fence, msm_obj->write_fence);
410 list_add_tail(&cb->work.entry, &priv->fence_cbs);
411 } else {
412 queue_work(priv->wq, &cb->work);
413 }
414 mutex_unlock(&dev->struct_mutex);
415
416 return ret;
417} 404}
418 405
419void msm_gem_move_to_active(struct drm_gem_object *obj, 406void msm_gem_move_to_active(struct drm_gem_object *obj,
@@ -452,12 +439,8 @@ int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
452 int ret = 0; 439 int ret = 0;
453 440
454 if (is_active(msm_obj)) { 441 if (is_active(msm_obj)) {
455 uint32_t fence = 0; 442 uint32_t fence = msm_gem_fence(msm_obj, op);
456 443
457 if (op & MSM_PREP_READ)
458 fence = msm_obj->write_fence;
459 if (op & MSM_PREP_WRITE)
460 fence = max(fence, msm_obj->read_fence);
461 if (op & MSM_PREP_NOSYNC) 444 if (op & MSM_PREP_NOSYNC)
462 timeout = NULL; 445 timeout = NULL;
463 446
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index bfb052688f8e..8fbbd0594c46 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -70,6 +70,19 @@ static inline bool is_active(struct msm_gem_object *msm_obj)
70 return msm_obj->gpu != NULL; 70 return msm_obj->gpu != NULL;
71} 71}
72 72
73static inline uint32_t msm_gem_fence(struct msm_gem_object *msm_obj,
74 uint32_t op)
75{
76 uint32_t fence = 0;
77
78 if (op & MSM_PREP_READ)
79 fence = msm_obj->write_fence;
80 if (op & MSM_PREP_WRITE)
81 fence = max(fence, msm_obj->read_fence);
82
83 return fence;
84}
85
73#define MAX_CMDS 4 86#define MAX_CMDS 4
74 87
75/* Created per submit-ioctl, to track bo's and cmdstream bufs, etc, 88/* Created per submit-ioctl, to track bo's and cmdstream bufs, etc,