Merge branch 'archit/wb-dispc-for-3.7'

Merge omapdss writeback work. These patches implement the low level writeback
features in the DISPC, but do not yet add a way to actually use the writeback
from the userspace.

* archit/wb-dispc-for-3.7:
  OMAPDSS: DISPC: Configure color conversion coefficients for writeback
  OMAPDSS: DISPC: Add manager like functions for writeback
  OMAPDSS: DISPC: Configure writeback FIFOs
  OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup()
  OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup
  OMAPDSS: DISPC: Add function to set channel in for writeback
  OMAPDSS: DISPC: Don't set chroma resampling bit for writeback
  OMAPDSS: DISPC: Downscale chroma if plane is writeback
  OMAPDSS: DISPC: Configure input and output sizes for writeback
  OMAPDSS: DISPC: Add writeback register offsets and dss features structs
  OMAPDSS: DISPC: Allow both upscaling and downscaling of chroma
  OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode
  OMAPDSS: DISPC: Don't pass channel out when configuring overlays
  OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common
  OMAPDSS: OVERLAY: Add position and replication as overlay caps
  OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions
  OMAPDSS: DISPC: Simplify function names for setting pipeline input and output sizes
  OMAPDSS: DISPC: Constify omap_overlay_info in dispc_ovl_setup()

7 files changed, 510 insertions, 185 deletions

diff --git a/drivers/video/omap2/dss/apply.c b/drivers/video/omap2/dss/apply.c
index 2b1fa851a8b9..19d66f471b4b 100644
--- a/drivers/video/omap2/dss/apply.c
+++ b/drivers/video/omap2/dss/apply.c
@@ -584,7 +584,7 @@ static void dss_ovl_write_regs(struct omap_overlay *ovl)
 
         replication = dss_ovl_use_replication(mp->lcd_config, oi->color_mode);
 
-        r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings);
+        r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings, false);
         if (r) {
                 /*
                  * We can't do much here, as this function can be called from
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 811fe381aaea..a173a9481a23 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -86,14 +86,15 @@ struct dispc_features {
         u16 sw_max;
         u16 vp_max;
         u16 hp_max;
-        int (*calc_scaling) (enum omap_channel channel,
+        int (*calc_scaling) (enum omap_plane plane,
                 const struct omap_video_timings *mgr_timings,
                 u16 width, u16 height, u16 out_width, u16 out_height,
                 enum omap_color_mode color_mode, bool *five_taps,
                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
-                u16 pos_x, unsigned long *core_clk);
-        unsigned long (*calc_core_clk) (enum omap_channel channel,
-                u16 width, u16 height, u16 out_width, u16 out_height);
+                u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
+        unsigned long (*calc_core_clk) (enum omap_plane plane,
+                u16 width, u16 height, u16 out_width, u16 out_height,
+                bool mem_to_mem);
         u8 num_fifos;
 
         /* swap GFX & WB fifos */
@@ -235,7 +236,14 @@ static const struct {
         },
 };
 
+struct color_conv_coef {
+        int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
+        int full_range;
+};
+
 static void _omap_dispc_set_irqs(void);
+static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
+static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 
 static inline void dispc_write_reg(const u16 idx, u32 val)
 {
@@ -533,6 +541,11 @@ u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
         return mgr_desc[channel].framedone_irq;
 }
 
+u32 dispc_wb_get_framedone_irq(void)
+{
+        return DISPC_IRQ_FRAMEDONEWB;
+}
+
 bool dispc_mgr_go_busy(enum omap_channel channel)
 {
         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
@@ -560,6 +573,30 @@ void dispc_mgr_go(enum omap_channel channel)
         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 }
 
+bool dispc_wb_go_busy(void)
+{
+        return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
+}
+
+void dispc_wb_go(void)
+{
+        enum omap_plane plane = OMAP_DSS_WB;
+        bool enable, go;
+
+        enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
+
+        if (!enable)
+                return;
+
+        go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
+        if (go) {
+                DSSERR("GO bit not down for WB\n");
+                return;
+        }
+
+        REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
+}
+
 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 {
         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
@@ -642,41 +679,41 @@ static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
         }
 }
 
-static void _dispc_setup_color_conv_coef(void)
-{
-        int i;
-        const struct color_conv_coef {
-                int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
-                int  full_range;
-        }  ctbl_bt601_5 = {
-                298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
-        };
-
-        const struct color_conv_coef *ct;
 
+static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
+                const struct color_conv_coef *ct)
+{
 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 
-        ct = &ctbl_bt601_5;
+        dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
+        dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
+        dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
+        dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
+        dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 
-        for (i = 1; i < dss_feat_get_num_ovls(); i++) {
-                dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
-                        CVAL(ct->rcr, ct->ry));
-                dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
-                        CVAL(ct->gy,  ct->rcb));
-                dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
-                        CVAL(ct->gcb, ct->gcr));
-                dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
-                        CVAL(ct->bcr, ct->by));
-                dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
-                        CVAL(0, ct->bcb));
-
-                REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
-                        11, 11);
-        }
+        REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 
 #undef CVAL
 }
 
+static void dispc_setup_color_conv_coef(void)
+{
+        int i;
+        int num_ovl = dss_feat_get_num_ovls();
+        int num_wb = dss_feat_get_num_wbs();
+        const struct color_conv_coef ctbl_bt601_5_ovl = {
+                298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
+        };
+        const struct color_conv_coef ctbl_bt601_5_wb = {
+                66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
+        };
+
+        for (i = 1; i < num_ovl; i++)
+                dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
+
+        for (; i < num_wb; i++)
+                dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
+}