diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2010-10-15 01:14:54 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-10-15 05:58:40 -0400 |
commit | 685e4080c62b4b5c6f67c7b088e416e98d06f7e6 (patch) | |
tree | 457954b1e78adf076be55eb2107f4cc35115c345 | |
parent | 90e09a59110949bda40c13b4e5925f3acd3597b0 (diff) |
ARM: mach-shmobile: clock-sh7372: add sh7372_ prefix to global clocks
This patch also registered global extal clocks to sh7372.h
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r-- | arch/arm/mach-shmobile/board-ap4evb.c | 14 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/clock-sh7372.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/include/mach/sh7372.h | 8 |
3 files changed, 24 insertions, 22 deletions
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index aaac8b09047b..f879eb3c3427 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c | |||
@@ -780,22 +780,22 @@ static int __init hdmi_init_pm_clock(void) | |||
780 | goto out; | 780 | goto out; |
781 | } | 781 | } |
782 | 782 | ||
783 | ret = clk_set_parent(&pllc2_clk, &dv_clki_div2_clk); | 783 | ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); |
784 | if (ret < 0) { | 784 | if (ret < 0) { |
785 | pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, pllc2_clk.usecount); | 785 | pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount); |
786 | goto out; | 786 | goto out; |
787 | } | 787 | } |
788 | 788 | ||
789 | pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&pllc2_clk)); | 789 | pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk)); |
790 | 790 | ||
791 | rate = clk_round_rate(&pllc2_clk, 594000000); | 791 | rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); |
792 | if (rate < 0) { | 792 | if (rate < 0) { |
793 | pr_err("Cannot get suitable rate: %ld\n", rate); | 793 | pr_err("Cannot get suitable rate: %ld\n", rate); |
794 | ret = rate; | 794 | ret = rate; |
795 | goto out; | 795 | goto out; |
796 | } | 796 | } |
797 | 797 | ||
798 | ret = clk_set_rate(&pllc2_clk, rate); | 798 | ret = clk_set_rate(&sh7372_pllc2_clk, rate); |
799 | if (ret < 0) { | 799 | if (ret < 0) { |
800 | pr_err("Cannot set rate %ld: %d\n", rate, ret); | 800 | pr_err("Cannot set rate %ld: %d\n", rate, ret); |
801 | goto out; | 801 | goto out; |
@@ -803,7 +803,7 @@ static int __init hdmi_init_pm_clock(void) | |||
803 | 803 | ||
804 | pr_debug("PLLC2 set frequency %lu\n", rate); | 804 | pr_debug("PLLC2 set frequency %lu\n", rate); |
805 | 805 | ||
806 | ret = clk_set_parent(hdmi_ick, &pllc2_clk); | 806 | ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); |
807 | if (ret < 0) { | 807 | if (ret < 0) { |
808 | pr_err("Cannot set HDMI parent: %d\n", ret); | 808 | pr_err("Cannot set HDMI parent: %d\n", ret); |
809 | goto out; | 809 | goto out; |
@@ -1132,7 +1132,7 @@ static void __init ap4evb_timer_init(void) | |||
1132 | shmobile_timer.init(); | 1132 | shmobile_timer.init(); |
1133 | 1133 | ||
1134 | /* External clock source */ | 1134 | /* External clock source */ |
1135 | clk_set_rate(&dv_clki_clk, 27000000); | 1135 | clk_set_rate(&sh7372_dv_clki_clk, 27000000); |
1136 | } | 1136 | } |
1137 | 1137 | ||
1138 | static struct sys_timer ap4evb_timer = { | 1138 | static struct sys_timer ap4evb_timer = { |
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 3ab190ab7d40..50c3971d3dcb 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c | |||
@@ -51,7 +51,7 @@ | |||
51 | #define SMSTPCR4 0xe6150140 | 51 | #define SMSTPCR4 0xe6150140 |
52 | 52 | ||
53 | /* Platforms must set frequency on their DV_CLKI pin */ | 53 | /* Platforms must set frequency on their DV_CLKI pin */ |
54 | struct clk dv_clki_clk = { | 54 | struct clk sh7372_dv_clki_clk = { |
55 | }; | 55 | }; |
56 | 56 | ||
57 | /* Fixed 32 KHz root clock from EXTALR pin */ | 57 | /* Fixed 32 KHz root clock from EXTALR pin */ |
@@ -86,9 +86,9 @@ static struct clk_ops div2_clk_ops = { | |||
86 | }; | 86 | }; |
87 | 87 | ||
88 | /* Divide dv_clki by two */ | 88 | /* Divide dv_clki by two */ |
89 | struct clk dv_clki_div2_clk = { | 89 | struct clk sh7372_dv_clki_div2_clk = { |
90 | .ops = &div2_clk_ops, | 90 | .ops = &div2_clk_ops, |
91 | .parent = &dv_clki_clk, | 91 | .parent = &sh7372_dv_clki_clk, |
92 | }; | 92 | }; |
93 | 93 | ||
94 | /* Divide extal1 by two */ | 94 | /* Divide extal1 by two */ |
@@ -150,7 +150,7 @@ static struct clk pllc1_div2_clk = { | |||
150 | static struct clk *pllc2_parent[] = { | 150 | static struct clk *pllc2_parent[] = { |
151 | [0] = &extal1_div2_clk, | 151 | [0] = &extal1_div2_clk, |
152 | [1] = &extal2_div2_clk, | 152 | [1] = &extal2_div2_clk, |
153 | [2] = &dv_clki_div2_clk, | 153 | [2] = &sh7372_dv_clki_div2_clk, |
154 | }; | 154 | }; |
155 | 155 | ||
156 | /* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */ | 156 | /* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */ |
@@ -284,7 +284,7 @@ static struct clk_ops pllc2_clk_ops = { | |||
284 | .set_parent = pllc2_set_parent, | 284 | .set_parent = pllc2_set_parent, |
285 | }; | 285 | }; |
286 | 286 | ||
287 | struct clk pllc2_clk = { | 287 | struct clk sh7372_pllc2_clk = { |
288 | .ops = &pllc2_clk_ops, | 288 | .ops = &pllc2_clk_ops, |
289 | .parent = &extal1_div2_clk, | 289 | .parent = &extal1_div2_clk, |
290 | .freq_table = pllc2_freq_table, | 290 | .freq_table = pllc2_freq_table, |
@@ -293,18 +293,18 @@ struct clk pllc2_clk = { | |||
293 | }; | 293 | }; |
294 | 294 | ||
295 | static struct clk *main_clks[] = { | 295 | static struct clk *main_clks[] = { |
296 | &dv_clki_clk, | 296 | &sh7372_dv_clki_clk, |
297 | &r_clk, | 297 | &r_clk, |
298 | &sh7372_extal1_clk, | 298 | &sh7372_extal1_clk, |
299 | &sh7372_extal2_clk, | 299 | &sh7372_extal2_clk, |
300 | &dv_clki_div2_clk, | 300 | &sh7372_dv_clki_div2_clk, |
301 | &extal1_div2_clk, | 301 | &extal1_div2_clk, |
302 | &extal2_div2_clk, | 302 | &extal2_div2_clk, |
303 | &extal2_div4_clk, | 303 | &extal2_div4_clk, |
304 | &pllc0_clk, | 304 | &pllc0_clk, |
305 | &pllc1_clk, | 305 | &pllc1_clk, |
306 | &pllc1_div2_clk, | 306 | &pllc1_div2_clk, |
307 | &pllc2_clk, | 307 | &sh7372_pllc2_clk, |
308 | }; | 308 | }; |
309 | 309 | ||
310 | static void div4_kick(struct clk *clk) | 310 | static void div4_kick(struct clk *clk) |
@@ -382,8 +382,8 @@ enum { DIV6_HDMI, DIV6_REPARENT_NR }; | |||
382 | /* Indices are important - they are the actual src selecting values */ | 382 | /* Indices are important - they are the actual src selecting values */ |
383 | static struct clk *hdmi_parent[] = { | 383 | static struct clk *hdmi_parent[] = { |
384 | [0] = &pllc1_div2_clk, | 384 | [0] = &pllc1_div2_clk, |
385 | [1] = &pllc2_clk, | 385 | [1] = &sh7372_pllc2_clk, |
386 | [2] = &dv_clki_clk, | 386 | [2] = &sh7372_dv_clki_clk, |
387 | [3] = NULL, /* pllc2_div4 not implemented yet */ | 387 | [3] = NULL, /* pllc2_div4 not implemented yet */ |
388 | }; | 388 | }; |
389 | 389 | ||
@@ -448,7 +448,7 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
448 | 448 | ||
449 | static struct clk_lookup lookups[] = { | 449 | static struct clk_lookup lookups[] = { |
450 | /* main clocks */ | 450 | /* main clocks */ |
451 | CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk), | 451 | CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk), |
452 | CLKDEV_CON_ID("r_clk", &r_clk), | 452 | CLKDEV_CON_ID("r_clk", &r_clk), |
453 | CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), | 453 | CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), |
454 | CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), | 454 | CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), |
@@ -458,7 +458,7 @@ static struct clk_lookup lookups[] = { | |||
458 | CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), | 458 | CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), |
459 | CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), | 459 | CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), |
460 | CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), | 460 | CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), |
461 | CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), | 461 | CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk), |
462 | 462 | ||
463 | /* DIV4 clocks */ | 463 | /* DIV4 clocks */ |
464 | CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), | 464 | CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), |
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index 33e9700ded7e..9838fcf03083 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h | |||
@@ -457,8 +457,10 @@ enum { | |||
457 | SHDMA_SLAVE_SDHI2_TX, | 457 | SHDMA_SLAVE_SDHI2_TX, |
458 | }; | 458 | }; |
459 | 459 | ||
460 | extern struct clk dv_clki_clk; | 460 | extern struct clk sh7372_extal1_clk; |
461 | extern struct clk dv_clki_div2_clk; | 461 | extern struct clk sh7372_extal2_clk; |
462 | extern struct clk pllc2_clk; | 462 | extern struct clk sh7372_dv_clki_clk; |
463 | extern struct clk sh7372_dv_clki_div2_clk; | ||
464 | extern struct clk sh7372_pllc2_clk; | ||
463 | 465 | ||
464 | #endif /* __ASM_SH7372_H__ */ | 466 | #endif /* __ASM_SH7372_H__ */ |