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authorJoseph CHANG <josright123@gmail.com>2013-03-28 19:13:42 -0400
committerDavid S. Miller <davem@davemloft.net>2013-03-31 19:43:23 -0400
commit6741f40d198c6a5feb23653a1efd4ca47f93d83d (patch)
tree99fd67ba30de5f59d1099e1f18c75247da21973d
parent3340d2aae3433ad9147f6bf0adc452b324e31591 (diff)
DM9000B: driver initialization upgrade
Fix bug for DM9000 revision B which contain a DSP PHY DM9000B use DSP PHY instead previouse DM9000 revisions' analog PHY, So need extra change in initialization, For explicity PHY Reset and PHY init parameter, and first DM9000_NCR reset need NCR_MAC_LBK bit by dm9000_probe(). Following DM9000_NCR reset cause by dm9000_open() clear the NCR_MAC_LBK bit. Without this fix, Power-up FIFO pointers error happen around 2% rate among Davicom's customers' boards. With this fix, All above cases can be solved. Signed-off-by: Joseph CHANG <josright123@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/davicom/dm9000.c214
-rw-r--r--drivers/net/ethernet/davicom/dm9000.h11
2 files changed, 120 insertions, 105 deletions
diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c
index 8cdf02503d13..9eada8e86078 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -257,6 +257,107 @@ static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
257 tmp = readl(reg); 257 tmp = readl(reg);
258} 258}
259 259
260/*
261 * Sleep, either by using msleep() or if we are suspending, then
262 * use mdelay() to sleep.
263 */
264static void dm9000_msleep(board_info_t *db, unsigned int ms)
265{
266 if (db->in_suspend)
267 mdelay(ms);
268 else
269 msleep(ms);
270}
271
272/* Read a word from phyxcer */
273static int
274dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
275{
276 board_info_t *db = netdev_priv(dev);
277 unsigned long flags;
278 unsigned int reg_save;
279 int ret;
280
281 mutex_lock(&db->addr_lock);
282
283 spin_lock_irqsave(&db->lock, flags);
284
285 /* Save previous register address */
286 reg_save = readb(db->io_addr);
287
288 /* Fill the phyxcer register into REG_0C */
289 iow(db, DM9000_EPAR, DM9000_PHY | reg);
290
291 /* Issue phyxcer read command */
292 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);
293
294 writeb(reg_save, db->io_addr);
295 spin_unlock_irqrestore(&db->lock, flags);
296
297 dm9000_msleep(db, 1); /* Wait read complete */
298
299 spin_lock_irqsave(&db->lock, flags);
300 reg_save = readb(db->io_addr);
301
302 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
303
304 /* The read data keeps on REG_0D & REG_0E */
305 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
306
307 /* restore the previous address */
308 writeb(reg_save, db->io_addr);
309 spin_unlock_irqrestore(&db->lock, flags);
310
311 mutex_unlock(&db->addr_lock);
312
313 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
314 return ret;
315}
316
317/* Write a word to phyxcer */
318static void
319dm9000_phy_write(struct net_device *dev,
320 int phyaddr_unused, int reg, int value)
321{
322 board_info_t *db = netdev_priv(dev);
323 unsigned long flags;
324 unsigned long reg_save;
325
326 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
327 mutex_lock(&db->addr_lock);
328
329 spin_lock_irqsave(&db->lock, flags);
330
331 /* Save previous register address */
332 reg_save = readb(db->io_addr);
333
334 /* Fill the phyxcer register into REG_0C */
335 iow(db, DM9000_EPAR, DM9000_PHY | reg);
336
337 /* Fill the written data into REG_0D & REG_0E */
338 iow(db, DM9000_EPDRL, value);
339 iow(db, DM9000_EPDRH, value >> 8);
340
341 /* Issue phyxcer write command */
342 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);
343
344 writeb(reg_save, db->io_addr);
345 spin_unlock_irqrestore(&db->lock, flags);
346
347 dm9000_msleep(db, 1); /* Wait write complete */
348
349 spin_lock_irqsave(&db->lock, flags);
350 reg_save = readb(db->io_addr);
351
352 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
353
354 /* restore the previous address */
355 writeb(reg_save, db->io_addr);
356
357 spin_unlock_irqrestore(&db->lock, flags);
358 mutex_unlock(&db->addr_lock);
359}
360
260/* dm9000_set_io 361/* dm9000_set_io
261 * 362 *
262 * select the specified set of io routines to use with the 363 * select the specified set of io routines to use with the
@@ -795,6 +896,9 @@ dm9000_init_dm9000(struct net_device *dev)
795 896
796 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ 897 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
797 898
899 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
900 dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); /* Init */
901
798 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0; 902 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
799 903
800 /* if wol is needed, then always set NCR_WAKEEN otherwise we end 904 /* if wol is needed, then always set NCR_WAKEEN otherwise we end
@@ -1201,109 +1305,6 @@ dm9000_open(struct net_device *dev)
1201 return 0; 1305 return 0;
1202} 1306}
1203 1307
1204/*
1205 * Sleep, either by using msleep() or if we are suspending, then
1206 * use mdelay() to sleep.
1207 */
1208static void dm9000_msleep(board_info_t *db, unsigned int ms)
1209{
1210 if (db->in_suspend)
1211 mdelay(ms);
1212 else
1213 msleep(ms);
1214}
1215
1216/*
1217 * Read a word from phyxcer
1218 */
1219static int
1220dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
1221{
1222 board_info_t *db = netdev_priv(dev);
1223 unsigned long flags;
1224 unsigned int reg_save;
1225 int ret;
1226
1227 mutex_lock(&db->addr_lock);
1228
1229 spin_lock_irqsave(&db->lock,flags);
1230
1231 /* Save previous register address */
1232 reg_save = readb(db->io_addr);
1233
1234 /* Fill the phyxcer register into REG_0C */
1235 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1236
1237 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); /* Issue phyxcer read command */
1238
1239 writeb(reg_save, db->io_addr);
1240 spin_unlock_irqrestore(&db->lock,flags);
1241
1242 dm9000_msleep(db, 1); /* Wait read complete */
1243
1244 spin_lock_irqsave(&db->lock,flags);
1245 reg_save = readb(db->io_addr);
1246
1247 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
1248
1249 /* The read data keeps on REG_0D & REG_0E */
1250 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
1251
1252 /* restore the previous address */
1253 writeb(reg_save, db->io_addr);
1254 spin_unlock_irqrestore(&db->lock,flags);
1255
1256 mutex_unlock(&db->addr_lock);
1257
1258 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
1259 return ret;
1260}
1261
1262/*
1263 * Write a word to phyxcer
1264 */
1265static void
1266dm9000_phy_write(struct net_device *dev,
1267 int phyaddr_unused, int reg, int value)
1268{
1269 board_info_t *db = netdev_priv(dev);
1270 unsigned long flags;
1271 unsigned long reg_save;
1272
1273 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
1274 mutex_lock(&db->addr_lock);
1275
1276 spin_lock_irqsave(&db->lock,flags);
1277
1278 /* Save previous register address */
1279 reg_save = readb(db->io_addr);
1280
1281 /* Fill the phyxcer register into REG_0C */
1282 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1283
1284 /* Fill the written data into REG_0D & REG_0E */
1285 iow(db, DM9000_EPDRL, value);
1286 iow(db, DM9000_EPDRH, value >> 8);
1287
1288 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */
1289
1290 writeb(reg_save, db->io_addr);
1291 spin_unlock_irqrestore(&db->lock, flags);
1292
1293 dm9000_msleep(db, 1); /* Wait write complete */
1294
1295 spin_lock_irqsave(&db->lock,flags);
1296 reg_save = readb(db->io_addr);
1297
1298 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
1299
1300 /* restore the previous address */
1301 writeb(reg_save, db->io_addr);
1302
1303 spin_unlock_irqrestore(&db->lock, flags);
1304 mutex_unlock(&db->addr_lock);
1305}
1306
1307static void 1308static void
1308dm9000_shutdown(struct net_device *dev) 1309dm9000_shutdown(struct net_device *dev)
1309{ 1310{
@@ -1502,7 +1503,12 @@ dm9000_probe(struct platform_device *pdev)
1502 db->flags |= DM9000_PLATF_SIMPLE_PHY; 1503 db->flags |= DM9000_PLATF_SIMPLE_PHY;
1503#endif 1504#endif
1504 1505
1505 dm9000_reset(db); 1506 /* Fixing bug on dm9000_probe, takeover dm9000_reset(db),
1507 * Need 'NCR_MAC_LBK' bit to indeed stable our DM9000 fifo
1508 * while probe stage.
1509 */
1510
1511 iow(db, DM9000_NCR, NCR_MAC_LBK | NCR_RST);
1506 1512
1507 /* try multiple times, DM9000 sometimes gets the read wrong */ 1513 /* try multiple times, DM9000 sometimes gets the read wrong */
1508 for (i = 0; i < 8; i++) { 1514 for (i = 0; i < 8; i++) {
diff --git a/drivers/net/ethernet/davicom/dm9000.h b/drivers/net/ethernet/davicom/dm9000.h
index 55688bd1a3ef..9ce058adabab 100644
--- a/drivers/net/ethernet/davicom/dm9000.h
+++ b/drivers/net/ethernet/davicom/dm9000.h
@@ -69,7 +69,9 @@
69#define NCR_WAKEEN (1<<6) 69#define NCR_WAKEEN (1<<6)
70#define NCR_FCOL (1<<4) 70#define NCR_FCOL (1<<4)
71#define NCR_FDX (1<<3) 71#define NCR_FDX (1<<3)
72#define NCR_LBK (3<<1) 72
73#define NCR_RESERVED (3<<1)
74#define NCR_MAC_LBK (1<<1)
73#define NCR_RST (1<<0) 75#define NCR_RST (1<<0)
74 76
75#define NSR_SPEED (1<<7) 77#define NSR_SPEED (1<<7)
@@ -167,5 +169,12 @@
167#define ISR_LNKCHNG (1<<5) 169#define ISR_LNKCHNG (1<<5)
168#define ISR_UNDERRUN (1<<4) 170#define ISR_UNDERRUN (1<<4)
169 171
172/* Davicom MII registers.
173 */
174
175#define MII_DM_DSPCR 0x1b /* DSP Control Register */
176
177#define DSPCR_INIT_PARAM 0xE100 /* DSP init parameter */
178
170#endif /* _DM9000X_H_ */ 179#endif /* _DM9000X_H_ */
171 180