ARM: dts: qcom: Add initial IFC6540 board device tree

Add basic support for the IFC6540 single-board computer boards, that are
based on the APQ8084 SoC. This patch adds the initial device tree and the
neccessary nodes required for enabling the serial port and eMMC.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

3 files changed, 47 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a097a042bdb3..aaa1a685d319 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -341,6 +341,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_QCOM) += \
         qcom-apq8064-ifc6410.dtb \
         qcom-apq8074-dragonboard.dtb \
+        qcom-apq8084-ifc6540.dtb \
         qcom-apq8084-mtp.dtb \
         qcom-ipq8064-ap148.dtb \
         qcom-msm8660-surf.dtb \
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
new file mode 100644
index 000000000000..c9ff10821ad9
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -0,0 +1,23 @@
+#include "qcom-apq8084.dtsi"
+
+/ {
+        model = "Qualcomm APQ8084/IFC6540";
+        compatible = "qcom,apq8084-ifc6540", "qcom,apq8084";
+
+        soc {
+                serial@f995e000 {
+                        status = "okay";
+                };
+
+                sdhci@f9824900 {
+                        bus-width = <8>;
+                        non-removable;
+                        status = "okay";
+                };
+
+                sdhci@f98a4900 {
+                        cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
+                        bus-width = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index b5b156e328a0..b9ac63cfe9e6 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -3,6 +3,7 @@
 #include "skeleton.dtsi"
 
 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Qualcomm APQ 8084";
@@ -193,5 +194,27 @@
                         clock-names = "core", "iface";
                         status = "disabled";
                 };
+
+                sdhci@f9824900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 123 0>, <0 138 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+
+                sdhci@f98a4900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 125 0>, <0 221 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
         };
 };