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authorLee Jones <lee.jones@linaro.org>2013-05-03 10:31:53 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-05-23 15:10:44 -0400
commit664a57ecb026dc47f9d8b002e6dcb557e877e4d1 (patch)
tree30460dbcbbcf0151df2ce389d7a5a60bfcc6bd5f
parentf722406faae2d073cc1d01063d1123c35425939e (diff)
dmaengine: ste_dma40: Assign memcpy channels in the driver
The channels reserved for memcpy are the same for all currently supported platforms. With this in mind, we can ease the platform data passing requirement by moving these assignments out from platform code and place them directly into the driver. Acked-by: Vinod Koul <vnod.koul@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c12
-rw-r--r--drivers/dma/ste_dma40.c12
-rw-r--r--include/linux/platform_data/dma-ste-dma40.h4
3 files changed, 7 insertions, 21 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 1cf94ce0feec..159855fae55b 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -146,22 +146,10 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
146 [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET, 146 [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
147}; 147};
148 148
149/* Reserved event lines for memcpy only */
150static int dma40_memcpy_event[] = {
151 DB8500_DMA_MEMCPY_TX_0,
152 DB8500_DMA_MEMCPY_TX_1,
153 DB8500_DMA_MEMCPY_TX_2,
154 DB8500_DMA_MEMCPY_TX_3,
155 DB8500_DMA_MEMCPY_TX_4,
156 DB8500_DMA_MEMCPY_TX_5,
157};
158
159static struct stedma40_platform_data dma40_plat_data = { 149static struct stedma40_platform_data dma40_plat_data = {
160 .dev_len = DB8500_DMA_NR_DEV, 150 .dev_len = DB8500_DMA_NR_DEV,
161 .dev_rx = dma40_rx_map, 151 .dev_rx = dma40_rx_map,
162 .dev_tx = dma40_tx_map, 152 .dev_tx = dma40_tx_map,
163 .memcpy = dma40_memcpy_event,
164 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
165 .memcpy_conf_phy = &dma40_memcpy_conf_phy, 153 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
166 .memcpy_conf_log = &dma40_memcpy_conf_log, 154 .memcpy_conf_log = &dma40_memcpy_conf_log,
167 .disabled_channels = {-1}, 155 .disabled_channels = {-1},
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 1734feec47b1..12de79e84b15 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -55,6 +55,9 @@
55 55
56#define MAX(a, b) (((a) < (b)) ? (b) : (a)) 56#define MAX(a, b) (((a) < (b)) ? (b) : (a))
57 57
58/* Reserved event lines for memcpy only. */
59static int dma40_memcpy_channels[] = { 56, 57, 58, 59, 60 };
60
58/** 61/**
59 * enum 40_command - The different commands and/or statuses. 62 * enum 40_command - The different commands and/or statuses.
60 * 63 *
@@ -2014,8 +2017,7 @@ static int d40_config_memcpy(struct d40_chan *d40c)
2014 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { 2017 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
2015 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; 2018 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
2016 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; 2019 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
2017 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> 2020 d40c->dma_cfg.dst_dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
2018 memcpy[d40c->chan.chan_id];
2019 2021
2020 } else if (dma_has_cap(DMA_MEMCPY, cap) && 2022 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2021 dma_has_cap(DMA_SLAVE, cap)) { 2023 dma_has_cap(DMA_SLAVE, cap)) {
@@ -2927,7 +2929,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
2927 } 2929 }
2928 2930
2929 d40_chan_init(base, &base->dma_memcpy, base->log_chans, 2931 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2930 base->num_log_chans, base->plat_data->memcpy_len); 2932 base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
2931 2933
2932 dma_cap_zero(base->dma_memcpy.cap_mask); 2934 dma_cap_zero(base->dma_memcpy.cap_mask);
2933 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); 2935 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3215,7 +3217,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3215 num_log_chans++; 3217 num_log_chans++;
3216 3218
3217 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + 3219 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3218 (num_phy_chans + num_log_chans + plat_data->memcpy_len) * 3220 (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
3219 sizeof(struct d40_chan), GFP_KERNEL); 3221 sizeof(struct d40_chan), GFP_KERNEL);
3220 3222
3221 if (base == NULL) { 3223 if (base == NULL) {
@@ -3276,7 +3278,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3276 if (!base->lookup_phy_chans) 3278 if (!base->lookup_phy_chans)
3277 goto failure; 3279 goto failure;
3278 3280
3279 if (num_log_chans + plat_data->memcpy_len) { 3281 if (num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) {
3280 /* 3282 /*
3281 * The max number of logical channels are event lines for all 3283 * The max number of logical channels are event lines for all
3282 * src devices and dst devices 3284 * src devices and dst devices
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 4b781014b0a0..a8087843a99b 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -141,8 +141,6 @@ struct stedma40_chan_cfg {
141 * @dev_len: length of dev_tx and dev_rx 141 * @dev_len: length of dev_tx and dev_rx
142 * @dev_tx: mapping between destination event line and io address 142 * @dev_tx: mapping between destination event line and io address
143 * @dev_rx: mapping between source event line and io address 143 * @dev_rx: mapping between source event line and io address
144 * @memcpy: list of memcpy event lines
145 * @memcpy_len: length of memcpy
146 * @memcpy_conf_phy: default configuration of physical channel memcpy 144 * @memcpy_conf_phy: default configuration of physical channel memcpy
147 * @memcpy_conf_log: default configuration of logical channel memcpy 145 * @memcpy_conf_log: default configuration of logical channel memcpy
148 * @disabled_channels: A vector, ending with -1, that marks physical channels 146 * @disabled_channels: A vector, ending with -1, that marks physical channels
@@ -162,8 +160,6 @@ struct stedma40_platform_data {
162 u32 dev_len; 160 u32 dev_len;
163 const dma_addr_t *dev_tx; 161 const dma_addr_t *dev_tx;
164 const dma_addr_t *dev_rx; 162 const dma_addr_t *dev_rx;
165 int *memcpy;
166 u32 memcpy_len;
167 struct stedma40_chan_cfg *memcpy_conf_phy; 163 struct stedma40_chan_cfg *memcpy_conf_phy;
168 struct stedma40_chan_cfg *memcpy_conf_log; 164 struct stedma40_chan_cfg *memcpy_conf_log;
169 int disabled_channels[STEDMA40_MAX_PHYS]; 165 int disabled_channels[STEDMA40_MAX_PHYS];