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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2014-01-07 03:22:56 -0500
committerSimon Horman <horms+renesas@verge.net.au>2014-02-03 20:16:59 -0500
commit65f05c38749f393f775c360b9b247fa4d63b72de (patch)
tree1ccd4dd07c4ac06dedb0f443cfe884cd689100d8
parentbccccc3d861567876a87441bc92f2e3b46cb38a9 (diff)
ARM: shmobile: r8a7791: Add SATA clocks to device tree
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 93c6f4d2866c..94e3cc17448c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -655,13 +655,15 @@
655 mstp8_clks: mstp8_clks@e6150990 { 655 mstp8_clks: mstp8_clks@e6150990 {
656 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 656 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
657 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 657 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
658 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>; 658 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
659 <&zs_clk>;
659 #clock-cells = <1>; 660 #clock-cells = <1>;
660 renesas,clock-indices = < 661 renesas,clock-indices = <
661 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 662 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
662 R8A7791_CLK_ETHER 663 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
663 >; 664 >;
664 clock-output-names = "vin2", "vin1", "vin0", "ether"; 665 clock-output-names =
666 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
665 }; 667 };
666 mstp9_clks: mstp9_clks@e6150994 { 668 mstp9_clks: mstp9_clks@e6150994 {
667 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 669 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";