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authorMichael Turquette <mturquette@linaro.org>2015-03-06 14:21:13 -0500
committerStephen Boyd <sboyd@codeaurora.org>2015-03-12 15:18:57 -0400
commit65bd20046f15c9c465df7aa9b86491e56e9c0d25 (patch)
tree1d97687fecdcfc43409a6874dcef6192cdb9b0e1
parent0bf0ff82c34da02ee5795101b328225a2d519594 (diff)
parentb2f0e5f28e0686c0d5db238357a2e32555e97633 (diff)
Merge tag 'v3.20-exynos5433-clk' of git://linuxtv.org/snawrocki/samsung into clk-next
Clock controller driver for Exynos 5433 SoC.
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5433-clock.txt462
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-exynos-clkout.c2
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c5423
-rw-r--r--include/dt-bindings/clock/exynos5433.h1403
5 files changed, 7291 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
new file mode 100644
index 000000000000..63379b04e052
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -0,0 +1,462 @@
1* Samsung Exynos5433 CMU (Clock Management Units)
2
3The Exynos5433 clock controller generates and supplies clock to various
4controllers within the Exynos5433 SoC.
5
6Required Properties:
7
8- compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
13 which generates clocks for LLI (Low Latency Interface) IP.
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
23 which generates clocks for G2D/MDMA IPs.
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
28 - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
30 which generates global data buses clock and global peripheral buses clock.
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
32 which generates clocks for 3D Graphics Engine IP.
33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
34 which generates clocks for GSCALER IPs.
35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
36 which generates clocks for Cortex-A53 Quad-core processor.
37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
38 which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
39 L2 cache controller.
40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
41 which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
43 which generates clocks for MFC(Multi-Format Codec) IP.
44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
45 which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
49 which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
50 IPs.
51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
52 which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
53
54- reg: physical base address of the controller and length of memory mapped
55 region.
56
57- #clock-cells: should be 1.
58
59- clocks: list of the clock controller input clock identifiers,
60 from common clock bindings. Please refer the next section
61 to find the input clocks for a given controller.
62
63- clock-names: list of the clock controller input clock names,
64 as described in clock-bindings.txt.
65
66 Input clocks for top clock controller:
67 - oscclk
68 - sclk_mphy_pll
69 - sclk_mfc_pll
70 - sclk_bus_pll
71
72 Input clocks for cpif clock controller:
73 - oscclk
74
75 Input clocks for mif clock controller:
76 - oscclk
77 - sclk_mphy_pll
78
79 Input clocks for fsys clock controller:
80 - oscclk
81 - sclk_ufs_mphy
82 - div_aclk_fsys_200
83 - sclk_pcie_100_fsys
84 - sclk_ufsunipro_fsys
85 - sclk_mmc2_fsys
86 - sclk_mmc1_fsys
87 - sclk_mmc0_fsys
88 - sclk_usbhost30_fsys
89 - sclk_usbdrd30_fsys
90
91 Input clocks for g2d clock controller:
92 - oscclk
93 - aclk_g2d_266
94 - aclk_g2d_400
95
96 Input clocks for disp clock controller:
97 - oscclk
98 - sclk_dsim1_disp
99 - sclk_dsim0_disp
100 - sclk_dsd_disp
101 - sclk_decon_tv_eclk_disp
102 - sclk_decon_vclk_disp
103 - sclk_decon_eclk_disp
104 - sclk_decon_tv_vclk_disp
105 - aclk_disp_333
106
107 Input clocks for bus0 clock controller:
108 - aclk_bus0_400
109
110 Input clocks for bus1 clock controller:
111 - aclk_bus1_400
112
113 Input clocks for bus2 clock controller:
114 - oscclk
115 - aclk_bus2_400
116
117 Input clocks for g3d clock controller:
118 - oscclk
119 - aclk_g3d_400
120
121 Input clocks for gscl clock controller:
122 - oscclk
123 - aclk_gscl_111
124 - aclk_gscl_333
125
126 Input clocks for apollo clock controller:
127 - oscclk
128 - sclk_bus_pll_apollo
129
130 Input clocks for atlas clock controller:
131 - oscclk
132 - sclk_bus_pll_atlas
133
134 Input clocks for mscl clock controller:
135 - oscclk
136 - sclk_jpeg_mscl
137 - aclk_mscl_400
138
139 Input clocks for mfc clock controller:
140 - oscclk
141 - aclk_mfc_400
142
143 Input clocks for hevc clock controller:
144 - oscclk
145 - aclk_hevc_400
146
147 Input clocks for isp clock controller:
148 - oscclk
149 - aclk_isp_dis_400
150 - aclk_isp_400
151
152 Input clocks for cam0 clock controller:
153 - oscclk
154 - aclk_cam0_333
155 - aclk_cam0_400
156 - aclk_cam0_552
157
158 Input clocks for cam1 clock controller:
159 - oscclk
160 - sclk_isp_uart_cam1
161 - sclk_isp_spi1_cam1
162 - sclk_isp_spi0_cam1
163 - aclk_cam1_333
164 - aclk_cam1_400
165 - aclk_cam1_552
166
167Each clock is assigned an identifier and client nodes can use this identifier
168to specify the clock which they consume.
169
170All available clocks are defined as preprocessor macros in
171dt-bindings/clock/exynos5433.h header and can be used in device
172tree sources.
173
174Example 1: Examples of 'oscclk' source clock node are listed below.
175
176 xxti: xxti {
177 compatible = "fixed-clock";
178 clock-output-names = "oscclk";
179 #clock-cells = <0>;
180 };
181
182Example 2: Examples of clock controller nodes are listed below.
183
184 cmu_top: clock-controller@10030000 {
185 compatible = "samsung,exynos5433-cmu-top";
186 reg = <0x10030000 0x0c04>;
187 #clock-cells = <1>;
188
189 clock-names = "oscclk",
190 "sclk_mphy_pll",
191 "sclk_mfc_pll",
192 "sclk_bus_pll";
193 clocks = <&xxti>,
194 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
195 <&cmu_mif CLK_SCLK_MFC_PLL>,
196 <&cmu_mif CLK_SCLK_BUS_PLL>;
197 };
198
199 cmu_cpif: clock-controller@10fc0000 {
200 compatible = "samsung,exynos5433-cmu-cpif";
201 reg = <0x10fc0000 0x0c04>;
202 #clock-cells = <1>;
203
204 clock-names = "oscclk";
205 clocks = <&xxti>;
206 };
207
208 cmu_mif: clock-controller@105b0000 {
209 compatible = "samsung,exynos5433-cmu-mif";
210 reg = <0x105b0000 0x100c>;
211 #clock-cells = <1>;
212
213 clock-names = "oscclk",
214 "sclk_mphy_pll";
215 clocks = <&xxti>,
216 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
217 };
218
219 cmu_peric: clock-controller@14c80000 {
220 compatible = "samsung,exynos5433-cmu-peric";
221 reg = <0x14c80000 0x0b08>;
222 #clock-cells = <1>;
223 };
224
225 cmu_peris: clock-controller@10040000 {
226 compatible = "samsung,exynos5433-cmu-peris";
227 reg = <0x10040000 0x0b20>;
228 #clock-cells = <1>;
229 };
230
231 cmu_fsys: clock-controller@156e0000 {
232 compatible = "samsung,exynos5433-cmu-fsys";
233 reg = <0x156e0000 0x0b04>;
234 #clock-cells = <1>;
235
236 clock-names = "oscclk",
237 "sclk_ufs_mphy",
238 "div_aclk_fsys_200",
239 "sclk_pcie_100_fsys",
240 "sclk_ufsunipro_fsys",
241 "sclk_mmc2_fsys",
242 "sclk_mmc1_fsys",
243 "sclk_mmc0_fsys",
244 "sclk_usbhost30_fsys",
245 "sclk_usbdrd30_fsys";
246 clocks = <&xxti>,
247 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
248 <&cmu_top CLK_DIV_ACLK_FSYS_200>,
249 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
250 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
251 <&cmu_top CLK_SCLK_MMC2_FSYS>,
252 <&cmu_top CLK_SCLK_MMC1_FSYS>,
253 <&cmu_top CLK_SCLK_MMC0_FSYS>,
254 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
255 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
256 };
257
258 cmu_g2d: clock-controller@12460000 {
259 compatible = "samsung,exynos5433-cmu-g2d";
260 reg = <0x12460000 0x0b08>;
261 #clock-cells = <1>;
262
263 clock-names = "oscclk",
264 "aclk_g2d_266",
265 "aclk_g2d_400";
266 clocks = <&xxti>,
267 <&cmu_top CLK_ACLK_G2D_266>,
268 <&cmu_top CLK_ACLK_G2D_400>;
269 };
270
271 cmu_disp: clock-controller@13b90000 {
272 compatible = "samsung,exynos5433-cmu-disp";
273 reg = <0x13b90000 0x0c04>;
274 #clock-cells = <1>;
275
276 clock-names = "oscclk",
277 "sclk_dsim1_disp",
278 "sclk_dsim0_disp",
279 "sclk_dsd_disp",
280 "sclk_decon_tv_eclk_disp",
281 "sclk_decon_vclk_disp",
282 "sclk_decon_eclk_disp",
283 "sclk_decon_tv_vclk_disp",
284 "aclk_disp_333";
285 clocks = <&xxti>,
286 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
287 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
288 <&cmu_mif CLK_SCLK_DSD_DISP>,
289 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
290 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
291 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
292 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
293 <&cmu_mif CLK_ACLK_DISP_333>;
294 };
295
296 cmu_aud: clock-controller@114c0000 {
297 compatible = "samsung,exynos5433-cmu-aud";
298 reg = <0x114c0000 0x0b04>;
299 #clock-cells = <1>;
300 };
301
302 cmu_bus0: clock-controller@13600000 {
303 compatible = "samsung,exynos5433-cmu-bus0";
304 reg = <0x13600000 0x0b04>;
305 #clock-cells = <1>;
306
307 clock-names = "aclk_bus0_400";
308 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
309 };
310
311 cmu_bus1: clock-controller@14800000 {
312 compatible = "samsung,exynos5433-cmu-bus1";
313 reg = <0x14800000 0x0b04>;
314 #clock-cells = <1>;
315
316 clock-names = "aclk_bus1_400";
317 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
318 };
319
320 cmu_bus2: clock-controller@13400000 {
321 compatible = "samsung,exynos5433-cmu-bus2";
322 reg = <0x13400000 0x0b04>;
323 #clock-cells = <1>;
324
325 clock-names = "oscclk", "aclk_bus2_400";
326 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
327 };
328
329 cmu_g3d: clock-controller@14aa0000 {
330 compatible = "samsung,exynos5433-cmu-g3d";
331 reg = <0x14aa0000 0x1000>;
332 #clock-cells = <1>;
333
334 clock-names = "oscclk", "aclk_g3d_400";
335 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
336 };
337
338 cmu_gscl: clock-controller@13cf0000 {
339 compatible = "samsung,exynos5433-cmu-gscl";
340 reg = <0x13cf0000 0x0b10>;
341 #clock-cells = <1>;
342
343 clock-names = "oscclk",
344 "aclk_gscl_111",
345 "aclk_gscl_333";
346 clocks = <&xxti>,
347 <&cmu_top CLK_ACLK_GSCL_111>,
348 <&cmu_top CLK_ACLK_GSCL_333>;
349 };
350
351 cmu_apollo: clock-controller@11900000 {
352 compatible = "samsung,exynos5433-cmu-apollo";
353 reg = <0x11900000 0x1088>;
354 #clock-cells = <1>;
355
356 clock-names = "oscclk", "sclk_bus_pll_apollo";
357 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
358 };
359
360 cmu_atlas: clock-controller@11800000 {
361 compatible = "samsung,exynos5433-cmu-atlas";
362 reg = <0x11800000 0x1088>;
363 #clock-cells = <1>;
364
365 clock-names = "oscclk", "sclk_bus_pll_atlas";
366 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
367 };
368
369 cmu_mscl: clock-controller@105d0000 {
370 compatible = "samsung,exynos5433-cmu-mscl";
371 reg = <0x105d0000 0x0b10>;
372 #clock-cells = <1>;
373
374 clock-names = "oscclk",
375 "sclk_jpeg_mscl",
376 "aclk_mscl_400";
377 clocks = <&xxti>,
378 <&cmu_top CLK_SCLK_JPEG_MSCL>,
379 <&cmu_top CLK_ACLK_MSCL_400>;
380 };
381
382 cmu_mfc: clock-controller@15280000 {
383 compatible = "samsung,exynos5433-cmu-mfc";
384 reg = <0x15280000 0x0b08>;
385 #clock-cells = <1>;
386
387 clock-names = "oscclk", "aclk_mfc_400";
388 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
389 };
390
391 cmu_hevc: clock-controller@14f80000 {
392 compatible = "samsung,exynos5433-cmu-hevc";
393 reg = <0x14f80000 0x0b08>;
394 #clock-cells = <1>;
395
396 clock-names = "oscclk", "aclk_hevc_400";
397 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
398 };
399
400 cmu_isp: clock-controller@146d0000 {
401 compatible = "samsung,exynos5433-cmu-isp";
402 reg = <0x146d0000 0x0b0c>;
403 #clock-cells = <1>;
404
405 clock-names = "oscclk",
406 "aclk_isp_dis_400",
407 "aclk_isp_400";
408 clocks = <&xxti>,
409 <&cmu_top CLK_ACLK_ISP_DIS_400>,
410 <&cmu_top CLK_ACLK_ISP_400>;
411 };
412
413 cmu_cam0: clock-controller@120d0000 {
414 compatible = "samsung,exynos5433-cmu-cam0";
415 reg = <0x120d0000 0x0b0c>;
416 #clock-cells = <1>;
417
418 clock-names = "oscclk",
419 "aclk_cam0_333",
420 "aclk_cam0_400",
421 "aclk_cam0_552";
422 clocks = <&xxti>,
423 <&cmu_top CLK_ACLK_CAM0_333>,
424 <&cmu_top CLK_ACLK_CAM0_400>,
425 <&cmu_top CLK_ACLK_CAM0_552>;
426 };
427
428 cmu_cam1: clock-controller@145d0000 {
429 compatible = "samsung,exynos5433-cmu-cam1";
430 reg = <0x145d0000 0x0b08>;
431 #clock-cells = <1>;
432
433 clock-names = "oscclk",
434 "sclk_isp_uart_cam1",
435 "sclk_isp_spi1_cam1",
436 "sclk_isp_spi0_cam1",
437 "aclk_cam1_333",
438 "aclk_cam1_400",
439 "aclk_cam1_552";
440 clocks = <&xxti>,
441 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
442 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
443 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
444 <&cmu_top CLK_ACLK_CAM1_333>,
445 <&cmu_top CLK_ACLK_CAM1_400>,
446 <&cmu_top CLK_ACLK_CAM1_552>;
447 };
448
449Example 3: UART controller node that consumes the clock generated by the clock
450 controller.
451
452 serial_0: serial@14C10000 {
453 compatible = "samsung,exynos5433-uart";
454 reg = <0x14C10000 0x100>;
455 interrupts = <0 421 0>;
456 clocks = <&cmu_peric CLK_PCLK_UART0>,
457 <&cmu_peric CLK_SCLK_UART0>;
458 clock-names = "uart", "clk_uart_baud0";
459 pinctrl-names = "default";
460 pinctrl-0 = <&uart0_bus>;
461 status = "disabled";
462 };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 006c6f294310..17e9af7fe81f 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
10obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o 10obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
11obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o 11obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
12obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 12obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
13obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o
13obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 14obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
14obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 15obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
15obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o 16obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
index 3a7cb2506731..1eb16b868421 100644
--- a/drivers/clk/samsung/clk-exynos-clkout.c
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -151,3 +151,5 @@ CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
151 exynos5_clkout_init); 151 exynos5_clkout_init);
152CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu", 152CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
153 exynos5_clkout_init); 153 exynos5_clkout_init);
154CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu",
155 exynos5_clkout_init);
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
new file mode 100644
index 000000000000..387e3e39e635
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -0,0 +1,5423 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5443 SoC.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16
17#include <dt-bindings/clock/exynos5433.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22/*
23 * Register offset definitions for CMU_TOP
24 */
25#define ISP_PLL_LOCK 0x0000
26#define AUD_PLL_LOCK 0x0004
27#define ISP_PLL_CON0 0x0100
28#define ISP_PLL_CON1 0x0104
29#define ISP_PLL_FREQ_DET 0x0108
30#define AUD_PLL_CON0 0x0110
31#define AUD_PLL_CON1 0x0114
32#define AUD_PLL_CON2 0x0118
33#define AUD_PLL_FREQ_DET 0x011c
34#define MUX_SEL_TOP0 0x0200
35#define MUX_SEL_TOP1 0x0204
36#define MUX_SEL_TOP2 0x0208
37#define MUX_SEL_TOP3 0x020c
38#define MUX_SEL_TOP4 0x0210
39#define MUX_SEL_TOP_MSCL 0x0220
40#define MUX_SEL_TOP_CAM1 0x0224
41#define MUX_SEL_TOP_DISP 0x0228
42#define MUX_SEL_TOP_FSYS0 0x0230
43#define MUX_SEL_TOP_FSYS1 0x0234
44#define MUX_SEL_TOP_PERIC0 0x0238
45#define MUX_SEL_TOP_PERIC1 0x023c
46#define MUX_ENABLE_TOP0 0x0300
47#define MUX_ENABLE_TOP1 0x0304
48#define MUX_ENABLE_TOP2 0x0308
49#define MUX_ENABLE_TOP3 0x030c
50#define MUX_ENABLE_TOP4 0x0310
51#define MUX_ENABLE_TOP_MSCL 0x0320
52#define MUX_ENABLE_TOP_CAM1 0x0324
53#define MUX_ENABLE_TOP_DISP 0x0328
54#define MUX_ENABLE_TOP_FSYS0 0x0330
55#define MUX_ENABLE_TOP_FSYS1 0x0334
56#define MUX_ENABLE_TOP_PERIC0 0x0338
57#define MUX_ENABLE_TOP_PERIC1 0x033c
58#define MUX_STAT_TOP0 0x0400
59#define MUX_STAT_TOP1 0x0404
60#define MUX_STAT_TOP2 0x0408
61#define MUX_STAT_TOP3 0x040c
62#define MUX_STAT_TOP4 0x0410
63#define MUX_STAT_TOP_MSCL 0x0420
64#define MUX_STAT_TOP_CAM1 0x0424
65#define MUX_STAT_TOP_FSYS0 0x0430
66#define MUX_STAT_TOP_FSYS1 0x0434
67#define MUX_STAT_TOP_PERIC0 0x0438
68#define MUX_STAT_TOP_PERIC1 0x043c
69#define DIV_TOP0 0x0600
70#define DIV_TOP1 0x0604
71#define DIV_TOP2 0x0608
72#define DIV_TOP3 0x060c
73#define DIV_TOP4 0x0610
74#define DIV_TOP_MSCL 0x0618
75#define DIV_TOP_CAM10 0x061c
76#define DIV_TOP_CAM11 0x0620
77#define DIV_TOP_FSYS0 0x062c
78#define DIV_TOP_FSYS1 0x0630
79#define DIV_TOP_FSYS2 0x0634
80#define DIV_TOP_PERIC0 0x0638
81#define DIV_TOP_PERIC1 0x063c
82#define DIV_TOP_PERIC2 0x0640
83#define DIV_TOP_PERIC3 0x0644
84#define DIV_TOP_PERIC4 0x0648
85#define DIV_TOP_PLL_FREQ_DET 0x064c
86#define DIV_STAT_TOP0 0x0700
87#define DIV_STAT_TOP1 0x0704
88#define DIV_STAT_TOP2 0x0708
89#define DIV_STAT_TOP3 0x070c
90#define DIV_STAT_TOP4 0x0710
91#define DIV_STAT_TOP_MSCL 0x0718
92#define DIV_STAT_TOP_CAM10 0x071c
93#define DIV_STAT_TOP_CAM11 0x0720
94#define DIV_STAT_TOP_FSYS0 0x072c
95#define DIV_STAT_TOP_FSYS1 0x0730
96#define DIV_STAT_TOP_FSYS2 0x0734
97#define DIV_STAT_TOP_PERIC0 0x0738
98#define DIV_STAT_TOP_PERIC1 0x073c
99#define DIV_STAT_TOP_PERIC2 0x0740
100#define DIV_STAT_TOP_PERIC3 0x0744
101#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
102#define ENABLE_ACLK_TOP 0x0800
103#define ENABLE_SCLK_TOP 0x0a00
104#define ENABLE_SCLK_TOP_MSCL 0x0a04
105#define ENABLE_SCLK_TOP_CAM1 0x0a08
106#define ENABLE_SCLK_TOP_DISP 0x0a0c
107#define ENABLE_SCLK_TOP_FSYS 0x0a10
108#define ENABLE_SCLK_TOP_PERIC 0x0a14
109#define ENABLE_IP_TOP 0x0b00
110#define ENABLE_CMU_TOP 0x0c00
111#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
112
113static unsigned long top_clk_regs[] __initdata = {
114 ISP_PLL_LOCK,
115 AUD_PLL_LOCK,
116 ISP_PLL_CON0,
117 ISP_PLL_CON1,
118 ISP_PLL_FREQ_DET,
119 AUD_PLL_CON0,
120 AUD_PLL_CON1,
121 AUD_PLL_CON2,
122 AUD_PLL_FREQ_DET,
123 MUX_SEL_TOP0,
124 MUX_SEL_TOP1,
125 MUX_SEL_TOP2,
126 MUX_SEL_TOP3,
127 MUX_SEL_TOP4,
128 MUX_SEL_TOP_MSCL,
129 MUX_SEL_TOP_CAM1,
130 MUX_SEL_TOP_DISP,
131 MUX_SEL_TOP_FSYS0,
132 MUX_SEL_TOP_FSYS1,
133 MUX_SEL_TOP_PERIC0,
134 MUX_SEL_TOP_PERIC1,
135 MUX_ENABLE_TOP0,
136 MUX_ENABLE_TOP1,
137 MUX_ENABLE_TOP2,
138 MUX_ENABLE_TOP3,
139 MUX_ENABLE_TOP4,
140 MUX_ENABLE_TOP_MSCL,
141 MUX_ENABLE_TOP_CAM1,
142 MUX_ENABLE_TOP_DISP,
143 MUX_ENABLE_TOP_FSYS0,
144 MUX_ENABLE_TOP_FSYS1,
145 MUX_ENABLE_TOP_PERIC0,
146 MUX_ENABLE_TOP_PERIC1,
147 MUX_STAT_TOP0,
148 MUX_STAT_TOP1,
149 MUX_STAT_TOP2,
150 MUX_STAT_TOP3,
151 MUX_STAT_TOP4,
152 MUX_STAT_TOP_MSCL,
153 MUX_STAT_TOP_CAM1,
154 MUX_STAT_TOP_FSYS0,
155 MUX_STAT_TOP_FSYS1,
156 MUX_STAT_TOP_PERIC0,
157 MUX_STAT_TOP_PERIC1,
158 DIV_TOP0,
159 DIV_TOP1,
160 DIV_TOP2,
161 DIV_TOP3,
162 DIV_TOP4,
163 DIV_TOP_MSCL,
164 DIV_TOP_CAM10,
165 DIV_TOP_CAM11,
166 DIV_TOP_FSYS0,
167 DIV_TOP_FSYS1,
168 DIV_TOP_FSYS2,
169 DIV_TOP_PERIC0,
170 DIV_TOP_PERIC1,
171 DIV_TOP_PERIC2,
172 DIV_TOP_PERIC3,
173 DIV_TOP_PERIC4,
174 DIV_TOP_PLL_FREQ_DET,
175 DIV_STAT_TOP0,
176 DIV_STAT_TOP1,
177 DIV_STAT_TOP2,
178 DIV_STAT_TOP3,
179 DIV_STAT_TOP4,
180 DIV_STAT_TOP_MSCL,
181 DIV_STAT_TOP_CAM10,
182 DIV_STAT_TOP_CAM11,
183 DIV_STAT_TOP_FSYS0,
184 DIV_STAT_TOP_FSYS1,
185 DIV_STAT_TOP_FSYS2,
186 DIV_STAT_TOP_PERIC0,
187 DIV_STAT_TOP_PERIC1,
188 DIV_STAT_TOP_PERIC2,
189 DIV_STAT_TOP_PERIC3,
190 DIV_STAT_TOP_PLL_FREQ_DET,
191 ENABLE_ACLK_TOP,
192 ENABLE_SCLK_TOP,
193 ENABLE_SCLK_TOP_MSCL,
194 ENABLE_SCLK_TOP_CAM1,
195 ENABLE_SCLK_TOP_DISP,
196 ENABLE_SCLK_TOP_FSYS,
197 ENABLE_SCLK_TOP_PERIC,
198 ENABLE_IP_TOP,
199 ENABLE_CMU_TOP,
200 ENABLE_CMU_TOP_DIV_STAT,
201};
202
203/* list of all parent clock list */
204PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
205PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
206PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
207PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
208PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
209PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
210PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
211PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
212
213PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
214PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
215PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
216 "mout_mfc_pll_user", };
217PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
218
219PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
220 "mout_mphy_pll_user", };
221PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
222 "mout_bus_pll_user", };
223PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
224
225PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
226 "mout_mphy_pll_user", };
227PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
228 "mout_mphy_pll_user", };
229PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
230 "mout_mphy_pll_user", };
231
232PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
233PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
234
235PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
236PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
237PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
238PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
239PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
240
241PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
247
248PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
249
250static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
251 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
252};
253
254static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
255 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
256 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
257 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
258 /* Xi2s1SDI input clock for SPDIF */
259 FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
260 /* XspiCLK[4:0] input clock for SPI */
261 FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
262 FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
263 FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
264 FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
265 FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
266 /* Xi2s1SCLK input clock for I2S1_BCLK */
267 FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
268};
269
270static struct samsung_mux_clock top_mux_clks[] __initdata = {
271 /* MUX_SEL_TOP0 */
272 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
273 4, 1),
274 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
275 0, 1),
276
277 /* MUX_SEL_TOP1 */
278 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
279 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
280 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
281 MUX_SEL_TOP1, 8, 1),
282 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
283 MUX_SEL_TOP1, 4, 1),
284 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
285 MUX_SEL_TOP1, 0, 1),
286
287 /* MUX_SEL_TOP2 */
288 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
289 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
290 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
291 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
292 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
293 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
294 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
295 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
296 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
297 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
298 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
299 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
300
301 /* MUX_SEL_TOP3 */
302 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
303 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
304 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
305 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
306 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
307 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
308 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
309 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
310 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
311 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
312 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
313 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
314
315 /* MUX_SEL_TOP4 */
316 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
317 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
318 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
319 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
320 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
321 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
322
323 /* MUX_SEL_TOP_MSCL */
324 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
325 MUX_SEL_TOP_MSCL, 8, 1),
326 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
327 MUX_SEL_TOP_MSCL, 4, 1),
328 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
329 MUX_SEL_TOP_MSCL, 0, 1),
330
331 /* MUX_SEL_TOP_CAM1 */
332 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
333 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
334 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
335 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
336 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
337 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
338 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
339 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
340 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
341 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
342 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
343 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
344
345 /* MUX_SEL_TOP_FSYS0 */
346 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
347 MUX_SEL_TOP_FSYS0, 28, 1),
348 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
349 MUX_SEL_TOP_FSYS0, 24, 1),
350 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
351 MUX_SEL_TOP_FSYS0, 20, 1),
352 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
353 MUX_SEL_TOP_FSYS0, 16, 1),
354 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
355 MUX_SEL_TOP_FSYS0, 12, 1),
356 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
357 MUX_SEL_TOP_FSYS0, 8, 1),
358 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
359 MUX_SEL_TOP_FSYS0, 4, 1),
360 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
361 MUX_SEL_TOP_FSYS0, 0, 1),
362
363 /* MUX_SEL_TOP_FSYS1 */
364 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
365 MUX_SEL_TOP_FSYS1, 12, 1),
366 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
367 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
368 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
369 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
370 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
371 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
372
373 /* MUX_SEL_TOP_PERIC0 */
374 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
375 MUX_SEL_TOP_PERIC0, 28, 1),
376 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
377 MUX_SEL_TOP_PERIC0, 24, 1),
378 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
379 MUX_SEL_TOP_PERIC0, 20, 1),
380 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
381 MUX_SEL_TOP_PERIC0, 16, 1),
382 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
383 MUX_SEL_TOP_PERIC0, 12, 1),
384 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
385 MUX_SEL_TOP_PERIC0, 8, 1),
386 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
387 MUX_SEL_TOP_PERIC0, 4, 1),
388 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
389 MUX_SEL_TOP_PERIC0, 0, 1),
390
391 /* MUX_SEL_TOP_PERIC1 */
392 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
393 MUX_SEL_TOP_PERIC1, 16, 1),
394 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
395 MUX_SEL_TOP_PERIC1, 12, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
397 MUX_SEL_TOP_PERIC1, 4, 2),
398 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
399 MUX_SEL_TOP_PERIC1, 0, 2),
400
401 /* MUX_SEL_TOP_DISP */
402 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
403 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
404};
405
406static struct samsung_div_clock top_div_clks[] __initdata = {
407 /* DIV_TOP0 */
408 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
409 DIV_TOP0, 28, 3),
410 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
411 DIV_TOP0, 24, 3),
412 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
413 DIV_TOP0, 20, 3),
414 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
415 DIV_TOP0, 16, 3),
416 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
417 DIV_TOP0, 12, 3),
418 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
419 DIV_TOP0, 8, 3),
420 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
421 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
422 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
423 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
424
425 /* DIV_TOP1 */
426 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
427 DIV_TOP1, 28, 3),
428 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
429 DIV_TOP1, 24, 3),
430 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
431 DIV_TOP1, 20, 3),
432 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
433 DIV_TOP1, 12, 3),
434 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
435 DIV_TOP1, 8, 3),
436 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
437 DIV_TOP1, 0, 3),
438
439 /* DIV_TOP2 */
440 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
441 DIV_TOP2, 4, 3),
442 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
443 DIV_TOP2, 0, 3),
444
445 /* DIV_TOP3 */
446 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
447 "mout_bus_pll_user", DIV_TOP3, 24, 3),
448 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
449 "mout_bus_pll_user", DIV_TOP3, 20, 3),
450 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
451 "mout_bus_pll_user", DIV_TOP3, 16, 3),
452 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
453 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
454 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
455 "mout_bus_pll_user", DIV_TOP3, 8, 3),
456 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
457 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
458 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
459 "mout_bus_pll_user", DIV_TOP3, 0, 3),
460
461 /* DIV_TOP4 */
462 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
463 DIV_TOP4, 8, 3),
464 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
465 DIV_TOP4, 4, 3),
466 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
467 DIV_TOP4, 0, 3),
468
469 /* DIV_TOP_MSCL */
470 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
471 DIV_TOP_MSCL, 0, 4),
472
473 /* DIV_TOP_CAM10 */
474 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
475 DIV_TOP_CAM10, 24, 5),
476 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
477 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
478 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
479 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
480 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
481 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
482 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
483 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
484
485 /* DIV_TOP_CAM11 */
486 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
487 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
488 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
489 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
490 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
491 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
492 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
493 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
494 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
495 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 12, 4),
496 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
497 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 8, 4),
498
499 /* DIV_TOP_FSYS0 */
500 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
501 DIV_TOP_FSYS0, 16, 8),
502 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
503 DIV_TOP_FSYS0, 12, 4),
504 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
505 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
506 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
507 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
508
509 /* DIV_TOP_FSYS1 */
510 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
511 DIV_TOP_FSYS1, 4, 8),
512 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
513 DIV_TOP_FSYS1, 0, 4),
514
515 /* DIV_TOP_FSYS2 */
516 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
517 DIV_TOP_FSYS2, 12, 3),
518 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
519 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
520 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
521 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
522 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
523 DIV_TOP_FSYS2, 0, 4),
524
525 /* DIV_TOP_PERIC0 */
526 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
527 DIV_TOP_PERIC0, 16, 8),
528 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
529 DIV_TOP_PERIC0, 12, 4),
530 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
531 DIV_TOP_PERIC0, 4, 8),
532 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
533 DIV_TOP_PERIC0, 0, 4),
534
535 /* DIV_TOP_PERIC1 */
536 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
537 DIV_TOP_PERIC1, 4, 8),
538 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
539 DIV_TOP_PERIC1, 0, 4),
540
541 /* DIV_TOP_PERIC2 */
542 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
543 DIV_TOP_PERIC2, 8, 4),
544 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
545 DIV_TOP_PERIC2, 4, 4),
546 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
547 DIV_TOP_PERIC2, 0, 4),
548
549 /* DIV_TOP_PERIC3 */
550 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
551 DIV_TOP_PERIC3, 16, 6),
552 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
553 DIV_TOP_PERIC3, 8, 8),
554 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
555 DIV_TOP_PERIC3, 4, 4),
556 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
557 DIV_TOP_PERIC3, 0, 4),
558
559 /* DIV_TOP_PERIC4 */
560 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
561 DIV_TOP_PERIC4, 16, 8),
562 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
563 DIV_TOP_PERIC4, 12, 4),
564 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
565 DIV_TOP_PERIC4, 4, 8),
566 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
567 DIV_TOP_PERIC4, 0, 4),
568};
569
570static struct samsung_gate_clock top_gate_clks[] __initdata = {
571 /* ENABLE_ACLK_TOP */
572 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
573 ENABLE_ACLK_TOP, 30, 0, 0),
574 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
575 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
576 29, CLK_IGNORE_UNUSED, 0),
577 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
578 ENABLE_ACLK_TOP, 26,
579 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
580 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
581 ENABLE_ACLK_TOP, 25,
582 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
583 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
584 ENABLE_ACLK_TOP, 24,
585 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
586 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
587 ENABLE_ACLK_TOP, 23,
588 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
589 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
590 ENABLE_ACLK_TOP, 22,
591 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
592 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
593 ENABLE_ACLK_TOP, 21,
594 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
595 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
596 ENABLE_ACLK_TOP, 19,
597 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
598 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
599 ENABLE_ACLK_TOP, 18,
600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
601 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
602 ENABLE_ACLK_TOP, 15,
603 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
604 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
605 ENABLE_ACLK_TOP, 14,
606 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
607 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
608 ENABLE_ACLK_TOP, 13,
609 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
610 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
611 ENABLE_ACLK_TOP, 12,
612 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
613 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
614 ENABLE_ACLK_TOP, 11,
615 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
616 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
617 ENABLE_ACLK_TOP, 10,
618 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
619 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
620 ENABLE_ACLK_TOP, 9,
621 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
622 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
623 ENABLE_ACLK_TOP, 8,
624 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
625 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
626 ENABLE_ACLK_TOP, 7,
627 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
628 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
629 ENABLE_ACLK_TOP, 6,
630 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
631 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
632 ENABLE_ACLK_TOP, 5,
633 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
634 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
635 ENABLE_ACLK_TOP, 3,
636 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
637 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
638 ENABLE_ACLK_TOP, 2,
639 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
640 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
641 ENABLE_ACLK_TOP, 0,
642 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
643
644 /* ENABLE_SCLK_TOP_MSCL */
645 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
646 ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
647
648 /* ENABLE_SCLK_TOP_CAM1 */
649 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
650 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
651 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
652 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
653 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
654 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
655 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
656 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
657 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
658 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
659 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
660 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
661 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
662 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
663
664 /* ENABLE_SCLK_TOP_DISP */
665 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
666 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
667 CLK_IGNORE_UNUSED, 0),
668
669 /* ENABLE_SCLK_TOP_FSYS */
670 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
671 ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
672 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
673 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
674 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
675 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
676 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
677 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
678 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
679 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
680 3, CLK_SET_RATE_PARENT, 0),
681 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
682 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
683 1, CLK_SET_RATE_PARENT, 0),
684 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
685 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
686 0, CLK_SET_RATE_PARENT, 0),
687
688 /* ENABLE_SCLK_TOP_PERIC */
689 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
690 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
691 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
692 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
693 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
694 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
695 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
696 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
697 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
698 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
699 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
700 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
701 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
702 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
703 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
704 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
705 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
706 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
707 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
708 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
709 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
710 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
711
712 /* MUX_ENABLE_TOP_PERIC1 */
713 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
714 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
715 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
716 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
717 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
718 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
719};
720
721/*
722 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
723 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
724 */
725static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
726 PLL_35XX_RATE(2500000000U, 625, 6, 0),
727 PLL_35XX_RATE(2400000000U, 500, 5, 0),
728 PLL_35XX_RATE(2300000000U, 575, 6, 0),
729 PLL_35XX_RATE(2200000000U, 550, 6, 0),
730 PLL_35XX_RATE(2100000000U, 350, 4, 0),
731 PLL_35XX_RATE(2000000000U, 500, 6, 0),
732 PLL_35XX_RATE(1900000000U, 475, 6, 0),
733 PLL_35XX_RATE(1800000000U, 375, 5, 0),
734 PLL_35XX_RATE(1700000000U, 425, 6, 0),
735 PLL_35XX_RATE(1600000000U, 400, 6, 0),
736 PLL_35XX_RATE(1500000000U, 250, 4, 0),
737 PLL_35XX_RATE(1400000000U, 350, 6, 0),
738 PLL_35XX_RATE(1332000000U, 222, 4, 0),
739 PLL_35XX_RATE(1300000000U, 325, 6, 0),
740 PLL_35XX_RATE(1200000000U, 500, 5, 1),
741 PLL_35XX_RATE(1100000000U, 550, 6, 1),
742 PLL_35XX_RATE(1086000000U, 362, 4, 1),
743 PLL_35XX_RATE(1066000000U, 533, 6, 1),
744 PLL_35XX_RATE(1000000000U, 500, 6, 1),
745 PLL_35XX_RATE(933000000U, 311, 4, 1),
746 PLL_35XX_RATE(921000000U, 307, 4, 1),
747 PLL_35XX_RATE(900000000U, 375, 5, 1),
748 PLL_35XX_RATE(825000000U, 275, 4, 1),
749 PLL_35XX_RATE(800000000U, 400, 6, 1),
750 PLL_35XX_RATE(733000000U, 733, 12, 1),
751 PLL_35XX_RATE(700000000U, 360, 6, 1),
752 PLL_35XX_RATE(667000000U, 222, 4, 1),
753 PLL_35XX_RATE(633000000U, 211, 4, 1),
754 PLL_35XX_RATE(600000000U, 500, 5, 2),
755 PLL_35XX_RATE(552000000U, 460, 5, 2),
756 PLL_35XX_RATE(550000000U, 550, 6, 2),
757 PLL_35XX_RATE(543000000U, 362, 4, 2),
758 PLL_35XX_RATE(533000000U, 533, 6, 2),
759 PLL_35XX_RATE(500000000U, 500, 6, 2),
760 PLL_35XX_RATE(444000000U, 370, 5, 2),
761 PLL_35XX_RATE(420000000U, 350, 5, 2),
762 PLL_35XX_RATE(400000000U, 400, 6, 2),
763 PLL_35XX_RATE(350000000U, 360, 6, 2),
764 PLL_35XX_RATE(333000000U, 222, 4, 2),
765 PLL_35XX_RATE(300000000U, 500, 5, 3),
766 PLL_35XX_RATE(266000000U, 532, 6, 3),
767 PLL_35XX_RATE(200000000U, 400, 6, 3),
768 PLL_35XX_RATE(166000000U, 332, 6, 3),
769 PLL_35XX_RATE(160000000U, 320, 6, 3),
770 PLL_35XX_RATE(133000000U, 552, 6, 4),
771 PLL_35XX_RATE(100000000U, 400, 6, 4),
772 { /* sentinel */ }
773};
774
775/* AUD_PLL */
776static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
777 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
778 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
779 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
780 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
781 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
782 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
783 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
784 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
785 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
786 { /* sentinel */ }
787};
788
789static struct samsung_pll_clock top_pll_clks[] __initdata = {
790 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
791 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
792 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
793 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
794};
795
796static struct samsung_cmu_info top_cmu_info __initdata = {
797 .pll_clks = top_pll_clks,
798 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
799 .mux_clks = top_mux_clks,
800 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
801 .div_clks = top_div_clks,
802 .nr_div_clks = ARRAY_SIZE(top_div_clks),
803 .gate_clks = top_gate_clks,
804 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
805 .fixed_clks = top_fixed_clks,
806 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
807 .fixed_factor_clks = top_fixed_factor_clks,
808 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
809 .nr_clk_ids = TOP_NR_CLK,
810 .clk_regs = top_clk_regs,
811 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
812};
813
814static void __init exynos5433_cmu_top_init(struct device_node *np)
815{
816 samsung_cmu_register_one(np, &top_cmu_info);
817}
818CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
819 exynos5433_cmu_top_init);
820
821/*
822 * Register offset definitions for CMU_CPIF
823 */
824#define MPHY_PLL_LOCK 0x0000
825#define MPHY_PLL_CON0 0x0100
826#define MPHY_PLL_CON1 0x0104
827#define MPHY_PLL_FREQ_DET 0x010c
828#define MUX_SEL_CPIF0 0x0200
829#define DIV_CPIF 0x0600
830#define ENABLE_SCLK_CPIF 0x0a00
831
832static unsigned long cpif_clk_regs[] __initdata = {
833 MPHY_PLL_LOCK,
834 MPHY_PLL_CON0,
835 MPHY_PLL_CON1,
836 MPHY_PLL_FREQ_DET,
837 MUX_SEL_CPIF0,
838 ENABLE_SCLK_CPIF,
839};
840
841/* list of all parent clock list */
842PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
843
844static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
845 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
846 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
847};
848
849static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
850 /* MUX_SEL_CPIF0 */
851 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
852 0, 1),
853};
854
855static struct samsung_div_clock cpif_div_clks[] __initdata = {
856 /* DIV_CPIF */
857 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
858 0, 6),
859};
860
861static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
862 /* ENABLE_SCLK_CPIF */
863 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
864 ENABLE_SCLK_CPIF, 9, 0, 0),
865 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
866 ENABLE_SCLK_CPIF, 4, 0, 0),
867};
868
869static struct samsung_cmu_info cpif_cmu_info __initdata = {
870 .pll_clks = cpif_pll_clks,
871 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
872 .mux_clks = cpif_mux_clks,
873 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
874 .div_clks = cpif_div_clks,
875 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
876 .gate_clks = cpif_gate_clks,
877 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
878 .nr_clk_ids = CPIF_NR_CLK,
879 .clk_regs = cpif_clk_regs,
880 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
881};
882
883static void __init exynos5433_cmu_cpif_init(struct device_node *np)
884{
885 samsung_cmu_register_one(np, &cpif_cmu_info);
886}
887CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
888 exynos5433_cmu_cpif_init);
889
890/*
891 * Register offset definitions for CMU_MIF
892 */
893#define MEM0_PLL_LOCK 0x0000
894#define MEM1_PLL_LOCK 0x0004
895#define BUS_PLL_LOCK 0x0008
896#define MFC_PLL_LOCK 0x000c
897#define MEM0_PLL_CON0 0x0100
898#define MEM0_PLL_CON1 0x0104
899#define MEM0_PLL_FREQ_DET 0x010c
900#define MEM1_PLL_CON0 0x0110
901#define MEM1_PLL_CON1 0x0114
902#define MEM1_PLL_FREQ_DET 0x011c
903#define BUS_PLL_CON0 0x0120
904#define BUS_PLL_CON1 0x0124
905#define BUS_PLL_FREQ_DET 0x012c
906#define MFC_PLL_CON0 0x0130
907#define MFC_PLL_CON1 0x0134
908#define MFC_PLL_FREQ_DET 0x013c
909#define MUX_SEL_MIF0 0x0200
910#define MUX_SEL_MIF1 0x0204
911#define MUX_SEL_MIF2 0x0208
912#define MUX_SEL_MIF3 0x020c
913#define MUX_SEL_MIF4 0x0210
914#define MUX_SEL_MIF5 0x0214
915#define MUX_SEL_MIF6 0x0218
916#define MUX_SEL_MIF7 0x021c
917#define MUX_ENABLE_MIF0 0x0300
918#define MUX_ENABLE_MIF1 0x0304
919#define MUX_ENABLE_MIF2 0x0308
920#define MUX_ENABLE_MIF3 0x030c
921#define MUX_ENABLE_MIF4 0x0310
922#define MUX_ENABLE_MIF5 0x0314
923#define MUX_ENABLE_MIF6 0x0318
924#define MUX_ENABLE_MIF7 0x031c
925#define MUX_STAT_MIF0 0x0400
926#define MUX_STAT_MIF1 0x0404
927#define MUX_STAT_MIF2 0x0408
928#define MUX_STAT_MIF3 0x040c
929#define MUX_STAT_MIF4 0x0410
930#define MUX_STAT_MIF5 0x0414
931#define MUX_STAT_MIF6 0x0418
932#define MUX_STAT_MIF7 0x041c
933#define DIV_MIF1 0x0604
934#define DIV_MIF2 0x0608
935#define DIV_MIF3 0x060c
936#define DIV_MIF4 0x0610
937#define DIV_MIF5 0x0614
938#define DIV_MIF_PLL_FREQ_DET 0x0618
939#define DIV_STAT_MIF1 0x0704
940#define DIV_STAT_MIF2 0x0708
941#define DIV_STAT_MIF3 0x070c
942#define DIV_STAT_MIF4 0x0710
943#define DIV_STAT_MIF5 0x0714
944#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
945#define ENABLE_ACLK_MIF0 0x0800
946#define ENABLE_ACLK_MIF1 0x0804
947#define ENABLE_ACLK_MIF2 0x0808
948#define ENABLE_ACLK_MIF3 0x080c
949#define ENABLE_PCLK_MIF 0x0900
950#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
951#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
952#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
953#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
954#define ENABLE_SCLK_MIF 0x0a00
955#define ENABLE_IP_MIF0 0x0b00
956#define ENABLE_IP_MIF1 0x0b04
957#define ENABLE_IP_MIF2 0x0b08
958#define ENABLE_IP_MIF3 0x0b0c
959#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
960#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
961#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
962#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
963#define CLKOUT_CMU_MIF 0x0c00
964#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
965#define DREX_FREQ_CTRL0 0x1000
966#define DREX_FREQ_CTRL1 0x1004
967#define PAUSE 0x1008
968#define DDRPHY_LOCK_CTRL 0x100c
969
970static unsigned long mif_clk_regs[] __initdata = {
971 MEM0_PLL_LOCK,
972 MEM1_PLL_LOCK,
973 BUS_PLL_LOCK,
974 MFC_PLL_LOCK,
975 MEM0_PLL_CON0,
976 MEM0_PLL_CON1,
977 MEM0_PLL_FREQ_DET,
978 MEM1_PLL_CON0,
979 MEM1_PLL_CON1,
980 MEM1_PLL_FREQ_DET,
981 BUS_PLL_CON0,
982 BUS_PLL_CON1,
983 BUS_PLL_FREQ_DET,
984 MFC_PLL_CON0,
985 MFC_PLL_CON1,
986 MFC_PLL_FREQ_DET,
987 MUX_SEL_MIF0,
988 MUX_SEL_MIF1,
989 MUX_SEL_MIF2,
990 MUX_SEL_MIF3,
991 MUX_SEL_MIF4,
992 MUX_SEL_MIF5,
993 MUX_SEL_MIF6,
994 MUX_SEL_MIF7,
995 MUX_ENABLE_MIF0,
996 MUX_ENABLE_MIF1,
997 MUX_ENABLE_MIF2,
998 MUX_ENABLE_MIF3,
999 MUX_ENABLE_MIF4,
1000 MUX_ENABLE_MIF5,
1001 MUX_ENABLE_MIF6,
1002 MUX_ENABLE_MIF7,
1003 MUX_STAT_MIF0,
1004 MUX_STAT_MIF1,
1005 MUX_STAT_MIF2,
1006 MUX_STAT_MIF3,
1007 MUX_STAT_MIF4,
1008 MUX_STAT_MIF5,
1009 MUX_STAT_MIF6,
1010 MUX_STAT_MIF7,
1011 DIV_MIF1,
1012 DIV_MIF2,
1013 DIV_MIF3,
1014 DIV_MIF4,
1015 DIV_MIF5,
1016 DIV_MIF_PLL_FREQ_DET,
1017 DIV_STAT_MIF1,
1018 DIV_STAT_MIF2,
1019 DIV_STAT_MIF3,
1020 DIV_STAT_MIF4,
1021 DIV_STAT_MIF5,
1022 DIV_STAT_MIF_PLL_FREQ_DET,
1023 ENABLE_ACLK_MIF0,
1024 ENABLE_ACLK_MIF1,
1025 ENABLE_ACLK_MIF2,
1026 ENABLE_ACLK_MIF3,
1027 ENABLE_PCLK_MIF,
1028 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1029 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1030 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1031 ENABLE_PCLK_MIF_SECURE_RTC,
1032 ENABLE_SCLK_MIF,
1033 ENABLE_IP_MIF0,
1034 ENABLE_IP_MIF1,
1035 ENABLE_IP_MIF2,
1036 ENABLE_IP_MIF3,
1037 ENABLE_IP_MIF_SECURE_DREX0_TZ,
1038 ENABLE_IP_MIF_SECURE_DREX1_TZ,
1039 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1040 ENABLE_IP_MIF_SECURE_RTC,
1041 CLKOUT_CMU_MIF,
1042 CLKOUT_CMU_MIF_DIV_STAT,
1043 DREX_FREQ_CTRL0,
1044 DREX_FREQ_CTRL1,
1045 PAUSE,
1046 DDRPHY_LOCK_CTRL,
1047};
1048
1049static struct samsung_pll_clock mif_pll_clks[] __initdata = {
1050 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1051 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1052 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1053 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
1054 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1055 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
1056 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1057 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
1058};
1059
1060/* list of all parent clock list */
1061PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1062PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1063PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1064PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1065PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1066PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1067PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1068PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1069
1070PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1071PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1072PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1073PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1074
1075PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1076PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1077
1078PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1079 "mout_bus_pll_div2", };
1080PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1081
1082PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1083 "sclk_mphy_pll", };
1084PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1085 "mout_mfc_pll_div2", };
1086PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1087PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1088 "sclk_mphy_pll", };
1089PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1090 "mout_mfc_pll_div2", };
1091
1092PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1093 "sclk_mphy_pll", };
1094PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1095 "mout_mfc_pll_div2", };
1096PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1097PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1098PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1099
1100PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1101PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1102
1103PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1104 "sclk_mphy_pll", };
1105PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1106 "mout_mfc_pll_div2", };
1107PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1108PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1109
1110static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1111 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1112 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1113 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1114 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1115 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1116};
1117
1118static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1119 /* MUX_SEL_MIF0 */
1120 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1121 MUX_SEL_MIF0, 28, 1),
1122 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1123 MUX_SEL_MIF0, 24, 1),
1124 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1125 MUX_SEL_MIF0, 20, 1),
1126 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1127 MUX_SEL_MIF0, 16, 1),
1128 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1129 12, 1),
1130 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1131 8, 1),
1132 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1133 4, 1),
1134 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1135 0, 1),
1136
1137 /* MUX_SEL_MIF1 */
1138 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1139 MUX_SEL_MIF1, 24, 1),
1140 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1141 MUX_SEL_MIF1, 20, 1),
1142 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1143 MUX_SEL_MIF1, 16, 1),
1144 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1145 MUX_SEL_MIF1, 12, 1),
1146 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1147 MUX_SEL_MIF1, 8, 1),
1148 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1149 MUX_SEL_MIF1, 4, 1),
1150
1151 /* MUX_SEL_MIF2 */
1152 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1153 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1154 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1155 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1156
1157 /* MUX_SEL_MIF3 */
1158 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1159 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1160 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1161 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1162
1163 /* MUX_SEL_MIF4 */
1164 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1165 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1166 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1167 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1168 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1169 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1170 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1171 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1172 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1173 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1174 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1175 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1176
1177 /* MUX_SEL_MIF5 */
1178 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1179 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1180 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1181 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1182 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1183 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1184 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1185 MUX_SEL_MIF5, 8, 1),
1186 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1187 MUX_SEL_MIF5, 4, 1),
1188 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1189 MUX_SEL_MIF5, 0, 1),
1190
1191 /* MUX_SEL_MIF6 */
1192 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1193 MUX_SEL_MIF6, 8, 1),
1194 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1195 MUX_SEL_MIF6, 4, 1),
1196 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1197 MUX_SEL_MIF6, 0, 1),
1198
1199 /* MUX_SEL_MIF7 */
1200 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1201 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1202 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1203 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1204 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1205 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1206 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1207 MUX_SEL_MIF7, 8, 1),
1208 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1209 MUX_SEL_MIF7, 4, 1),
1210 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1211 MUX_SEL_MIF7, 0, 1),
1212};
1213
1214static struct samsung_div_clock mif_div_clks[] __initdata = {
1215 /* DIV_MIF1 */
1216 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1217 DIV_MIF1, 16, 2),
1218 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1219 12, 2),
1220 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1221 8, 2),
1222 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1223 4, 4),
1224
1225 /* DIV_MIF2 */
1226 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1227 DIV_MIF2, 20, 3),
1228 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1229 DIV_MIF2, 16, 4),
1230 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1231 DIV_MIF2, 12, 4),
1232 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1233 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1234 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1235 DIV_MIF2, 4, 2),
1236 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1237 DIV_MIF2, 0, 3),
1238
1239 /* DIV_MIF3 */
1240 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1241 DIV_MIF3, 16, 4),
1242 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1243 DIV_MIF3, 4, 3),
1244 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1245 DIV_MIF3, 0, 3),
1246
1247 /* DIV_MIF4 */
1248 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1249 DIV_MIF4, 24, 4),
1250 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1251 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1252 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1253 DIV_MIF4, 16, 4),
1254 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1255 DIV_MIF4, 12, 4),
1256 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1257 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1258 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1259 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1260 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1261 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1262
1263 /* DIV_MIF5 */
1264 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1265 0, 3),
1266};
1267
1268static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1269 /* ENABLE_ACLK_MIF0 */
1270 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1271 19, CLK_IGNORE_UNUSED, 0),
1272 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1273 18, CLK_IGNORE_UNUSED, 0),
1274 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1275 17, CLK_IGNORE_UNUSED, 0),
1276 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1277 16, CLK_IGNORE_UNUSED, 0),
1278 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1279 15, CLK_IGNORE_UNUSED, 0),
1280 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1281 14, CLK_IGNORE_UNUSED, 0),
1282 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1283 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1284 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1285 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1286 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1287 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1288 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1289 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1290 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1291 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1292 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1293 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1294 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1295 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1296 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1297 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1298 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1299 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1300 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1301 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1302 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1303 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1304 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1305 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1306 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1307 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1308 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1309 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1310
1311 /* ENABLE_ACLK_MIF1 */
1312 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1313 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1314 CLK_IGNORE_UNUSED, 0),
1315 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1316 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1317 27, CLK_IGNORE_UNUSED, 0),
1318 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1319 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1320 26, CLK_IGNORE_UNUSED, 0),
1321 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1322 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1323 25, CLK_IGNORE_UNUSED, 0),
1324 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1325 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1326 24, CLK_IGNORE_UNUSED, 0),
1327 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1328 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1329 23, CLK_IGNORE_UNUSED, 0),
1330 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1331 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1332 22, CLK_IGNORE_UNUSED, 0),
1333 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1334 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1335 21, CLK_IGNORE_UNUSED, 0),
1336 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1337 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1338 20, CLK_IGNORE_UNUSED, 0),
1339 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1340 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1341 19, CLK_IGNORE_UNUSED, 0),
1342 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1343 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1344 18, CLK_IGNORE_UNUSED, 0),
1345 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1346 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1347 17, CLK_IGNORE_UNUSED, 0),
1348 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1349 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1350 16, CLK_IGNORE_UNUSED, 0),
1351 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1352 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1353 15, CLK_IGNORE_UNUSED, 0),
1354 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1355 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1356 14, CLK_IGNORE_UNUSED, 0),
1357 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1358 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1359 13, CLK_IGNORE_UNUSED, 0),
1360 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1361 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1362 12, CLK_IGNORE_UNUSED, 0),
1363 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1364 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1365 11, CLK_IGNORE_UNUSED, 0),
1366 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1367 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1368 10, CLK_IGNORE_UNUSED, 0),
1369 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1370 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1371 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1372 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1373 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1374 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1375 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1376 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1377 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1378 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1379 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1380 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1381 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1382 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1383 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1384 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1385 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1386 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1387 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1388 0, CLK_IGNORE_UNUSED, 0),
1389
1390 /* ENABLE_ACLK_MIF2 */
1391 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1392 ENABLE_ACLK_MIF2, 20, 0, 0),
1393 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1394 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1395 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1396 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1397 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1398 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1399 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1400 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1401 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1402 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1403 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1404 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1405 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1406 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1407 CLK_IGNORE_UNUSED, 0),
1408 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1409 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1410 5, CLK_IGNORE_UNUSED, 0),
1411 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1412 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1413 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1414 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1415 3, CLK_IGNORE_UNUSED, 0),
1416 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1417 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1418
1419 /* ENABLE_ACLK_MIF3 */
1420 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1421 ENABLE_ACLK_MIF3, 4,
1422 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1423 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1424 ENABLE_ACLK_MIF3, 1,
1425 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1426 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1427 ENABLE_ACLK_MIF3, 0,
1428 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1429
1430 /* ENABLE_PCLK_MIF */
1431 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1432 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1433 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1434 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1435 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1436 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1437 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1438 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1439 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1440 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1441 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1442 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1443 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1444 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1445 CLK_IGNORE_UNUSED, 0),
1446 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1447 ENABLE_PCLK_MIF, 19, 0, 0),
1448 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1449 ENABLE_PCLK_MIF, 18, 0, 0),
1450 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1451 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1452 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1453 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1454 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1455 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1456 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1457 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1458 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1459 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1460 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1461 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1462 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1463 ENABLE_PCLK_MIF, 11, 0, 0),
1464 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1465 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1466 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1467 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1468 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1469 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1470 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1471 ENABLE_PCLK_MIF, 7, 0, 0),
1472 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1473 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1474 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1475 ENABLE_PCLK_MIF, 5, 0, 0),
1476 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1477 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1478 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1479 ENABLE_PCLK_MIF, 2, 0, 0),
1480 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1481 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1482
1483 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1484 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1485 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1486
1487 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1488 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1489 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1490
1491 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1492 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1493 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1494
1495 /* ENABLE_PCLK_MIF_SECURE_RTC */
1496 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1497 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1498
1499 /* ENABLE_SCLK_MIF */
1500 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1501 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1502 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1503 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1504 14, CLK_IGNORE_UNUSED, 0),
1505 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1506 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1507 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1508 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1509 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1510 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1511 7, CLK_IGNORE_UNUSED, 0),
1512 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1513 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1514 6, CLK_IGNORE_UNUSED, 0),
1515 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1516 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1517 5, CLK_IGNORE_UNUSED, 0),
1518 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1519 ENABLE_SCLK_MIF, 4,
1520 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1521 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1522 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1523 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1524 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1525 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1526 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1527 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1528 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1529};
1530
1531static struct samsung_cmu_info mif_cmu_info __initdata = {
1532 .pll_clks = mif_pll_clks,
1533 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1534 .mux_clks = mif_mux_clks,
1535 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1536 .div_clks = mif_div_clks,
1537 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1538 .gate_clks = mif_gate_clks,
1539 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1540 .fixed_factor_clks = mif_fixed_factor_clks,
1541 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1542 .nr_clk_ids = MIF_NR_CLK,
1543 .clk_regs = mif_clk_regs,
1544 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1545};
1546
1547static void __init exynos5433_cmu_mif_init(struct device_node *np)
1548{
1549 samsung_cmu_register_one(np, &mif_cmu_info);
1550}
1551CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1552 exynos5433_cmu_mif_init);
1553
1554/*
1555 * Register offset definitions for CMU_PERIC
1556 */
1557#define DIV_PERIC 0x0600
1558#define DIV_STAT_PERIC 0x0700
1559#define ENABLE_ACLK_PERIC 0x0800
1560#define ENABLE_PCLK_PERIC0 0x0900
1561#define ENABLE_PCLK_PERIC1 0x0904
1562#define ENABLE_SCLK_PERIC 0x0A00
1563#define ENABLE_IP_PERIC0 0x0B00
1564#define ENABLE_IP_PERIC1 0x0B04
1565#define ENABLE_IP_PERIC2 0x0B08
1566
1567static unsigned long peric_clk_regs[] __initdata = {
1568 DIV_PERIC,
1569 DIV_STAT_PERIC,
1570 ENABLE_ACLK_PERIC,
1571 ENABLE_PCLK_PERIC0,
1572 ENABLE_PCLK_PERIC1,
1573 ENABLE_SCLK_PERIC,
1574 ENABLE_IP_PERIC0,
1575 ENABLE_IP_PERIC1,
1576 ENABLE_IP_PERIC2,
1577};
1578
1579static struct samsung_div_clock peric_div_clks[] __initdata = {
1580 /* DIV_PERIC */
1581 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1582 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1583};
1584
1585static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1586 /* ENABLE_ACLK_PERIC */
1587 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1588 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1589 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1590 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1591 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1592 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1593 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1594 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1595
1596 /* ENABLE_PCLK_PERIC0 */
1597 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1598 31, CLK_SET_RATE_PARENT, 0),
1599 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1600 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1601 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1602 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1603 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1604 28, CLK_SET_RATE_PARENT, 0),
1605 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1606 26, CLK_SET_RATE_PARENT, 0),
1607 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1608 25, CLK_SET_RATE_PARENT, 0),
1609 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1610 24, CLK_SET_RATE_PARENT, 0),
1611 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1612 23, CLK_SET_RATE_PARENT, 0),
1613 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1614 22, CLK_SET_RATE_PARENT, 0),
1615 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1616 21, CLK_SET_RATE_PARENT, 0),
1617 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1618 20, CLK_SET_RATE_PARENT, 0),
1619 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1620 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1621 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1622 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1623 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1624 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1625 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1626 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1627 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1628 ENABLE_PCLK_PERIC0, 15,
1629 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1630 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1631 14, CLK_SET_RATE_PARENT, 0),
1632 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1633 13, CLK_SET_RATE_PARENT, 0),
1634 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1635 12, CLK_SET_RATE_PARENT, 0),
1636 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1637 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1638 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1639 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1640 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1641 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1642 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1643 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1644 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1645 7, CLK_SET_RATE_PARENT, 0),
1646 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1647 6, CLK_SET_RATE_PARENT, 0),
1648 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1649 5, CLK_SET_RATE_PARENT, 0),
1650 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1651 4, CLK_SET_RATE_PARENT, 0),
1652 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1653 3, CLK_SET_RATE_PARENT, 0),
1654 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1655 2, CLK_SET_RATE_PARENT, 0),
1656 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1657 1, CLK_SET_RATE_PARENT, 0),
1658 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1659 0, CLK_SET_RATE_PARENT, 0),
1660
1661 /* ENABLE_PCLK_PERIC1 */
1662 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1663 9, CLK_SET_RATE_PARENT, 0),
1664 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1665 8, CLK_SET_RATE_PARENT, 0),
1666 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1667 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1668 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1669 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1670 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1671 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1673 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1675 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1676 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1677 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1678 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1679 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1680 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1681 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1682
1683 /* ENABLE_SCLK_PERIC */
1684 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1685 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1686 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1687 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1688 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1689 19, CLK_SET_RATE_PARENT, 0),
1690 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1691 18, CLK_SET_RATE_PARENT, 0),
1692 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1693 17, 0, 0),
1694 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1695 16, 0, 0),
1696 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1697 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1698 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1699 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1700 ENABLE_SCLK_PERIC, 12,
1701 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1702 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1703 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1704 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1705 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1706 CLK_SET_RATE_PARENT, 0),
1707 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1708 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1709 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1710 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1711 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1712 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1713 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1714 5, CLK_SET_RATE_PARENT, 0),
1715 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1716 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1717 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1718 3, CLK_SET_RATE_PARENT, 0),
1719 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1720 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1721 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1722 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1723 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1724 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1725};
1726
1727static struct samsung_cmu_info peric_cmu_info __initdata = {
1728 .div_clks = peric_div_clks,
1729 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1730 .gate_clks = peric_gate_clks,
1731 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1732 .nr_clk_ids = PERIC_NR_CLK,
1733 .clk_regs = peric_clk_regs,
1734 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1735};
1736
1737static void __init exynos5433_cmu_peric_init(struct device_node *np)
1738{
1739 samsung_cmu_register_one(np, &peric_cmu_info);
1740}
1741
1742CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1743 exynos5433_cmu_peric_init);
1744
1745/*
1746 * Register offset definitions for CMU_PERIS
1747 */
1748#define ENABLE_ACLK_PERIS 0x0800
1749#define ENABLE_PCLK_PERIS 0x0900
1750#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1751#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1752#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1753#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1754#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1755#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1756#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1757#define ENABLE_SCLK_PERIS 0x0a00
1758#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1759#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1760#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1761#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1762#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1763#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1764#define ENABLE_IP_PERIS0 0x0b00
1765#define ENABLE_IP_PERIS1 0x0b04
1766#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1767#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1768#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1769#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1770#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1771#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1772#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1773
1774static unsigned long peris_clk_regs[] __initdata = {
1775 ENABLE_ACLK_PERIS,
1776 ENABLE_PCLK_PERIS,
1777 ENABLE_PCLK_PERIS_SECURE_TZPC,
1778 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1779 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1780 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1781 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1782 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1783 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1784 ENABLE_SCLK_PERIS,
1785 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1786 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1787 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1788 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1789 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1790 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1791 ENABLE_IP_PERIS0,
1792 ENABLE_IP_PERIS1,
1793 ENABLE_IP_PERIS_SECURE_TZPC,
1794 ENABLE_IP_PERIS_SECURE_SECKEY,
1795 ENABLE_IP_PERIS_SECURE_CHIPID,
1796 ENABLE_IP_PERIS_SECURE_TOPRTC,
1797 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1798 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1799 ENABLE_IP_PERIS_SECURE_OTP_CON,
1800};
1801
1802static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1803 /* ENABLE_ACLK_PERIS */
1804 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1805 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1806 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1807 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1808 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1809 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1810
1811 /* ENABLE_PCLK_PERIS */
1812 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1813 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1814 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1815 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1816 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1817 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1818 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1819 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1820 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1821 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1822 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1823 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1824 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1825 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1826 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1827 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1828 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1829 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1830 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1831 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1832
1833 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1834 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1835 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
1836 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1837 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
1838 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1839 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
1840 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1841 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
1842 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1843 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
1844 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1845 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
1846 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1847 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
1848 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1849 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
1850 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1851 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
1852 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1853 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
1854 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1855 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
1856 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1857 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
1858 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1859 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
1860
1861 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1862 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1863 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
1864
1865 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1866 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1867 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
1868
1869 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1870 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1871 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1872
1873 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1874 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1875 "aclk_peris_66",
1876 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1877
1878 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1879 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1880 "aclk_peris_66",
1881 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1882
1883 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1884 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1885 "aclk_peris_66",
1886 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1887
1888 /* ENABLE_SCLK_PERIS */
1889 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1890 ENABLE_SCLK_PERIS, 10, 0, 0),
1891 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1892 ENABLE_SCLK_PERIS, 4, 0, 0),
1893 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1894 ENABLE_SCLK_PERIS, 3, 0, 0),
1895
1896 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1897 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1898 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
1899
1900 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1901 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1902 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
1903
1904 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1905 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1906 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1907
1908 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1909 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1910 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1911
1912 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1913 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1914 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1915
1916 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1917 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1918 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1919};
1920
1921static struct samsung_cmu_info peris_cmu_info __initdata = {
1922 .gate_clks = peris_gate_clks,
1923 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1924 .nr_clk_ids = PERIS_NR_CLK,
1925 .clk_regs = peris_clk_regs,
1926 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1927};
1928
1929static void __init exynos5433_cmu_peris_init(struct device_node *np)
1930{
1931 samsung_cmu_register_one(np, &peris_cmu_info);
1932}
1933
1934CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1935 exynos5433_cmu_peris_init);
1936
1937/*
1938 * Register offset definitions for CMU_FSYS
1939 */
1940#define MUX_SEL_FSYS0 0x0200
1941#define MUX_SEL_FSYS1 0x0204
1942#define MUX_SEL_FSYS2 0x0208
1943#define MUX_SEL_FSYS3 0x020c
1944#define MUX_SEL_FSYS4 0x0210
1945#define MUX_ENABLE_FSYS0 0x0300
1946#define MUX_ENABLE_FSYS1 0x0304
1947#define MUX_ENABLE_FSYS2 0x0308
1948#define MUX_ENABLE_FSYS3 0x030c
1949#define MUX_ENABLE_FSYS4 0x0310
1950#define MUX_STAT_FSYS0 0x0400
1951#define MUX_STAT_FSYS1 0x0404
1952#define MUX_STAT_FSYS2 0x0408
1953#define MUX_STAT_FSYS3 0x040c
1954#define MUX_STAT_FSYS4 0x0410
1955#define MUX_IGNORE_FSYS2 0x0508
1956#define MUX_IGNORE_FSYS3 0x050c
1957#define ENABLE_ACLK_FSYS0 0x0800
1958#define ENABLE_ACLK_FSYS1 0x0804
1959#define ENABLE_PCLK_FSYS 0x0900
1960#define ENABLE_SCLK_FSYS 0x0a00
1961#define ENABLE_IP_FSYS0 0x0b00
1962#define ENABLE_IP_FSYS1 0x0b04
1963
1964/* list of all parent clock list */
1965PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1966PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
1967PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1968PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1969PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1970PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1971PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1972PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1973PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1974
1975PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1976 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1977PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1978 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1979PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1980 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1981PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1982 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1983PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1984 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1985PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1986 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1987PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1988 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1989PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1990 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1991PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1992 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1993PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1994 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1995PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1996 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1997PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1998 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1999PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
2000 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2001PNAME(mout_sclk_mphy_p)
2002 = { "mout_sclk_ufs_mphy_user",
2003 "mout_phyclk_lli_mphy_to_ufs_user", };
2004
2005static unsigned long fsys_clk_regs[] __initdata = {
2006 MUX_SEL_FSYS0,
2007 MUX_SEL_FSYS1,
2008 MUX_SEL_FSYS2,
2009 MUX_SEL_FSYS3,
2010 MUX_SEL_FSYS4,
2011 MUX_ENABLE_FSYS0,
2012 MUX_ENABLE_FSYS1,
2013 MUX_ENABLE_FSYS2,
2014 MUX_ENABLE_FSYS3,
2015 MUX_ENABLE_FSYS4,
2016 MUX_STAT_FSYS0,
2017 MUX_STAT_FSYS1,
2018 MUX_STAT_FSYS2,
2019 MUX_STAT_FSYS3,
2020 MUX_STAT_FSYS4,
2021 MUX_IGNORE_FSYS2,
2022 MUX_IGNORE_FSYS3,
2023 ENABLE_ACLK_FSYS0,
2024 ENABLE_ACLK_FSYS1,
2025 ENABLE_PCLK_FSYS,
2026 ENABLE_SCLK_FSYS,
2027 ENABLE_IP_FSYS0,
2028 ENABLE_IP_FSYS1,
2029};
2030
2031static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
2032 /* PHY clocks from USBDRD30_PHY */
2033 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2034 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2035 CLK_IS_ROOT, 60000000),
2036 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2037 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2038 CLK_IS_ROOT, 125000000),
2039 /* PHY clocks from USBHOST30_PHY */
2040 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2041 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2042 CLK_IS_ROOT, 60000000),
2043 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2044 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2045 CLK_IS_ROOT, 125000000),
2046 /* PHY clocks from USBHOST20_PHY */
2047 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2048 "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
2049 60000000),
2050 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2051 "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
2052 60000000),
2053 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2054 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2055 CLK_IS_ROOT, 48000000),
2056 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2057 "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
2058 60000000),
2059 /* PHY clocks from UFS_PHY */
2060 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2061 NULL, CLK_IS_ROOT, 300000000),
2062 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2063 NULL, CLK_IS_ROOT, 300000000),
2064 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2065 NULL, CLK_IS_ROOT, 300000000),
2066 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2067 NULL, CLK_IS_ROOT, 300000000),
2068 /* PHY clocks from LLI_PHY */
2069 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2070 NULL, CLK_IS_ROOT, 26000000),
2071};
2072
2073static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
2074 /* MUX_SEL_FSYS0 */
2075 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2076 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2077 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2078 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2079
2080 /* MUX_SEL_FSYS1 */
2081 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2082 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2083 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2084 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2085 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2086 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2087 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2088 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2089 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2090 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2091 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2092 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2093 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2094 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2095
2096 /* MUX_SEL_FSYS2 */
2097 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2098 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2099 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2100 MUX_SEL_FSYS2, 28, 1),
2101 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2102 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2103 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2104 MUX_SEL_FSYS2, 24, 1),
2105 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2106 "mout_phyclk_usbhost20_phy_hsic1",
2107 mout_phyclk_usbhost20_phy_hsic1_p,
2108 MUX_SEL_FSYS2, 20, 1),
2109 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2110 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2111 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2112 MUX_SEL_FSYS2, 16, 1),
2113 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2114 "mout_phyclk_usbhost20_phy_phyclock_user",
2115 mout_phyclk_usbhost20_phy_phyclock_user_p,
2116 MUX_SEL_FSYS2, 12, 1),
2117 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2118 "mout_phyclk_usbhost20_phy_freeclk_user",
2119 mout_phyclk_usbhost20_phy_freeclk_user_p,
2120 MUX_SEL_FSYS2, 8, 1),
2121 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2122 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2123 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2124 MUX_SEL_FSYS2, 4, 1),
2125 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2126 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2127 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2128 MUX_SEL_FSYS2, 0, 1),
2129
2130 /* MUX_SEL_FSYS3 */
2131 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2132 "mout_phyclk_ufs_rx1_symbol_user",
2133 mout_phyclk_ufs_rx1_symbol_user_p,
2134 MUX_SEL_FSYS3, 16, 1),
2135 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2136 "mout_phyclk_ufs_rx0_symbol_user",
2137 mout_phyclk_ufs_rx0_symbol_user_p,
2138 MUX_SEL_FSYS3, 12, 1),
2139 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2140 "mout_phyclk_ufs_tx1_symbol_user",
2141 mout_phyclk_ufs_tx1_symbol_user_p,
2142 MUX_SEL_FSYS3, 8, 1),
2143 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2144 "mout_phyclk_ufs_tx0_symbol_user",
2145 mout_phyclk_ufs_tx0_symbol_user_p,
2146 MUX_SEL_FSYS3, 4, 1),
2147 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2148 "mout_phyclk_lli_mphy_to_ufs_user",
2149 mout_phyclk_lli_mphy_to_ufs_user_p,
2150 MUX_SEL_FSYS3, 0, 1),
2151
2152 /* MUX_SEL_FSYS4 */
2153 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2154 MUX_SEL_FSYS4, 0, 1),
2155};
2156
2157static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2158 /* ENABLE_ACLK_FSYS0 */
2159 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2160 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2161 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2162 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2163 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2164 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2165 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2166 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2167 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2168 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2169 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2170 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2171 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2172 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2173 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2174 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2175 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2176 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2177 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2178 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2179 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2180 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2181
2182 /* ENABLE_ACLK_FSYS1 */
2183 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2184 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2185 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2186 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2187 26, CLK_IGNORE_UNUSED, 0),
2188 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2189 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2190 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2191 ENABLE_ACLK_FSYS1, 24, 0, 0),
2192 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2193 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2194 22, CLK_IGNORE_UNUSED, 0),
2195 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2196 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2197 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2198 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2199 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2200 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2201 13, 0, 0),
2202 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2203 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2204 12, 0, 0),
2205 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2206 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2207 11, CLK_IGNORE_UNUSED, 0),
2208 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2209 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2210 10, CLK_IGNORE_UNUSED, 0),
2211 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2212 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2213 9, CLK_IGNORE_UNUSED, 0),
2214 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2215 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2216 8, CLK_IGNORE_UNUSED, 0),
2217 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2218 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2219 7, CLK_IGNORE_UNUSED, 0),
2220 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2221 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2222 6, CLK_IGNORE_UNUSED, 0),
2223 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2224 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2225 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2226 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2227 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2228 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2229 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2230 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2231 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2232 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2233 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2234 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2235
2236 /* ENABLE_PCLK_FSYS */
2237 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2238 ENABLE_PCLK_FSYS, 17, 0, 0),
2239 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2240 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2241 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2242 ENABLE_PCLK_FSYS, 14, 0, 0),
2243 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2244 ENABLE_PCLK_FSYS, 13, 0, 0),
2245 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2246 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2247 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2248 ENABLE_PCLK_FSYS, 5, 0, 0),
2249 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2250 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2251 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2252 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2253 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2254 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2255 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2256 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2257 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2258 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2259 0, CLK_IGNORE_UNUSED, 0),
2260
2261 /* ENABLE_SCLK_FSYS */
2262 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2263 ENABLE_SCLK_FSYS, 21, 0, 0),
2264 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2265 "phyclk_usbhost30_uhost30_pipe_pclk",
2266 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2267 ENABLE_SCLK_FSYS, 18, 0, 0),
2268 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2269 "phyclk_usbhost30_uhost30_phyclock",
2270 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2271 ENABLE_SCLK_FSYS, 17, 0, 0),
2272 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2273 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2274 16, 0, 0),
2275 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2276 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2277 15, 0, 0),
2278 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2279 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2280 14, 0, 0),
2281 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2282 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2283 13, 0, 0),
2284 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2285 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2286 12, 0, 0),
2287 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2288 "phyclk_usbhost20_phy_clk48mohci",
2289 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2290 ENABLE_SCLK_FSYS, 11, 0, 0),
2291 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2292 "phyclk_usbhost20_phy_phyclock",
2293 "mout_phyclk_usbhost20_phy_phyclock_user",
2294 ENABLE_SCLK_FSYS, 10, 0, 0),
2295 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2296 "phyclk_usbhost20_phy_freeclk",
2297 "mout_phyclk_usbhost20_phy_freeclk_user",
2298 ENABLE_SCLK_FSYS, 9, 0, 0),
2299 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2300 "phyclk_usbdrd30_udrd30_pipe_pclk",
2301 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2302 ENABLE_SCLK_FSYS, 8, 0, 0),
2303 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2304 "phyclk_usbdrd30_udrd30_phyclock",
2305 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2306 ENABLE_SCLK_FSYS, 7, 0, 0),
2307 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2308 ENABLE_SCLK_FSYS, 6, 0, 0),
2309 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2310 ENABLE_SCLK_FSYS, 5, 0, 0),
2311 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2312 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2313 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2314 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2315 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2316 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2317 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2318 ENABLE_SCLK_FSYS, 1, 0, 0),
2319 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2320 ENABLE_SCLK_FSYS, 0, 0, 0),
2321
2322 /* ENABLE_IP_FSYS0 */
2323 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2324 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2325};
2326
2327static struct samsung_cmu_info fsys_cmu_info __initdata = {
2328 .mux_clks = fsys_mux_clks,
2329 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2330 .gate_clks = fsys_gate_clks,
2331 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2332 .fixed_clks = fsys_fixed_clks,
2333 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2334 .nr_clk_ids = FSYS_NR_CLK,
2335 .clk_regs = fsys_clk_regs,
2336 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2337};
2338
2339static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2340{
2341 samsung_cmu_register_one(np, &fsys_cmu_info);
2342}
2343
2344CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2345 exynos5433_cmu_fsys_init);
2346
2347/*
2348 * Register offset definitions for CMU_G2D
2349 */
2350#define MUX_SEL_G2D0 0x0200
2351#define MUX_SEL_ENABLE_G2D0 0x0300
2352#define MUX_SEL_STAT_G2D0 0x0400
2353#define DIV_G2D 0x0600
2354#define DIV_STAT_G2D 0x0700
2355#define DIV_ENABLE_ACLK_G2D 0x0800
2356#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2357#define DIV_ENABLE_PCLK_G2D 0x0900
2358#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2359#define DIV_ENABLE_IP_G2D0 0x0b00
2360#define DIV_ENABLE_IP_G2D1 0x0b04
2361#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2362
2363static unsigned long g2d_clk_regs[] __initdata = {
2364 MUX_SEL_G2D0,
2365 MUX_SEL_ENABLE_G2D0,
2366 MUX_SEL_STAT_G2D0,
2367 DIV_G2D,
2368 DIV_STAT_G2D,
2369 DIV_ENABLE_ACLK_G2D,
2370 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2371 DIV_ENABLE_PCLK_G2D,
2372 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2373 DIV_ENABLE_IP_G2D0,
2374 DIV_ENABLE_IP_G2D1,
2375 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2376};
2377
2378/* list of all parent clock list */
2379PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2380PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2381
2382static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2383 /* MUX_SEL_G2D0 */
2384 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2385 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2386 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2387 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2388};
2389
2390static struct samsung_div_clock g2d_div_clks[] __initdata = {
2391 /* DIV_G2D */
2392 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2393 DIV_G2D, 0, 2),
2394};
2395
2396static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2397 /* DIV_ENABLE_ACLK_G2D */
2398 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2399 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2400 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2401 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2402 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2403 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2404 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2405 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2406 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2407 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2408 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2409 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2410 7, 0, 0),
2411 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2412 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2413 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2414 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2415 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2416 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2417 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2418 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2419 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2420 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2421 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2422 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2423 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2424 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2425
2426 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2427 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2428 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2429
2430 /* DIV_ENABLE_PCLK_G2D */
2431 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2432 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2433 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2434 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2435 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2436 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2437 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2438 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2439 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2440 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2441 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2442 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2443 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2444 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2445 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2446 0, 0, 0),
2447
2448 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2449 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2450 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2451};
2452
2453static struct samsung_cmu_info g2d_cmu_info __initdata = {
2454 .mux_clks = g2d_mux_clks,
2455 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2456 .div_clks = g2d_div_clks,
2457 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2458 .gate_clks = g2d_gate_clks,
2459 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2460 .nr_clk_ids = G2D_NR_CLK,
2461 .clk_regs = g2d_clk_regs,
2462 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2463};
2464
2465static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2466{
2467 samsung_cmu_register_one(np, &g2d_cmu_info);
2468}
2469
2470CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2471 exynos5433_cmu_g2d_init);
2472
2473/*
2474 * Register offset definitions for CMU_DISP
2475 */
2476#define DISP_PLL_LOCK 0x0000
2477#define DISP_PLL_CON0 0x0100
2478#define DISP_PLL_CON1 0x0104
2479#define DISP_PLL_FREQ_DET 0x0108
2480#define MUX_SEL_DISP0 0x0200
2481#define MUX_SEL_DISP1 0x0204
2482#define MUX_SEL_DISP2 0x0208
2483#define MUX_SEL_DISP3 0x020c
2484#define MUX_SEL_DISP4 0x0210
2485#define MUX_ENABLE_DISP0 0x0300
2486#define MUX_ENABLE_DISP1 0x0304
2487#define MUX_ENABLE_DISP2 0x0308
2488#define MUX_ENABLE_DISP3 0x030c
2489#define MUX_ENABLE_DISP4 0x0310
2490#define MUX_STAT_DISP0 0x0400
2491#define MUX_STAT_DISP1 0x0404
2492#define MUX_STAT_DISP2 0x0408
2493#define MUX_STAT_DISP3 0x040c
2494#define MUX_STAT_DISP4 0x0410
2495#define MUX_IGNORE_DISP2 0x0508
2496#define DIV_DISP 0x0600
2497#define DIV_DISP_PLL_FREQ_DET 0x0604
2498#define DIV_STAT_DISP 0x0700
2499#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2500#define ENABLE_ACLK_DISP0 0x0800
2501#define ENABLE_ACLK_DISP1 0x0804
2502#define ENABLE_PCLK_DISP 0x0900
2503#define ENABLE_SCLK_DISP 0x0a00
2504#define ENABLE_IP_DISP0 0x0b00
2505#define ENABLE_IP_DISP1 0x0b04
2506#define CLKOUT_CMU_DISP 0x0c00
2507#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2508
2509static unsigned long disp_clk_regs[] __initdata = {
2510 DISP_PLL_LOCK,
2511 DISP_PLL_CON0,
2512 DISP_PLL_CON1,
2513 DISP_PLL_FREQ_DET,
2514 MUX_SEL_DISP0,
2515 MUX_SEL_DISP1,
2516 MUX_SEL_DISP2,
2517 MUX_SEL_DISP3,
2518 MUX_SEL_DISP4,
2519 MUX_ENABLE_DISP0,
2520 MUX_ENABLE_DISP1,
2521 MUX_ENABLE_DISP2,
2522 MUX_ENABLE_DISP3,
2523 MUX_ENABLE_DISP4,
2524 MUX_STAT_DISP0,
2525 MUX_STAT_DISP1,
2526 MUX_STAT_DISP2,
2527 MUX_STAT_DISP3,
2528 MUX_STAT_DISP4,
2529 MUX_IGNORE_DISP2,
2530 DIV_DISP,
2531 DIV_DISP_PLL_FREQ_DET,
2532 DIV_STAT_DISP,
2533 DIV_STAT_DISP_PLL_FREQ_DET,
2534 ENABLE_ACLK_DISP0,
2535 ENABLE_ACLK_DISP1,
2536 ENABLE_PCLK_DISP,
2537 ENABLE_SCLK_DISP,
2538 ENABLE_IP_DISP0,
2539 ENABLE_IP_DISP1,
2540 CLKOUT_CMU_DISP,
2541 CLKOUT_CMU_DISP_DIV_STAT,
2542};
2543
2544/* list of all parent clock list */
2545PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2546PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2547PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2548PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2549PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2550 "sclk_decon_tv_eclk_disp", };
2551PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2552 "sclk_decon_vclk_disp", };
2553PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2554 "sclk_decon_eclk_disp", };
2555PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2556 "sclk_decon_tv_vclk_disp", };
2557PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2558
2559PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2560 "phyclk_mipidphy1_bitclkdiv8_phy", };
2561PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2562 "phyclk_mipidphy1_rxclkesc0_phy", };
2563PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2564 "phyclk_mipidphy0_bitclkdiv8_phy", };
2565PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2566 "phyclk_mipidphy0_rxclkesc0_phy", };
2567PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2568 "phyclk_hdmiphy_tmds_clko_phy", };
2569PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2570 "phyclk_hdmiphy_pixel_clko_phy", };
2571
2572PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2573 "mout_sclk_dsim0_user", };
2574PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2575 "mout_sclk_decon_tv_eclk_user", };
2576PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2577 "mout_sclk_decon_vclk_user", };
2578PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2579 "mout_sclk_decon_eclk_user", };
2580
2581PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2582 "mout_sclk_dsim1_user", };
2583PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2584 "mout_phyclk_hdmiphy_pixel_clko_user",
2585 "mout_sclk_decon_tv_vclk_b_disp", };
2586PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2587 "mout_sclk_decon_tv_vclk_user", };
2588
2589static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2590 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2591 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2592};
2593
2594static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2595 /*
2596 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2597 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2598 * and sclk_decon_{vclk|tv_vclk}.
2599 */
2600 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2601 1, 2, 0),
2602 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2603 1, 2, 0),
2604};
2605
2606static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2607 /* PHY clocks from MIPI_DPHY1 */
2608 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2609 188000000),
2610 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2611 100000000),
2612 /* PHY clocks from MIPI_DPHY0 */
2613 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2614 188000000),
2615 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2616 100000000),
2617 /* PHY clocks from HDMI_PHY */
2618 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
2619 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
2620};
2621
2622static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2623 /* MUX_SEL_DISP0 */
2624 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2625 0, 1),
2626
2627 /* MUX_SEL_DISP1 */
2628 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2629 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2630 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2631 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2632 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2633 MUX_SEL_DISP1, 20, 1),
2634 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2635 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2636 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2637 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2638 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2639 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2640 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2641 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2642 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2643 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2644
2645 /* MUX_SEL_DISP2 */
2646 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2647 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2648 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2649 20, 1),
2650 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2651 "mout_phyclk_mipidphy1_rxclkesc0_user",
2652 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2653 16, 1),
2654 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2655 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2656 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2657 12, 1),
2658 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2659 "mout_phyclk_mipidphy0_rxclkesc0_user",
2660 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2661 8, 1),
2662 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2663 "mout_phyclk_hdmiphy_tmds_clko_user",
2664 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2665 4, 1),
2666 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2667 "mout_phyclk_hdmiphy_pixel_clko_user",
2668 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2669 0, 1),
2670
2671 /* MUX_SEL_DISP3 */
2672 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2673 MUX_SEL_DISP3, 12, 1),
2674 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2675 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2676 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2677 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2678 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2679 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2680
2681 /* MUX_SEL_DISP4 */
2682 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2683 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2684 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2685 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2686 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2687 "mout_sclk_decon_tv_vclk_c_disp",
2688 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2689 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2690 "mout_sclk_decon_tv_vclk_b_disp",
2691 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2692 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2693 "mout_sclk_decon_tv_vclk_a_disp",
2694 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2695};
2696
2697static struct samsung_div_clock disp_div_clks[] __initdata = {
2698 /* DIV_DISP */
2699 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2700 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2701 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2702 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2703 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2704 DIV_DISP, 16, 3),
2705 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2706 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2707 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2708 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2709 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2710 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2711 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2712 DIV_DISP, 0, 2),
2713};
2714
2715static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2716 /* ENABLE_ACLK_DISP0 */
2717 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2718 ENABLE_ACLK_DISP0, 2, 0, 0),
2719 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2720 ENABLE_ACLK_DISP0, 0, 0, 0),
2721
2722 /* ENABLE_ACLK_DISP1 */
2723 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2724 ENABLE_ACLK_DISP1, 25, 0, 0),
2725 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2726 ENABLE_ACLK_DISP1, 24, 0, 0),
2727 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2728 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2729 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2730 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2731 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2732 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2733 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2734 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2735 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2736 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2737 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2738 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2739 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2740 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2741 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2742 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2743 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2744 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2745 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2746 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2747 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2748 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2749 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2750 "div_pclk_disp", ENABLE_ACLK_DISP1,
2751 12, CLK_IGNORE_UNUSED, 0),
2752 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2753 "div_pclk_disp", ENABLE_ACLK_DISP1,
2754 11, CLK_IGNORE_UNUSED, 0),
2755 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2756 "div_pclk_disp", ENABLE_ACLK_DISP1,
2757 10, CLK_IGNORE_UNUSED, 0),
2758 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2759 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2760 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2761 ENABLE_ACLK_DISP1, 7, 0, 0),
2762 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2763 ENABLE_ACLK_DISP1, 6, 0, 0),
2764 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2765 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2766 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2767 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2768 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2769 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2770 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2771 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2772 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2773 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2774 CLK_IGNORE_UNUSED, 0),
2775 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2776 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2777 0, CLK_IGNORE_UNUSED, 0),
2778
2779 /* ENABLE_PCLK_DISP */
2780 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2781 ENABLE_PCLK_DISP, 23, 0, 0),
2782 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2783 ENABLE_PCLK_DISP, 22, 0, 0),
2784 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2785 ENABLE_PCLK_DISP, 21, 0, 0),
2786 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2787 ENABLE_PCLK_DISP, 20, 0, 0),
2788 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2789 ENABLE_PCLK_DISP, 19, 0, 0),
2790 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2791 ENABLE_PCLK_DISP, 18, 0, 0),
2792 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2793 ENABLE_PCLK_DISP, 17, 0, 0),
2794 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2795 ENABLE_PCLK_DISP, 16, 0, 0),
2796 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2797 ENABLE_PCLK_DISP, 15, 0, 0),
2798 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2799 ENABLE_PCLK_DISP, 14, 0, 0),
2800 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2801 ENABLE_PCLK_DISP, 13, 0, 0),
2802 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2803 ENABLE_PCLK_DISP, 12, 0, 0),
2804 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2805 ENABLE_PCLK_DISP, 11, 0, 0),
2806 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2807 ENABLE_PCLK_DISP, 10, 0, 0),
2808 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2809 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2810 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2811 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2812 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2813 ENABLE_PCLK_DISP, 7, 0, 0),
2814 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2815 ENABLE_PCLK_DISP, 6, 0, 0),
2816 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2817 ENABLE_PCLK_DISP, 5, 0, 0),
2818 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2819 ENABLE_PCLK_DISP, 3, 0, 0),
2820 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2821 ENABLE_PCLK_DISP, 2, 0, 0),
2822 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2823 ENABLE_PCLK_DISP, 1, 0, 0),
2824
2825 /* ENABLE_SCLK_DISP */
2826 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2827 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2828 ENABLE_SCLK_DISP, 26, 0, 0),
2829 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2830 "mout_phyclk_mipidphy1_rxclkesc0_user",
2831 ENABLE_SCLK_DISP, 25, 0, 0),
2832 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2833 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2834 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2835 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2836 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2837 ENABLE_SCLK_DISP, 22, 0, 0),
2838 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2839 "div_sclk_decon_tv_vclk_disp",
2840 ENABLE_SCLK_DISP, 21, 0, 0),
2841 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2842 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2843 ENABLE_SCLK_DISP, 15, 0, 0),
2844 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2845 "mout_phyclk_mipidphy0_rxclkesc0_user",
2846 ENABLE_SCLK_DISP, 14, 0, 0),
2847 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2848 "mout_phyclk_hdmiphy_tmds_clko_user",
2849 ENABLE_SCLK_DISP, 13, 0, 0),
2850 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2851 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2852 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2853 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2854 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2855 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2856 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2857 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2858 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2859 ENABLE_SCLK_DISP, 7, 0, 0),
2860 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2861 ENABLE_SCLK_DISP, 6, 0, 0),
2862 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2863 ENABLE_SCLK_DISP, 5, 0, 0),
2864 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2865 "div_sclk_decon_tv_eclk_disp",
2866 ENABLE_SCLK_DISP, 4, 0, 0),
2867 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2868 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2869 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2870 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2871};
2872
2873static struct samsung_cmu_info disp_cmu_info __initdata = {
2874 .pll_clks = disp_pll_clks,
2875 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2876 .mux_clks = disp_mux_clks,
2877 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2878 .div_clks = disp_div_clks,
2879 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2880 .gate_clks = disp_gate_clks,
2881 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2882 .fixed_clks = disp_fixed_clks,
2883 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2884 .fixed_factor_clks = disp_fixed_factor_clks,
2885 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2886 .nr_clk_ids = DISP_NR_CLK,
2887 .clk_regs = disp_clk_regs,
2888 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2889};
2890
2891static void __init exynos5433_cmu_disp_init(struct device_node *np)
2892{
2893 samsung_cmu_register_one(np, &disp_cmu_info);
2894}
2895
2896CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2897 exynos5433_cmu_disp_init);
2898
2899/*
2900 * Register offset definitions for CMU_AUD
2901 */
2902#define MUX_SEL_AUD0 0x0200
2903#define MUX_SEL_AUD1 0x0204
2904#define MUX_ENABLE_AUD0 0x0300
2905#define MUX_ENABLE_AUD1 0x0304
2906#define MUX_STAT_AUD0 0x0400
2907#define DIV_AUD0 0x0600
2908#define DIV_AUD1 0x0604
2909#define DIV_STAT_AUD0 0x0700
2910#define DIV_STAT_AUD1 0x0704
2911#define ENABLE_ACLK_AUD 0x0800
2912#define ENABLE_PCLK_AUD 0x0900
2913#define ENABLE_SCLK_AUD0 0x0a00
2914#define ENABLE_SCLK_AUD1 0x0a04
2915#define ENABLE_IP_AUD0 0x0b00
2916#define ENABLE_IP_AUD1 0x0b04
2917
2918static unsigned long aud_clk_regs[] __initdata = {
2919 MUX_SEL_AUD0,
2920 MUX_SEL_AUD1,
2921 MUX_ENABLE_AUD0,
2922 MUX_ENABLE_AUD1,
2923 MUX_STAT_AUD0,
2924 DIV_AUD0,
2925 DIV_AUD1,
2926 DIV_STAT_AUD0,
2927 DIV_STAT_AUD1,
2928 ENABLE_ACLK_AUD,
2929 ENABLE_PCLK_AUD,
2930 ENABLE_SCLK_AUD0,
2931 ENABLE_SCLK_AUD1,
2932 ENABLE_IP_AUD0,
2933 ENABLE_IP_AUD1,
2934};
2935
2936/* list of all parent clock list */
2937PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2938PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2939
2940static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
2941 FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
2942 FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
2943 FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
2944};
2945
2946static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2947 /* MUX_SEL_AUD0 */
2948 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2949 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2950
2951 /* MUX_SEL_AUD1 */
2952 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2953 MUX_SEL_AUD1, 8, 1),
2954 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2955 MUX_SEL_AUD1, 0, 1),
2956};
2957
2958static struct samsung_div_clock aud_div_clks[] __initdata = {
2959 /* DIV_AUD0 */
2960 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2961 12, 4),
2962 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2963 8, 4),
2964 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2965 4, 4),
2966 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2967 0, 4),
2968
2969 /* DIV_AUD1 */
2970 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2971 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2972 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2973 DIV_AUD1, 12, 4),
2974 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2975 DIV_AUD1, 4, 8),
2976 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2977 DIV_AUD1, 0, 4),
2978};
2979
2980static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2981 /* ENABLE_ACLK_AUD */
2982 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2983 ENABLE_ACLK_AUD, 12, 0, 0),
2984 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2985 ENABLE_ACLK_AUD, 7, 0, 0),
2986 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2987 ENABLE_ACLK_AUD, 0, 4, 0),
2988 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2989 ENABLE_ACLK_AUD, 0, 3, 0),
2990 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2991 ENABLE_ACLK_AUD, 0, 2, 0),
2992 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2993 0, 1, 0),
2994 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2995 0, CLK_IGNORE_UNUSED, 0),
2996
2997 /* ENABLE_PCLK_AUD */
2998 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2999 13, 0, 0),
3000 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3001 12, 0, 0),
3002 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3003 11, 0, 0),
3004 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3005 ENABLE_PCLK_AUD, 10, 0, 0),
3006 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3007 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3008 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3009 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3010 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3011 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3012 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3013 ENABLE_PCLK_AUD, 6, 0, 0),
3014 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3015 ENABLE_PCLK_AUD, 5, 0, 0),
3016 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3017 ENABLE_PCLK_AUD, 4, 0, 0),
3018 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3019 ENABLE_PCLK_AUD, 3, 0, 0),
3020 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3021 2, 0, 0),
3022 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3023 ENABLE_PCLK_AUD, 0, 0, 0),
3024
3025 /* ENABLE_SCLK_AUD0 */
3026 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3027 2, 0, 0),
3028 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3029 ENABLE_SCLK_AUD0, 1, 0, 0),
3030 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3031 0, 0, 0),
3032
3033 /* ENABLE_SCLK_AUD1 */
3034 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3035 ENABLE_SCLK_AUD1, 6, 0, 0),
3036 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3037 ENABLE_SCLK_AUD1, 5, 0, 0),
3038 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3039 ENABLE_SCLK_AUD1, 4, 0, 0),
3040 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3041 ENABLE_SCLK_AUD1, 3, 0, 0),
3042 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3043 ENABLE_SCLK_AUD1, 2, 0, 0),
3044 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3045 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3046 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3047 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3048};
3049
3050static struct samsung_cmu_info aud_cmu_info __initdata = {
3051 .mux_clks = aud_mux_clks,
3052 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
3053 .div_clks = aud_div_clks,
3054 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
3055 .gate_clks = aud_gate_clks,
3056 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
3057 .fixed_clks = aud_fixed_clks,
3058 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
3059 .nr_clk_ids = AUD_NR_CLK,
3060 .clk_regs = aud_clk_regs,
3061 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3062};
3063
3064static void __init exynos5433_cmu_aud_init(struct device_node *np)
3065{
3066 samsung_cmu_register_one(np, &aud_cmu_info);
3067}
3068CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
3069 exynos5433_cmu_aud_init);
3070
3071
3072/*
3073 * Register offset definitions for CMU_BUS{0|1|2}
3074 */
3075#define DIV_BUS 0x0600
3076#define DIV_STAT_BUS 0x0700
3077#define ENABLE_ACLK_BUS 0x0800
3078#define ENABLE_PCLK_BUS 0x0900
3079#define ENABLE_IP_BUS0 0x0b00
3080#define ENABLE_IP_BUS1 0x0b04
3081
3082#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3083#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3084#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3085
3086/* list of all parent clock list */
3087PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3088
3089#define CMU_BUS_COMMON_CLK_REGS \
3090 DIV_BUS, \
3091 DIV_STAT_BUS, \
3092 ENABLE_ACLK_BUS, \
3093 ENABLE_PCLK_BUS, \
3094 ENABLE_IP_BUS0, \
3095 ENABLE_IP_BUS1
3096
3097static unsigned long bus01_clk_regs[] __initdata = {
3098 CMU_BUS_COMMON_CLK_REGS,
3099};
3100
3101static unsigned long bus2_clk_regs[] __initdata = {
3102 MUX_SEL_BUS2,
3103 MUX_ENABLE_BUS2,
3104 MUX_STAT_BUS2,
3105 CMU_BUS_COMMON_CLK_REGS,
3106};
3107
3108static struct samsung_div_clock bus0_div_clks[] __initdata = {
3109 /* DIV_BUS0 */
3110 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3111 DIV_BUS, 0, 3),
3112};
3113
3114/* CMU_BUS0 clocks */
3115static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3116 /* ENABLE_ACLK_BUS0 */
3117 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3118 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3119 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3120 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3121 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3122 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3123
3124 /* ENABLE_PCLK_BUS0 */
3125 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3126 ENABLE_PCLK_BUS, 2, 0, 0),
3127 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3128 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3129 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3130 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3131};
3132
3133/* CMU_BUS1 clocks */
3134static struct samsung_div_clock bus1_div_clks[] __initdata = {
3135 /* DIV_BUS1 */
3136 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3137 DIV_BUS, 0, 3),
3138};
3139
3140static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3141 /* ENABLE_ACLK_BUS1 */
3142 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3143 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3144 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3145 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3146 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3147 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3148
3149 /* ENABLE_PCLK_BUS1 */
3150 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3151 ENABLE_PCLK_BUS, 2, 0, 0),
3152 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3153 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3154 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3155 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3156};
3157
3158/* CMU_BUS2 clocks */
3159static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
3160 /* MUX_SEL_BUS2 */
3161 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3162 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3163};
3164
3165static struct samsung_div_clock bus2_div_clks[] __initdata = {
3166 /* DIV_BUS2 */
3167 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3168 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3169};
3170
3171static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3172 /* ENABLE_ACLK_BUS2 */
3173 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3174 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3175 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3176 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3177 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3178 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3179 1, CLK_IGNORE_UNUSED, 0),
3180 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3181 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3182 0, CLK_IGNORE_UNUSED, 0),
3183
3184 /* ENABLE_PCLK_BUS2 */
3185 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3186 ENABLE_PCLK_BUS, 2, 0, 0),
3187 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3188 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3189 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3190 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3191};
3192
3193#define CMU_BUS_INFO_CLKS(id) \
3194 .div_clks = bus##id##_div_clks, \
3195 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3196 .gate_clks = bus##id##_gate_clks, \
3197 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3198 .nr_clk_ids = BUSx_NR_CLK
3199
3200static struct samsung_cmu_info bus0_cmu_info __initdata = {
3201 CMU_BUS_INFO_CLKS(0),
3202 .clk_regs = bus01_clk_regs,
3203 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3204};
3205
3206static struct samsung_cmu_info bus1_cmu_info __initdata = {
3207 CMU_BUS_INFO_CLKS(1),
3208 .clk_regs = bus01_clk_regs,
3209 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3210};
3211
3212static struct samsung_cmu_info bus2_cmu_info __initdata = {
3213 CMU_BUS_INFO_CLKS(2),
3214 .mux_clks = bus2_mux_clks,
3215 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3216 .clk_regs = bus2_clk_regs,
3217 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3218};
3219
3220#define exynos5433_cmu_bus_init(id) \
3221static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3222{ \
3223 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3224} \
3225CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3226 "samsung,exynos5433-cmu-bus"#id, \
3227 exynos5433_cmu_bus##id##_init)
3228
3229exynos5433_cmu_bus_init(0);
3230exynos5433_cmu_bus_init(1);
3231exynos5433_cmu_bus_init(2);
3232
3233/*
3234 * Register offset definitions for CMU_G3D
3235 */
3236#define G3D_PLL_LOCK 0x0000
3237#define G3D_PLL_CON0 0x0100
3238#define G3D_PLL_CON1 0x0104
3239#define G3D_PLL_FREQ_DET 0x010c
3240#define MUX_SEL_G3D 0x0200
3241#define MUX_ENABLE_G3D 0x0300
3242#define MUX_STAT_G3D 0x0400
3243#define DIV_G3D 0x0600
3244#define DIV_G3D_PLL_FREQ_DET 0x0604
3245#define DIV_STAT_G3D 0x0700
3246#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3247#define ENABLE_ACLK_G3D 0x0800
3248#define ENABLE_PCLK_G3D 0x0900
3249#define ENABLE_SCLK_G3D 0x0a00
3250#define ENABLE_IP_G3D0 0x0b00
3251#define ENABLE_IP_G3D1 0x0b04
3252#define CLKOUT_CMU_G3D 0x0c00
3253#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3254#define CLK_STOPCTRL 0x1000
3255
3256static unsigned long g3d_clk_regs[] __initdata = {
3257 G3D_PLL_LOCK,
3258 G3D_PLL_CON0,
3259 G3D_PLL_CON1,
3260 G3D_PLL_FREQ_DET,
3261 MUX_SEL_G3D,
3262 MUX_ENABLE_G3D,
3263 MUX_STAT_G3D,
3264 DIV_G3D,
3265 DIV_G3D_PLL_FREQ_DET,
3266 DIV_STAT_G3D,
3267 DIV_STAT_G3D_PLL_FREQ_DET,
3268 ENABLE_ACLK_G3D,
3269 ENABLE_PCLK_G3D,
3270 ENABLE_SCLK_G3D,
3271 ENABLE_IP_G3D0,
3272 ENABLE_IP_G3D1,
3273 CLKOUT_CMU_G3D,
3274 CLKOUT_CMU_G3D_DIV_STAT,
3275 CLK_STOPCTRL,
3276};
3277
3278/* list of all parent clock list */
3279PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3280PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3281
3282static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
3283 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3284 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3285};
3286
3287static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3288 /* MUX_SEL_G3D */
3289 MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3290 MUX_SEL_G3D, 8, 1),
3291 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3292 MUX_SEL_G3D, 0, 1),
3293};
3294
3295static struct samsung_div_clock g3d_div_clks[] __initdata = {
3296 /* DIV_G3D */
3297 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3298 8, 2),
3299 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3300 4, 3),
3301 DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3302 0, 3),
3303};
3304
3305static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3306 /* ENABLE_ACLK_G3D */
3307 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3308 ENABLE_ACLK_G3D, 7, 0, 0),
3309 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3310 ENABLE_ACLK_G3D, 6, 0, 0),
3311 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3312 ENABLE_ACLK_G3D, 5, 0, 0),
3313 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3314 ENABLE_ACLK_G3D, 4, 0, 0),
3315 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3316 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3317 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3318 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3319 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3320 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3321 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3322 ENABLE_ACLK_G3D, 0, 0, 0),
3323
3324 /* ENABLE_PCLK_G3D */
3325 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3326 ENABLE_PCLK_G3D, 3, 0, 0),
3327 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3328 ENABLE_PCLK_G3D, 2, 0, 0),
3329 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3330 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3331 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3332 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3333
3334 /* ENABLE_SCLK_G3D */
3335 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3336 ENABLE_SCLK_G3D, 0, 0, 0),
3337};
3338
3339static struct samsung_cmu_info g3d_cmu_info __initdata = {
3340 .pll_clks = g3d_pll_clks,
3341 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3342 .mux_clks = g3d_mux_clks,
3343 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3344 .div_clks = g3d_div_clks,
3345 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3346 .gate_clks = g3d_gate_clks,
3347 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3348 .nr_clk_ids = G3D_NR_CLK,
3349 .clk_regs = g3d_clk_regs,
3350 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3351};
3352
3353static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3354{
3355 samsung_cmu_register_one(np, &g3d_cmu_info);
3356}
3357CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3358 exynos5433_cmu_g3d_init);
3359
3360/*
3361 * Register offset definitions for CMU_GSCL
3362 */
3363#define MUX_SEL_GSCL 0x0200
3364#define MUX_ENABLE_GSCL 0x0300
3365#define MUX_STAT_GSCL 0x0400
3366#define ENABLE_ACLK_GSCL 0x0800
3367#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3368#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3369#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3370#define ENABLE_PCLK_GSCL 0x0900
3371#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3372#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3373#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3374#define ENABLE_IP_GSCL0 0x0b00
3375#define ENABLE_IP_GSCL1 0x0b04
3376#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3377#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3378#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3379
3380static unsigned long gscl_clk_regs[] __initdata = {
3381 MUX_SEL_GSCL,
3382 MUX_ENABLE_GSCL,
3383 MUX_STAT_GSCL,
3384 ENABLE_ACLK_GSCL,
3385 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3386 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3387 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3388 ENABLE_PCLK_GSCL,
3389 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3390 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3391 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3392 ENABLE_IP_GSCL0,
3393 ENABLE_IP_GSCL1,
3394 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3395 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3396 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3397};
3398
3399/* list of all parent clock list */
3400PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3401PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3402
3403static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3404 /* MUX_SEL_GSCL */
3405 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3406 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3407 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3408 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3409};
3410
3411static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3412 /* ENABLE_ACLK_GSCL */
3413 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3414 ENABLE_ACLK_GSCL, 11, 0, 0),
3415 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3416 ENABLE_ACLK_GSCL, 10, 0, 0),
3417 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3418 ENABLE_ACLK_GSCL, 9, 0, 0),
3419 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3420 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3421 8, CLK_IGNORE_UNUSED, 0),
3422 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3423 ENABLE_ACLK_GSCL, 7, 0, 0),
3424 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3425 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3426 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3427 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
3428 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3429 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
3430 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3431 ENABLE_ACLK_GSCL, 3, 0, 0),
3432 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3433 ENABLE_ACLK_GSCL, 2, 0, 0),
3434 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3435 ENABLE_ACLK_GSCL, 1, 0, 0),
3436 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3437 ENABLE_ACLK_GSCL, 0, 0, 0),
3438
3439 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3440 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3441 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3442
3443 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3444 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3445 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3446
3447 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3448 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3449 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3450
3451 /* ENABLE_PCLK_GSCL */
3452 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3453 ENABLE_PCLK_GSCL, 7, 0, 0),
3454 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3455 ENABLE_PCLK_GSCL, 6, 0, 0),
3456 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3457 ENABLE_PCLK_GSCL, 5, 0, 0),
3458 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3459 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3460 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3461 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3462 3, CLK_IGNORE_UNUSED, 0),
3463 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3464 ENABLE_PCLK_GSCL, 2, 0, 0),
3465 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3466 ENABLE_PCLK_GSCL, 1, 0, 0),
3467 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3468 ENABLE_PCLK_GSCL, 0, 0, 0),
3469
3470 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3471 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3472 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3473
3474 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3475 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3476 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3477
3478 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3479 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3480 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3481};
3482
3483static struct samsung_cmu_info gscl_cmu_info __initdata = {
3484 .mux_clks = gscl_mux_clks,
3485 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3486 .gate_clks = gscl_gate_clks,
3487 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3488 .nr_clk_ids = GSCL_NR_CLK,
3489 .clk_regs = gscl_clk_regs,
3490 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3491};
3492
3493static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3494{
3495 samsung_cmu_register_one(np, &gscl_cmu_info);
3496}
3497CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3498 exynos5433_cmu_gscl_init);
3499
3500/*
3501 * Register offset definitions for CMU_APOLLO
3502 */
3503#define APOLLO_PLL_LOCK 0x0000
3504#define APOLLO_PLL_CON0 0x0100
3505#define APOLLO_PLL_CON1 0x0104
3506#define APOLLO_PLL_FREQ_DET 0x010c
3507#define MUX_SEL_APOLLO0 0x0200
3508#define MUX_SEL_APOLLO1 0x0204
3509#define MUX_SEL_APOLLO2 0x0208
3510#define MUX_ENABLE_APOLLO0 0x0300
3511#define MUX_ENABLE_APOLLO1 0x0304
3512#define MUX_ENABLE_APOLLO2 0x0308
3513#define MUX_STAT_APOLLO0 0x0400
3514#define MUX_STAT_APOLLO1 0x0404
3515#define MUX_STAT_APOLLO2 0x0408
3516#define DIV_APOLLO0 0x0600
3517#define DIV_APOLLO1 0x0604
3518#define DIV_APOLLO_PLL_FREQ_DET 0x0608
3519#define DIV_STAT_APOLLO0 0x0700
3520#define DIV_STAT_APOLLO1 0x0704
3521#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3522#define ENABLE_ACLK_APOLLO 0x0800
3523#define ENABLE_PCLK_APOLLO 0x0900
3524#define ENABLE_SCLK_APOLLO 0x0a00
3525#define ENABLE_IP_APOLLO0 0x0b00
3526#define ENABLE_IP_APOLLO1 0x0b04
3527#define CLKOUT_CMU_APOLLO 0x0c00
3528#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3529#define ARMCLK_STOPCTRL 0x1000
3530#define APOLLO_PWR_CTRL 0x1020
3531#define APOLLO_PWR_CTRL2 0x1024
3532#define APOLLO_INTR_SPREAD_ENABLE 0x1080
3533#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3534#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3535
3536static unsigned long apollo_clk_regs[] __initdata = {
3537 APOLLO_PLL_LOCK,
3538 APOLLO_PLL_CON0,
3539 APOLLO_PLL_CON1,
3540 APOLLO_PLL_FREQ_DET,
3541 MUX_SEL_APOLLO0,
3542 MUX_SEL_APOLLO1,
3543 MUX_SEL_APOLLO2,
3544 MUX_ENABLE_APOLLO0,
3545 MUX_ENABLE_APOLLO1,
3546 MUX_ENABLE_APOLLO2,
3547 MUX_STAT_APOLLO0,
3548 MUX_STAT_APOLLO1,
3549 MUX_STAT_APOLLO2,
3550 DIV_APOLLO0,
3551 DIV_APOLLO1,
3552 DIV_APOLLO_PLL_FREQ_DET,
3553 DIV_STAT_APOLLO0,
3554 DIV_STAT_APOLLO1,
3555 DIV_STAT_APOLLO_PLL_FREQ_DET,
3556 ENABLE_ACLK_APOLLO,
3557 ENABLE_PCLK_APOLLO,
3558 ENABLE_SCLK_APOLLO,
3559 ENABLE_IP_APOLLO0,
3560 ENABLE_IP_APOLLO1,
3561 CLKOUT_CMU_APOLLO,
3562 CLKOUT_CMU_APOLLO_DIV_STAT,
3563 ARMCLK_STOPCTRL,
3564 APOLLO_PWR_CTRL,
3565 APOLLO_PWR_CTRL2,
3566 APOLLO_INTR_SPREAD_ENABLE,
3567 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3568 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3569};
3570
3571/* list of all parent clock list */
3572PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3573PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3574PNAME(mout_apollo_p) = { "mout_apollo_pll",
3575 "mout_bus_pll_apollo_user", };
3576
3577static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
3578 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3579 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3580};
3581
3582static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3583 /* MUX_SEL_APOLLO0 */
3584 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3585 MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY),
3586
3587 /* MUX_SEL_APOLLO1 */
3588 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3589 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3590
3591 /* MUX_SEL_APOLLO2 */
3592 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3593 0, 1, 0, CLK_MUX_READ_ONLY),
3594};
3595
3596static struct samsung_div_clock apollo_div_clks[] __initdata = {
3597 /* DIV_APOLLO0 */
3598 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3599 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3600 CLK_DIVIDER_READ_ONLY),
3601 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3602 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3603 CLK_DIVIDER_READ_ONLY),
3604 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3605 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3606 CLK_DIVIDER_READ_ONLY),
3607 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3608 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3609 CLK_DIVIDER_READ_ONLY),
3610 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3611 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3612 CLK_DIVIDER_READ_ONLY),
3613 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3614 DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE,
3615 CLK_DIVIDER_READ_ONLY),
3616 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3617 DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE,
3618 CLK_DIVIDER_READ_ONLY),
3619
3620 /* DIV_APOLLO1 */
3621 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3622 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3623 CLK_DIVIDER_READ_ONLY),
3624 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3625 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3626 CLK_DIVIDER_READ_ONLY),
3627};
3628
3629static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3630 /* ENABLE_ACLK_APOLLO */
3631 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3632 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3633 6, CLK_IGNORE_UNUSED, 0),
3634 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3635 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3636 5, CLK_IGNORE_UNUSED, 0),
3637 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3638 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3639 4, CLK_IGNORE_UNUSED, 0),
3640 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3641 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3642 3, CLK_IGNORE_UNUSED, 0),
3643 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3644 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3645 2, CLK_IGNORE_UNUSED, 0),
3646 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3647 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3648 1, CLK_IGNORE_UNUSED, 0),
3649 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3650 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3651 0, CLK_IGNORE_UNUSED, 0),
3652
3653 /* ENABLE_PCLK_APOLLO */
3654 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3655 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3656 2, CLK_IGNORE_UNUSED, 0),
3657 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3658 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3659 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3660 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3661 0, CLK_IGNORE_UNUSED, 0),
3662
3663 /* ENABLE_SCLK_APOLLO */
3664 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3665 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3666 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3667 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3668 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
3669 ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
3670};
3671
3672static struct samsung_cmu_info apollo_cmu_info __initdata = {
3673 .pll_clks = apollo_pll_clks,
3674 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
3675 .mux_clks = apollo_mux_clks,
3676 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
3677 .div_clks = apollo_div_clks,
3678 .nr_div_clks = ARRAY_SIZE(apollo_div_clks),
3679 .gate_clks = apollo_gate_clks,
3680 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
3681 .nr_clk_ids = APOLLO_NR_CLK,
3682 .clk_regs = apollo_clk_regs,
3683 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
3684};
3685
3686static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3687{
3688 samsung_cmu_register_one(np, &apollo_cmu_info);
3689}
3690CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3691 exynos5433_cmu_apollo_init);
3692
3693/*
3694 * Register offset definitions for CMU_ATLAS
3695 */
3696#define ATLAS_PLL_LOCK 0x0000
3697#define ATLAS_PLL_CON0 0x0100
3698#define ATLAS_PLL_CON1 0x0104
3699#define ATLAS_PLL_FREQ_DET 0x010c
3700#define MUX_SEL_ATLAS0 0x0200
3701#define MUX_SEL_ATLAS1 0x0204
3702#define MUX_SEL_ATLAS2 0x0208
3703#define MUX_ENABLE_ATLAS0 0x0300
3704#define MUX_ENABLE_ATLAS1 0x0304
3705#define MUX_ENABLE_ATLAS2 0x0308
3706#define MUX_STAT_ATLAS0 0x0400
3707#define MUX_STAT_ATLAS1 0x0404
3708#define MUX_STAT_ATLAS2 0x0408
3709#define DIV_ATLAS0 0x0600
3710#define DIV_ATLAS1 0x0604
3711#define DIV_ATLAS_PLL_FREQ_DET 0x0608
3712#define DIV_STAT_ATLAS0 0x0700
3713#define DIV_STAT_ATLAS1 0x0704
3714#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3715#define ENABLE_ACLK_ATLAS 0x0800
3716#define ENABLE_PCLK_ATLAS 0x0900
3717#define ENABLE_SCLK_ATLAS 0x0a00
3718#define ENABLE_IP_ATLAS0 0x0b00
3719#define ENABLE_IP_ATLAS1 0x0b04
3720#define CLKOUT_CMU_ATLAS 0x0c00
3721#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3722#define ARMCLK_STOPCTRL 0x1000
3723#define ATLAS_PWR_CTRL 0x1020
3724#define ATLAS_PWR_CTRL2 0x1024
3725#define ATLAS_INTR_SPREAD_ENABLE 0x1080
3726#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3727#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3728
3729static unsigned long atlas_clk_regs[] __initdata = {
3730 ATLAS_PLL_LOCK,
3731 ATLAS_PLL_CON0,
3732 ATLAS_PLL_CON1,
3733 ATLAS_PLL_FREQ_DET,
3734 MUX_SEL_ATLAS0,
3735 MUX_SEL_ATLAS1,
3736 MUX_SEL_ATLAS2,
3737 MUX_ENABLE_ATLAS0,
3738 MUX_ENABLE_ATLAS1,
3739 MUX_ENABLE_ATLAS2,
3740 MUX_STAT_ATLAS0,
3741 MUX_STAT_ATLAS1,
3742 MUX_STAT_ATLAS2,
3743 DIV_ATLAS0,
3744 DIV_ATLAS1,
3745 DIV_ATLAS_PLL_FREQ_DET,
3746 DIV_STAT_ATLAS0,
3747 DIV_STAT_ATLAS1,
3748 DIV_STAT_ATLAS_PLL_FREQ_DET,
3749 ENABLE_ACLK_ATLAS,
3750 ENABLE_PCLK_ATLAS,
3751 ENABLE_SCLK_ATLAS,
3752 ENABLE_IP_ATLAS0,
3753 ENABLE_IP_ATLAS1,
3754 CLKOUT_CMU_ATLAS,
3755 CLKOUT_CMU_ATLAS_DIV_STAT,
3756 ARMCLK_STOPCTRL,
3757 ATLAS_PWR_CTRL,
3758 ATLAS_PWR_CTRL2,
3759 ATLAS_INTR_SPREAD_ENABLE,
3760 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3761 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3762};
3763
3764/* list of all parent clock list */
3765PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3766PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3767PNAME(mout_atlas_p) = { "mout_atlas_pll",
3768 "mout_bus_pll_atlas_user", };
3769
3770static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
3771 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3772 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3773};
3774
3775static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3776 /* MUX_SEL_ATLAS0 */
3777 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3778 MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY),
3779
3780 /* MUX_SEL_ATLAS1 */
3781 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3782 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3783
3784 /* MUX_SEL_ATLAS2 */
3785 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3786 0, 1, 0, CLK_MUX_READ_ONLY),
3787};
3788
3789static struct samsung_div_clock atlas_div_clks[] __initdata = {
3790 /* DIV_ATLAS0 */
3791 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3792 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3793 CLK_DIVIDER_READ_ONLY),
3794 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3795 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3796 CLK_DIVIDER_READ_ONLY),
3797 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3798 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3799 CLK_DIVIDER_READ_ONLY),
3800 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3801 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3802 CLK_DIVIDER_READ_ONLY),
3803 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3804 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3805 CLK_DIVIDER_READ_ONLY),
3806 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3807 DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE,
3808 CLK_DIVIDER_READ_ONLY),
3809 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3810 DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE,
3811 CLK_DIVIDER_READ_ONLY),
3812
3813 /* DIV_ATLAS1 */
3814 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3815 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3816 CLK_DIVIDER_READ_ONLY),
3817 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3818 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3819 CLK_DIVIDER_READ_ONLY),
3820};
3821
3822static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3823 /* ENABLE_ACLK_ATLAS */
3824 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3825 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3826 9, CLK_IGNORE_UNUSED, 0),
3827 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3828 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3829 8, CLK_IGNORE_UNUSED, 0),
3830 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3831 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3832 7, CLK_IGNORE_UNUSED, 0),
3833 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3834 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3835 6, CLK_IGNORE_UNUSED, 0),
3836 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3837 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3838 5, CLK_IGNORE_UNUSED, 0),
3839 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3840 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3841 4, CLK_IGNORE_UNUSED, 0),
3842 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3843 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3844 3, CLK_IGNORE_UNUSED, 0),
3845 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3846 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3847 2, CLK_IGNORE_UNUSED, 0),
3848 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3849 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3850 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3851 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3852
3853 /* ENABLE_PCLK_ATLAS */
3854 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3855 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3856 5, CLK_IGNORE_UNUSED, 0),
3857 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3858 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3859 4, CLK_IGNORE_UNUSED, 0),
3860 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3861 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3862 3, CLK_IGNORE_UNUSED, 0),
3863 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3864 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3865 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3866 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3867 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3868 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3869
3870 /* ENABLE_SCLK_ATLAS */
3871 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3872 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3873 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3874 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3875 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3876 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3877 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3878 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3879 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3880 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3881 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3882 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3883 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3884 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3885 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3886 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3887 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3888 ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3889};
3890
3891static struct samsung_cmu_info atlas_cmu_info __initdata = {
3892 .pll_clks = atlas_pll_clks,
3893 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
3894 .mux_clks = atlas_mux_clks,
3895 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
3896 .div_clks = atlas_div_clks,
3897 .nr_div_clks = ARRAY_SIZE(atlas_div_clks),
3898 .gate_clks = atlas_gate_clks,
3899 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
3900 .nr_clk_ids = ATLAS_NR_CLK,
3901 .clk_regs = atlas_clk_regs,
3902 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
3903};
3904
3905static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3906{
3907 samsung_cmu_register_one(np, &atlas_cmu_info);
3908}
3909CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3910 exynos5433_cmu_atlas_init);
3911
3912/*
3913 * Register offset definitions for CMU_MSCL
3914 */
3915#define MUX_SEL_MSCL0 0x0200
3916#define MUX_SEL_MSCL1 0x0204
3917#define MUX_ENABLE_MSCL0 0x0300
3918#define MUX_ENABLE_MSCL1 0x0304
3919#define MUX_STAT_MSCL0 0x0400
3920#define MUX_STAT_MSCL1 0x0404
3921#define DIV_MSCL 0x0600
3922#define DIV_STAT_MSCL 0x0700
3923#define ENABLE_ACLK_MSCL 0x0800
3924#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3925#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3926#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3927#define ENABLE_PCLK_MSCL 0x0900
3928#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3929#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3930#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x000c
3931#define ENABLE_SCLK_MSCL 0x0a00
3932#define ENABLE_IP_MSCL0 0x0b00
3933#define ENABLE_IP_MSCL1 0x0b04
3934#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3935#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3936#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3937
3938static unsigned long mscl_clk_regs[] __initdata = {
3939 MUX_SEL_MSCL0,
3940 MUX_SEL_MSCL1,
3941 MUX_ENABLE_MSCL0,
3942 MUX_ENABLE_MSCL1,
3943 MUX_STAT_MSCL0,
3944 MUX_STAT_MSCL1,
3945 DIV_MSCL,
3946 DIV_STAT_MSCL,
3947 ENABLE_ACLK_MSCL,
3948 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3949 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3950 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3951 ENABLE_PCLK_MSCL,
3952 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3953 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3954 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3955 ENABLE_SCLK_MSCL,
3956 ENABLE_IP_MSCL0,
3957 ENABLE_IP_MSCL1,
3958 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3959 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3960 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3961};
3962
3963/* list of all parent clock list */
3964PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3965PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3966PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3967 "mout_aclk_mscl_400_user", };
3968
3969static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3970 /* MUX_SEL_MSCL0 */
3971 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3972 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3973 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3974 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3975
3976 /* MUX_SEL_MSCL1 */
3977 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3978 MUX_SEL_MSCL1, 0, 1),
3979};
3980
3981static struct samsung_div_clock mscl_div_clks[] __initdata = {
3982 /* DIV_MSCL */
3983 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3984 DIV_MSCL, 0, 3),
3985};
3986
3987static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3988 /* ENABLE_ACLK_MSCL */
3989 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3990 ENABLE_ACLK_MSCL, 9, 0, 0),
3991 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
3992 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
3993 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
3994 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
3995 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3996 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
3997 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3998 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
3999 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4000 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4001 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4002 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4003 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4004 ENABLE_ACLK_MSCL, 2, 0, 0),
4005 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4006 ENABLE_ACLK_MSCL, 1, 0, 0),
4007 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4008 ENABLE_ACLK_MSCL, 0, 0, 0),
4009
4010 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4011 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4012 "mout_aclk_mscl_400_user",
4013 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4014 0, CLK_IGNORE_UNUSED, 0),
4015
4016 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4017 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4018 "mout_aclk_mscl_400_user",
4019 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4020 0, CLK_IGNORE_UNUSED, 0),
4021
4022 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4023 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4024 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4025 0, CLK_IGNORE_UNUSED, 0),
4026
4027 /* ENABLE_PCLK_MSCL */
4028 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4029 ENABLE_PCLK_MSCL, 7, 0, 0),
4030 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4031 ENABLE_PCLK_MSCL, 6, 0, 0),
4032 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4033 ENABLE_PCLK_MSCL, 5, 0, 0),
4034 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4035 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4036 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4037 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4038 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4039 ENABLE_PCLK_MSCL, 2, 0, 0),
4040 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4041 ENABLE_PCLK_MSCL, 1, 0, 0),
4042 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4043 ENABLE_PCLK_MSCL, 0, 0, 0),
4044
4045 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4046 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4047 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4048 0, CLK_IGNORE_UNUSED, 0),
4049
4050 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4051 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4052 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4053 0, CLK_IGNORE_UNUSED, 0),
4054
4055 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4056 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4057 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4058 0, CLK_IGNORE_UNUSED, 0),
4059
4060 /* ENABLE_SCLK_MSCL */
4061 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4062 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4063};
4064
4065static struct samsung_cmu_info mscl_cmu_info __initdata = {
4066 .mux_clks = mscl_mux_clks,
4067 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
4068 .div_clks = mscl_div_clks,
4069 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
4070 .gate_clks = mscl_gate_clks,
4071 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
4072 .nr_clk_ids = MSCL_NR_CLK,
4073 .clk_regs = mscl_clk_regs,
4074 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4075};
4076
4077static void __init exynos5433_cmu_mscl_init(struct device_node *np)
4078{
4079 samsung_cmu_register_one(np, &mscl_cmu_info);
4080}
4081CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4082 exynos5433_cmu_mscl_init);
4083
4084/*
4085 * Register offset definitions for CMU_MFC
4086 */
4087#define MUX_SEL_MFC 0x0200
4088#define MUX_ENABLE_MFC 0x0300
4089#define MUX_STAT_MFC 0x0400
4090#define DIV_MFC 0x0600
4091#define DIV_STAT_MFC 0x0700
4092#define ENABLE_ACLK_MFC 0x0800
4093#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4094#define ENABLE_PCLK_MFC 0x0900
4095#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4096#define ENABLE_IP_MFC0 0x0b00
4097#define ENABLE_IP_MFC1 0x0b04
4098#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4099
4100static unsigned long mfc_clk_regs[] __initdata = {
4101 MUX_SEL_MFC,
4102 MUX_ENABLE_MFC,
4103 MUX_STAT_MFC,
4104 DIV_MFC,
4105 DIV_STAT_MFC,
4106 ENABLE_ACLK_MFC,
4107 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4108 ENABLE_PCLK_MFC,
4109 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4110 ENABLE_IP_MFC0,
4111 ENABLE_IP_MFC1,
4112 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4113};
4114
4115PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4116
4117static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
4118 /* MUX_SEL_MFC */
4119 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4120 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4121};
4122
4123static struct samsung_div_clock mfc_div_clks[] __initdata = {
4124 /* DIV_MFC */
4125 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4126 DIV_MFC, 0, 2),
4127};
4128
4129static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4130 /* ENABLE_ACLK_MFC */
4131 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4132 ENABLE_ACLK_MFC, 6, 0, 0),
4133 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4134 ENABLE_ACLK_MFC, 5, 0, 0),
4135 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4136 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4137 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4138 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4139 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4140 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4141 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4142 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4143 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4144 ENABLE_ACLK_MFC, 0, 0, 0),
4145
4146 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4147 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4148 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4149 1, CLK_IGNORE_UNUSED, 0),
4150 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4151 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4152 0, CLK_IGNORE_UNUSED, 0),
4153
4154 /* ENABLE_PCLK_MFC */
4155 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4156 ENABLE_PCLK_MFC, 4, 0, 0),
4157 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4158 ENABLE_PCLK_MFC, 3, 0, 0),
4159 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4160 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4161 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4162 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4163 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4164 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4165
4166 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4167 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4168 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4169 1, CLK_IGNORE_UNUSED, 0),
4170 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4171 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4172 0, CLK_IGNORE_UNUSED, 0),
4173};
4174
4175static struct samsung_cmu_info mfc_cmu_info __initdata = {
4176 .mux_clks = mfc_mux_clks,
4177 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4178 .div_clks = mfc_div_clks,
4179 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4180 .gate_clks = mfc_gate_clks,
4181 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4182 .nr_clk_ids = MFC_NR_CLK,
4183 .clk_regs = mfc_clk_regs,
4184 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4185};
4186
4187static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4188{
4189 samsung_cmu_register_one(np, &mfc_cmu_info);
4190}
4191CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4192 exynos5433_cmu_mfc_init);
4193
4194/*
4195 * Register offset definitions for CMU_HEVC
4196 */
4197#define MUX_SEL_HEVC 0x0200
4198#define MUX_ENABLE_HEVC 0x0300
4199#define MUX_STAT_HEVC 0x0400
4200#define DIV_HEVC 0x0600
4201#define DIV_STAT_HEVC 0x0700
4202#define ENABLE_ACLK_HEVC 0x0800
4203#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4204#define ENABLE_PCLK_HEVC 0x0900
4205#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4206#define ENABLE_IP_HEVC0 0x0b00
4207#define ENABLE_IP_HEVC1 0x0b04
4208#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4209
4210static unsigned long hevc_clk_regs[] __initdata = {
4211 MUX_SEL_HEVC,
4212 MUX_ENABLE_HEVC,
4213 MUX_STAT_HEVC,
4214 DIV_HEVC,
4215 DIV_STAT_HEVC,
4216 ENABLE_ACLK_HEVC,
4217 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4218 ENABLE_PCLK_HEVC,
4219 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4220 ENABLE_IP_HEVC0,
4221 ENABLE_IP_HEVC1,
4222 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4223};
4224
4225PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4226
4227static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
4228 /* MUX_SEL_HEVC */
4229 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4230 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4231};
4232
4233static struct samsung_div_clock hevc_div_clks[] __initdata = {
4234 /* DIV_HEVC */
4235 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4236 DIV_HEVC, 0, 2),
4237};
4238
4239static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4240 /* ENABLE_ACLK_HEVC */
4241 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4242 ENABLE_ACLK_HEVC, 6, 0, 0),
4243 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4244 ENABLE_ACLK_HEVC, 5, 0, 0),
4245 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4246 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4247 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4248 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4249 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4250 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4251 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4252 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4253 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4254 ENABLE_ACLK_HEVC, 0, 0, 0),
4255
4256 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4257 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4258 "mout_aclk_hevc_400_user",
4259 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4260 1, CLK_IGNORE_UNUSED, 0),
4261 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4262 "mout_aclk_hevc_400_user",
4263 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4264 0, CLK_IGNORE_UNUSED, 0),
4265
4266 /* ENABLE_PCLK_HEVC */
4267 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4268 ENABLE_PCLK_HEVC, 4, 0, 0),
4269 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4270 ENABLE_PCLK_HEVC, 3, 0, 0),
4271 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4272 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4273 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4274 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4275 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4276 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4277
4278 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4279 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4280 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4281 1, CLK_IGNORE_UNUSED, 0),
4282 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4283 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4284 0, CLK_IGNORE_UNUSED, 0),
4285};
4286
4287static struct samsung_cmu_info hevc_cmu_info __initdata = {
4288 .mux_clks = hevc_mux_clks,
4289 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4290 .div_clks = hevc_div_clks,
4291 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4292 .gate_clks = hevc_gate_clks,
4293 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4294 .nr_clk_ids = HEVC_NR_CLK,
4295 .clk_regs = hevc_clk_regs,
4296 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4297};
4298
4299static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4300{
4301 samsung_cmu_register_one(np, &hevc_cmu_info);
4302}
4303CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4304 exynos5433_cmu_hevc_init);
4305
4306/*
4307 * Register offset definitions for CMU_ISP
4308 */
4309#define MUX_SEL_ISP 0x0200
4310#define MUX_ENABLE_ISP 0x0300
4311#define MUX_STAT_ISP 0x0400
4312#define DIV_ISP 0x0600
4313#define DIV_STAT_ISP 0x0700
4314#define ENABLE_ACLK_ISP0 0x0800
4315#define ENABLE_ACLK_ISP1 0x0804
4316#define ENABLE_ACLK_ISP2 0x0808
4317#define ENABLE_PCLK_ISP 0x0900
4318#define ENABLE_SCLK_ISP 0x0a00
4319#define ENABLE_IP_ISP0 0x0b00
4320#define ENABLE_IP_ISP1 0x0b04
4321#define ENABLE_IP_ISP2 0x0b08
4322#define ENABLE_IP_ISP3 0x0b0c
4323
4324static unsigned long isp_clk_regs[] __initdata = {
4325 MUX_SEL_ISP,
4326 MUX_ENABLE_ISP,
4327 MUX_STAT_ISP,
4328 DIV_ISP,
4329 DIV_STAT_ISP,
4330 ENABLE_ACLK_ISP0,
4331 ENABLE_ACLK_ISP1,
4332 ENABLE_ACLK_ISP2,
4333 ENABLE_PCLK_ISP,
4334 ENABLE_SCLK_ISP,
4335 ENABLE_IP_ISP0,
4336 ENABLE_IP_ISP1,
4337 ENABLE_IP_ISP2,
4338 ENABLE_IP_ISP3,
4339};
4340
4341PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4342PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4343
4344static struct samsung_mux_clock isp_mux_clks[] __initdata = {
4345 /* MUX_SEL_ISP */
4346 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4347 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4348 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4349 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4350};
4351
4352static struct samsung_div_clock isp_div_clks[] __initdata = {
4353 /* DIV_ISP */
4354 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4355 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4356 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4357 DIV_ISP, 8, 3),
4358 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4359 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4360 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4361 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4362};
4363
4364static struct samsung_gate_clock isp_gate_clks[] __initdata = {
4365 /* ENABLE_ACLK_ISP0 */
4366 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4367 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4368 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4369 ENABLE_ACLK_ISP0, 5, 0, 0),
4370 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4371 ENABLE_ACLK_ISP0, 4, 0, 0),
4372 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4373 ENABLE_ACLK_ISP0, 3, 0, 0),
4374 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4375 ENABLE_ACLK_ISP0, 2, 0, 0),
4376 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4377 ENABLE_ACLK_ISP0, 1, 0, 0),
4378 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4379 ENABLE_ACLK_ISP0, 0, 0, 0),
4380
4381 /* ENABLE_ACLK_ISP1 */
4382 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4383 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4384 17, CLK_IGNORE_UNUSED, 0),
4385 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4386 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4387 16, CLK_IGNORE_UNUSED, 0),
4388 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4389 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4390 15, CLK_IGNORE_UNUSED, 0),
4391 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4392 "div_pclk_isp", ENABLE_ACLK_ISP1,
4393 14, CLK_IGNORE_UNUSED, 0),
4394 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4395 "div_pclk_isp", ENABLE_ACLK_ISP1,
4396 13, CLK_IGNORE_UNUSED, 0),
4397 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4398 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4399 12, CLK_IGNORE_UNUSED, 0),
4400 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4401 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4402 11, CLK_IGNORE_UNUSED, 0),
4403 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4404 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4405 10, CLK_IGNORE_UNUSED, 0),
4406 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4407 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4408 9, CLK_IGNORE_UNUSED, 0),
4409 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4410 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4411 8, CLK_IGNORE_UNUSED, 0),
4412 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4413 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4414 7, CLK_IGNORE_UNUSED, 0),
4415 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4416 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4417 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4418 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4419 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4420 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4421 4, CLK_IGNORE_UNUSED, 0),
4422 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4423 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4424 3, CLK_IGNORE_UNUSED, 0),
4425 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4426 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4427 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4428 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4429 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4430 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4431
4432 /* ENABLE_ACLK_ISP2 */
4433 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4434 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4435 13, CLK_IGNORE_UNUSED, 0),
4436 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4437 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4438 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4439 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4440 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4441 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4442 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4443 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4444 9, CLK_IGNORE_UNUSED, 0),
4445 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4446 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4447 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4448 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4449 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4450 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4451 6, CLK_IGNORE_UNUSED, 0),
4452 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4453 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4454 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4455 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4456 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4457 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4458 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4459 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4460 2, CLK_IGNORE_UNUSED, 0),
4461 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4462 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4463 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4464 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4465
4466 /* ENABLE_PCLK_ISP */
4467 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4468 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4469 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4470 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4471 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4472 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4473 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4474 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4475 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4476 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4477 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4478 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4479 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4480 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4481 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4482 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4483 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4484 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4485 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4486 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4487 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4488 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4489 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4490 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4491 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4492 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4493 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4494 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4495 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4496 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4497 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4498 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4499 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4500 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4501 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4502 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4503 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4504 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4505 7, CLK_IGNORE_UNUSED, 0),
4506 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4507 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4508 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4509 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4510 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4511 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4512 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4513 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4514 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4515 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4516 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4517 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4518 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4519 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4520
4521 /* ENABLE_SCLK_ISP */
4522 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4523 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4524 5, CLK_IGNORE_UNUSED, 0),
4525 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4526 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4527 4, CLK_IGNORE_UNUSED, 0),
4528 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4529 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4530 3, CLK_IGNORE_UNUSED, 0),
4531 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4532 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4533 2, CLK_IGNORE_UNUSED, 0),
4534 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4535 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4536 1, CLK_IGNORE_UNUSED, 0),
4537 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4538 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4539 0, CLK_IGNORE_UNUSED, 0),
4540};
4541
4542static struct samsung_cmu_info isp_cmu_info __initdata = {
4543 .mux_clks = isp_mux_clks,
4544 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4545 .div_clks = isp_div_clks,
4546 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4547 .gate_clks = isp_gate_clks,
4548 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4549 .nr_clk_ids = ISP_NR_CLK,
4550 .clk_regs = isp_clk_regs,
4551 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4552};
4553
4554static void __init exynos5433_cmu_isp_init(struct device_node *np)
4555{
4556 samsung_cmu_register_one(np, &isp_cmu_info);
4557}
4558CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4559 exynos5433_cmu_isp_init);
4560
4561/*
4562 * Register offset definitions for CMU_CAM0
4563 */
4564#define MUX_SEL_CAM00 0x0200
4565#define MUX_SEL_CAM01 0x0204
4566#define MUX_SEL_CAM02 0x0208
4567#define MUX_SEL_CAM03 0x020c
4568#define MUX_SEL_CAM04 0x0210
4569#define MUX_ENABLE_CAM00 0x0300
4570#define MUX_ENABLE_CAM01 0x0304
4571#define MUX_ENABLE_CAM02 0x0308
4572#define MUX_ENABLE_CAM03 0x030c
4573#define MUX_ENABLE_CAM04 0x0310
4574#define MUX_STAT_CAM00 0x0400
4575#define MUX_STAT_CAM01 0x0404
4576#define MUX_STAT_CAM02 0x0408
4577#define MUX_STAT_CAM03 0x040c
4578#define MUX_STAT_CAM04 0x0410
4579#define MUX_IGNORE_CAM01 0x0504
4580#define DIV_CAM00 0x0600
4581#define DIV_CAM01 0x0604
4582#define DIV_CAM02 0x0608
4583#define DIV_CAM03 0x060c
4584#define DIV_STAT_CAM00 0x0700
4585#define DIV_STAT_CAM01 0x0704
4586#define DIV_STAT_CAM02 0x0708
4587#define DIV_STAT_CAM03 0x070c
4588#define ENABLE_ACLK_CAM00 0X0800
4589#define ENABLE_ACLK_CAM01 0X0804
4590#define ENABLE_ACLK_CAM02 0X0808
4591#define ENABLE_PCLK_CAM0 0X0900
4592#define ENABLE_SCLK_CAM0 0X0a00
4593#define ENABLE_IP_CAM00 0X0b00
4594#define ENABLE_IP_CAM01 0X0b04
4595#define ENABLE_IP_CAM02 0X0b08
4596#define ENABLE_IP_CAM03 0X0b0C
4597
4598static unsigned long cam0_clk_regs[] __initdata = {
4599 MUX_SEL_CAM00,
4600 MUX_SEL_CAM01,
4601 MUX_SEL_CAM02,
4602 MUX_SEL_CAM03,
4603 MUX_SEL_CAM04,
4604 MUX_ENABLE_CAM00,
4605 MUX_ENABLE_CAM01,
4606 MUX_ENABLE_CAM02,
4607 MUX_ENABLE_CAM03,
4608 MUX_ENABLE_CAM04,
4609 MUX_STAT_CAM00,
4610 MUX_STAT_CAM01,
4611 MUX_STAT_CAM02,
4612 MUX_STAT_CAM03,
4613 MUX_STAT_CAM04,
4614 MUX_IGNORE_CAM01,
4615 DIV_CAM00,
4616 DIV_CAM01,
4617 DIV_CAM02,
4618 DIV_CAM03,
4619 DIV_STAT_CAM00,
4620 DIV_STAT_CAM01,
4621 DIV_STAT_CAM02,
4622 DIV_STAT_CAM03,
4623 ENABLE_ACLK_CAM00,
4624 ENABLE_ACLK_CAM01,
4625 ENABLE_ACLK_CAM02,
4626 ENABLE_PCLK_CAM0,
4627 ENABLE_SCLK_CAM0,
4628 ENABLE_IP_CAM00,
4629 ENABLE_IP_CAM01,
4630 ENABLE_IP_CAM02,
4631 ENABLE_IP_CAM03,
4632};
4633PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4634PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4635PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4636
4637PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4638 "phyclk_rxbyteclkhs0_s4_phy", };
4639PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4640 "phyclk_rxbyteclkhs0_s2a_phy", };
4641
4642PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4643 "mout_aclk_cam0_333_user", };
4644PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4645 "mout_aclk_cam0_400_user", };
4646PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4647 "mout_aclk_cam0_333_user", };
4648PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4649 "mout_aclk_cam0_400_user", };
4650PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4651 "mout_aclk_cam0_333_user", };
4652PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4653 "mout_aclk_cam0_400_user", };
4654PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4655 "mout_aclk_cam0_333_user", };
4656
4657PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4658 "mout_aclk_cam0_333_user" };
4659PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4660 "mout_aclk_cam0_400_user", };
4661PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4662 "mout_aclk_cam0_333_user", };
4663PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4664 "mout_aclk-cam0_400_user", };
4665PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4666 "mout_aclk_cam0_333_user", };
4667PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4668 "mout_aclk_cam0_400_user", };
4669PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4670 "mout_aclk_cam0_333_user", };
4671PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4672 "mout_aclk_cam0_400_user", };
4673
4674PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4675 "div_pclk_lite_d", };
4676PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4677 "div_pclk_pixelasync_lite_c", };
4678PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4679 "div_pclk_lite_b", };
4680PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4681 "mout_aclk_cam0_333_user", };
4682PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4683 "mout_aclk_cam0_400_user", };
4684PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4685 "mout_sclk_pixelasync_lite_c_init_a",
4686 "mout_aclk_cam0_400_user", };
4687PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4688 "mout_aclk_cam0_552_user",
4689 "mout_aclk_cam0_400_user", };
4690
4691static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = {
4692 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4693 NULL, CLK_IS_ROOT, 100000000),
4694 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4695 NULL, CLK_IS_ROOT, 100000000),
4696};
4697
4698static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
4699 /* MUX_SEL_CAM00 */
4700 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4701 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4702 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4703 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4704 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4705 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4706
4707 /* MUX_SEL_CAM01 */
4708 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4709 "mout_phyclk_rxbyteclkhs0_s4_user",
4710 mout_phyclk_rxbyteclkhs0_s4_user_p,
4711 MUX_SEL_CAM01, 4, 1),
4712 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4713 "mout_phyclk_rxbyteclkhs0_s2a_user",
4714 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4715 MUX_SEL_CAM01, 0, 1),
4716
4717 /* MUX_SEL_CAM02 */
4718 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4719 MUX_SEL_CAM02, 24, 1),
4720 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4721 MUX_SEL_CAM02, 20, 1),
4722 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4723 MUX_SEL_CAM02, 16, 1),
4724 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4725 MUX_SEL_CAM02, 12, 1),
4726 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4727 MUX_SEL_CAM02, 8, 1),
4728 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4729 MUX_SEL_CAM02, 4, 1),
4730 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4731 MUX_SEL_CAM02, 0, 1),
4732
4733 /* MUX_SEL_CAM03 */
4734 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4735 MUX_SEL_CAM03, 28, 1),
4736 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4737 MUX_SEL_CAM03, 24, 1),
4738 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4739 MUX_SEL_CAM03, 20, 1),
4740 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4741 MUX_SEL_CAM03, 16, 1),
4742 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4743 MUX_SEL_CAM03, 12, 1),
4744 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4745 MUX_SEL_CAM03, 8, 1),
4746 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4747 MUX_SEL_CAM03, 4, 1),
4748 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4749 MUX_SEL_CAM03, 0, 1),
4750
4751 /* MUX_SEL_CAM04 */
4752 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4753 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4754 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4755 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1),
4756 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4757 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1),
4758 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4759 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1),
4760 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4761 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1),
4762 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4763 "mout_sclk_pixelasync_lite_c_init_b",
4764 mout_sclk_pixelasync_lite_c_init_b_p,
4765 MUX_SEL_CAM04, 24, 1),
4766 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4767 "mout_sclk_pixelasync_lite_c_init_a",
4768 mout_sclk_pixelasync_lite_c_init_a_p,
4769 MUX_SEL_CAM04, 24, 1),
4770};
4771
4772static struct samsung_div_clock cam0_div_clks[] __initdata = {
4773 /* DIV_CAM00 */
4774 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4775 DIV_CAM00, 8, 2),
4776 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4777 DIV_CAM00, 4, 3),
4778 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4779 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4780
4781 /* DIV_CAM01 */
4782 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4783 DIV_CAM01, 20, 2),
4784 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4785 DIV_CAM01, 16, 3),
4786 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4787 DIV_CAM01, 12, 2),
4788 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4789 DIV_CAM01, 8, 3),
4790 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4791 DIV_CAM01, 4, 2),
4792 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4793 DIV_CAM01, 0, 3),
4794
4795 /* DIV_CAM02 */
4796 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4797 DIV_CAM02, 20, 3),
4798 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4799 DIV_CAM02, 16, 3),
4800 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4801 DIV_CAM02, 12, 2),
4802 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4803 DIV_CAM02, 8, 3),
4804 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4805 DIV_CAM02, 4, 2),
4806 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4807 DIV_CAM02, 0, 3),
4808
4809 /* DIV_CAM03 */
4810 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4811 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4812 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4813 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4814 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4815 "div_sclk_pixelasync_lite_c_init",
4816 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4817};
4818
4819static struct samsung_gate_clock cam0_gate_clks[] __initdata = {
4820 /* ENABLE_ACLK_CAM00 */
4821 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4822 6, 0, 0),
4823 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4824 5, 0, 0),
4825 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4826 4, 0, 0),
4827 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4828 3, 0, 0),
4829 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4830 ENABLE_ACLK_CAM00, 2, 0, 0),
4831 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4832 ENABLE_ACLK_CAM00, 1, 0, 0),
4833 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4834 ENABLE_ACLK_CAM00, 0, 0, 0),
4835
4836 /* ENABLE_ACLK_CAM01 */
4837 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4838 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4839 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4840 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4841 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4842 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4843 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4844 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4845 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4846 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4847 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4848 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4849 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4850 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4851 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4852 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4853 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4854 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4855 23, CLK_IGNORE_UNUSED, 0),
4856 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4857 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4858 22, CLK_IGNORE_UNUSED, 0),
4859 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4860 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4861 21, CLK_IGNORE_UNUSED, 0),
4862 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4863 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4864 20, CLK_IGNORE_UNUSED, 0),
4865 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4866 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4867 19, CLK_IGNORE_UNUSED, 0),
4868 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4869 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4870 18, CLK_IGNORE_UNUSED, 0),
4871 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4872 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4873 17, CLK_IGNORE_UNUSED, 0),
4874 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4875 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4876 16, CLK_IGNORE_UNUSED, 0),
4877 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4878 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4879 15, CLK_IGNORE_UNUSED, 0),
4880 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4881 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4882 14, CLK_IGNORE_UNUSED, 0),
4883 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4884 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4885 13, CLK_IGNORE_UNUSED, 0),
4886 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4887 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4888 12, CLK_IGNORE_UNUSED, 0),
4889 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4890 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4891 11, CLK_IGNORE_UNUSED, 0),
4892 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4893 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4894 10, CLK_IGNORE_UNUSED, 0),
4895 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4896 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4897 9, CLK_IGNORE_UNUSED, 0),
4898 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4899 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4900 8, CLK_IGNORE_UNUSED, 0),
4901 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4902 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4903 7, CLK_IGNORE_UNUSED, 0),
4904 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4905 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4906 6, CLK_IGNORE_UNUSED, 0),
4907 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4908 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4909 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4910 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4911 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4912 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4913 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4914 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4915 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4916 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4917 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4918 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4919
4920 /* ENABLE_ACLK_CAM02 */
4921 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4922 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4923 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4924 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4925 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4926 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4927 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4928 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4929 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4930 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4931 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4932 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4933 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4934 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4935 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4936 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4937 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4938 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4939 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4940 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4941
4942 /* ENABLE_PCLK_CAM0 */
4943 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4944 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4945 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4946 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4947 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4948 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4949 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4950 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4951 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4952 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4953 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4954 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4955 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4956 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4957 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4958 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4959 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4960 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4961 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4962 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4963 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4964 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4965 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4966 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
4967 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4968 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
4969 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
4970 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4971 12, CLK_IGNORE_UNUSED, 0),
4972 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
4973 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4974 11, CLK_IGNORE_UNUSED, 0),
4975 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
4976 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4977 10, CLK_IGNORE_UNUSED, 0),
4978 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
4979 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
4980 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
4981 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
4982 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
4983 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
4984 7, CLK_IGNORE_UNUSED, 0),
4985 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
4986 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
4987 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
4988 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
4989 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
4990 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
4991 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
4992 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
4993 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
4994 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
4995 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
4996 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
4997 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
4998 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
4999
5000 /* ENABLE_SCLK_CAM0 */
5001 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5002 "mout_phyclk_rxbyteclkhs0_s4_user",
5003 ENABLE_SCLK_CAM0, 8, 0, 0),
5004 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5005 "mout_phyclk_rxbyteclkhs0_s2a_user",
5006 ENABLE_SCLK_CAM0, 7, 0, 0),
5007 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5008 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5009 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5010 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5011 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5012 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5013 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5014 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5015 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5016 "div_sclk_pixelasync_lite_c",
5017 ENABLE_SCLK_CAM0, 2, 0, 0),
5018 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5019 "div_sclk_pixelasync_lite_c_init",
5020 ENABLE_SCLK_CAM0, 1, 0, 0),
5021 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5022 "div_sclk_pixelasync_lite_c",
5023 ENABLE_SCLK_CAM0, 0, 0, 0),
5024};
5025
5026static struct samsung_cmu_info cam0_cmu_info __initdata = {
5027 .mux_clks = cam0_mux_clks,
5028 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
5029 .div_clks = cam0_div_clks,
5030 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
5031 .gate_clks = cam0_gate_clks,
5032 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
5033 .fixed_clks = cam0_fixed_clks,
5034 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
5035 .nr_clk_ids = CAM0_NR_CLK,
5036 .clk_regs = cam0_clk_regs,
5037 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5038};
5039
5040static void __init exynos5433_cmu_cam0_init(struct device_node *np)
5041{
5042 samsung_cmu_register_one(np, &cam0_cmu_info);
5043}
5044CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
5045 exynos5433_cmu_cam0_init);
5046
5047/*
5048 * Register offset definitions for CMU_CAM1
5049 */
5050#define MUX_SEL_CAM10 0x0200
5051#define MUX_SEL_CAM11 0x0204
5052#define MUX_SEL_CAM12 0x0208
5053#define MUX_ENABLE_CAM10 0x0300
5054#define MUX_ENABLE_CAM11 0x0304
5055#define MUX_ENABLE_CAM12 0x0308
5056#define MUX_STAT_CAM10 0x0400
5057#define MUX_STAT_CAM11 0x0404
5058#define MUX_STAT_CAM12 0x0408
5059#define MUX_IGNORE_CAM11 0x0504
5060#define DIV_CAM10 0x0600
5061#define DIV_CAM11 0x0604
5062#define DIV_STAT_CAM10 0x0700
5063#define DIV_STAT_CAM11 0x0704
5064#define ENABLE_ACLK_CAM10 0X0800
5065#define ENABLE_ACLK_CAM11 0X0804
5066#define ENABLE_ACLK_CAM12 0X0808
5067#define ENABLE_PCLK_CAM1 0X0900
5068#define ENABLE_SCLK_CAM1 0X0a00
5069#define ENABLE_IP_CAM10 0X0b00
5070#define ENABLE_IP_CAM11 0X0b04
5071#define ENABLE_IP_CAM12 0X0b08
5072
5073static unsigned long cam1_clk_regs[] __initdata = {
5074 MUX_SEL_CAM10,
5075 MUX_SEL_CAM11,
5076 MUX_SEL_CAM12,
5077 MUX_ENABLE_CAM10,
5078 MUX_ENABLE_CAM11,
5079 MUX_ENABLE_CAM12,
5080 MUX_STAT_CAM10,
5081 MUX_STAT_CAM11,
5082 MUX_STAT_CAM12,
5083 MUX_IGNORE_CAM11,
5084 DIV_CAM10,
5085 DIV_CAM11,
5086 DIV_STAT_CAM10,
5087 DIV_STAT_CAM11,
5088 ENABLE_ACLK_CAM10,
5089 ENABLE_ACLK_CAM11,
5090 ENABLE_ACLK_CAM12,
5091 ENABLE_PCLK_CAM1,
5092 ENABLE_SCLK_CAM1,
5093 ENABLE_IP_CAM10,
5094 ENABLE_IP_CAM11,
5095 ENABLE_IP_CAM12,
5096};
5097
5098PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5099PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5100PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
5101
5102PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
5103PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
5104PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5105
5106PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5107 "phyclk_rxbyteclkhs0_s2b_phy", };
5108
5109PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5110 "mout_aclk_cam1_333_user", };
5111PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5112 "mout_aclk_cam1_400_user", };
5113
5114PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5115 "mout_aclk_cam1_333_user", };
5116PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5117 "mout_aclk_cam1_400_user", };
5118
5119PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5120 "mout_aclk_cam1_333_user", };
5121PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5122 "mout_aclk_cam1_400_user", };
5123
5124static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = {
5125 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5126 CLK_IS_ROOT, 100000000),
5127};
5128
5129static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
5130 /* MUX_SEL_CAM10 */
5131 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5132 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5133 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5134 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5135 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5136 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5137 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5138 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5139 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5140 mout_aclk_cam1_400_user_p, MUX_SEL_CAM01, 4, 1),
5141 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5142 mout_aclk_cam1_552_user_p, MUX_SEL_CAM01, 0, 1),
5143
5144 /* MUX_SEL_CAM11 */
5145 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5146 "mout_phyclk_rxbyteclkhs0_s2b_user",
5147 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5148 MUX_SEL_CAM11, 0, 1),
5149
5150 /* MUX_SEL_CAM12 */
5151 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5152 MUX_SEL_CAM12, 20, 1),
5153 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5154 MUX_SEL_CAM12, 16, 1),
5155 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5156 MUX_SEL_CAM12, 12, 1),
5157 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5158 MUX_SEL_CAM12, 8, 1),
5159 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5160 MUX_SEL_CAM12, 4, 1),
5161 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5162 MUX_SEL_CAM12, 0, 1),
5163};
5164
5165static struct samsung_div_clock cam1_div_clks[] __initdata = {
5166 /* DIV_CAM10 */
5167 DIV(CLK_DIV_SCLK_ISP_WPWM, "div_sclk_isp_wpwm",
5168 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5169 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5170 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5171 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5172 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5173 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5174 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5175 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5176 DIV_CAM10, 0, 3),
5177
5178 /* DIV_CAM11 */
5179 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5180 DIV_CAM11, 16, 3),
5181 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5182 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5183 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5184 DIV_CAM11, 4, 2),
5185 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5186 DIV_CAM11, 0, 3),
5187};
5188
5189static struct samsung_gate_clock cam1_gate_clks[] __initdata = {
5190 /* ENABLE_ACLK_CAM10 */
5191 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5192 ENABLE_ACLK_CAM10, 4, 0, 0),
5193 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5194 ENABLE_ACLK_CAM10, 3, 0, 0),
5195 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5196 ENABLE_ACLK_CAM10, 1, 0, 0),
5197 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5198 ENABLE_ACLK_CAM10, 0, 0, 0),
5199
5200 /* ENABLE_ACLK_CAM11 */
5201 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5202 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5203 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5204 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5205 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5206 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5207 27, CLK_IGNORE_UNUSED, 0),
5208 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5209 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5210 26, CLK_IGNORE_UNUSED, 0),
5211 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5212 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5213 25, CLK_IGNORE_UNUSED, 0),
5214 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5215 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5216 24, CLK_IGNORE_UNUSED, 0),
5217 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5218 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5219 23, CLK_IGNORE_UNUSED, 0),
5220 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5221 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5222 22, CLK_IGNORE_UNUSED, 0),
5223 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5224 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5225 21, CLK_IGNORE_UNUSED, 0),
5226 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5227 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5228 20, CLK_IGNORE_UNUSED, 0),
5229 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5230 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5231 19, CLK_IGNORE_UNUSED, 0),
5232 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5233 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5234 18, CLK_IGNORE_UNUSED, 0),
5235 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5236 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5237 17, CLK_IGNORE_UNUSED, 0),
5238 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5239 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5240 16, CLK_IGNORE_UNUSED, 0),
5241 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5242 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5243 15, CLK_IGNORE_UNUSED, 0),
5244 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5245 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5246 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5247 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5248 13, CLK_IGNORE_UNUSED, 0),
5249 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5250 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5251 12, CLK_IGNORE_UNUSED, 0),
5252 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5253 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5254 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5255 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5256 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5257 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5258 9, CLK_IGNORE_UNUSED, 0),
5259 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5260 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5261 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5262 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5263 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5264 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5265 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5266 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5267 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5268 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5269 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5270 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5271 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5272 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5273 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5274 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5275 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5276 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5277
5278 /* ENABLE_ACLK_CAM12 */
5279 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5280 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5281 10, CLK_IGNORE_UNUSED, 0),
5282 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5283 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5284 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5285 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5286 8, CLK_IGNORE_UNUSED, 0),
5287 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5288 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5289 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5290 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5291 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5292 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5293 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5294 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5295 4, CLK_IGNORE_UNUSED, 0),
5296 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5297 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5298 3, CLK_IGNORE_UNUSED, 0),
5299 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5300 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5301 2, CLK_IGNORE_UNUSED, 0),
5302 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5303 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5304 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5305 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5306 0, CLK_IGNORE_UNUSED, 0),
5307
5308 /* ENABLE_PCLK_CAM1 */
5309 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5310 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5311 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5312 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5313 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5314 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5315 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5316 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5317 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5318 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5319 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5320 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5321 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5322 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5323 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5324 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5325 20, CLK_IGNORE_UNUSED, 0),
5326 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5327 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5328 19, CLK_IGNORE_UNUSED, 0),
5329 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5330 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5331 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5332 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5333 17, CLK_IGNORE_UNUSED, 0),
5334 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5335 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5336 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5337 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5338 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5339 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5340 14, CLK_IGNORE_UNUSED, 0),
5341 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5342 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5343 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5344 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5345 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5346 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5347 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5348 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5349 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5350 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5351 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5352 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5353 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5354 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5355 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5356 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5357 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5358 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5359 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5360 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5361 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_wpwm", "div_pclk_cam1_83",
5362 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5363 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5364 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5365 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5366 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5367 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5368 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5369
5370 /* ENABLE_SCLK_CAM1 */
5371 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5372 15, 0, 0),
5373 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5374 14, 0, 0),
5375 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5376 13, 0, 0),
5377 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5378 12, 0, 0),
5379 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5380 "mout_phyclk_rxbyteclkhs0_s2b_user",
5381 ENABLE_SCLK_CAM1, 11, 0, 0),
5382 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5383 ENABLE_SCLK_CAM1, 10, 0, 0),
5384 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5385 ENABLE_SCLK_CAM1, 9, 0, 0),
5386 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5387 ENABLE_SCLK_CAM1, 7, 0, 0),
5388 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5389 ENABLE_SCLK_CAM1, 6, 0, 0),
5390 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5391 ENABLE_SCLK_CAM1, 5, 0, 0),
5392 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5393 ENABLE_SCLK_CAM1, 4, 0, 0),
5394 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_wpwm", "div_sclk_isp_wpwm",
5395 ENABLE_SCLK_CAM1, 3, 0, 0),
5396 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5397 ENABLE_SCLK_CAM1, 2, 0, 0),
5398 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5399 ENABLE_SCLK_CAM1, 1, 0, 0),
5400 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5401 ENABLE_SCLK_CAM1, 0, 0, 0),
5402};
5403
5404static struct samsung_cmu_info cam1_cmu_info __initdata = {
5405 .mux_clks = cam1_mux_clks,
5406 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5407 .div_clks = cam1_div_clks,
5408 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5409 .gate_clks = cam1_gate_clks,
5410 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5411 .fixed_clks = cam1_fixed_clks,
5412 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5413 .nr_clk_ids = CAM1_NR_CLK,
5414 .clk_regs = cam1_clk_regs,
5415 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5416};
5417
5418static void __init exynos5433_cmu_cam1_init(struct device_node *np)
5419{
5420 samsung_cmu_register_one(np, &cam1_cmu_info);
5421}
5422CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
5423 exynos5433_cmu_cam1_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
new file mode 100644
index 000000000000..5bd80d5ecd0f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -0,0 +1,1403 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
11#define _DT_BINDINGS_CLOCK_EXYNOS5433_H
12
13/* CMU_TOP */
14#define CLK_FOUT_ISP_PLL 1
15#define CLK_FOUT_AUD_PLL 2
16
17#define CLK_MOUT_AUD_PLL 10
18#define CLK_MOUT_ISP_PLL 11
19#define CLK_MOUT_AUD_PLL_USER_T 12
20#define CLK_MOUT_MPHY_PLL_USER 13
21#define CLK_MOUT_MFC_PLL_USER 14
22#define CLK_MOUT_BUS_PLL_USER 15
23#define CLK_MOUT_ACLK_HEVC_400 16
24#define CLK_MOUT_ACLK_CAM1_333 17
25#define CLK_MOUT_ACLK_CAM1_552_B 18
26#define CLK_MOUT_ACLK_CAM1_552_A 19
27#define CLK_MOUT_ACLK_ISP_DIS_400 20
28#define CLK_MOUT_ACLK_ISP_400 21
29#define CLK_MOUT_ACLK_BUS0_400 22
30#define CLK_MOUT_ACLK_MSCL_400_B 23
31#define CLK_MOUT_ACLK_MSCL_400_A 24
32#define CLK_MOUT_ACLK_GSCL_333 25
33#define CLK_MOUT_ACLK_G2D_400_B 26
34#define CLK_MOUT_ACLK_G2D_400_A 27
35#define CLK_MOUT_SCLK_JPEG_C 28
36#define CLK_MOUT_SCLK_JPEG_B 29
37#define CLK_MOUT_SCLK_JPEG_A 30
38#define CLK_MOUT_SCLK_MMC2_B 31
39#define CLK_MOUT_SCLK_MMC2_A 32
40#define CLK_MOUT_SCLK_MMC1_B 33
41#define CLK_MOUT_SCLK_MMC1_A 34
42#define CLK_MOUT_SCLK_MMC0_D 35
43#define CLK_MOUT_SCLK_MMC0_C 36
44#define CLK_MOUT_SCLK_MMC0_B 37
45#define CLK_MOUT_SCLK_MMC0_A 38
46#define CLK_MOUT_SCLK_SPI4 39
47#define CLK_MOUT_SCLK_SPI3 40
48#define CLK_MOUT_SCLK_UART2 41
49#define CLK_MOUT_SCLK_UART1 42
50#define CLK_MOUT_SCLK_UART0 43
51#define CLK_MOUT_SCLK_SPI2 44
52#define CLK_MOUT_SCLK_SPI1 45
53#define CLK_MOUT_SCLK_SPI0 46
54#define CLK_MOUT_ACLK_MFC_400_C 47
55#define CLK_MOUT_ACLK_MFC_400_B 48
56#define CLK_MOUT_ACLK_MFC_400_A 49
57#define CLK_MOUT_SCLK_ISP_SENSOR2 50
58#define CLK_MOUT_SCLK_ISP_SENSOR1 51
59#define CLK_MOUT_SCLK_ISP_SENSOR0 52
60#define CLK_MOUT_SCLK_ISP_UART 53
61#define CLK_MOUT_SCLK_ISP_SPI1 54
62#define CLK_MOUT_SCLK_ISP_SPI0 55
63#define CLK_MOUT_SCLK_PCIE_100 56
64#define CLK_MOUT_SCLK_UFSUNIPRO 57
65#define CLK_MOUT_SCLK_USBHOST30 58
66#define CLK_MOUT_SCLK_USBDRD30 59
67#define CLK_MOUT_SCLK_SLIMBUS 60
68#define CLK_MOUT_SCLK_SPDIF 61
69#define CLK_MOUT_SCLK_AUDIO1 62
70#define CLK_MOUT_SCLK_AUDIO0 63
71#define CLK_MOUT_SCLK_HDMI_SPDIF 64
72
73#define CLK_DIV_ACLK_FSYS_200 100
74#define CLK_DIV_ACLK_IMEM_SSSX_266 101
75#define CLK_DIV_ACLK_IMEM_200 102
76#define CLK_DIV_ACLK_IMEM_266 103
77#define CLK_DIV_ACLK_PERIC_66_B 104
78#define CLK_DIV_ACLK_PERIC_66_A 105
79#define CLK_DIV_ACLK_PERIS_66_B 106
80#define CLK_DIV_ACLK_PERIS_66_A 107
81#define CLK_DIV_SCLK_MMC1_B 108
82#define CLK_DIV_SCLK_MMC1_A 109
83#define CLK_DIV_SCLK_MMC0_B 110
84#define CLK_DIV_SCLK_MMC0_A 111
85#define CLK_DIV_SCLK_MMC2_B 112
86#define CLK_DIV_SCLK_MMC2_A 113
87#define CLK_DIV_SCLK_SPI1_B 114
88#define CLK_DIV_SCLK_SPI1_A 115
89#define CLK_DIV_SCLK_SPI0_B 116
90#define CLK_DIV_SCLK_SPI0_A 117
91#define CLK_DIV_SCLK_SPI2_B 118
92#define CLK_DIV_SCLK_SPI2_A 119
93#define CLK_DIV_SCLK_UART2 120
94#define CLK_DIV_SCLK_UART1 121
95#define CLK_DIV_SCLK_UART0 122
96#define CLK_DIV_SCLK_SPI4_B 123
97#define CLK_DIV_SCLK_SPI4_A 124
98#define CLK_DIV_SCLK_SPI3_B 125
99#define CLK_DIV_SCLK_SPI3_A 126
100#define CLK_DIV_SCLK_I2S1 127
101#define CLK_DIV_SCLK_PCM1 128
102#define CLK_DIV_SCLK_AUDIO1 129
103#define CLK_DIV_SCLK_AUDIO0 130
104#define CLK_DIV_ACLK_GSCL_111 131
105#define CLK_DIV_ACLK_GSCL_333 132
106#define CLK_DIV_ACLK_HEVC_400 133
107#define CLK_DIV_ACLK_MFC_400 134
108#define CLK_DIV_ACLK_G2D_266 135
109#define CLK_DIV_ACLK_G2D_400 136
110#define CLK_DIV_ACLK_G3D_400 137
111#define CLK_DIV_ACLK_BUS0_400 138
112#define CLK_DIV_ACLK_BUS1_400 139
113#define CLK_DIV_SCLK_PCIE_100 140
114#define CLK_DIV_SCLK_USBHOST30 141
115#define CLK_DIV_SCLK_UFSUNIPRO 142
116#define CLK_DIV_SCLK_USBDRD30 143
117#define CLK_DIV_SCLK_JPEG 144
118#define CLK_DIV_ACLK_MSCL_400 145
119#define CLK_DIV_ACLK_ISP_DIS_400 146
120#define CLK_DIV_ACLK_ISP_400 147
121#define CLK_DIV_ACLK_CAM0_333 148
122#define CLK_DIV_ACLK_CAM0_400 149
123#define CLK_DIV_ACLK_CAM0_552 150
124#define CLK_DIV_ACLK_CAM1_333 151
125#define CLK_DIV_ACLK_CAM1_400 152
126#define CLK_DIV_ACLK_CAM1_552 153
127#define CLK_DIV_SCLK_ISP_UART 154
128#define CLK_DIV_SCLK_ISP_SPI1_B 155
129#define CLK_DIV_SCLK_ISP_SPI1_A 156
130#define CLK_DIV_SCLK_ISP_SPI0_B 157
131#define CLK_DIV_SCLK_ISP_SPI0_A 158
132#define CLK_DIV_SCLK_ISP_SENSOR2_B 159
133#define CLK_DIV_SCLK_ISP_SENSOR2_A 160
134#define CLK_DIV_SCLK_ISP_SENSOR1_B 161
135#define CLK_DIV_SCLK_ISP_SENSOR1_A 162
136#define CLK_DIV_SCLK_ISP_SENSOR0_B 163
137#define CLK_DIV_SCLK_ISP_SENSOR0_A 164
138
139#define CLK_ACLK_PERIC_66 200
140#define CLK_ACLK_PERIS_66 201
141#define CLK_ACLK_FSYS_200 202
142#define CLK_SCLK_MMC2_FSYS 203
143#define CLK_SCLK_MMC1_FSYS 204
144#define CLK_SCLK_MMC0_FSYS 205
145#define CLK_SCLK_SPI4_PERIC 206
146#define CLK_SCLK_SPI3_PERIC 207
147#define CLK_SCLK_UART2_PERIC 208
148#define CLK_SCLK_UART1_PERIC 209
149#define CLK_SCLK_UART0_PERIC 210
150#define CLK_SCLK_SPI2_PERIC 211
151#define CLK_SCLK_SPI1_PERIC 212
152#define CLK_SCLK_SPI0_PERIC 213
153#define CLK_SCLK_SPDIF_PERIC 214
154#define CLK_SCLK_I2S1_PERIC 215
155#define CLK_SCLK_PCM1_PERIC 216
156#define CLK_SCLK_SLIMBUS 217
157#define CLK_SCLK_AUDIO1 218
158#define CLK_SCLK_AUDIO0 219
159#define CLK_ACLK_G2D_266 220
160#define CLK_ACLK_G2D_400 221
161#define CLK_ACLK_G3D_400 222
162#define CLK_ACLK_IMEM_SSX_266 223
163#define CLK_ACLK_BUS0_400 224
164#define CLK_ACLK_BUS1_400 225
165#define CLK_ACLK_IMEM_200 226
166#define CLK_ACLK_IMEM_266 227
167#define CLK_SCLK_PCIE_100_FSYS 228
168#define CLK_SCLK_UFSUNIPRO_FSYS 229
169#define CLK_SCLK_USBHOST30_FSYS 230
170#define CLK_SCLK_USBDRD30_FSYS 231
171#define CLK_ACLK_GSCL_111 232
172#define CLK_ACLK_GSCL_333 233
173#define CLK_SCLK_JPEG_MSCL 234
174#define CLK_ACLK_MSCL_400 235
175#define CLK_ACLK_MFC_400 236
176#define CLK_ACLK_HEVC_400 237
177#define CLK_ACLK_ISP_DIS_400 238
178#define CLK_ACLK_ISP_400 239
179#define CLK_ACLK_CAM0_333 240
180#define CLK_ACLK_CAM0_400 241
181#define CLK_ACLK_CAM0_552 242
182#define CLK_ACLK_CAM1_333 243
183#define CLK_ACLK_CAM1_400 244
184#define CLK_ACLK_CAM1_552 245
185#define CLK_SCLK_ISP_SENSOR2 246
186#define CLK_SCLK_ISP_SENSOR1 247
187#define CLK_SCLK_ISP_SENSOR0 248
188#define CLK_SCLK_ISP_MCTADC_CAM1 249
189#define CLK_SCLK_ISP_UART_CAM1 250
190#define CLK_SCLK_ISP_SPI1_CAM1 251
191#define CLK_SCLK_ISP_SPI0_CAM1 252
192#define CLK_SCLK_HDMI_SPDIF_DISP 253
193
194#define TOP_NR_CLK 254
195
196/* CMU_CPIF */
197#define CLK_FOUT_MPHY_PLL 1
198
199#define CLK_MOUT_MPHY_PLL 2
200
201#define CLK_DIV_SCLK_MPHY 10
202
203#define CLK_SCLK_MPHY_PLL 11
204#define CLK_SCLK_UFS_MPHY 11
205
206#define CPIF_NR_CLK 12
207
208/* CMU_MIF */
209#define CLK_FOUT_MEM0_PLL 1
210#define CLK_FOUT_MEM1_PLL 2
211#define CLK_FOUT_BUS_PLL 3
212#define CLK_FOUT_MFC_PLL 4
213#define CLK_DOUT_MFC_PLL 5
214#define CLK_DOUT_BUS_PLL 6
215#define CLK_DOUT_MEM1_PLL 7
216#define CLK_DOUT_MEM0_PLL 8
217
218#define CLK_MOUT_MFC_PLL_DIV2 10
219#define CLK_MOUT_BUS_PLL_DIV2 11
220#define CLK_MOUT_MEM1_PLL_DIV2 12
221#define CLK_MOUT_MEM0_PLL_DIV2 13
222#define CLK_MOUT_MFC_PLL 14
223#define CLK_MOUT_BUS_PLL 15
224#define CLK_MOUT_MEM1_PLL 16
225#define CLK_MOUT_MEM0_PLL 17
226#define CLK_MOUT_CLK2X_PHY_C 18
227#define CLK_MOUT_CLK2X_PHY_B 19
228#define CLK_MOUT_CLK2X_PHY_A 20
229#define CLK_MOUT_CLKM_PHY_C 21
230#define CLK_MOUT_CLKM_PHY_B 22
231#define CLK_MOUT_CLKM_PHY_A 23
232#define CLK_MOUT_ACLK_MIFNM_200 24
233#define CLK_MOUT_ACLK_MIFNM_400 25
234#define CLK_MOUT_ACLK_DISP_333_B 26
235#define CLK_MOUT_ACLK_DISP_333_A 27
236#define CLK_MOUT_SCLK_DECON_VCLK_C 28
237#define CLK_MOUT_SCLK_DECON_VCLK_B 29
238#define CLK_MOUT_SCLK_DECON_VCLK_A 30
239#define CLK_MOUT_SCLK_DECON_ECLK_C 31
240#define CLK_MOUT_SCLK_DECON_ECLK_B 32
241#define CLK_MOUT_SCLK_DECON_ECLK_A 33
242#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
243#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
244#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
245#define CLK_MOUT_SCLK_DSD_C 37
246#define CLK_MOUT_SCLK_DSD_B 38
247#define CLK_MOUT_SCLK_DSD_A 39
248#define CLK_MOUT_SCLK_DSIM0_C 40
249#define CLK_MOUT_SCLK_DSIM0_B 41
250#define CLK_MOUT_SCLK_DSIM0_A 42
251#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
252#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
253#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
254#define CLK_MOUT_SCLK_DSIM1_C 49
255#define CLK_MOUT_SCLK_DSIM1_B 50
256#define CLK_MOUT_SCLK_DSIM1_A 51
257
258#define CLK_DIV_SCLK_HPM_MIF 55
259#define CLK_DIV_ACLK_DREX1 56
260#define CLK_DIV_ACLK_DREX0 57
261#define CLK_DIV_CLK2XPHY 58
262#define CLK_DIV_ACLK_MIF_266 59
263#define CLK_DIV_ACLK_MIFND_133 60
264#define CLK_DIV_ACLK_MIF_133 61
265#define CLK_DIV_ACLK_MIFNM_200 62
266#define CLK_DIV_ACLK_MIF_200 63
267#define CLK_DIV_ACLK_MIF_400 64
268#define CLK_DIV_ACLK_BUS2_400 65
269#define CLK_DIV_ACLK_DISP_333 66
270#define CLK_DIV_ACLK_CPIF_200 67
271#define CLK_DIV_SCLK_DSIM1 68
272#define CLK_DIV_SCLK_DECON_TV_VCLK 69
273#define CLK_DIV_SCLK_DSIM0 70
274#define CLK_DIV_SCLK_DSD 71
275#define CLK_DIV_SCLK_DECON_TV_ECLK 72
276#define CLK_DIV_SCLK_DECON_VCLK 73
277#define CLK_DIV_SCLK_DECON_ECLK 74
278#define CLK_DIV_MIF_PRE 75
279
280#define CLK_CLK2X_PHY1 80
281#define CLK_CLK2X_PHY0 81
282#define CLK_CLKM_PHY1 82
283#define CLK_CLKM_PHY0 83
284#define CLK_RCLK_DREX1 84
285#define CLK_RCLK_DREX0 85
286#define CLK_ACLK_DREX1_TZ 86
287#define CLK_ACLK_DREX0_TZ 87
288#define CLK_ACLK_DREX1_PEREV 88
289#define CLK_ACLK_DREX0_PEREV 89
290#define CLK_ACLK_DREX1_MEMIF 90
291#define CLK_ACLK_DREX0_MEMIF 91
292#define CLK_ACLK_DREX1_SCH 92
293#define CLK_ACLK_DREX0_SCH 93
294#define CLK_ACLK_DREX1_BUSIF 94
295#define CLK_ACLK_DREX0_BUSIF 95
296#define CLK_ACLK_DREX1_BUSIF_RD 96
297#define CLK_ACLK_DREX0_BUSIF_RD 97
298#define CLK_ACLK_DREX1 98
299#define CLK_ACLK_DREX0 99
300#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
301#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
302#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
303#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
304#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
305#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
306#define CLK_ACLK_ASYNCAXIS_CP1 106
307#define CLK_ACLK_ASYNCAXIM_CP1 107
308#define CLK_ACLK_ASYNCAXIS_CP0 108
309#define CLK_ACLK_ASYNCAXIM_CP0 109
310#define CLK_ACLK_ASYNCAXIS_DREX1_3 110
311#define CLK_ACLK_ASYNCAXIM_DREX1_3 111
312#define CLK_ACLK_ASYNCAXIS_DREX1_1 112
313#define CLK_ACLK_ASYNCAXIM_DREX1_1 113
314#define CLK_ACLK_ASYNCAXIS_DREX1_0 114
315#define CLK_ACLK_ASYNCAXIM_DREX1_0 115
316#define CLK_ACLK_ASYNCAXIS_DREX0_3 116
317#define CLK_ACLK_ASYNCAXIM_DREX0_3 117
318#define CLK_ACLK_ASYNCAXIS_DREX0_1 118
319#define CLK_ACLK_ASYNCAXIM_DREX0_1 119
320#define CLK_ACLK_ASYNCAXIS_DREX0_0 120
321#define CLK_ACLK_ASYNCAXIM_DREX0_0 121
322#define CLK_ACLK_AHB2APB_MIF2P 122
323#define CLK_ACLK_AHB2APB_MIF1P 123
324#define CLK_ACLK_AHB2APB_MIF0P 124
325#define CLK_ACLK_IXIU_CCI 125
326#define CLK_ACLK_XIU_MIFSFRX 126
327#define CLK_ACLK_MIFNP_133 127
328#define CLK_ACLK_MIFNM_200 128
329#define CLK_ACLK_MIFND_133 129
330#define CLK_ACLK_MIFND_400 130
331#define CLK_ACLK_CCI 131
332#define CLK_ACLK_MIFND_266 132
333#define CLK_ACLK_PPMU_DREX1S3 133
334#define CLK_ACLK_PPMU_DREX1S1 134
335#define CLK_ACLK_PPMU_DREX1S0 135
336#define CLK_ACLK_PPMU_DREX0S3 136
337#define CLK_ACLK_PPMU_DREX0S1 137
338#define CLK_ACLK_PPMU_DREX0S0 138
339#define CLK_ACLK_BTS_APOLLO 139
340#define CLK_ACLK_BTS_ATLAS 140
341#define CLK_ACLK_ACE_SEL_APOLL 141
342#define CLK_ACLK_ACE_SEL_ATLAS 142
343#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
344#define CLK_ACLK_AXIUS_ATLAS_CCI 144
345#define CLK_ACLK_AXISYNCDNS_CCI 145
346#define CLK_ACLK_AXISYNCDN_CCI 146
347#define CLK_ACLK_AXISYNCDN_NOC_D 147
348#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
349#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
350#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
351#define CLK_ACLK_BUS2_400 151
352#define CLK_ACLK_DISP_333 152
353#define CLK_ACLK_CPIF_200 153
354#define CLK_PCLK_PPMU_DREX1S3 154
355#define CLK_PCLK_PPMU_DREX1S1 155
356#define CLK_PCLK_PPMU_DREX1S0 156
357#define CLK_PCLK_PPMU_DREX0S3 157
358#define CLK_PCLK_PPMU_DREX0S1 158
359#define CLK_PCLK_PPMU_DREX0S0 159
360#define CLK_PCLK_BTS_APOLLO 160
361#define CLK_PCLK_BTS_ATLAS 161
362#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
363#define CLK_PCLK_ASYNCAXI_CP1 163
364#define CLK_PCLK_ASYNCAXI_CP0 164
365#define CLK_PCLK_ASYNCAXI_DREX1_3 165
366#define CLK_PCLK_ASYNCAXI_DREX1_1 166
367#define CLK_PCLK_ASYNCAXI_DREX1_0 167
368#define CLK_PCLK_ASYNCAXI_DREX0_3 168
369#define CLK_PCLK_ASYNCAXI_DREX0_1 169
370#define CLK_PCLK_ASYNCAXI_DREX0_0 170
371#define CLK_PCLK_MIFSRVND_133 171
372#define CLK_PCLK_PMU_MIF 172
373#define CLK_PCLK_SYSREG_MIF 173
374#define CLK_PCLK_GPIO_ALIVE 174
375#define CLK_PCLK_ABB 175
376#define CLK_PCLK_PMU_APBIF 176
377#define CLK_PCLK_DDR_PHY1 177
378#define CLK_PCLK_DREX1 178
379#define CLK_PCLK_DDR_PHY0 179
380#define CLK_PCLK_DREX0 180
381#define CLK_PCLK_DREX0_TZ 181
382#define CLK_PCLK_DREX1_TZ 182
383#define CLK_PCLK_MONOTONIC_CNT 183
384#define CLK_PCLK_RTC 184
385#define CLK_SCLK_DSIM1_DISP 185
386#define CLK_SCLK_DECON_TV_VCLK_DISP 186
387#define CLK_SCLK_FREQ_DET_BUS_PLL 187
388#define CLK_SCLK_FREQ_DET_MFC_PLL 188
389#define CLK_SCLK_FREQ_DET_MEM0_PLL 189
390#define CLK_SCLK_FREQ_DET_MEM1_PLL 190
391#define CLK_SCLK_DSIM0_DISP 191
392#define CLK_SCLK_DSD_DISP 192
393#define CLK_SCLK_DECON_TV_ECLK_DISP 193
394#define CLK_SCLK_DECON_VCLK_DISP 194
395#define CLK_SCLK_DECON_ECLK_DISP 195
396#define CLK_SCLK_HPM_MIF 196
397#define CLK_SCLK_MFC_PLL 197
398#define CLK_SCLK_BUS_PLL 198
399#define CLK_SCLK_BUS_PLL_APOLLO 199
400#define CLK_SCLK_BUS_PLL_ATLAS 200
401
402#define MIF_NR_CLK 201
403
404/* CMU_PERIC */
405#define CLK_PCLK_SPI2 1
406#define CLK_PCLK_SPI1 2
407#define CLK_PCLK_SPI0 3
408#define CLK_PCLK_UART2 4
409#define CLK_PCLK_UART1 5
410#define CLK_PCLK_UART0 6
411#define CLK_PCLK_HSI2C3 7
412#define CLK_PCLK_HSI2C2 8
413#define CLK_PCLK_HSI2C1 9
414#define CLK_PCLK_HSI2C0 10
415#define CLK_PCLK_I2C7 11
416#define CLK_PCLK_I2C6 12
417#define CLK_PCLK_I2C5 13
418#define CLK_PCLK_I2C4 14
419#define CLK_PCLK_I2C3 15
420#define CLK_PCLK_I2C2 16
421#define CLK_PCLK_I2C1 17
422#define CLK_PCLK_I2C0 18
423#define CLK_PCLK_SPI4 19
424#define CLK_PCLK_SPI3 20
425#define CLK_PCLK_HSI2C11 21
426#define CLK_PCLK_HSI2C10 22
427#define CLK_PCLK_HSI2C9 23
428#define CLK_PCLK_HSI2C8 24
429#define CLK_PCLK_HSI2C7 25
430#define CLK_PCLK_HSI2C6 26
431#define CLK_PCLK_HSI2C5 27
432#define CLK_PCLK_HSI2C4 28
433#define CLK_SCLK_SPI4 29
434#define CLK_SCLK_SPI3 30
435#define CLK_SCLK_SPI2 31
436#define CLK_SCLK_SPI1 32
437#define CLK_SCLK_SPI0 33
438#define CLK_SCLK_UART2 34
439#define CLK_SCLK_UART1 35
440#define CLK_SCLK_UART0 36
441#define CLK_ACLK_AHB2APB_PERIC2P 37
442#define CLK_ACLK_AHB2APB_PERIC1P 38
443#define CLK_ACLK_AHB2APB_PERIC0P 39
444#define CLK_ACLK_PERICNP_66 40
445#define CLK_PCLK_SCI 41
446#define CLK_PCLK_GPIO_FINGER 42
447#define CLK_PCLK_GPIO_ESE 43
448#define CLK_PCLK_PWM 44
449#define CLK_PCLK_SPDIF 45
450#define CLK_PCLK_PCM1 46
451#define CLK_PCLK_I2S1 47
452#define CLK_PCLK_ADCIF 48
453#define CLK_PCLK_GPIO_TOUCH 49
454#define CLK_PCLK_GPIO_NFC 50
455#define CLK_PCLK_GPIO_PERIC 51
456#define CLK_PCLK_PMU_PERIC 52
457#define CLK_PCLK_SYSREG_PERIC 53
458#define CLK_SCLK_IOCLK_SPI4 54
459#define CLK_SCLK_IOCLK_SPI3 55
460#define CLK_SCLK_SCI 56
461#define CLK_SCLK_SC_IN 57
462#define CLK_SCLK_PWM 58
463#define CLK_SCLK_IOCLK_SPI2 59
464#define CLK_SCLK_IOCLK_SPI1 60
465#define CLK_SCLK_IOCLK_SPI0 61
466#define CLK_SCLK_IOCLK_I2S1_BCLK 62
467#define CLK_SCLK_SPDIF 63
468#define CLK_SCLK_PCM1 64
469#define CLK_SCLK_I2S1 65
470
471#define CLK_DIV_SCLK_SCI 70
472#define CLK_DIV_SCLK_SC_IN 71
473
474#define PERIC_NR_CLK 72
475
476/* CMU_PERIS */
477#define CLK_PCLK_HPM_APBIF 1
478#define CLK_PCLK_TMU1_APBIF 2
479#define CLK_PCLK_TMU0_APBIF 3
480#define CLK_PCLK_PMU_PERIS 4
481#define CLK_PCLK_SYSREG_PERIS 5
482#define CLK_PCLK_CMU_TOP_APBIF 6
483#define CLK_PCLK_WDT_APOLLO 7
484#define CLK_PCLK_WDT_ATLAS 8
485#define CLK_PCLK_MCT 9
486#define CLK_PCLK_HDMI_CEC 10
487#define CLK_ACLK_AHB2APB_PERIS1P 11
488#define CLK_ACLK_AHB2APB_PERIS0P 12
489#define CLK_ACLK_PERISNP_66 13
490#define CLK_PCLK_TZPC12 14
491#define CLK_PCLK_TZPC11 15
492#define CLK_PCLK_TZPC10 16
493#define CLK_PCLK_TZPC9 17
494#define CLK_PCLK_TZPC8 18
495#define CLK_PCLK_TZPC7 19
496#define CLK_PCLK_TZPC6 20
497#define CLK_PCLK_TZPC5 21
498#define CLK_PCLK_TZPC4 22
499#define CLK_PCLK_TZPC3 23
500#define CLK_PCLK_TZPC2 24
501#define CLK_PCLK_TZPC1 25
502#define CLK_PCLK_TZPC0 26
503#define CLK_PCLK_SECKEY_APBIF 27
504#define CLK_PCLK_CHIPID_APBIF 28
505#define CLK_PCLK_TOPRTC 29
506#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
507#define CLK_PCLK_ANTIRBK_CNT_APBIF 31
508#define CLK_PCLK_OTP_CON_APBIF 32
509#define CLK_SCLK_ASV_TB 33
510#define CLK_SCLK_TMU1 34
511#define CLK_SCLK_TMU0 35
512#define CLK_SCLK_SECKEY 36
513#define CLK_SCLK_CHIPID 37
514#define CLK_SCLK_TOPRTC 38
515#define CLK_SCLK_CUSTOM_EFUSE 39
516#define CLK_SCLK_ANTIRBK_CNT 40
517#define CLK_SCLK_OTP_CON 41
518
519#define PERIS_NR_CLK 42
520
521/* CMU_FSYS */
522#define CLK_MOUT_ACLK_FSYS_200_USER 1
523#define CLK_MOUT_SCLK_MMC2_USER 2
524#define CLK_MOUT_SCLK_MMC1_USER 3
525#define CLK_MOUT_SCLK_MMC0_USER 4
526#define CLK_MOUT_SCLK_UFS_MPHY_USER 5
527#define CLK_MOUT_SCLK_PCIE_100_USER 6
528#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
529#define CLK_MOUT_SCLK_USBHOST30_USER 8
530#define CLK_MOUT_SCLK_USBDRD30_USER 9
531#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10
532#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11
533#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12
534#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13
535#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14
536#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15
537#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16
538#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17
539#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
540#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19
541#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20
542#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21
543#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22
544#define CLK_MOUT_SCLK_MPHY 23
545
546#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
547#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26
548#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27
549#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28
550#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29
551#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30
552#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31
553#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32
554#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33
555#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34
556#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
557#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
558#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37
559
560#define CLK_ACLK_PCIE 50
561#define CLK_ACLK_PDMA1 51
562#define CLK_ACLK_TSI 52
563#define CLK_ACLK_MMC2 53
564#define CLK_ACLK_MMC1 54
565#define CLK_ACLK_MMC0 55
566#define CLK_ACLK_UFS 56
567#define CLK_ACLK_USBHOST20 57
568#define CLK_ACLK_USBHOST30 58
569#define CLK_ACLK_USBDRD30 59
570#define CLK_ACLK_PDMA0 60
571#define CLK_SCLK_MMC2 61
572#define CLK_SCLK_MMC1 62
573#define CLK_SCLK_MMC0 63
574#define CLK_PDMA1 64
575#define CLK_PDMA0 65
576#define CLK_ACLK_XIU_FSYSPX 66
577#define CLK_ACLK_AHB_USBLINKH1 67
578#define CLK_ACLK_SMMU_PDMA1 68
579#define CLK_ACLK_BTS_PCIE 69
580#define CLK_ACLK_AXIUS_PDMA1 70
581#define CLK_ACLK_SMMU_PDMA0 71
582#define CLK_ACLK_BTS_UFS 72
583#define CLK_ACLK_BTS_USBHOST30 73
584#define CLK_ACLK_BTS_USBDRD30 74
585#define CLK_ACLK_AXIUS_PDMA0 75
586#define CLK_ACLK_AXIUS_USBHS 76
587#define CLK_ACLK_AXIUS_FSYSSX 77
588#define CLK_ACLK_AHB2APB_FSYSP 78
589#define CLK_ACLK_AHB2AXI_USBHS 79
590#define CLK_ACLK_AHB_USBLINKH0 80
591#define CLK_ACLK_AHB_USBHS 81
592#define CLK_ACLK_AHB_FSYSH 82
593#define CLK_ACLK_XIU_FSYSX 83
594#define CLK_ACLK_XIU_FSYSSX 84
595#define CLK_ACLK_FSYSNP_200 85
596#define CLK_ACLK_FSYSND_200 86
597#define CLK_PCLK_PCIE_CTRL 87
598#define CLK_PCLK_SMMU_PDMA1 88
599#define CLK_PCLK_PCIE_PHY 89
600#define CLK_PCLK_BTS_PCIE 90
601#define CLK_PCLK_SMMU_PDMA0 91
602#define CLK_PCLK_BTS_UFS 92
603#define CLK_PCLK_BTS_USBHOST30 93
604#define CLK_PCLK_BTS_USBDRD30 94
605#define CLK_PCLK_GPIO_FSYS 95
606#define CLK_PCLK_PMU_FSYS 96
607#define CLK_PCLK_SYSREG_FSYS 97
608#define CLK_SCLK_PCIE_100 98
609#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99
610#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100
611#define CLK_PHYCLK_UFS_RX1_SYMBOL 101
612#define CLK_PHYCLK_UFS_RX0_SYMBOL 102
613#define CLK_PHYCLK_UFS_TX1_SYMBOL 103
614#define CLK_PHYCLK_UFS_TX0_SYMBOL 104
615#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105
616#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106
617#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107
618#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108
619#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109
620#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110
621#define CLK_SCLK_MPHY 111
622#define CLK_SCLK_UFSUNIPRO 112
623#define CLK_SCLK_USBHOST30 113
624#define CLK_SCLK_USBDRD30 114
625
626#define FSYS_NR_CLK 115
627
628/* CMU_G2D */
629#define CLK_MUX_ACLK_G2D_266_USER 1
630#define CLK_MUX_ACLK_G2D_400_USER 2
631
632#define CLK_DIV_PCLK_G2D 3
633
634#define CLK_ACLK_SMMU_MDMA1 4
635#define CLK_ACLK_BTS_MDMA1 5
636#define CLK_ACLK_BTS_G2D 6
637#define CLK_ACLK_ALB_G2D 7
638#define CLK_ACLK_AXIUS_G2DX 8
639#define CLK_ACLK_ASYNCAXI_SYSX 9
640#define CLK_ACLK_AHB2APB_G2D1P 10
641#define CLK_ACLK_AHB2APB_G2D0P 11
642#define CLK_ACLK_XIU_G2DX 12
643#define CLK_ACLK_G2DNP_133 13
644#define CLK_ACLK_G2DND_400 14
645#define CLK_ACLK_MDMA1 15
646#define CLK_ACLK_G2D 16
647#define CLK_ACLK_SMMU_G2D 17
648#define CLK_PCLK_SMMU_MDMA1 18
649#define CLK_PCLK_BTS_MDMA1 19
650#define CLK_PCLK_BTS_G2D 20
651#define CLK_PCLK_ALB_G2D 21
652#define CLK_PCLK_ASYNCAXI_SYSX 22
653#define CLK_PCLK_PMU_G2D 23
654#define CLK_PCLK_SYSREG_G2D 24
655#define CLK_PCLK_G2D 25
656#define CLK_PCLK_SMMU_G2D 26
657
658#define G2D_NR_CLK 27
659
660/* CMU_DISP */
661#define CLK_FOUT_DISP_PLL 1
662
663#define CLK_MOUT_DISP_PLL 2
664#define CLK_MOUT_SCLK_DSIM1_USER 3
665#define CLK_MOUT_SCLK_DSIM0_USER 4
666#define CLK_MOUT_SCLK_DSD_USER 5
667#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6
668#define CLK_MOUT_SCLK_DECON_VCLK_USER 7
669#define CLK_MOUT_SCLK_DECON_ECLK_USER 8
670#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9
671#define CLK_MOUT_ACLK_DISP_333_USER 10
672#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11
673#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12
674#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13
675#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14
676#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15
677#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16
678#define CLK_MOUT_SCLK_DSIM0 17
679#define CLK_MOUT_SCLK_DECON_TV_ECLK 18
680#define CLK_MOUT_SCLK_DECON_VCLK 19
681#define CLK_MOUT_SCLK_DECON_ECLK 20
682#define CLK_MOUT_SCLK_DSIM1_B_DISP 21
683#define CLK_MOUT_SCLK_DSIM1_A_DISP 22
684#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23
685#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24
686#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
687
688#define CLK_DIV_SCLK_DSIM1_DISP 30
689#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31
690#define CLK_DIV_SCLK_DSIM0_DISP 32
691#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33
692#define CLK_DIV_SCLK_DECON_VCLK_DISP 34
693#define CLK_DIV_SCLK_DECON_ECLK_DISP 35
694#define CLK_DIV_PCLK_DISP 36
695
696#define CLK_ACLK_DECON_TV 40
697#define CLK_ACLK_DECON 41
698#define CLK_ACLK_SMMU_TV1X 42
699#define CLK_ACLK_SMMU_TV0X 43
700#define CLK_ACLK_SMMU_DECON1X 44
701#define CLK_ACLK_SMMU_DECON0X 45
702#define CLK_ACLK_BTS_DECON_TV_M3 46
703#define CLK_ACLK_BTS_DECON_TV_M2 47
704#define CLK_ACLK_BTS_DECON_TV_M1 48
705#define CLK_ACLK_BTS_DECON_TV_M0 49
706#define CLK_ACLK_BTS_DECON_NM4 50
707#define CLK_ACLK_BTS_DECON_NM3 51
708#define CLK_ACLK_BTS_DECON_NM2 52
709#define CLK_ACLK_BTS_DECON_NM1 53
710#define CLK_ACLK_BTS_DECON_NM0 54
711#define CLK_ACLK_AHB2APB_DISPSFR2P 55
712#define CLK_ACLK_AHB2APB_DISPSFR1P 56
713#define CLK_ACLK_AHB2APB_DISPSFR0P 57
714#define CLK_ACLK_AHB_DISPH 58
715#define CLK_ACLK_XIU_TV1X 59
716#define CLK_ACLK_XIU_TV0X 60
717#define CLK_ACLK_XIU_DECON1X 61
718#define CLK_ACLK_XIU_DECON0X 62
719#define CLK_ACLK_XIU_DISP1X 63
720#define CLK_ACLK_XIU_DISPNP_100 64
721#define CLK_ACLK_DISP1ND_333 65
722#define CLK_ACLK_DISP0ND_333 66
723#define CLK_PCLK_SMMU_TV1X 67
724#define CLK_PCLK_SMMU_TV0X 68
725#define CLK_PCLK_SMMU_DECON1X 69
726#define CLK_PCLK_SMMU_DECON0X 70
727#define CLK_PCLK_BTS_DECON_TV_M3 71
728#define CLK_PCLK_BTS_DECON_TV_M2 72
729#define CLK_PCLK_BTS_DECON_TV_M1 73
730#define CLK_PCLK_BTS_DECON_TV_M0 74
731#define CLK_PCLK_BTS_DECONM4 75
732#define CLK_PCLK_BTS_DECONM3 76
733#define CLK_PCLK_BTS_DECONM2 77
734#define CLK_PCLK_BTS_DECONM1 78
735#define CLK_PCLK_BTS_DECONM0 79
736#define CLK_PCLK_MIC1 80
737#define CLK_PCLK_PMU_DISP 81
738#define CLK_PCLK_SYSREG_DISP 82
739#define CLK_PCLK_HDMIPHY 83
740#define CLK_PCLK_HDMI 84
741#define CLK_PCLK_MIC0 85
742#define CLK_PCLK_DSIM1 86
743#define CLK_PCLK_DSIM0 87
744#define CLK_PCLK_DECON_TV 88
745#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89
746#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90
747#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91
748#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92
749#define CLK_SCLK_DSIM1 93
750#define CLK_SCLK_DECON_TV_VCLK 94
751#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95
752#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96
753#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97
754#define CLK_PHYCLK_HDMI_PIXEL 98
755#define CLK_SCLK_RGB_VCLK_TO_SMIES 99
756#define CLK_SCLK_FREQ_DET_DISP_PLL 100
757#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101
758#define CLK_SCLK_RGB_VCLK_TO_MIC0 102
759#define CLK_SCLK_DSD 103
760#define CLK_SCLK_HDMI_SPDIF 104
761#define CLK_SCLK_DSIM0 105
762#define CLK_SCLK_DECON_TV_ECLK 106
763#define CLK_SCLK_DECON_VCLK 107
764#define CLK_SCLK_DECON_ECLK 108
765#define CLK_SCLK_RGB_VCLK 109
766#define CLK_SCLK_RGB_TV_VCLK 110
767
768#define DISP_NR_CLK 111
769
770/* CMU_AUD */
771#define CLK_MOUT_AUD_PLL_USER 1
772#define CLK_MOUT_SCLK_AUD_PCM 2
773#define CLK_MOUT_SCLK_AUD_I2S 3
774
775#define CLK_DIV_ATCLK_AUD 4
776#define CLK_DIV_PCLK_DBG_AUD 5
777#define CLK_DIV_ACLK_AUD 6
778#define CLK_DIV_AUD_CA5 7
779#define CLK_DIV_SCLK_AUD_SLIMBUS 8
780#define CLK_DIV_SCLK_AUD_UART 9
781#define CLK_DIV_SCLK_AUD_PCM 10
782#define CLK_DIV_SCLK_AUD_I2S 11
783
784#define CLK_ACLK_INTR_CTRL 12
785#define CLK_ACLK_AXIDS2_LPASSP 13
786#define CLK_ACLK_AXIDS1_LPASSP 14
787#define CLK_ACLK_AXI2APB1_LPASSP 15
788#define CLK_ACLK_AXI2APH_LPASSP 16
789#define CLK_ACLK_SMMU_LPASSX 17
790#define CLK_ACLK_AXIDS0_LPASSP 18
791#define CLK_ACLK_AXI2APB0_LPASSP 19
792#define CLK_ACLK_XIU_LPASSX 20
793#define CLK_ACLK_AUDNP_133 21
794#define CLK_ACLK_AUDND_133 22
795#define CLK_ACLK_SRAMC 23
796#define CLK_ACLK_DMAC 24
797#define CLK_PCLK_WDT1 25
798#define CLK_PCLK_WDT0 26
799#define CLK_PCLK_SFR1 27
800#define CLK_PCLK_SMMU_LPASSX 28
801#define CLK_PCLK_GPIO_AUD 29
802#define CLK_PCLK_PMU_AUD 30
803#define CLK_PCLK_SYSREG_AUD 31
804#define CLK_PCLK_AUD_SLIMBUS 32
805#define CLK_PCLK_AUD_UART 33
806#define CLK_PCLK_AUD_PCM 34
807#define CLK_PCLK_AUD_I2S 35
808#define CLK_PCLK_TIMER 36
809#define CLK_PCLK_SFR0_CTRL 37
810#define CLK_ATCLK_AUD 38
811#define CLK_PCLK_DBG_AUD 39
812#define CLK_SCLK_AUD_CA5 40
813#define CLK_SCLK_JTAG_TCK 41
814#define CLK_SCLK_SLIMBUS_CLKIN 42
815#define CLK_SCLK_AUD_SLIMBUS 43
816#define CLK_SCLK_AUD_UART 44
817#define CLK_SCLK_AUD_PCM 45
818#define CLK_SCLK_I2S_BCLK 46
819#define CLK_SCLK_AUD_I2S 47
820
821#define AUD_NR_CLK 48
822
823/* CMU_BUS{0|1|2} */
824#define CLK_DIV_PCLK_BUS_133 1
825
826#define CLK_ACLK_AHB2APB_BUSP 2
827#define CLK_ACLK_BUSNP_133 3
828#define CLK_ACLK_BUSND_400 4
829#define CLK_PCLK_BUSSRVND_133 5
830#define CLK_PCLK_PMU_BUS 6
831#define CLK_PCLK_SYSREG_BUS 7
832
833#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */
834#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
835#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
836
837#define BUSx_NR_CLK 11
838
839/* CMU_G3D */
840#define CLK_FOUT_G3D_PLL 1
841
842#define CLK_MOUT_ACLK_G3D_400 2
843#define CLK_MOUT_G3D_PLL 3
844
845#define CLK_DIV_SCLK_HPM_G3D 4
846#define CLK_DIV_PCLK_G3D 5
847#define CLK_DIV_ACLK_G3D 6
848#define CLK_ACLK_BTS_G3D1 7
849#define CLK_ACLK_BTS_G3D0 8
850#define CLK_ACLK_ASYNCAPBS_G3D 9
851#define CLK_ACLK_ASYNCAPBM_G3D 10
852#define CLK_ACLK_AHB2APB_G3DP 11
853#define CLK_ACLK_G3DNP_150 12
854#define CLK_ACLK_G3DND_600 13
855#define CLK_ACLK_G3D 14
856#define CLK_PCLK_BTS_G3D1 15
857#define CLK_PCLK_BTS_G3D0 16
858#define CLK_PCLK_PMU_G3D 17
859#define CLK_PCLK_SYSREG_G3D 18
860#define CLK_SCLK_HPM_G3D 19
861
862#define G3D_NR_CLK 20
863
864/* CMU_GSCL */
865#define CLK_MOUT_ACLK_GSCL_111_USER 1
866#define CLK_MOUT_ACLK_GSCL_333_USER 2
867
868#define CLK_ACLK_BTS_GSCL2 3
869#define CLK_ACLK_BTS_GSCL1 4
870#define CLK_ACLK_BTS_GSCL0 5
871#define CLK_ACLK_AHB2APB_GSCLP 6
872#define CLK_ACLK_XIU_GSCLX 7
873#define CLK_ACLK_GSCLNP_111 8
874#define CLK_ACLK_GSCLRTND_333 9
875#define CLK_ACLK_GSCLBEND_333 10
876#define CLK_ACLK_GSD 11
877#define CLK_ACLK_GSCL2 12
878#define CLK_ACLK_GSCL1 13
879#define CLK_ACLK_GSCL0 14
880#define CLK_ACLK_SMMU_GSCL0 15
881#define CLK_ACLK_SMMU_GSCL1 16
882#define CLK_ACLK_SMMU_GSCL2 17
883#define CLK_PCLK_BTS_GSCL2 18
884#define CLK_PCLK_BTS_GSCL1 19
885#define CLK_PCLK_BTS_GSCL0 20
886#define CLK_PCLK_PMU_GSCL 21
887#define CLK_PCLK_SYSREG_GSCL 22
888#define CLK_PCLK_GSCL2 23
889#define CLK_PCLK_GSCL1 24
890#define CLK_PCLK_GSCL0 25
891#define CLK_PCLK_SMMU_GSCL0 26
892#define CLK_PCLK_SMMU_GSCL1 27
893#define CLK_PCLK_SMMU_GSCL2 28
894
895#define GSCL_NR_CLK 29
896
897/* CMU_APOLLO */
898#define CLK_FOUT_APOLLO_PLL 1
899
900#define CLK_MOUT_APOLLO_PLL 2
901#define CLK_MOUT_BUS_PLL_APOLLO_USER 3
902#define CLK_MOUT_APOLLO 4
903
904#define CLK_DIV_CNTCLK_APOLLO 5
905#define CLK_DIV_PCLK_DBG_APOLLO 6
906#define CLK_DIV_ATCLK_APOLLO 7
907#define CLK_DIV_PCLK_APOLLO 8
908#define CLK_DIV_ACLK_APOLLO 9
909#define CLK_DIV_APOLLO2 10
910#define CLK_DIV_APOLLO1 11
911#define CLK_DIV_SCLK_HPM_APOLLO 12
912#define CLK_DIV_APOLLO_PLL 13
913
914#define CLK_ACLK_ATBDS_APOLLO_3 14
915#define CLK_ACLK_ATBDS_APOLLO_2 15
916#define CLK_ACLK_ATBDS_APOLLO_1 16
917#define CLK_ACLK_ATBDS_APOLLO_0 17
918#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
919#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19
920#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20
921#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21
922#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22
923#define CLK_ACLK_AHB2APB_APOLLOP 23
924#define CLK_ACLK_APOLLONP_200 24
925#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
926#define CLK_PCLK_PMU_APOLLO 26
927#define CLK_PCLK_SYSREG_APOLLO 27
928#define CLK_CNTCLK_APOLLO 28
929#define CLK_SCLK_HPM_APOLLO 29
930#define CLK_SCLK_APOLLO 30
931
932#define APOLLO_NR_CLK 31
933
934/* CMU_ATLAS */
935#define CLK_FOUT_ATLAS_PLL 1
936
937#define CLK_MOUT_ATLAS_PLL 2
938#define CLK_MOUT_BUS_PLL_ATLAS_USER 3
939#define CLK_MOUT_ATLAS 4
940
941#define CLK_DIV_CNTCLK_ATLAS 5
942#define CLK_DIV_PCLK_DBG_ATLAS 6
943#define CLK_DIV_ATCLK_ATLASO 7
944#define CLK_DIV_PCLK_ATLAS 8
945#define CLK_DIV_ACLK_ATLAS 9
946#define CLK_DIV_ATLAS2 10
947#define CLK_DIV_ATLAS1 11
948#define CLK_DIV_SCLK_HPM_ATLAS 12
949#define CLK_DIV_ATLAS_PLL 13
950
951#define CLK_ACLK_ATB_AUD_CSSYS 14
952#define CLK_ACLK_ATB_APOLLO3_CSSYS 15
953#define CLK_ACLK_ATB_APOLLO2_CSSYS 16
954#define CLK_ACLK_ATB_APOLLO1_CSSYS 17
955#define CLK_ACLK_ATB_APOLLO0_CSSYS 18
956#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19
957#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20
958#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21
959#define CLK_ACLK_AHB2APB_ATLASP 22
960#define CLK_ACLK_ATLASNP_200 23
961#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24
962#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25
963#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26
964#define CLK_PCLK_PMU_ATLAS 27
965#define CLK_PCLK_SYSREG_ATLAS 28
966#define CLK_PCLK_SECJTAG 29
967#define CLK_CNTCLK_ATLAS 30
968#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31
969#define CLK_SCLK_HPM_ATLAS 32
970#define CLK_TRACECLK 33
971#define CLK_CTMCLK 34
972#define CLK_HCLK_CSSYS 35
973#define CLK_PCLK_DBG_CSSYS 36
974#define CLK_PCLK_DBG 37
975#define CLK_ATCLK 38
976#define CLK_SCLK_ATLAS 39
977
978#define ATLAS_NR_CLK 40
979
980/* CMU_MSCL */
981#define CLK_MOUT_SCLK_JPEG_USER 1
982#define CLK_MOUT_ACLK_MSCL_400_USER 2
983#define CLK_MOUT_SCLK_JPEG 3
984
985#define CLK_DIV_PCLK_MSCL 4
986
987#define CLK_ACLK_BTS_JPEG 5
988#define CLK_ACLK_BTS_M2MSCALER1 6
989#define CLK_ACLK_BTS_M2MSCALER0 7
990#define CLK_ACLK_AHB2APB_MSCL0P 8
991#define CLK_ACLK_XIU_MSCLX 9
992#define CLK_ACLK_MSCLNP_100 10
993#define CLK_ACLK_MSCLND_400 11
994#define CLK_ACLK_JPEG 12
995#define CLK_ACLK_M2MSCALER1 13
996#define CLK_ACLK_M2MSCALER0 14
997#define CLK_ACLK_SMMU_M2MSCALER0 15
998#define CLK_ACLK_SMMU_M2MSCALER1 16
999#define CLK_ACLK_SMMU_JPEG 17
1000#define CLK_PCLK_BTS_JPEG 18
1001#define CLK_PCLK_BTS_M2MSCALER1 19
1002#define CLK_PCLK_BTS_M2MSCALER0 20
1003#define CLK_PCLK_PMU_MSCL 21
1004#define CLK_PCLK_SYSREG_MSCL 22
1005#define CLK_PCLK_JPEG 23
1006#define CLK_PCLK_M2MSCALER1 24
1007#define CLK_PCLK_M2MSCALER0 25
1008#define CLK_PCLK_SMMU_M2MSCALER0 26
1009#define CLK_PCLK_SMMU_M2MSCALER1 27
1010#define CLK_PCLK_SMMU_JPEG 28
1011#define CLK_SCLK_JPEG 29
1012
1013#define MSCL_NR_CLK 30
1014
1015/* CMU_MFC */
1016#define CLK_MOUT_ACLK_MFC_400_USER 1
1017
1018#define CLK_DIV_PCLK_MFC 2
1019
1020#define CLK_ACLK_BTS_MFC_1 3
1021#define CLK_ACLK_BTS_MFC_0 4
1022#define CLK_ACLK_AHB2APB_MFCP 5
1023#define CLK_ACLK_XIU_MFCX 6
1024#define CLK_ACLK_MFCNP_100 7
1025#define CLK_ACLK_MFCND_400 8
1026#define CLK_ACLK_MFC 9
1027#define CLK_ACLK_SMMU_MFC_1 10
1028#define CLK_ACLK_SMMU_MFC_0 11
1029#define CLK_PCLK_BTS_MFC_1 12
1030#define CLK_PCLK_BTS_MFC_0 13
1031#define CLK_PCLK_PMU_MFC 14
1032#define CLK_PCLK_SYSREG_MFC 15
1033#define CLK_PCLK_MFC 16
1034#define CLK_PCLK_SMMU_MFC_1 17
1035#define CLK_PCLK_SMMU_MFC_0 18
1036
1037#define MFC_NR_CLK 19
1038
1039/* CMU_HEVC */
1040#define CLK_MOUT_ACLK_HEVC_400_USER 1
1041
1042#define CLK_DIV_PCLK_HEVC 2
1043
1044#define CLK_ACLK_BTS_HEVC_1 3
1045#define CLK_ACLK_BTS_HEVC_0 4
1046#define CLK_ACLK_AHB2APB_HEVCP 5
1047#define CLK_ACLK_XIU_HEVCX 6
1048#define CLK_ACLK_HEVCNP_100 7
1049#define CLK_ACLK_HEVCND_400 8
1050#define CLK_ACLK_HEVC 9
1051#define CLK_ACLK_SMMU_HEVC_1 10
1052#define CLK_ACLK_SMMU_HEVC_0 11
1053#define CLK_PCLK_BTS_HEVC_1 12
1054#define CLK_PCLK_BTS_HEVC_0 13
1055#define CLK_PCLK_PMU_HEVC 14
1056#define CLK_PCLK_SYSREG_HEVC 15
1057#define CLK_PCLK_HEVC 16
1058#define CLK_PCLK_SMMU_HEVC_1 17
1059#define CLK_PCLK_SMMU_HEVC_0 18
1060
1061#define HEVC_NR_CLK 19
1062
1063/* CMU_ISP */
1064#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
1065#define CLK_MOUT_ACLK_ISP_400_USER 2
1066
1067#define CLK_DIV_PCLK_ISP_DIS 3
1068#define CLK_DIV_PCLK_ISP 4
1069#define CLK_DIV_ACLK_ISP_D_200 5
1070#define CLK_DIV_ACLK_ISP_C_200 6
1071
1072#define CLK_ACLK_ISP_D_GLUE 7
1073#define CLK_ACLK_SCALERP 8
1074#define CLK_ACLK_3DNR 9
1075#define CLK_ACLK_DIS 10
1076#define CLK_ACLK_SCALERC 11
1077#define CLK_ACLK_DRC 12
1078#define CLK_ACLK_ISP 13
1079#define CLK_ACLK_AXIUS_SCALERP 14
1080#define CLK_ACLK_AXIUS_SCALERC 15
1081#define CLK_ACLK_AXIUS_DRC 16
1082#define CLK_ACLK_ASYNCAHBM_ISP2P 17
1083#define CLK_ACLK_ASYNCAHBM_ISP1P 18
1084#define CLK_ACLK_ASYNCAXIS_DIS1 19
1085#define CLK_ACLK_ASYNCAXIS_DIS0 20
1086#define CLK_ACLK_ASYNCAXIM_DIS1 21
1087#define CLK_ACLK_ASYNCAXIM_DIS0 22
1088#define CLK_ACLK_ASYNCAXIM_ISP2P 23
1089#define CLK_ACLK_ASYNCAXIM_ISP1P 24
1090#define CLK_ACLK_AHB2APB_ISP2P 25
1091#define CLK_ACLK_AHB2APB_ISP1P 26
1092#define CLK_ACLK_AXI2APB_ISP2P 27
1093#define CLK_ACLK_AXI2APB_ISP1P 28
1094#define CLK_ACLK_XIU_ISPEX1 29
1095#define CLK_ACLK_XIU_ISPEX0 30
1096#define CLK_ACLK_ISPND_400 31
1097#define CLK_ACLK_SMMU_SCALERP 32
1098#define CLK_ACLK_SMMU_3DNR 33
1099#define CLK_ACLK_SMMU_DIS1 34
1100#define CLK_ACLK_SMMU_DIS0 35
1101#define CLK_ACLK_SMMU_SCALERC 36
1102#define CLK_ACLK_SMMU_DRC 37
1103#define CLK_ACLK_SMMU_ISP 38
1104#define CLK_ACLK_BTS_SCALERP 39
1105#define CLK_ACLK_BTS_3DR 40
1106#define CLK_ACLK_BTS_DIS1 41
1107#define CLK_ACLK_BTS_DIS0 42
1108#define CLK_ACLK_BTS_SCALERC 43
1109#define CLK_ACLK_BTS_DRC 44
1110#define CLK_ACLK_BTS_ISP 45
1111#define CLK_PCLK_SMMU_SCALERP 46
1112#define CLK_PCLK_SMMU_3DNR 47
1113#define CLK_PCLK_SMMU_DIS1 48
1114#define CLK_PCLK_SMMU_DIS0 49
1115#define CLK_PCLK_SMMU_SCALERC 50
1116#define CLK_PCLK_SMMU_DRC 51
1117#define CLK_PCLK_SMMU_ISP 52
1118#define CLK_PCLK_BTS_SCALERP 53
1119#define CLK_PCLK_BTS_3DNR 54
1120#define CLK_PCLK_BTS_DIS1 55
1121#define CLK_PCLK_BTS_DIS0 56
1122#define CLK_PCLK_BTS_SCALERC 57
1123#define CLK_PCLK_BTS_DRC 58
1124#define CLK_PCLK_BTS_ISP 59
1125#define CLK_PCLK_ASYNCAXI_DIS1 60
1126#define CLK_PCLK_ASYNCAXI_DIS0 61
1127#define CLK_PCLK_PMU_ISP 62
1128#define CLK_PCLK_SYSREG_ISP 63
1129#define CLK_PCLK_CMU_ISP_LOCAL 64
1130#define CLK_PCLK_SCALERP 65
1131#define CLK_PCLK_3DNR 66
1132#define CLK_PCLK_DIS_CORE 67
1133#define CLK_PCLK_DIS 68
1134#define CLK_PCLK_SCALERC 69
1135#define CLK_PCLK_DRC 70
1136#define CLK_PCLK_ISP 71
1137#define CLK_SCLK_PIXELASYNCS_DIS 72
1138#define CLK_SCLK_PIXELASYNCM_DIS 73
1139#define CLK_SCLK_PIXELASYNCS_SCALERP 74
1140#define CLK_SCLK_PIXELASYNCM_ISPD 75
1141#define CLK_SCLK_PIXELASYNCS_ISPC 76
1142#define CLK_SCLK_PIXELASYNCM_ISPC 77
1143
1144#define ISP_NR_CLK 78
1145
1146/* CMU_CAM0 */
1147#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
1148#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
1149
1150#define CLK_MOUT_ACLK_CAM0_333_USER 3
1151#define CLK_MOUT_ACLK_CAM0_400_USER 4
1152#define CLK_MOUT_ACLK_CAM0_552_USER 5
1153#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6
1154#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7
1155#define CLK_MOUT_ACLK_LITE_D_B 8
1156#define CLK_MOUT_ACLK_LITE_D_A 9
1157#define CLK_MOUT_ACLK_LITE_B_B 10
1158#define CLK_MOUT_ACLK_LITE_B_A 11
1159#define CLK_MOUT_ACLK_LITE_A_B 12
1160#define CLK_MOUT_ACLK_LITE_A_A 13
1161#define CLK_MOUT_ACLK_CAM0_400 14
1162#define CLK_MOUT_ACLK_CSIS1_B 15
1163#define CLK_MOUT_ACLK_CSIS1_A 16
1164#define CLK_MOUT_ACLK_CSIS0_B 17
1165#define CLK_MOUT_ACLK_CSIS0_A 18
1166#define CLK_MOUT_ACLK_3AA1_B 19
1167#define CLK_MOUT_ACLK_3AA1_A 20
1168#define CLK_MOUT_ACLK_3AA0_B 21
1169#define CLK_MOUT_ACLK_3AA0_A 22
1170#define CLK_MOUT_SCLK_LITE_FREECNT_C 23
1171#define CLK_MOUT_SCLK_LITE_FREECNT_B 24
1172#define CLK_MOUT_SCLK_LITE_FREECNT_A 25
1173#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26
1174#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27
1175#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28
1176#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29
1177
1178#define CLK_DIV_PCLK_CAM0_50 30
1179#define CLK_DIV_ACLK_CAM0_200 31
1180#define CLK_DIV_ACLK_CAM0_BUS_400 32
1181#define CLK_DIV_PCLK_LITE_D 33
1182#define CLK_DIV_ACLK_LITE_D 34
1183#define CLK_DIV_PCLK_LITE_B 35
1184#define CLK_DIV_ACLK_LITE_B 36
1185#define CLK_DIV_PCLK_LITE_A 37
1186#define CLK_DIV_ACLK_LITE_A 38
1187#define CLK_DIV_ACLK_CSIS1 39
1188#define CLK_DIV_ACLK_CSIS0 40
1189#define CLK_DIV_PCLK_3AA1 41
1190#define CLK_DIV_ACLK_3AA1 42
1191#define CLK_DIV_PCLK_3AA0 43
1192#define CLK_DIV_ACLK_3AA0 44
1193#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45
1194#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46
1195#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47
1196
1197#define CLK_ACLK_CSIS1 50
1198#define CLK_ACLK_CSIS0 51
1199#define CLK_ACLK_3AA1 52
1200#define CLK_ACLK_3AA0 53
1201#define CLK_ACLK_LITE_D 54
1202#define CLK_ACLK_LITE_B 55
1203#define CLK_ACLK_LITE_A 56
1204#define CLK_ACLK_AHBSYNCDN 57
1205#define CLK_ACLK_AXIUS_LITE_D 58
1206#define CLK_ACLK_AXIUS_LITE_B 59
1207#define CLK_ACLK_AXIUS_LITE_A 60
1208#define CLK_ACLK_ASYNCAPBM_3AA1 61
1209#define CLK_ACLK_ASYNCAPBS_3AA1 62
1210#define CLK_ACLK_ASYNCAPBM_3AA0 63
1211#define CLK_ACLK_ASYNCAPBS_3AA0 64
1212#define CLK_ACLK_ASYNCAPBM_LITE_D 65
1213#define CLK_ACLK_ASYNCAPBS_LITE_D 66
1214#define CLK_ACLK_ASYNCAPBM_LITE_B 67
1215#define CLK_ACLK_ASYNCAPBS_LITE_B 68
1216#define CLK_ACLK_ASYNCAPBM_LITE_A 69
1217#define CLK_ACLK_ASYNCAPBS_LITE_A 70
1218#define CLK_ACLK_ASYNCAXIM_ISP0P 71
1219#define CLK_ACLK_ASYNCAXIM_3AA1 72
1220#define CLK_ACLK_ASYNCAXIS_3AA1 73
1221#define CLK_ACLK_ASYNCAXIM_3AA0 74
1222#define CLK_ACLK_ASYNCAXIS_3AA0 75
1223#define CLK_ACLK_ASYNCAXIM_LITE_D 76
1224#define CLK_ACLK_ASYNCAXIS_LITE_D 77
1225#define CLK_ACLK_ASYNCAXIM_LITE_B 78
1226#define CLK_ACLK_ASYNCAXIS_LITE_B 79
1227#define CLK_ACLK_ASYNCAXIM_LITE_A 80
1228#define CLK_ACLK_ASYNCAXIS_LITE_A 81
1229#define CLK_ACLK_AHB2APB_ISPSFRP 82
1230#define CLK_ACLK_AXI2APB_ISP0P 83
1231#define CLK_ACLK_AXI2AHB_ISP0P 84
1232#define CLK_ACLK_XIU_IS0X 85
1233#define CLK_ACLK_XIU_ISP0EX 86
1234#define CLK_ACLK_CAM0NP_276 87
1235#define CLK_ACLK_CAM0ND_400 88
1236#define CLK_ACLK_SMMU_3AA1 89
1237#define CLK_ACLK_SMMU_3AA0 90
1238#define CLK_ACLK_SMMU_LITE_D 91
1239#define CLK_ACLK_SMMU_LITE_B 92
1240#define CLK_ACLK_SMMU_LITE_A 93
1241#define CLK_ACLK_BTS_3AA1 94
1242#define CLK_ACLK_BTS_3AA0 95
1243#define CLK_ACLK_BTS_LITE_D 96
1244#define CLK_ACLK_BTS_LITE_B 97
1245#define CLK_ACLK_BTS_LITE_A 98
1246#define CLK_PCLK_SMMU_3AA1 99
1247#define CLK_PCLK_SMMU_3AA0 100
1248#define CLK_PCLK_SMMU_LITE_D 101
1249#define CLK_PCLK_SMMU_LITE_B 102
1250#define CLK_PCLK_SMMU_LITE_A 103
1251#define CLK_PCLK_BTS_3AA1 104
1252#define CLK_PCLK_BTS_3AA0 105
1253#define CLK_PCLK_BTS_LITE_D 106
1254#define CLK_PCLK_BTS_LITE_B 107
1255#define CLK_PCLK_BTS_LITE_A 108
1256#define CLK_PCLK_ASYNCAXI_CAM1 109
1257#define CLK_PCLK_ASYNCAXI_3AA1 110
1258#define CLK_PCLK_ASYNCAXI_3AA0 111
1259#define CLK_PCLK_ASYNCAXI_LITE_D 112
1260#define CLK_PCLK_ASYNCAXI_LITE_B 113
1261#define CLK_PCLK_ASYNCAXI_LITE_A 114
1262#define CLK_PCLK_PMU_CAM0 115
1263#define CLK_PCLK_SYSREG_CAM0 116
1264#define CLK_PCLK_CMU_CAM0_LOCAL 117
1265#define CLK_PCLK_CSIS1 118
1266#define CLK_PCLK_CSIS0 119
1267#define CLK_PCLK_3AA1 120
1268#define CLK_PCLK_3AA0 121
1269#define CLK_PCLK_LITE_D 122
1270#define CLK_PCLK_LITE_B 123
1271#define CLK_PCLK_LITE_A 124
1272#define CLK_PHYCLK_RXBYTECLKHS0_S4 125
1273#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126
1274#define CLK_SCLK_LITE_FREECNT 127
1275#define CLK_SCLK_PIXELASYNCM_3AA1 128
1276#define CLK_SCLK_PIXELASYNCM_3AA0 129
1277#define CLK_SCLK_PIXELASYNCS_3AA0 130
1278#define CLK_SCLK_PIXELASYNCM_LITE_C 131
1279#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
1280#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
1281
1282#define CAM0_NR_CLK 134
1283
1284/* CMU_CAM1 */
1285#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1
1286
1287#define CLK_MOUT_SCLK_ISP_UART_USER 2
1288#define CLK_MOUT_SCLK_ISP_SPI1_USER 3
1289#define CLK_MOUT_SCLK_ISP_SPI0_USER 4
1290#define CLK_MOUT_ACLK_CAM1_333_USER 5
1291#define CLK_MOUT_ACLK_CAM1_400_USER 6
1292#define CLK_MOUT_ACLK_CAM1_552_USER 7
1293#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8
1294#define CLK_MOUT_ACLK_CSIS2_B 9
1295#define CLK_MOUT_ACLK_CSIS2_A 10
1296#define CLK_MOUT_ACLK_FD_B 11
1297#define CLK_MOUT_ACLK_FD_A 12
1298#define CLK_MOUT_ACLK_LITE_C_B 13
1299#define CLK_MOUT_ACLK_LITE_C_A 14
1300
1301#define CLK_DIV_SCLK_ISP_WPWM 15
1302#define CLK_DIV_PCLK_CAM1_83 16
1303#define CLK_DIV_PCLK_CAM1_166 17
1304#define CLK_DIV_PCLK_DBG_CAM1 18
1305#define CLK_DIV_ATCLK_CAM1 19
1306#define CLK_DIV_ACLK_CSIS2 20
1307#define CLK_DIV_PCLK_FD 21
1308#define CLK_DIV_ACLK_FD 22
1309#define CLK_DIV_PCLK_LITE_C 23
1310#define CLK_DIV_ACLK_LITE_C 24
1311
1312#define CLK_ACLK_ISP_GIC 25
1313#define CLK_ACLK_FD 26
1314#define CLK_ACLK_LITE_C 27
1315#define CLK_ACLK_CSIS2 28
1316#define CLK_ACLK_ASYNCAPBM_FD 29
1317#define CLK_ACLK_ASYNCAPBS_FD 30
1318#define CLK_ACLK_ASYNCAPBM_LITE_C 31
1319#define CLK_ACLK_ASYNCAPBS_LITE_C 32
1320#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33
1321#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34
1322#define CLK_ACLK_ASYNCAXIM_CA5 35
1323#define CLK_ACLK_ASYNCAXIS_CA5 36
1324#define CLK_ACLK_ASYNCAXIS_ISPX2 37
1325#define CLK_ACLK_ASYNCAXIS_ISPX1 38
1326#define CLK_ACLK_ASYNCAXIS_ISPX0 39
1327#define CLK_ACLK_ASYNCAXIM_ISPEX 40
1328#define CLK_ACLK_ASYNCAXIM_ISP3P 41
1329#define CLK_ACLK_ASYNCAXIS_ISP3P 42
1330#define CLK_ACLK_ASYNCAXIM_FD 43
1331#define CLK_ACLK_ASYNCAXIS_FD 44
1332#define CLK_ACLK_ASYNCAXIM_LITE_C 45
1333#define CLK_ACLK_ASYNCAXIS_LITE_C 46
1334#define CLK_ACLK_AHB2APB_ISP5P 47
1335#define CLK_ACLK_AHB2APB_ISP3P 48
1336#define CLK_ACLK_AXI2APB_ISP3P 49
1337#define CLK_ACLK_AHB_SFRISP2H 50
1338#define CLK_ACLK_AXI_ISP_HX_R 51
1339#define CLK_ACLK_AXI_ISP_CX_R 52
1340#define CLK_ACLK_AXI_ISP_HX 53
1341#define CLK_ACLK_AXI_ISP_CX 54
1342#define CLK_ACLK_XIU_ISPX 55
1343#define CLK_ACLK_XIU_ISPEX 56
1344#define CLK_ACLK_CAM1NP_333 57
1345#define CLK_ACLK_CAM1ND_400 58
1346#define CLK_ACLK_SMMU_ISPCPU 59
1347#define CLK_ACLK_SMMU_FD 60
1348#define CLK_ACLK_SMMU_LITE_C 61
1349#define CLK_ACLK_BTS_ISP3P 62
1350#define CLK_ACLK_BTS_FD 63
1351#define CLK_ACLK_BTS_LITE_C 64
1352#define CLK_ACLK_AHBDN_SFRISP2H 65
1353#define CLK_ACLK_AHBDN_ISP5P 66
1354#define CLK_ACLK_AXIUS_ISP3P 67
1355#define CLK_ACLK_AXIUS_FD 68
1356#define CLK_ACLK_AXIUS_LITE_C 69
1357#define CLK_PCLK_SMMU_ISPCPU 70
1358#define CLK_PCLK_SMMU_FD 71
1359#define CLK_PCLK_SMMU_LITE_C 72
1360#define CLK_PCLK_BTS_ISP3P 73
1361#define CLK_PCLK_BTS_FD 74
1362#define CLK_PCLK_BTS_LITE_C 75
1363#define CLK_PCLK_ASYNCAXIM_CA5 76
1364#define CLK_PCLK_ASYNCAXIM_ISPEX 77
1365#define CLK_PCLK_ASYNCAXIM_ISP3P 78
1366#define CLK_PCLK_ASYNCAXIM_FD 79
1367#define CLK_PCLK_ASYNCAXIM_LITE_C 80
1368#define CLK_PCLK_PMU_CAM1 81
1369#define CLK_PCLK_SYSREG_CAM1 82
1370#define CLK_PCLK_CMU_CAM1_LOCAL 83
1371#define CLK_PCLK_ISP_MCTADC 84
1372#define CLK_PCLK_ISP_WDT 85
1373#define CLK_PCLK_ISP_PWM 86
1374#define CLK_PCLK_ISP_UART 87
1375#define CLK_PCLK_ISP_MCUCTL 88
1376#define CLK_PCLK_ISP_SPI1 89
1377#define CLK_PCLK_ISP_SPI0 90
1378#define CLK_PCLK_ISP_I2C2 91
1379#define CLK_PCLK_ISP_I2C1 92
1380#define CLK_PCLK_ISP_I2C0 93
1381#define CLK_PCLK_ISP_MPWM 94
1382#define CLK_PCLK_FD 95
1383#define CLK_PCLK_LITE_C 96
1384#define CLK_PCLK_CSIS2 97
1385#define CLK_SCLK_ISP_I2C2 98
1386#define CLK_SCLK_ISP_I2C1 99
1387#define CLK_SCLK_ISP_I2C0 100
1388#define CLK_SCLK_ISP_PWM 101
1389#define CLK_PHYCLK_RXBYTECLKHS0_S2B 102
1390#define CLK_SCLK_LITE_C_FREECNT 103
1391#define CLK_SCLK_PIXELASYNCM_FD 104
1392#define CLK_SCLK_ISP_MCTADC 105
1393#define CLK_SCLK_ISP_UART 106
1394#define CLK_SCLK_ISP_SPI1 107
1395#define CLK_SCLK_ISP_SPI0 108
1396#define CLK_SCLK_ISP_MPWM 109
1397#define CLK_PCLK_DBG_ISP 110
1398#define CLK_ATCLK_ISP 111
1399#define CLK_SCLK_ISP_CA5 112
1400
1401#define CAM1_NR_CLK 113
1402
1403#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 19:27:46 -0500