diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2014-12-01 17:18:53 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-12-03 18:26:51 -0500 |
commit | 6554d9a0e65d2ca0e9ac66c445d617be5d311703 (patch) | |
tree | 5bb602dd99053e23fb021ee6220c334c6ceb6b58 | |
parent | c9d61b00b9e7782191aa567d8dc09b1962d1db6a (diff) |
drm/radeon: fix copy paste typos in fan control for si/ci
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/ci_dpm.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/si_dpm.c | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 3f898d020ae6..a42f0eceffc8 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c | |||
@@ -937,7 +937,7 @@ static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) | |||
937 | tmp |= TMIN(0); | 937 | tmp |= TMIN(0); |
938 | WREG32_SMC(CG_FDO_CTRL2, tmp); | 938 | WREG32_SMC(CG_FDO_CTRL2, tmp); |
939 | 939 | ||
940 | tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; | 940 | tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; |
941 | tmp |= FDO_PWM_MODE(mode); | 941 | tmp |= FDO_PWM_MODE(mode); |
942 | WREG32_SMC(CG_FDO_CTRL2, tmp); | 942 | WREG32_SMC(CG_FDO_CTRL2, tmp); |
943 | } | 943 | } |
@@ -1162,7 +1162,7 @@ static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, | |||
1162 | tmp |= TARGET_PERIOD(tach_period); | 1162 | tmp |= TARGET_PERIOD(tach_period); |
1163 | WREG32_SMC(CG_TACH_CTRL, tmp); | 1163 | WREG32_SMC(CG_TACH_CTRL, tmp); |
1164 | 1164 | ||
1165 | ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); | 1165 | ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); |
1166 | 1166 | ||
1167 | return 0; | 1167 | return 0; |
1168 | } | 1168 | } |
@@ -1178,7 +1178,7 @@ static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev) | |||
1178 | tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); | 1178 | tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); |
1179 | WREG32_SMC(CG_FDO_CTRL2, tmp); | 1179 | WREG32_SMC(CG_FDO_CTRL2, tmp); |
1180 | 1180 | ||
1181 | tmp = RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK; | 1181 | tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; |
1182 | tmp |= TMIN(pi->t_min); | 1182 | tmp |= TMIN(pi->t_min); |
1183 | WREG32_SMC(CG_FDO_CTRL2, tmp); | 1183 | WREG32_SMC(CG_FDO_CTRL2, tmp); |
1184 | pi->fan_ctrl_is_in_default_mode = true; | 1184 | pi->fan_ctrl_is_in_default_mode = true; |
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index cf4c420b5572..32e354b8b0ab 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c | |||
@@ -5893,7 +5893,7 @@ static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) | |||
5893 | tmp |= TMIN(0); | 5893 | tmp |= TMIN(0); |
5894 | WREG32(CG_FDO_CTRL2, tmp); | 5894 | WREG32(CG_FDO_CTRL2, tmp); |
5895 | 5895 | ||
5896 | tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; | 5896 | tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; |
5897 | tmp |= FDO_PWM_MODE(mode); | 5897 | tmp |= FDO_PWM_MODE(mode); |
5898 | WREG32(CG_FDO_CTRL2, tmp); | 5898 | WREG32(CG_FDO_CTRL2, tmp); |
5899 | } | 5899 | } |
@@ -6098,7 +6098,7 @@ static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, | |||
6098 | tmp |= TARGET_PERIOD(tach_period); | 6098 | tmp |= TARGET_PERIOD(tach_period); |
6099 | WREG32(CG_TACH_CTRL, tmp); | 6099 | WREG32(CG_TACH_CTRL, tmp); |
6100 | 6100 | ||
6101 | si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); | 6101 | si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); |
6102 | 6102 | ||
6103 | return 0; | 6103 | return 0; |
6104 | } | 6104 | } |
@@ -6114,7 +6114,7 @@ static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) | |||
6114 | tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); | 6114 | tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); |
6115 | WREG32(CG_FDO_CTRL2, tmp); | 6115 | WREG32(CG_FDO_CTRL2, tmp); |
6116 | 6116 | ||
6117 | tmp = RREG32(CG_FDO_CTRL2) & TMIN_MASK; | 6117 | tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; |
6118 | tmp |= TMIN(si_pi->t_min); | 6118 | tmp |= TMIN(si_pi->t_min); |
6119 | WREG32(CG_FDO_CTRL2, tmp); | 6119 | WREG32(CG_FDO_CTRL2, tmp); |
6120 | si_pi->fan_ctrl_is_in_default_mode = true; | 6120 | si_pi->fan_ctrl_is_in_default_mode = true; |