diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-17 11:28:29 -0500 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2012-01-20 11:19:35 -0500 |
| commit | 6522ecdcfaae90ad1d2dd868fbdf3a2ddfc5f257 (patch) | |
| tree | 2d09bd02ec649657dfce40c6762a91639776a43e | |
| parent | 8134ff55646bd2c059ddfd0d479882a06d6ef09a (diff) | |
ARM: at91: fix cap9 ddrsdr register
fix AT91_DDRSDRC_MODE it's 3bit
add missing AT91_DDRSDRC_NR_14, AT91_DDRSDRC_DBW (16 and 32 bits support)
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h index 976f4a6c3353..d21932dcd6fa 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #define AT91CAP9_DDRSDR_H | 16 | #define AT91CAP9_DDRSDR_H |
| 17 | 17 | ||
| 18 | #define AT91_DDRSDRC_MR 0x00 /* Mode Register */ | 18 | #define AT91_DDRSDRC_MR 0x00 /* Mode Register */ |
| 19 | #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ | 19 | #define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ |
| 20 | #define AT91_DDRSDRC_MODE_NORMAL 0 | 20 | #define AT91_DDRSDRC_MODE_NORMAL 0 |
| 21 | #define AT91_DDRSDRC_MODE_NOP 1 | 21 | #define AT91_DDRSDRC_MODE_NOP 1 |
| 22 | #define AT91_DDRSDRC_MODE_PRECHARGE 2 | 22 | #define AT91_DDRSDRC_MODE_PRECHARGE 2 |
| @@ -42,6 +42,7 @@ | |||
| 42 | #define AT91_DDRSDRC_NR_11 (0 << 2) | 42 | #define AT91_DDRSDRC_NR_11 (0 << 2) |
| 43 | #define AT91_DDRSDRC_NR_12 (1 << 2) | 43 | #define AT91_DDRSDRC_NR_12 (1 << 2) |
| 44 | #define AT91_DDRSDRC_NR_13 (2 << 2) | 44 | #define AT91_DDRSDRC_NR_13 (2 << 2) |
| 45 | #define AT91_DDRSDRC_NR_14 (3 << 2) | ||
| 45 | #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ | 46 | #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ |
| 46 | #define AT91_DDRSDRC_CAS_2 (2 << 4) | 47 | #define AT91_DDRSDRC_CAS_2 (2 << 4) |
| 47 | #define AT91_DDRSDRC_CAS_3 (3 << 4) | 48 | #define AT91_DDRSDRC_CAS_3 (3 << 4) |
| @@ -86,6 +87,9 @@ | |||
| 86 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | 87 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
| 87 | #define AT91_DDRSDRC_MD_DDR 2 | 88 | #define AT91_DDRSDRC_MD_DDR 2 |
| 88 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | 89 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
| 90 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ | ||
| 91 | #define AT91_DDRSDRC_DBW_32BITS (0 << 4) | ||
| 92 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) | ||
| 89 | 93 | ||
| 90 | #define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ | 94 | #define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ |
| 91 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | 95 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |