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authorPalash Bandyopadhyay <palash.bandyopadhyay@conexant.com>2010-07-06 17:12:25 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-10-20 23:17:10 -0400
commit64fbf44455260684fa5bfdd3121af3d0ef0b48dd (patch)
tree3e823c84d187b8de0731cd0b703b341abd92350e
parent47b75ec14653f12f9fd6fd76bfd5891ba35e1e79 (diff)
[media] cx231xx: Added support for Carraera, Shelby, RDx_253S and VIDEO_GRABBER
Added support for new cx231xx boards - Carraera, Shelby, RDx_253S and VIDEO_GRABBER. [mchehab@redhat.com: Fix a merge conflict with BKL removal patches] Signed-off-by: Palash Bandyopadhyay <palash.bandyopadhyay@conexant.com> Signed-off-by: Devin Heitmueller <dheitmueller@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r--drivers/media/video/cx231xx/Makefile2
-rw-r--r--drivers/media/video/cx231xx/cx231xx-417.c2230
-rw-r--r--drivers/media/video/cx231xx/cx231xx-audio.c189
-rw-r--r--drivers/media/video/cx231xx/cx231xx-avcore.c631
-rw-r--r--drivers/media/video/cx231xx/cx231xx-cards.c328
-rw-r--r--drivers/media/video/cx231xx/cx231xx-conf-reg.h1
-rw-r--r--drivers/media/video/cx231xx/cx231xx-core.c662
-rw-r--r--drivers/media/video/cx231xx/cx231xx-dif.h3178
-rw-r--r--drivers/media/video/cx231xx/cx231xx-dvb.c185
-rw-r--r--drivers/media/video/cx231xx/cx231xx-i2c.c8
-rw-r--r--drivers/media/video/cx231xx/cx231xx-input.c49
-rw-r--r--drivers/media/video/cx231xx/cx231xx-vbi.c86
-rw-r--r--drivers/media/video/cx231xx/cx231xx-vbi.h2
-rw-r--r--drivers/media/video/cx231xx/cx231xx-video.c451
-rw-r--r--drivers/media/video/cx231xx/cx231xx.h231
15 files changed, 7996 insertions, 237 deletions
diff --git a/drivers/media/video/cx231xx/Makefile b/drivers/media/video/cx231xx/Makefile
index 6f2b57384488..a6bc4cc54677 100644
--- a/drivers/media/video/cx231xx/Makefile
+++ b/drivers/media/video/cx231xx/Makefile
@@ -1,5 +1,5 @@
1cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \ 1cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \
2 cx231xx-avcore.o cx231xx-pcb-cfg.o cx231xx-vbi.o 2 cx231xx-avcore.o cx231xx-417.o cx231xx-pcb-cfg.o cx231xx-vbi.o
3 3
4cx231xx-alsa-objs := cx231xx-audio.o 4cx231xx-alsa-objs := cx231xx-audio.o
5 5
diff --git a/drivers/media/video/cx231xx/cx231xx-417.c b/drivers/media/video/cx231xx/cx231xx-417.c
new file mode 100644
index 000000000000..d0e0d713a466
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-417.c
@@ -0,0 +1,2230 @@
1/*
2 *
3 * Support for a cx23417 mpeg encoder via cx231xx host port.
4 *
5 * (c) 2004 Jelle Foks <jelle@foks.us>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
8 * - CX23885/7/8 support
9 *
10 * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/fs.h>
31#include <linux/delay.h>
32#include <linux/device.h>
33#include <linux/firmware.h>
34#include <linux/smp_lock.h>
35#include <media/v4l2-common.h>
36#include <media/v4l2-ioctl.h>
37#include <media/cx2341x.h>
38#include <linux/usb.h>
39
40#include "cx231xx.h"
41/*#include "cx23885-ioctl.h"*/
42
43#define CX231xx_FIRM_IMAGE_SIZE 376836
44#define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
45
46/* for polaris ITVC*/
47#define ITVC_WRITE_DIR 0x03FDFC00
48#define ITVC_READ_DIR 0x0001FC00
49
50#define MCI_MEMORY_DATA_BYTE0 0x00
51#define MCI_MEMORY_DATA_BYTE1 0x08
52#define MCI_MEMORY_DATA_BYTE2 0x10
53#define MCI_MEMORY_DATA_BYTE3 0x18
54
55#define MCI_MEMORY_ADDRESS_BYTE2 0x20
56#define MCI_MEMORY_ADDRESS_BYTE1 0x28
57#define MCI_MEMORY_ADDRESS_BYTE0 0x30
58
59#define MCI_REGISTER_DATA_BYTE0 0x40
60#define MCI_REGISTER_DATA_BYTE1 0x48
61#define MCI_REGISTER_DATA_BYTE2 0x50
62#define MCI_REGISTER_DATA_BYTE3 0x58
63
64#define MCI_REGISTER_ADDRESS_BYTE0 0x60
65#define MCI_REGISTER_ADDRESS_BYTE1 0x68
66
67#define MCI_REGISTER_MODE 0x70
68
69/*Read and write modes
70 for polaris ITVC*/
71#define MCI_MODE_REGISTER_READ 0x000
72#define MCI_MODE_REGISTER_WRITE 0x100
73#define MCI_MODE_MEMORY_READ 0x000
74#define MCI_MODE_MEMORY_WRITE 0x4000
75
76static unsigned int mpegbufs = 8;
77module_param(mpegbufs, int, 0644);
78MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
79static unsigned int mpeglines = 128;
80module_param(mpeglines, int, 0644);
81MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
82static unsigned int mpeglinesize = 512;
83module_param(mpeglinesize, int, 0644);
84MODULE_PARM_DESC(mpeglinesize,
85 "number of bytes in each line of an MPEG buffer, range 512-1024");
86
87static unsigned int v4l_debug = 1;
88module_param(v4l_debug, int, 0644);
89MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
90struct cx231xx_dmaqueue *dma_qq;
91#define dprintk(level, fmt, arg...)\
92 do { if (v4l_debug >= level) \
93 printk(KERN_INFO "%s: " fmt, \
94 (dev) ? dev->name : "cx231xx[?]", ## arg); \
95 } while (0)
96
97static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
98 {
99 .name = "NTSC-M",
100 .id = V4L2_STD_NTSC_M,
101 }, {
102 .name = "NTSC-JP",
103 .id = V4L2_STD_NTSC_M_JP,
104 }, {
105 .name = "PAL-BG",
106 .id = V4L2_STD_PAL_BG,
107 }, {
108 .name = "PAL-DK",
109 .id = V4L2_STD_PAL_DK,
110 }, {
111 .name = "PAL-I",
112 .id = V4L2_STD_PAL_I,
113 }, {
114 .name = "PAL-M",
115 .id = V4L2_STD_PAL_M,
116 }, {
117 .name = "PAL-N",
118 .id = V4L2_STD_PAL_N,
119 }, {
120 .name = "PAL-Nc",
121 .id = V4L2_STD_PAL_Nc,
122 }, {
123 .name = "PAL-60",
124 .id = V4L2_STD_PAL_60,
125 }, {
126 .name = "SECAM-L",
127 .id = V4L2_STD_SECAM_L,
128 }, {
129 .name = "SECAM-DK",
130 .id = V4L2_STD_SECAM_DK,
131 }
132};
133
134/* ------------------------------------------------------------------ */
135enum cx231xx_capture_type {
136 CX231xx_MPEG_CAPTURE,
137 CX231xx_RAW_CAPTURE,
138 CX231xx_RAW_PASSTHRU_CAPTURE
139};
140enum cx231xx_capture_bits {
141 CX231xx_RAW_BITS_NONE = 0x00,
142 CX231xx_RAW_BITS_YUV_CAPTURE = 0x01,
143 CX231xx_RAW_BITS_PCM_CAPTURE = 0x02,
144 CX231xx_RAW_BITS_VBI_CAPTURE = 0x04,
145 CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
146 CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10
147};
148enum cx231xx_capture_end {
149 CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
150 CX231xx_END_NOW, /* stop immediately, no irq */
151};
152enum cx231xx_framerate {
153 CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
154 CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */
155};
156enum cx231xx_stream_port {
157 CX231xx_OUTPUT_PORT_MEMORY,
158 CX231xx_OUTPUT_PORT_STREAMING,
159 CX231xx_OUTPUT_PORT_SERIAL
160};
161enum cx231xx_data_xfer_status {
162 CX231xx_MORE_BUFFERS_FOLLOW,
163 CX231xx_LAST_BUFFER,
164};
165enum cx231xx_picture_mask {
166 CX231xx_PICTURE_MASK_NONE,
167 CX231xx_PICTURE_MASK_I_FRAMES,
168 CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
169 CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
170};
171enum cx231xx_vbi_mode_bits {
172 CX231xx_VBI_BITS_SLICED,
173 CX231xx_VBI_BITS_RAW,
174};
175enum cx231xx_vbi_insertion_bits {
176 CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
177 CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
178 CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
179 CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
180 CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
181};
182enum cx231xx_dma_unit {
183 CX231xx_DMA_BYTES,
184 CX231xx_DMA_FRAMES,
185};
186enum cx231xx_dma_transfer_status_bits {
187 CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
188 CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
189 CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
190};
191enum cx231xx_pause {
192 CX231xx_PAUSE_ENCODING,
193 CX231xx_RESUME_ENCODING,
194};
195enum cx231xx_copyright {
196 CX231xx_COPYRIGHT_OFF,
197 CX231xx_COPYRIGHT_ON,
198};
199enum cx231xx_notification_type {
200 CX231xx_NOTIFICATION_REFRESH,
201};
202enum cx231xx_notification_status {
203 CX231xx_NOTIFICATION_OFF,
204 CX231xx_NOTIFICATION_ON,
205};
206enum cx231xx_notification_mailbox {
207 CX231xx_NOTIFICATION_NO_MAILBOX = -1,
208};
209enum cx231xx_field1_lines {
210 CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
211 CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
212 CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
213};
214enum cx231xx_field2_lines {
215 CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
216 CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
217 CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
218};
219enum cx231xx_custom_data_type {
220 CX231xx_CUSTOM_EXTENSION_USR_DATA,
221 CX231xx_CUSTOM_PRIVATE_PACKET,
222};
223enum cx231xx_mute {
224 CX231xx_UNMUTE,
225 CX231xx_MUTE,
226};
227enum cx231xx_mute_video_mask {
228 CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
229 CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
230 CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
231};
232enum cx231xx_mute_video_shift {
233 CX231xx_MUTE_VIDEO_V_SHIFT = 8,
234 CX231xx_MUTE_VIDEO_U_SHIFT = 16,
235 CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
236};
237
238/* defines below are from ivtv-driver.h */
239#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
240
241/* Firmware API commands */
242#define IVTV_API_STD_TIMEOUT 500
243
244/* Registers */
245/* IVTV_REG_OFFSET */
246#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
247#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
248#define IVTV_REG_SPU (0x9050)
249#define IVTV_REG_HW_BLOCKS (0x9054)
250#define IVTV_REG_VPU (0x9058)
251#define IVTV_REG_APU (0xA064)
252
253/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
254 bits 31-16
255+-----------+
256| Reserved |
257+-----------+
258 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
259+-------+-------+-------+-------+-------+-------+-------+-------+
260| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
261+-------+-------+-------+-------+-------+-------+-------+-------+
262 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
263+-------+-------+-------+-------+-------+-------+-------+-------+
264|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
265+-------+-------+-------+-------+-------+-------+-------+-------+
266***/
267#define MC417_MIWR 0x8000
268#define MC417_MIRD 0x4000
269#define MC417_MICS 0x2000
270#define MC417_MIRDY 0x1000
271#define MC417_MIADDR 0x0F00
272#define MC417_MIDATA 0x00FF
273
274
275/*** Bit definitions for MC417_CTL register ****
276 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
277+--------+-------------+--------+--------------+------------+
278|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
279+--------+-------------+--------+--------------+------------+
280***/
281#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
282#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
283#define MC417_UART_GPIO_EN 0x00000001
284
285/* Values for speed control */
286#define MC417_SPD_CTL_SLOW 0x1
287#define MC417_SPD_CTL_MEDIUM 0x0
288#define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
289
290/* Values for GPIO select */
291#define MC417_GPIO_SEL_GPIO3 0x3
292#define MC417_GPIO_SEL_GPIO2 0x2
293#define MC417_GPIO_SEL_GPIO1 0x1
294#define MC417_GPIO_SEL_GPIO0 0x0
295
296
297#define CX23417_GPIO_MASK 0xFC0003FF
298int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value)
299{
300 int status = 0;
301 u32 _gpio_direction = 0;
302
303 _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
304 _gpio_direction = _gpio_direction|gpio_direction;
305 status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
306 (u8 *)&value, 4, 0, 0);
307 return status;
308}
309int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
310{
311 int status = 0;
312 u32 _gpio_direction = 0;
313
314 _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
315 _gpio_direction = _gpio_direction|gpio_direction;
316
317 status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
318 (u8 *)pValue, 4, 0, 1);
319 return status;
320}
321int waitForMciComplete(struct cx231xx *dev)
322{
323 u32 gpio;
324 u32 gpio_driection = 0;
325 u8 count = 0;
326 getITVCReg(dev, gpio_driection, &gpio);
327
328 while (!(gpio&0x020000)) {
329 msleep(10);
330
331 getITVCReg(dev, gpio_driection, &gpio);
332
333 if (count++ > 100) {
334 dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
335 return -1;
336 }
337 }
338 return 0;
339}
340int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
341{
342 u32 temp;
343 int status = 0;
344
345 temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8);
346 temp = temp<<10;
347 status = setITVCReg(dev, ITVC_WRITE_DIR, temp);
348 if (status < 0)
349 return status;
350 temp = temp|((0x05)<<10);
351 setITVCReg(dev, ITVC_WRITE_DIR, temp);
352
353 /*write data byte 1;*/
354 temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00);
355 temp = temp<<10;
356 setITVCReg(dev, ITVC_WRITE_DIR, temp);
357 temp = temp|((0x05)<<10);
358 setITVCReg(dev, ITVC_WRITE_DIR, temp);
359
360 /*write data byte 2;*/
361 temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8);
362 temp = temp<<10;
363 setITVCReg(dev, ITVC_WRITE_DIR, temp);
364 temp = temp|((0x05)<<10);
365 setITVCReg(dev, ITVC_WRITE_DIR, temp);
366
367 /*write data byte 3;*/
368 temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16);
369 temp = temp<<10;
370 setITVCReg(dev, ITVC_WRITE_DIR, temp);
371 temp = temp|((0x05)<<10);
372 setITVCReg(dev, ITVC_WRITE_DIR, temp);
373
374 /*write address byte 0;*/
375 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8);
376 temp = temp<<10;
377 setITVCReg(dev, ITVC_WRITE_DIR, temp);
378 temp = temp|((0x05)<<10);
379 setITVCReg(dev, ITVC_WRITE_DIR, temp);
380
381 /*write address byte 1;*/
382 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00);
383 temp = temp<<10;
384 setITVCReg(dev, ITVC_WRITE_DIR, temp);
385 temp = temp|((0x05)<<10);
386 setITVCReg(dev, ITVC_WRITE_DIR, temp);
387
388 /*Write that the mode is write.*/
389 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
390 temp = temp<<10;
391 setITVCReg(dev, ITVC_WRITE_DIR, temp);
392 temp = temp|((0x05)<<10);
393 setITVCReg(dev, ITVC_WRITE_DIR, temp);
394
395 return waitForMciComplete(dev);
396
397}
398
399
400int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
401{
402 /*write address byte 0;*/
403 u32 temp;
404 u32 return_value = 0;
405 int ret = 0;
406
407 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x00FF)<<8);
408 temp = temp<<10;
409 setITVCReg(dev, ITVC_WRITE_DIR, temp);
410 temp = temp|((0x05)<<10);
411 setITVCReg(dev, ITVC_WRITE_DIR, temp);
412
413 /*write address byte 1;*/
414 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0xFF00);
415 temp = temp<<10;
416 setITVCReg(dev, ITVC_WRITE_DIR, temp);
417 temp = temp|((0x05)<<10);
418 setITVCReg(dev, ITVC_WRITE_DIR, temp);
419
420 /*write that the mode is read;*/
421 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
422 temp = temp<<10;
423 setITVCReg(dev, ITVC_WRITE_DIR, temp);
424 temp = temp|((0x05)<<10);
425 setITVCReg(dev, ITVC_WRITE_DIR, temp);
426
427 /*wait for the MIRDY line to be asserted ,
428 signalling that the read is done;*/
429 ret = waitForMciComplete(dev);
430
431
432 /*switch the DATA- GPIO to input mode;*/
433
434 /*Read data byte 0;*/
435 temp = (0x82|MCI_REGISTER_DATA_BYTE0)<<10;
436 setITVCReg(dev, ITVC_READ_DIR, temp);
437 temp = ((0x81|MCI_REGISTER_DATA_BYTE0)<<10);
438 setITVCReg(dev, ITVC_READ_DIR, temp);
439 getITVCReg(dev, ITVC_READ_DIR, &temp);
440 return_value |= ((temp&0x03FC0000)>>18);
441 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
442
443 /* Read data byte 1;*/
444 temp = (0x82|MCI_REGISTER_DATA_BYTE1)<<10;
445 setITVCReg(dev, ITVC_READ_DIR, temp);
446 temp = ((0x81|MCI_REGISTER_DATA_BYTE1)<<10);
447 setITVCReg(dev, ITVC_READ_DIR, temp);
448 getITVCReg(dev, ITVC_READ_DIR, &temp);
449
450 return_value |= ((temp&0x03FC0000)>>10);
451 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
452
453 /*Read data byte 2;*/
454 temp = (0x82|MCI_REGISTER_DATA_BYTE2)<<10;
455 setITVCReg(dev, ITVC_READ_DIR, temp);
456 temp = ((0x81|MCI_REGISTER_DATA_BYTE2)<<10);
457 setITVCReg(dev, ITVC_READ_DIR, temp);
458 getITVCReg(dev, ITVC_READ_DIR, &temp);
459 return_value |= ((temp&0x03FC0000)>>2);
460 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
461
462 /*Read data byte 3;*/
463 temp = (0x82|MCI_REGISTER_DATA_BYTE3)<<10;
464 setITVCReg(dev, ITVC_READ_DIR, temp);
465 temp = ((0x81|MCI_REGISTER_DATA_BYTE3)<<10);
466 setITVCReg(dev, ITVC_READ_DIR, temp);
467 getITVCReg(dev, ITVC_READ_DIR, &temp);
468 return_value |= ((temp&0x03FC0000)<<6);
469 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
470
471 *value = return_value;
472
473
474 return ret;
475}
476
477int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
478{
479
480 /*write data byte 0;*/
481
482 u32 temp;
483 int ret = 0;
484
485 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
486 temp = temp<<10;
487 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
488 if (ret < 0)
489 return ret;
490 temp = temp|((0x05)<<10);
491 setITVCReg(dev, ITVC_WRITE_DIR, temp);
492
493 /*write data byte 1;*/
494 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
495 temp = temp<<10;
496 setITVCReg(dev, ITVC_WRITE_DIR, temp);
497 temp = temp|((0x05)<<10);
498 setITVCReg(dev, ITVC_WRITE_DIR, temp);
499
500 /*write data byte 2;*/
501 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
502 temp = temp<<10;
503 setITVCReg(dev, ITVC_WRITE_DIR, temp);
504 temp = temp|((0x05)<<10);
505 setITVCReg(dev, ITVC_WRITE_DIR, temp);
506
507 /*write data byte 3;*/
508 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
509 temp = temp<<10;
510 setITVCReg(dev, ITVC_WRITE_DIR, temp);
511 temp = temp|((0x05)<<10);
512 setITVCReg(dev, ITVC_WRITE_DIR, temp);
513
514 /* write address byte 2;*/
515 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
516 ((address & 0x003F0000)>>8);
517 temp = temp<<10;
518 setITVCReg(dev, ITVC_WRITE_DIR, temp);
519 temp = temp|((0x05)<<10);
520 setITVCReg(dev, ITVC_WRITE_DIR, temp);
521
522 /* write address byte 1;*/
523 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
524 temp = temp<<10;
525 setITVCReg(dev, ITVC_WRITE_DIR, temp);
526 temp = temp|((0x05)<<10);
527 setITVCReg(dev, ITVC_WRITE_DIR, temp);
528
529 /* write address byte 0;*/
530 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
531 temp = temp<<10;
532 setITVCReg(dev, ITVC_WRITE_DIR, temp);
533 temp = temp|((0x05)<<10);
534 setITVCReg(dev, ITVC_WRITE_DIR, temp);
535
536 /*wait for MIRDY line;*/
537 waitForMciComplete(dev);
538
539return 0;
540
541}
542
543int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
544{
545
546 u32 temp = 0;
547 u32 return_value = 0;
548 int ret = 0;
549
550 /*write address byte 2;*/
551 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
552 ((address & 0x003F0000)>>8);
553 temp = temp<<10;
554 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
555 if (ret < 0)
556 return ret;
557 temp = temp|((0x05)<<10);
558 setITVCReg(dev, ITVC_WRITE_DIR, temp);
559
560 /*write address byte 1*/
561 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
562 temp = temp<<10;
563 setITVCReg(dev, ITVC_WRITE_DIR, temp);
564 temp = temp|((0x05)<<10);
565 setITVCReg(dev, ITVC_WRITE_DIR, temp);
566
567 /*write address byte 0*/
568 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8);
569 temp = temp<<10;
570 setITVCReg(dev, ITVC_WRITE_DIR, temp);
571 temp = temp|((0x05)<<10);
572 setITVCReg(dev, ITVC_WRITE_DIR, temp);
573
574 /*Wait for MIRDY line*/
575 ret = waitForMciComplete(dev);
576
577
578 /*Read data byte 3;*/
579 temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10;
580 setITVCReg(dev, ITVC_READ_DIR, temp);
581 temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10);
582 setITVCReg(dev, ITVC_READ_DIR, temp);
583 getITVCReg(dev, ITVC_READ_DIR, &temp);
584 return_value |= ((temp&0x03FC0000)<<6);
585 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
586
587 /*Read data byte 2;*/
588 temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10;
589 setITVCReg(dev, ITVC_READ_DIR, temp);
590 temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10);
591 setITVCReg(dev, ITVC_READ_DIR, temp);
592 getITVCReg(dev, ITVC_READ_DIR, &temp);
593 return_value |= ((temp&0x03FC0000)>>2);
594 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
595
596 /* Read data byte 1;*/
597 temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10;
598 setITVCReg(dev, ITVC_READ_DIR, temp);
599 temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10);
600 setITVCReg(dev, ITVC_READ_DIR, temp);
601 getITVCReg(dev, ITVC_READ_DIR, &temp);
602 return_value |= ((temp&0x03FC0000)>>10);
603 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
604
605 /*Read data byte 0;*/
606 temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10;
607 setITVCReg(dev, ITVC_READ_DIR, temp);
608 temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10);
609 setITVCReg(dev, ITVC_READ_DIR, temp);
610 getITVCReg(dev, ITVC_READ_DIR, &temp);
611 return_value |= ((temp&0x03FC0000)>>18);
612 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
613
614 *value = return_value;
615 return ret;
616}
617
618void mc417_gpio_set(struct cx231xx *dev, u32 mask)
619{
620 u32 val;
621
622 /* Set the gpio value */
623 mc417_register_read(dev, 0x900C, &val);
624 val |= (mask & 0x000ffff);
625 mc417_register_write(dev, 0x900C, val);
626}
627
628void mc417_gpio_clear(struct cx231xx *dev, u32 mask)
629{
630 u32 val;
631
632 /* Clear the gpio value */
633 mc417_register_read(dev, 0x900C, &val);
634 val &= ~(mask & 0x0000ffff);
635 mc417_register_write(dev, 0x900C, val);
636}
637
638void mc417_gpio_enable(struct cx231xx *dev, u32 mask, int asoutput)
639{
640 u32 val;
641
642 /* Enable GPIO direction bits */
643 mc417_register_read(dev, 0x9020, &val);
644 if (asoutput)
645 val |= (mask & 0x0000ffff);
646 else
647 val &= ~(mask & 0x0000ffff);
648
649 mc417_register_write(dev, 0x9020, val);
650}
651/* ------------------------------------------------------------------ */
652
653/* MPEG encoder API */
654static char *cmd_to_str(int cmd)
655{
656 switch (cmd) {
657 case CX2341X_ENC_PING_FW:
658 return "PING_FW";
659 case CX2341X_ENC_START_CAPTURE:
660 return "START_CAPTURE";
661 case CX2341X_ENC_STOP_CAPTURE:
662 return "STOP_CAPTURE";
663 case CX2341X_ENC_SET_AUDIO_ID:
664 return "SET_AUDIO_ID";
665 case CX2341X_ENC_SET_VIDEO_ID:
666 return "SET_VIDEO_ID";
667 case CX2341X_ENC_SET_PCR_ID:
668 return "SET_PCR_PID";
669 case CX2341X_ENC_SET_FRAME_RATE:
670 return "SET_FRAME_RATE";
671 case CX2341X_ENC_SET_FRAME_SIZE:
672 return "SET_FRAME_SIZE";
673 case CX2341X_ENC_SET_BIT_RATE:
674 return "SET_BIT_RATE";
675 case CX2341X_ENC_SET_GOP_PROPERTIES:
676 return "SET_GOP_PROPERTIES";
677 case CX2341X_ENC_SET_ASPECT_RATIO:
678 return "SET_ASPECT_RATIO";
679 case CX2341X_ENC_SET_DNR_FILTER_MODE:
680 return "SET_DNR_FILTER_PROPS";
681 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
682 return "SET_DNR_FILTER_PROPS";
683 case CX2341X_ENC_SET_CORING_LEVELS:
684 return "SET_CORING_LEVELS";
685 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
686 return "SET_SPATIAL_FILTER_TYPE";
687 case CX2341X_ENC_SET_VBI_LINE:
688 return "SET_VBI_LINE";
689 case CX2341X_ENC_SET_STREAM_TYPE:
690 return "SET_STREAM_TYPE";
691 case CX2341X_ENC_SET_OUTPUT_PORT:
692 return "SET_OUTPUT_PORT";
693 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
694 return "SET_AUDIO_PROPERTIES";
695 case CX2341X_ENC_HALT_FW:
696 return "HALT_FW";
697 case CX2341X_ENC_GET_VERSION:
698 return "GET_VERSION";
699 case CX2341X_ENC_SET_GOP_CLOSURE:
700 return "SET_GOP_CLOSURE";
701 case CX2341X_ENC_GET_SEQ_END:
702 return "GET_SEQ_END";
703 case CX2341X_ENC_SET_PGM_INDEX_INFO:
704 return "SET_PGM_INDEX_INFO";
705 case CX2341X_ENC_SET_VBI_CONFIG:
706 return "SET_VBI_CONFIG";
707 case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
708 return "SET_DMA_BLOCK_SIZE";
709 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
710 return "GET_PREV_DMA_INFO_MB_10";
711 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
712 return "GET_PREV_DMA_INFO_MB_9";
713 case CX2341X_ENC_SCHED_DMA_TO_HOST:
714 return "SCHED_DMA_TO_HOST";
715 case CX2341X_ENC_INITIALIZE_INPUT:
716 return "INITIALIZE_INPUT";
717 case CX2341X_ENC_SET_FRAME_DROP_RATE:
718 return "SET_FRAME_DROP_RATE";
719 case CX2341X_ENC_PAUSE_ENCODER:
720 return "PAUSE_ENCODER";
721 case CX2341X_ENC_REFRESH_INPUT:
722 return "REFRESH_INPUT";
723 case CX2341X_ENC_SET_COPYRIGHT:
724 return "SET_COPYRIGHT";
725 case CX2341X_ENC_SET_EVENT_NOTIFICATION:
726 return "SET_EVENT_NOTIFICATION";
727 case CX2341X_ENC_SET_NUM_VSYNC_LINES:
728 return "SET_NUM_VSYNC_LINES";
729 case CX2341X_ENC_SET_PLACEHOLDER:
730 return "SET_PLACEHOLDER";
731 case CX2341X_ENC_MUTE_VIDEO:
732 return "MUTE_VIDEO";
733 case CX2341X_ENC_MUTE_AUDIO:
734 return "MUTE_AUDIO";
735 case CX2341X_ENC_MISC:
736 return "MISC";
737 default:
738 return "UNKNOWN";
739 }
740}
741
742static int cx231xx_mbox_func(void *priv,
743 u32 command,
744 int in,
745 int out,
746 u32 data[CX2341X_MBOX_MAX_DATA])
747{
748 struct cx231xx *dev = priv;
749 unsigned long timeout;
750 u32 value, flag, retval = 0;
751 int i;
752
753 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
754 cmd_to_str(command));
755
756 /* this may not be 100% safe if we can't read any memory location
757 without side effects */
758 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
759 if (value != 0x12345678) {
760 dprintk(3,
761 "Firmware and/or mailbox pointer not initialized "
762 "or corrupted, signature = 0x%x, cmd = %s\n", value,
763 cmd_to_str(command));
764 return -1;
765 }
766
767 /* This read looks at 32 bits, but flag is only 8 bits.
768 * Seems we also bail if CMD or TIMEOUT bytes are set???
769 */
770 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
771 if (flag) {
772 dprintk(3, "ERROR: Mailbox appears to be in use "
773 "(%x), cmd = %s\n", flag, cmd_to_str(command));
774 return -1;
775 }
776
777 flag |= 1; /* tell 'em we're working on it */
778 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
779
780 /* write command + args + fill remaining with zeros */
781 /* command code */
782 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
783 mc417_memory_write(dev, dev->cx23417_mailbox + 3,
784 IVTV_API_STD_TIMEOUT); /* timeout */
785 for (i = 0; i < in; i++) {
786 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
787 dprintk(3, "API Input %d = %d\n", i, data[i]);
788 }
789 for (; i < CX2341X_MBOX_MAX_DATA; i++)
790 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
791
792 flag |= 3; /* tell 'em we're done writing */
793 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
794
795 /* wait for firmware to handle the API command */
796 timeout = jiffies + msecs_to_jiffies(10);
797 for (;;) {
798 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
799 if (0 != (flag & 4))
800 break;
801 if (time_after(jiffies, timeout)) {
802 dprintk(3, "ERROR: API Mailbox timeout\n");
803 return -1;
804 }
805 udelay(10);
806 }
807
808 /* read output values */
809 for (i = 0; i < out; i++) {
810 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
811 dprintk(3, "API Output %d = %d\n", i, data[i]);
812 }
813
814 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
815 dprintk(3, "API result = %d\n", retval);
816
817 flag = 0;
818 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
819
820 return retval;
821}
822
823/* We don't need to call the API often, so using just one
824 * mailbox will probably suffice
825 */
826static int cx231xx_api_cmd(struct cx231xx *dev,
827 u32 command,
828 u32 inputcnt,
829 u32 outputcnt,
830 ...)
831{
832 u32 data[CX2341X_MBOX_MAX_DATA];
833 va_list vargs;
834 int i, err;
835
836 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
837
838 va_start(vargs, outputcnt);
839 for (i = 0; i < inputcnt; i++)
840 data[i] = va_arg(vargs, int);
841
842 err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
843 for (i = 0; i < outputcnt; i++) {
844 int *vptr = va_arg(vargs, int *);
845 *vptr = data[i];
846 }
847 va_end(vargs);
848
849 return err;
850}
851
852static int cx231xx_find_mailbox(struct cx231xx *dev)
853{
854 u32 signature[4] = {
855 0x12345678, 0x34567812, 0x56781234, 0x78123456
856 };
857 int signaturecnt = 0;
858 u32 value;
859 int i;
860 int ret = 0;
861
862 dprintk(2, "%s()\n", __func__);
863
864 for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
865 ret = mc417_memory_read(dev, i, &value);
866 if (ret < 0)
867 return ret;
868 if (value == signature[signaturecnt])
869 signaturecnt++;
870 else
871 signaturecnt = 0;
872 if (4 == signaturecnt) {
873 dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
874 return i+1;
875 }
876 }
877 dprintk(3, "Mailbox signature values not found!\n");
878 return -1;
879}
880void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value,
881 u32 *p_fw_image)
882{
883
884 u32 temp = 0;
885 int i = 0;
886
887 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
888 temp = temp<<10;
889 *p_fw_image = temp;
890 p_fw_image++;
891 temp = temp|((0x05)<<10);
892 *p_fw_image = temp;
893 p_fw_image++;
894
895 /*write data byte 1;*/
896 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
897 temp = temp<<10;
898 *p_fw_image = temp;
899 p_fw_image++;
900 temp = temp|((0x05)<<10);
901 *p_fw_image = temp;
902 p_fw_image++;
903
904 /*write data byte 2;*/
905 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
906 temp = temp<<10;
907 *p_fw_image = temp;
908 p_fw_image++;
909 temp = temp|((0x05)<<10);
910 *p_fw_image = temp;
911 p_fw_image++;
912
913 /*write data byte 3;*/
914 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
915 temp = temp<<10;
916 *p_fw_image = temp;
917 p_fw_image++;
918 temp = temp|((0x05)<<10);
919 *p_fw_image = temp;
920 p_fw_image++;
921
922 /* write address byte 2;*/
923 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
924 ((address & 0x003F0000)>>8);
925 temp = temp<<10;
926 *p_fw_image = temp;
927 p_fw_image++;
928 temp = temp|((0x05)<<10);
929 *p_fw_image = temp;
930 p_fw_image++;
931
932 /* write address byte 1;*/
933 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
934 temp = temp<<10;
935 *p_fw_image = temp;
936 p_fw_image++;
937 temp = temp|((0x05)<<10);
938 *p_fw_image = temp;
939 p_fw_image++;
940
941 /* write address byte 0;*/
942 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
943 temp = temp<<10;
944 *p_fw_image = temp;
945 p_fw_image++;
946 temp = temp|((0x05)<<10);
947 *p_fw_image = temp;
948 p_fw_image++;
949
950 for (i = 0; i < 6; i++) {
951 *p_fw_image = 0xFFFFFFFF;
952 p_fw_image++;
953 }
954
955}
956
957
958static int cx231xx_load_firmware(struct cx231xx *dev)
959{
960 static const unsigned char magic[8] = {
961 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
962 };
963 const struct firmware *firmware;
964 int i, retval = 0;
965 u32 value = 0;
966 u32 gpio_output = 0;
967 /*u32 checksum = 0;*/
968 /*u32 *dataptr;*/
969 u32 transfer_size = 0;
970 u32 fw_data = 0;
971 u32 address = 0;
972 /*u32 current_fw[800];*/
973 u32 *p_current_fw, *p_fw;
974 u32 *p_fw_data;
975 int frame = 0;
976 u16 _buffer_size = 4096;
977 u8 *p_buffer;
978
979 p_current_fw = (u32 *)vmalloc(1884180*4);
980 p_fw = p_current_fw;
981 if (p_current_fw == 0) {
982 dprintk(2, "FAIL!!!\n");
983 return -1;
984 }
985
986 p_buffer = (u8 *)vmalloc(4096);
987 if (p_buffer == 0) {
988 dprintk(2, "FAIL!!!\n");
989 return -1;
990 }
991
992 dprintk(2, "%s()\n", __func__);
993
994 /* Save GPIO settings before reset of APU */
995 retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
996 retval |= mc417_memory_read(dev, 0x900C, &value);
997
998 retval = mc417_register_write(dev,
999 IVTV_REG_VPU, 0xFFFFFFED);
1000 retval |= mc417_register_write(dev,
1001 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
1002 retval |= mc417_register_write(dev,
1003 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
1004 retval |= mc417_register_write(dev,
1005 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
1006 retval |= mc417_register_write(dev,
1007 IVTV_REG_APU, 0);
1008
1009 if (retval != 0) {
1010 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1011 __func__);
1012 return -1;
1013 }
1014
1015 retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
1016 &dev->udev->dev);
1017
1018 if (retval != 0) {
1019 printk(KERN_ERR
1020 "ERROR: Hotplug firmware request failed (%s).\n",
1021 CX231xx_FIRM_IMAGE_NAME);
1022 printk(KERN_ERR "Please fix your hotplug setup, the board will "
1023 "not work without firmware loaded!\n");
1024 return -1;
1025 }
1026
1027 if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
1028 printk(KERN_ERR "ERROR: Firmware size mismatch "
1029 "(have %zd, expected %d)\n",
1030 firmware->size, CX231xx_FIRM_IMAGE_SIZE);
1031 release_firmware(firmware);
1032 return -1;
1033 }
1034
1035 if (0 != memcmp(firmware->data, magic, 8)) {
1036 printk(KERN_ERR
1037 "ERROR: Firmware magic mismatch, wrong file?\n");
1038 release_firmware(firmware);
1039 return -1;
1040 }
1041
1042 initGPIO(dev);
1043
1044 /* transfer to the chip */
1045 dprintk(2, "Loading firmware to GPIO...\n");
1046 p_fw_data = (u32 *)firmware->data;
1047 dprintk(2, "firmware->size=%d\n", firmware->size);
1048 for (transfer_size = 0; transfer_size < firmware->size;
1049 transfer_size += 4) {
1050 fw_data = *p_fw_data;
1051
1052 mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw);
1053 address = address + 1;
1054 p_current_fw += 20;
1055 p_fw_data += 1;
1056 }
1057
1058/*download the firmware by ep5-out*/
1059
1060 for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1061 frame++) {
1062 for (i = 0; i < _buffer_size; i++) {
1063 *(p_buffer+i) =
1064 (u8)(*(p_fw+(frame*128*8+(i++/4))) & 0x000000FF);
1065 *(p_buffer+i) =
1066 (u8)((*(p_fw+(frame*128*8+(i++/4))) & 0x0000FF00)>>8);
1067 *(p_buffer+i) =
1068 (u8)((*(p_fw+(frame*128*8+(i++/4))) & 0x00FF0000)>>16);
1069 *(p_buffer+i) =
1070 (u8)((*(p_fw+(frame*128*8+(i/4))) & 0xFF000000)>>24);
1071 }
1072 cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1073 }
1074
1075 p_current_fw = p_fw;
1076 vfree(p_current_fw);
1077 p_current_fw = NULL;
1078 uninitGPIO(dev);
1079 release_firmware(firmware);
1080 dprintk(1, "Firmware upload successful.\n");
1081
1082 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1083 IVTV_CMD_HW_BLOCKS_RST);
1084 if (retval < 0) {
1085 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1086 __func__);
1087 return retval;
1088 }
1089 /* F/W power up disturbs the GPIOs, restore state */
1090 retval |= mc417_register_write(dev, 0x9020, gpio_output);
1091 retval |= mc417_register_write(dev, 0x900C, value);
1092
1093 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1094 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1095
1096 if (retval < 0) {
1097 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1098 __func__);
1099 return retval;
1100 }
1101 return 0;
1102}
1103
1104void cx231xx_417_check_encoder(struct cx231xx *dev)
1105{
1106 u32 status, seq;
1107
1108 status = 0;
1109 seq = 0;
1110 cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1111 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1112}
1113
1114static void cx231xx_codec_settings(struct cx231xx *dev)
1115{
1116 dprintk(1, "%s()\n", __func__);
1117
1118 /* assign frame size */
1119 cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1120 dev->ts1.height, dev->ts1.width);
1121
1122 dev->mpeg_params.width = dev->ts1.width;
1123 dev->mpeg_params.height = dev->ts1.height;
1124
1125 cx2341x_update(dev, cx231xx_mbox_func, NULL, &dev->mpeg_params);
1126
1127 cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1128 cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1129}
1130
1131static int cx231xx_initialize_codec(struct cx231xx *dev)
1132{
1133 int version;
1134 int retval;
1135 u32 i, data[7];
1136 u32 val = 0;
1137
1138 dprintk(1, "%s()\n", __func__);
1139 cx231xx_disable656(dev);
1140 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1141 if (retval < 0) {
1142 dprintk(2, "%s() PING OK\n", __func__);
1143 retval = cx231xx_load_firmware(dev);
1144 if (retval < 0) {
1145 printk(KERN_ERR "%s() f/w load failed\n", __func__);
1146 return retval;
1147 }
1148 retval = cx231xx_find_mailbox(dev);
1149 if (retval < 0) {
1150 printk(KERN_ERR "%s() mailbox < 0, error\n",
1151 __func__);
1152 return -1;
1153 }
1154 dev->cx23417_mailbox = retval;
1155 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1156 if (retval < 0) {
1157 printk(KERN_ERR
1158 "ERROR: cx23417 firmware ping failed!\n");
1159 return -1;
1160 }
1161 retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1162 &version);
1163 if (retval < 0) {
1164 printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1165 "version failed!\n");
1166 return -1;
1167 }
1168 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1169 msleep(200);
1170 }
1171
1172 for (i = 0; i < 1; i++) {
1173 retval = mc417_register_read(dev, 0x20f8, &val);
1174 dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n",
1175 val);
1176 if (retval < 0)
1177 return retval;
1178 }
1179
1180 cx231xx_enable656(dev);
1181 /* stop mpeg capture */
1182 cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
1183 3, 0, 1, 3, 4);
1184
1185 cx231xx_codec_settings(dev);
1186 msleep(60);
1187
1188/* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1189 CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1190 cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1191 CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1192 0, 0);
1193*/
1194 /* Setup to capture VBI */
1195 data[0] = 0x0001BD00;
1196 data[1] = 1; /* frames per interrupt */
1197 data[2] = 4; /* total bufs */
1198 data[3] = 0x91559155; /* start codes */
1199 data[4] = 0x206080C0; /* stop codes */
1200 data[5] = 6; /* lines */
1201 data[6] = 64; /* BPL */
1202/*
1203 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1204 data[2], data[3], data[4], data[5], data[6]);
1205
1206 for (i = 2; i <= 24; i++) {
1207 int valid;
1208
1209 valid = ((i >= 19) && (i <= 21));
1210 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1211 valid, 0 , 0, 0);
1212 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1213 i | 0x80000000, valid, 0, 0, 0);
1214 }
1215*/
1216/* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1217 msleep(60);
1218*/
1219 /* initialize the video input */
1220 retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1221 if (retval < 0)
1222 return retval;
1223 msleep(60);
1224
1225 /* Enable VIP style pixel invalidation so we work with scaled mode */
1226 mc417_memory_write(dev, 2120, 0x00000080);
1227
1228 /* start capturing to the host interface */
1229 retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1230 CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1231 if (retval < 0)
1232 return retval;
1233 msleep(10);
1234
1235 for (i = 0; i < 1; i++) {
1236 mc417_register_read(dev, 0x20f8, &val);
1237 dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1238 }
1239
1240 return 0;
1241}
1242
1243/* ------------------------------------------------------------------ */
1244
1245static int bb_buf_setup(struct videobuf_queue *q,
1246 unsigned int *count, unsigned int *size)
1247{
1248 struct cx231xx_fh *fh = q->priv_data;
1249
1250 fh->dev->ts1.ts_packet_size = mpeglinesize;
1251 fh->dev->ts1.ts_packet_count = mpeglines;
1252
1253 *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1254 *count = mpegbufs;
1255
1256 return 0;
1257}
1258static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1259{
1260 struct cx231xx_fh *fh = vq->priv_data;
1261 struct cx231xx *dev = fh->dev;
1262 unsigned long flags = 0;
1263
1264 if (in_interrupt())
1265 BUG();
1266
1267 spin_lock_irqsave(&dev->video_mode.slock, flags);
1268 if (dev->USE_ISO) {
1269 if (dev->video_mode.isoc_ctl.buf == buf)
1270 dev->video_mode.isoc_ctl.buf = NULL;
1271 } else {
1272 if (dev->video_mode.bulk_ctl.buf == buf)
1273 dev->video_mode.bulk_ctl.buf = NULL;
1274 }
1275 spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1276 videobuf_waiton(vq, &buf->vb, 0, 0);
1277 videobuf_vmalloc_free(&buf->vb);
1278 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1279}
1280
1281void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1282 struct cx231xx_dmaqueue *dma_q)
1283{
1284 void *vbuf;
1285 struct cx231xx_buffer *buf;
1286 u32 tail_data = 0;
1287 char *p_data;
1288
1289 if (dma_q->mpeg_buffer_done == 0) {
1290 if (list_empty(&dma_q->active))
1291 return;
1292
1293 buf = list_entry(dma_q->active.next,
1294 struct cx231xx_buffer, vb.queue);
1295 dev->video_mode.isoc_ctl.buf = buf;
1296 dma_q->mpeg_buffer_done = 1;
1297 }
1298 /* Fill buffer */
1299 buf = dev->video_mode.isoc_ctl.buf;
1300 vbuf = videobuf_to_vmalloc(&buf->vb);
1301
1302 if ((dma_q->mpeg_buffer_completed+len) <
1303 mpeglines*mpeglinesize) {
1304 if (dma_q->add_ps_package_head ==
1305 CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1306 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1307 dma_q->ps_head, 3);
1308 dma_q->mpeg_buffer_completed =
1309 dma_q->mpeg_buffer_completed + 3;
1310 dma_q->add_ps_package_head =
1311 CX231XX_NONEED_PS_PACKAGE_HEAD;
1312 }
1313 memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1314 dma_q->mpeg_buffer_completed =
1315 dma_q->mpeg_buffer_completed + len;
1316 } else {
1317 dma_q->mpeg_buffer_done = 0;
1318
1319 tail_data =
1320 mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1321 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1322 data, tail_data);
1323
1324 buf->vb.state = VIDEOBUF_DONE;
1325 buf->vb.field_count++;
1326 do_gettimeofday(&buf->vb.ts);
1327 list_del(&buf->vb.queue);
1328 wake_up(&buf->vb.done);
1329 dma_q->mpeg_buffer_completed = 0;
1330
1331 if (len - tail_data > 0) {
1332 p_data = data + tail_data;
1333 dma_q->left_data_count = len - tail_data;
1334 memcpy(dma_q->p_left_data,
1335 p_data, len - tail_data);
1336 }
1337
1338 }
1339
1340 return;
1341}
1342
1343void buffer_filled(char *data, int len, struct urb *urb,
1344 struct cx231xx_dmaqueue *dma_q)
1345{
1346 void *vbuf;
1347 struct cx231xx_buffer *buf;
1348
1349 if (list_empty(&dma_q->active))
1350 return;
1351
1352
1353 buf = list_entry(dma_q->active.next,
1354 struct cx231xx_buffer, vb.queue);
1355
1356
1357 /* Fill buffer */
1358 vbuf = videobuf_to_vmalloc(&buf->vb);
1359 memcpy(vbuf, data, len);
1360 buf->vb.state = VIDEOBUF_DONE;
1361 buf->vb.field_count++;
1362 do_gettimeofday(&buf->vb.ts);
1363 list_del(&buf->vb.queue);
1364 wake_up(&buf->vb.done);
1365
1366 return;
1367}
1368static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1369{
1370 struct cx231xx_dmaqueue *dma_q = urb->context;
1371 unsigned char *p_buffer;
1372 u32 buffer_size = 0;
1373 u32 i = 0;
1374
1375 for (i = 0; i < urb->number_of_packets; i++) {
1376 if (dma_q->left_data_count > 0) {
1377 buffer_copy(dev, dma_q->p_left_data,
1378 dma_q->left_data_count, urb, dma_q);
1379 dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1380 dma_q->left_data_count = 0;
1381 }
1382
1383 p_buffer = urb->transfer_buffer +
1384 urb->iso_frame_desc[i].offset;
1385 buffer_size = urb->iso_frame_desc[i].actual_length;
1386
1387 if (buffer_size > 0)
1388 buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1389 }
1390
1391 return 0;
1392}
1393static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1394{
1395
1396 /*char *outp;*/
1397 /*struct cx231xx_buffer *buf;*/
1398 struct cx231xx_dmaqueue *dma_q = urb->context;
1399 unsigned char *p_buffer, *buffer;
1400 u32 buffer_size = 0;
1401
1402 p_buffer = urb->transfer_buffer;
1403 buffer_size = urb->actual_length;
1404
1405 buffer = kmalloc(buffer_size, GFP_ATOMIC);
1406
1407 memcpy(buffer, dma_q->ps_head, 3);
1408 memcpy(buffer+3, p_buffer, buffer_size-3);
1409 memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1410
1411 p_buffer = buffer;
1412 buffer_filled(p_buffer, buffer_size, urb, dma_q);
1413
1414 kfree(buffer);
1415 return 0;
1416}
1417
1418static int bb_buf_prepare(struct videobuf_queue *q,
1419 struct videobuf_buffer *vb, enum v4l2_field field)
1420{
1421 struct cx231xx_fh *fh = q->priv_data;
1422 struct cx231xx_buffer *buf =
1423 container_of(vb, struct cx231xx_buffer, vb);
1424 struct cx231xx *dev = fh->dev;
1425 int rc = 0, urb_init = 0;
1426 int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1427
1428 dma_qq = &dev->video_mode.vidq;
1429
1430 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1431 return -EINVAL;
1432 buf->vb.width = fh->dev->ts1.ts_packet_size;
1433 buf->vb.height = fh->dev->ts1.ts_packet_count;
1434 buf->vb.size = size;
1435 buf->vb.field = field;
1436
1437 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1438 rc = videobuf_iolock(q, &buf->vb, NULL);
1439 if (rc < 0)
1440 goto fail;
1441 }
1442
1443 if (dev->USE_ISO) {
1444 if (!dev->video_mode.isoc_ctl.num_bufs)
1445 urb_init = 1;
1446 } else {
1447 if (!dev->video_mode.bulk_ctl.num_bufs)
1448 urb_init = 1;
1449 }
1450 /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1451 urb_init, dev->video_mode.max_pkt_size);*/
1452 dev->mode_tv = 1;
1453
1454 if (urb_init) {
1455 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1456 rc = cx231xx_unmute_audio(dev);
1457 if (dev->USE_ISO) {
1458 cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1459 rc = cx231xx_init_isoc(dev, mpeglines,
1460 mpegbufs,
1461 dev->ts1_mode.max_pkt_size,
1462 cx231xx_isoc_copy);
1463 } else {
1464 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1465 rc = cx231xx_init_bulk(dev, mpeglines,
1466 mpegbufs,
1467 dev->ts1_mode.max_pkt_size,
1468 cx231xx_bulk_copy);
1469 }
1470 if (rc < 0)
1471 goto fail;
1472 }
1473
1474 buf->vb.state = VIDEOBUF_PREPARED;
1475 return 0;
1476
1477fail:
1478 free_buffer(q, buf);
1479 return rc;
1480}
1481
1482static void bb_buf_queue(struct videobuf_queue *q,
1483 struct videobuf_buffer *vb)
1484{
1485 struct cx231xx_fh *fh = q->priv_data;
1486
1487 struct cx231xx_buffer *buf =
1488 container_of(vb, struct cx231xx_buffer, vb);
1489 struct cx231xx *dev = fh->dev;
1490 struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1491
1492 buf->vb.state = VIDEOBUF_QUEUED;
1493 list_add_tail(&buf->vb.queue, &vidq->active);
1494
1495}
1496
1497static void bb_buf_release(struct videobuf_queue *q,
1498 struct videobuf_buffer *vb)
1499{
1500 struct cx231xx_buffer *buf =
1501 container_of(vb, struct cx231xx_buffer, vb);
1502 /*struct cx231xx_fh *fh = q->priv_data;*/
1503 /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1504
1505 free_buffer(q, buf);
1506}
1507
1508static struct videobuf_queue_ops cx231xx_qops = {
1509 .buf_setup = bb_buf_setup,
1510 .buf_prepare = bb_buf_prepare,
1511 .buf_queue = bb_buf_queue,
1512 .buf_release = bb_buf_release,
1513};
1514
1515/* ------------------------------------------------------------------ */
1516
1517static const u32 *ctrl_classes[] = {
1518 cx2341x_mpeg_ctrls,
1519 NULL
1520};
1521
1522static int cx231xx_queryctrl(struct cx231xx *dev,
1523 struct v4l2_queryctrl *qctrl)
1524{
1525 qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1526 if (qctrl->id == 0)
1527 return -EINVAL;
1528
1529 /* MPEG V4L2 controls */
1530 if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1531 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1532
1533 return 0;
1534}
1535
1536static int cx231xx_querymenu(struct cx231xx *dev,
1537 struct v4l2_querymenu *qmenu)
1538{
1539 struct v4l2_queryctrl qctrl;
1540
1541 qctrl.id = qmenu->id;
1542 cx231xx_queryctrl(dev, &qctrl);
1543 return v4l2_ctrl_query_menu(qmenu, &qctrl,
1544 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1545}
1546
1547static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1548{
1549 struct cx231xx_fh *fh = file->private_data;
1550 struct cx231xx *dev = fh->dev;
1551
1552 *norm = dev->encodernorm.id;
1553 return 0;
1554}
1555static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1556{
1557 struct cx231xx_fh *fh = file->private_data;
1558 struct cx231xx *dev = fh->dev;
1559 unsigned int i;
1560
1561 for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1562 if (*id & cx231xx_tvnorms[i].id)
1563 break;
1564 if (i == ARRAY_SIZE(cx231xx_tvnorms))
1565 return -EINVAL;
1566 dev->encodernorm = cx231xx_tvnorms[i];
1567
1568 if (dev->encodernorm.id & 0xb000) {
1569 dprintk(3, "encodernorm set to NTSC\n");
1570 dev->norm = V4L2_STD_NTSC;
1571 dev->ts1.height = 480;
1572 dev->mpeg_params.is_50hz = 0;
1573 } else {
1574 dprintk(3, "encodernorm set to PAL\n");
1575 dev->norm = V4L2_STD_PAL_B;
1576 dev->ts1.height = 576;
1577 dev->mpeg_params.is_50hz = 1;
1578 }
1579 call_all(dev, core, s_std, dev->norm);
1580 /* do mode control overrides */
1581 cx231xx_do_mode_ctrl_overrides(dev);
1582
1583 dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1584 return 0;
1585}
1586static int vidioc_g_audio(struct file *file, void *fh,
1587 struct v4l2_audio *a)
1588{
1589 struct v4l2_audio *vin = a;
1590
1591 int ret = -EINVAL;
1592 if (vin->index > 0)
1593 return ret;
1594 strncpy(vin->name, "VideoGrabber Audio", 14);
1595 vin->capability = V4L2_AUDCAP_STEREO;
1596return 0;
1597}
1598static int vidioc_enumaudio(struct file *file, void *fh,
1599 struct v4l2_audio *a)
1600{
1601 struct v4l2_audio *vin = a;
1602
1603 int ret = -EINVAL;
1604
1605 if (vin->index > 0)
1606 return ret;
1607 strncpy(vin->name, "VideoGrabber Audio", 14);
1608 vin->capability = V4L2_AUDCAP_STEREO;
1609
1610
1611return 0;
1612}
1613static const char *iname[] = {
1614 [CX231XX_VMUX_COMPOSITE1] = "Composite1",
1615 [CX231XX_VMUX_SVIDEO] = "S-Video",
1616 [CX231XX_VMUX_TELEVISION] = "Television",
1617 [CX231XX_VMUX_CABLE] = "Cable TV",
1618 [CX231XX_VMUX_DVB] = "DVB",
1619 [CX231XX_VMUX_DEBUG] = "for debug only",
1620};
1621static int vidioc_enum_input(struct file *file, void *priv,
1622 struct v4l2_input *i)
1623{
1624 struct cx231xx_fh *fh = file->private_data;
1625 struct cx231xx *dev = fh->dev;
1626 struct cx231xx_input *input;
1627 int n;
1628 dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i->index);
1629
1630 if (i->index >= 4)
1631 return -EINVAL;
1632
1633
1634 input = &cx231xx_boards[dev->model].input[i->index];
1635
1636 if (input->type == 0)
1637 return -EINVAL;
1638
1639 /* FIXME
1640 * strcpy(i->name, input->name); */
1641
1642 n = i->index;
1643 strcpy(i->name, iname[INPUT(n)->type]);
1644
1645 if (input->type == CX231XX_VMUX_TELEVISION ||
1646 input->type == CX231XX_VMUX_CABLE)
1647 i->type = V4L2_INPUT_TYPE_TUNER;
1648 else
1649 i->type = V4L2_INPUT_TYPE_CAMERA;
1650
1651
1652 return 0;
1653}
1654
1655static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1656{
1657 *i = 0;
1658 return 0;
1659}
1660
1661static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1662{
1663 struct cx231xx_fh *fh = file->private_data;
1664 struct cx231xx *dev = fh->dev;
1665
1666 dprintk(3, "enter vidioc_s_input() i=%d\n", i);
1667
1668 mutex_lock(&dev->lock);
1669
1670 video_mux(dev, i);
1671
1672 mutex_unlock(&dev->lock);
1673
1674 if (i >= 4)
1675 return -EINVAL;
1676 dev->input = i;
1677 dprintk(3, "exit vidioc_s_input()\n");
1678 return 0;
1679}
1680
1681static int vidioc_g_tuner(struct file *file, void *priv,
1682 struct v4l2_tuner *t)
1683{
1684 return 0;
1685}
1686
1687static int vidioc_s_tuner(struct file *file, void *priv,
1688 struct v4l2_tuner *t)
1689{
1690 return 0;
1691}
1692
1693static int vidioc_g_frequency(struct file *file, void *priv,
1694 struct v4l2_frequency *f)
1695{
1696 return 0;
1697}
1698
1699static int vidioc_s_frequency(struct file *file, void *priv,
1700 struct v4l2_frequency *f)
1701{
1702
1703
1704 return 0;
1705}
1706
1707static int vidioc_s_ctrl(struct file *file, void *priv,
1708 struct v4l2_control *ctl)
1709{
1710 struct cx231xx_fh *fh = file->private_data;
1711 struct cx231xx *dev = fh->dev;
1712 dprintk(3, "enter vidioc_s_ctrl()\n");
1713 /* Update the A/V core */
1714 call_all(dev, core, s_ctrl, ctl);
1715 dprintk(3, "exit vidioc_s_ctrl()\n");
1716 return 0;
1717}
1718static struct v4l2_capability pvr_capability = {
1719 .driver = "cx231xx",
1720 .card = "VideoGrabber",
1721 .bus_info = "usb",
1722 .version = 1,
1723 .capabilities = (V4L2_CAP_VIDEO_CAPTURE |
1724 V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_RADIO |
1725 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE),
1726 .reserved = {0, 0, 0, 0}
1727};
1728static int vidioc_querycap(struct file *file, void *priv,
1729 struct v4l2_capability *cap)
1730{
1731
1732
1733
1734 memcpy(cap, &pvr_capability, sizeof(struct v4l2_capability));
1735 return 0;
1736}
1737
1738static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1739 struct v4l2_fmtdesc *f)
1740{
1741
1742 if (f->index != 0)
1743 return -EINVAL;
1744
1745 strlcpy(f->description, "MPEG", sizeof(f->description));
1746 f->pixelformat = V4L2_PIX_FMT_MPEG;
1747
1748 return 0;
1749}
1750
1751static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1752 struct v4l2_format *f)
1753{
1754 struct cx231xx_fh *fh = file->private_data;
1755 struct cx231xx *dev = fh->dev;
1756 dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1757 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1758 f->fmt.pix.bytesperline = 0;
1759 f->fmt.pix.sizeimage =
1760 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1761 f->fmt.pix.colorspace = 0;
1762 f->fmt.pix.width = dev->ts1.width;
1763 f->fmt.pix.height = dev->ts1.height;
1764 f->fmt.pix.field = fh->vidq.field;
1765 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1766 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1767 dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1768 return 0;
1769}
1770
1771static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1772 struct v4l2_format *f)
1773{
1774 struct cx231xx_fh *fh = file->private_data;
1775 struct cx231xx *dev = fh->dev;
1776 dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1777 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1778 f->fmt.pix.bytesperline = 0;
1779 f->fmt.pix.sizeimage =
1780 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1781 f->fmt.pix.colorspace = 0;
1782 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1783 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1784 dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1785 return 0;
1786}
1787
1788static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1789 struct v4l2_format *f)
1790{
1791
1792 return 0;
1793}
1794
1795static int vidioc_reqbufs(struct file *file, void *priv,
1796 struct v4l2_requestbuffers *p)
1797{
1798 struct cx231xx_fh *fh = file->private_data;
1799
1800 return videobuf_reqbufs(&fh->vidq, p);
1801}
1802
1803static int vidioc_querybuf(struct file *file, void *priv,
1804 struct v4l2_buffer *p)
1805{
1806 struct cx231xx_fh *fh = file->private_data;
1807
1808 return videobuf_querybuf(&fh->vidq, p);
1809}
1810
1811static int vidioc_qbuf(struct file *file, void *priv,
1812 struct v4l2_buffer *p)
1813{
1814 struct cx231xx_fh *fh = file->private_data;
1815
1816 return videobuf_qbuf(&fh->vidq, p);
1817}
1818
1819static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1820{
1821 struct cx231xx_fh *fh = priv;
1822
1823 return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1824}
1825
1826
1827static int vidioc_streamon(struct file *file, void *priv,
1828 enum v4l2_buf_type i)
1829{
1830 struct cx231xx_fh *fh = file->private_data;
1831
1832 struct cx231xx *dev = fh->dev;
1833 int rc = 0;
1834 dprintk(3, "enter vidioc_streamon()\n");
1835 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1836 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1837 if (dev->USE_ISO)
1838 rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1839 CX231XX_NUM_BUFS,
1840 dev->video_mode.max_pkt_size,
1841 cx231xx_isoc_copy);
1842 else {
1843 rc = cx231xx_init_bulk(dev, 320,
1844 5,
1845 dev->ts1_mode.max_pkt_size,
1846 cx231xx_bulk_copy);
1847 }
1848 dprintk(3, "exit vidioc_streamon()\n");
1849 return videobuf_streamon(&fh->vidq);
1850}
1851
1852static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1853{
1854 struct cx231xx_fh *fh = file->private_data;
1855
1856 return videobuf_streamoff(&fh->vidq);
1857}
1858
1859static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1860 struct v4l2_ext_controls *f)
1861{
1862 struct cx231xx_fh *fh = priv;
1863 struct cx231xx *dev = fh->dev;
1864 dprintk(3, "enter vidioc_g_ext_ctrls()\n");
1865 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1866 return -EINVAL;
1867 dprintk(3, "exit vidioc_g_ext_ctrls()\n");
1868 return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1869}
1870
1871static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1872 struct v4l2_ext_controls *f)
1873{
1874 struct cx231xx_fh *fh = priv;
1875 struct cx231xx *dev = fh->dev;
1876 struct cx2341x_mpeg_params p;
1877 int err;
1878 dprintk(3, "enter vidioc_s_ext_ctrls()\n");
1879 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1880 return -EINVAL;
1881
1882 p = dev->mpeg_params;
1883 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1884 if (err == 0) {
1885 err = cx2341x_update(dev, cx231xx_mbox_func,
1886 &dev->mpeg_params, &p);
1887 dev->mpeg_params = p;
1888 }
1889
1890 return err;
1891
1892
1893return 0;
1894}
1895
1896static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1897 struct v4l2_ext_controls *f)
1898{
1899 struct cx231xx_fh *fh = priv;
1900 struct cx231xx *dev = fh->dev;
1901 struct cx2341x_mpeg_params p;
1902 int err;
1903 dprintk(3, "enter vidioc_try_ext_ctrls()\n");
1904 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1905 return -EINVAL;
1906
1907 p = dev->mpeg_params;
1908 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1909 dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err);
1910 return err;
1911}
1912
1913static int vidioc_log_status(struct file *file, void *priv)
1914{
1915 struct cx231xx_fh *fh = priv;
1916 struct cx231xx *dev = fh->dev;
1917 char name[32 + 2];
1918
1919 snprintf(name, sizeof(name), "%s/2", dev->name);
1920 dprintk(3,
1921 "%s/2: ============ START LOG STATUS ============\n",
1922 dev->name);
1923 call_all(dev, core, log_status);
1924 cx2341x_log_status(&dev->mpeg_params, name);
1925 dprintk(3,
1926 "%s/2: ============= END LOG STATUS =============\n",
1927 dev->name);
1928 return 0;
1929}
1930
1931static int vidioc_querymenu(struct file *file, void *priv,
1932 struct v4l2_querymenu *a)
1933{
1934 struct cx231xx_fh *fh = priv;
1935 struct cx231xx *dev = fh->dev;
1936 dprintk(3, "enter vidioc_querymenu()\n");
1937 dprintk(3, "exit vidioc_querymenu()\n");
1938 return cx231xx_querymenu(dev, a);
1939}
1940
1941static int vidioc_queryctrl(struct file *file, void *priv,
1942 struct v4l2_queryctrl *c)
1943{
1944 struct cx231xx_fh *fh = priv;
1945 struct cx231xx *dev = fh->dev;
1946 dprintk(3, "enter vidioc_queryctrl()\n");
1947 dprintk(3, "exit vidioc_queryctrl()\n");
1948 return cx231xx_queryctrl(dev, c);
1949}
1950
1951static int mpeg_open(struct file *file)
1952{
1953 int minor = video_devdata(file)->minor;
1954 struct cx231xx *h, *dev = NULL;
1955 /*struct list_head *list;*/
1956 struct cx231xx_fh *fh;
1957 /*u32 value = 0;*/
1958
1959 dprintk(2, "%s()\n", __func__);
1960
1961 list_for_each_entry(h, &cx231xx_devlist, devlist) {
1962 if (h->v4l_device->minor == minor)
1963 dev = h;
1964 }
1965
1966 if (dev == NULL) {
1967 unlock_kernel();
1968 return -ENODEV;
1969 }
1970 mutex_lock(&dev->lock);
1971
1972 /* allocate + initialize per filehandle data */
1973 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1974 if (NULL == fh) {
1975 mutex_unlock(&dev->lock);
1976 return -ENOMEM;
1977 }
1978
1979 file->private_data = fh;
1980 fh->dev = dev;
1981
1982
1983 videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1984 NULL, &dev->video_mode.slock,
1985 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1986 sizeof(struct cx231xx_buffer), fh, NULL);
1987/*
1988 videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1989 &dev->udev->dev, &dev->ts1.slock,
1990 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1991 V4L2_FIELD_INTERLACED,
1992 sizeof(struct cx231xx_buffer),
1993 fh, NULL);
1994*/
1995
1996
1997 cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1998 cx231xx_set_gpio_value(dev, 2, 0);
1999
2000 cx231xx_initialize_codec(dev);
2001
2002 mutex_unlock(&dev->lock);
2003 cx231xx_start_TS1(dev);
2004
2005 return 0;
2006}
2007
2008static int mpeg_release(struct file *file)
2009{
2010 struct cx231xx_fh *fh = file->private_data;
2011 struct cx231xx *dev = fh->dev;
2012
2013 dprintk(3, "mpeg_release()! dev=0x%x\n", dev);
2014
2015 if (!dev) {
2016 dprintk(3, "abort!!!\n");
2017 return 0;
2018 }
2019
2020 mutex_lock(&dev->lock);
2021
2022 cx231xx_stop_TS1(dev);
2023
2024 /* do this before setting alternate! */
2025 if (dev->USE_ISO)
2026 cx231xx_uninit_isoc(dev);
2027 else
2028 cx231xx_uninit_bulk(dev);
2029 cx231xx_set_mode(dev, CX231XX_SUSPEND);
2030
2031 cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
2032 CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
2033 CX231xx_RAW_BITS_NONE);
2034
2035 /* FIXME: Review this crap */
2036 /* Shut device down on last close */
2037 if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
2038 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
2039 /* stop mpeg capture */
2040
2041 msleep(500);
2042 cx231xx_417_check_encoder(dev);
2043
2044 }
2045 }
2046
2047 if (fh->vidq.streaming)
2048 videobuf_streamoff(&fh->vidq);
2049 if (fh->vidq.reading)
2050 videobuf_read_stop(&fh->vidq);
2051
2052 videobuf_mmap_free(&fh->vidq);
2053 file->private_data = NULL;
2054 kfree(fh);
2055 mutex_unlock(&dev->lock);
2056 return 0;
2057}
2058
2059static ssize_t mpeg_read(struct file *file, char __user *data,
2060 size_t count, loff_t *ppos)
2061{
2062 struct cx231xx_fh *fh = file->private_data;
2063 struct cx231xx *dev = fh->dev;
2064
2065
2066 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
2067 /* Start mpeg encoder on first read. */
2068 if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
2069 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
2070 if (cx231xx_initialize_codec(dev) < 0)
2071 return -EINVAL;
2072 }
2073 }
2074
2075 return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
2076 file->f_flags & O_NONBLOCK);
2077}
2078
2079static unsigned int mpeg_poll(struct file *file,
2080 struct poll_table_struct *wait)
2081{
2082 struct cx231xx_fh *fh = file->private_data;
2083 /*struct cx231xx *dev = fh->dev;*/
2084
2085 /*dprintk(2, "%s\n", __func__);*/
2086
2087 return videobuf_poll_stream(file, &fh->vidq, wait);
2088}
2089
2090static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
2091{
2092 struct cx231xx_fh *fh = file->private_data;
2093 struct cx231xx *dev = fh->dev;
2094
2095 dprintk(2, "%s()\n", __func__);
2096
2097 return videobuf_mmap_mapper(&fh->vidq, vma);
2098}
2099
2100static struct v4l2_file_operations mpeg_fops = {
2101 .owner = THIS_MODULE,
2102 .open = mpeg_open,
2103 .release = mpeg_release,
2104 .read = mpeg_read,
2105 .poll = mpeg_poll,
2106 .mmap = mpeg_mmap,
2107 .ioctl = video_ioctl2,
2108};
2109
2110static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
2111 .vidioc_s_std = vidioc_s_std,
2112 .vidioc_g_std = vidioc_g_std,
2113 .vidioc_enum_input = vidioc_enum_input,
2114 .vidioc_enumaudio = vidioc_enumaudio,
2115 .vidioc_g_audio = vidioc_g_audio,
2116 .vidioc_g_input = vidioc_g_input,
2117 .vidioc_s_input = vidioc_s_input,
2118 .vidioc_g_tuner = vidioc_g_tuner,
2119 .vidioc_s_tuner = vidioc_s_tuner,
2120 .vidioc_g_frequency = vidioc_g_frequency,
2121 .vidioc_s_frequency = vidioc_s_frequency,
2122 .vidioc_s_ctrl = vidioc_s_ctrl,
2123 .vidioc_querycap = vidioc_querycap,
2124 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
2125 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
2126 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
2127 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
2128 .vidioc_reqbufs = vidioc_reqbufs,
2129 .vidioc_querybuf = vidioc_querybuf,
2130 .vidioc_qbuf = vidioc_qbuf,
2131 .vidioc_dqbuf = vidioc_dqbuf,
2132 .vidioc_streamon = vidioc_streamon,
2133 .vidioc_streamoff = vidioc_streamoff,
2134 .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
2135 .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
2136 .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
2137 .vidioc_log_status = vidioc_log_status,
2138 .vidioc_querymenu = vidioc_querymenu,
2139 .vidioc_queryctrl = vidioc_queryctrl,
2140/* .vidioc_g_chip_ident = cx231xx_g_chip_ident,*/
2141#ifdef CONFIG_VIDEO_ADV_DEBUG
2142/* .vidioc_g_register = cx231xx_g_register,*/
2143/* .vidioc_s_register = cx231xx_s_register,*/
2144#endif
2145};
2146
2147static struct video_device cx231xx_mpeg_template = {
2148 .name = "cx231xx",
2149 .fops = &mpeg_fops,
2150 .ioctl_ops = &mpeg_ioctl_ops,
2151 .minor = -1,
2152 .tvnorms = CX231xx_NORMS,
2153 .current_norm = V4L2_STD_NTSC_M,
2154};
2155
2156void cx231xx_417_unregister(struct cx231xx *dev)
2157{
2158 dprintk(1, "%s()\n", __func__);
2159 dprintk(3, "%s()\n", __func__);
2160
2161 if (dev->v4l_device) {
2162 if (-1 != dev->v4l_device->minor)
2163 video_unregister_device(dev->v4l_device);
2164 else
2165 video_device_release(dev->v4l_device);
2166 dev->v4l_device = NULL;
2167 }
2168}
2169
2170static struct video_device *cx231xx_video_dev_alloc(
2171 struct cx231xx *dev,
2172 struct usb_device *usbdev,
2173 struct video_device *template,
2174 char *type)
2175{
2176 struct video_device *vfd;
2177
2178 dprintk(1, "%s()\n", __func__);
2179 vfd = video_device_alloc();
2180 if (NULL == vfd)
2181 return NULL;
2182 *vfd = *template;
2183 vfd->minor = -1;
2184 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
2185 type, cx231xx_boards[dev->model].name);
2186
2187 vfd->v4l2_dev = &dev->v4l2_dev;
2188 vfd->release = video_device_release;
2189
2190 return vfd;
2191
2192}
2193
2194int cx231xx_417_register(struct cx231xx *dev)
2195{
2196 /* FIXME: Port1 hardcoded here */
2197 int err = -ENODEV;
2198 struct cx231xx_tsport *tsport = &dev->ts1;
2199
2200 dprintk(1, "%s()\n", __func__);
2201
2202 /* Set default TV standard */
2203 dev->encodernorm = cx231xx_tvnorms[0];
2204
2205 if (dev->encodernorm.id & V4L2_STD_525_60)
2206 tsport->height = 480;
2207 else
2208 tsport->height = 576;
2209
2210 tsport->width = 720;
2211 cx2341x_fill_defaults(&dev->mpeg_params);
2212 dev->norm = V4L2_STD_NTSC;
2213
2214 dev->mpeg_params.port = CX2341X_PORT_SERIAL;
2215
2216 /* Allocate and initialize V4L video device */
2217 dev->v4l_device = cx231xx_video_dev_alloc(dev,
2218 dev->udev, &cx231xx_mpeg_template, "mpeg");
2219 err = video_register_device(dev->v4l_device,
2220 VFL_TYPE_GRABBER, -1);
2221 if (err < 0) {
2222 dprintk(3, "%s: can't register mpeg device\n", dev->name);
2223 return err;
2224 }
2225
2226 dprintk(3, "%s: registered device video%d [mpeg]\n",
2227 dev->name, dev->v4l_device->num);
2228
2229 return 0;
2230}
diff --git a/drivers/media/video/cx231xx/cx231xx-audio.c b/drivers/media/video/cx231xx/cx231xx-audio.c
index 7cae95a2245e..6ac418cc6895 100644
--- a/drivers/media/video/cx231xx/cx231xx-audio.c
+++ b/drivers/media/video/cx231xx/cx231xx-audio.c
@@ -75,6 +75,30 @@ static int cx231xx_isoc_audio_deinit(struct cx231xx *dev)
75 return 0; 75 return 0;
76} 76}
77 77
78static int cx231xx_bulk_audio_deinit(struct cx231xx *dev)
79{
80 int i;
81
82 dprintk("Stopping bulk\n");
83
84 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
85 if (dev->adev.urb[i]) {
86 if (!irqs_disabled())
87 usb_kill_urb(dev->adev.urb[i]);
88 else
89 usb_unlink_urb(dev->adev.urb[i]);
90
91 usb_free_urb(dev->adev.urb[i]);
92 dev->adev.urb[i] = NULL;
93
94 kfree(dev->adev.transfer_buffer[i]);
95 dev->adev.transfer_buffer[i] = NULL;
96 }
97 }
98
99 return 0;
100}
101
78static void cx231xx_audio_isocirq(struct urb *urb) 102static void cx231xx_audio_isocirq(struct urb *urb)
79{ 103{
80 struct cx231xx *dev = urb->context; 104 struct cx231xx *dev = urb->context;
@@ -158,14 +182,92 @@ static void cx231xx_audio_isocirq(struct urb *urb)
158 return; 182 return;
159} 183}
160 184
185static void cx231xx_audio_bulkirq(struct urb *urb)
186{
187 struct cx231xx *dev = urb->context;
188 unsigned int oldptr;
189 int period_elapsed = 0;
190 int status;
191 unsigned char *cp;
192 unsigned int stride;
193 struct snd_pcm_substream *substream;
194 struct snd_pcm_runtime *runtime;
195
196 switch (urb->status) {
197 case 0: /* success */
198 case -ETIMEDOUT: /* NAK */
199 break;
200 case -ECONNRESET: /* kill */
201 case -ENOENT:
202 case -ESHUTDOWN:
203 return;
204 default: /* error */
205 dprintk("urb completition error %d.\n", urb->status);
206 break;
207 }
208
209 if (dev->adev.capture_pcm_substream) {
210 substream = dev->adev.capture_pcm_substream;
211 runtime = substream->runtime;
212 stride = runtime->frame_bits >> 3;
213
214 if (1) {
215 int length = urb->actual_length /
216 stride;
217 cp = (unsigned char *)urb->transfer_buffer;
218
219 oldptr = dev->adev.hwptr_done_capture;
220 if (oldptr + length >= runtime->buffer_size) {
221 unsigned int cnt;
222
223 cnt = runtime->buffer_size - oldptr;
224 memcpy(runtime->dma_area + oldptr * stride, cp,
225 cnt * stride);
226 memcpy(runtime->dma_area, cp + cnt * stride,
227 length * stride - cnt * stride);
228 } else {
229 memcpy(runtime->dma_area + oldptr * stride, cp,
230 length * stride);
231 }
232
233 snd_pcm_stream_lock(substream);
234
235 dev->adev.hwptr_done_capture += length;
236 if (dev->adev.hwptr_done_capture >=
237 runtime->buffer_size)
238 dev->adev.hwptr_done_capture -=
239 runtime->buffer_size;
240
241 dev->adev.capture_transfer_done += length;
242 if (dev->adev.capture_transfer_done >=
243 runtime->period_size) {
244 dev->adev.capture_transfer_done -=
245 runtime->period_size;
246 period_elapsed = 1;
247 }
248 snd_pcm_stream_unlock(substream);
249 }
250 if (period_elapsed)
251 snd_pcm_period_elapsed(substream);
252 }
253 urb->status = 0;
254
255 status = usb_submit_urb(urb, GFP_ATOMIC);
256 if (status < 0) {
257 cx231xx_errdev("resubmit of audio urb failed (error=%i)\n",
258 status);
259 }
260 return;
261}
262
161static int cx231xx_init_audio_isoc(struct cx231xx *dev) 263static int cx231xx_init_audio_isoc(struct cx231xx *dev)
162{ 264{
163 int i, errCode; 265 int i, errCode;
164 int sb_size; 266 int sb_size;
165 267
166 cx231xx_info("%s: Starting AUDIO transfers\n", __func__); 268 cx231xx_info("%s: Starting ISO AUDIO transfers\n", __func__);
167 269
168 sb_size = CX231XX_NUM_AUDIO_PACKETS * dev->adev.max_pkt_size; 270 sb_size = CX231XX_ISO_NUM_AUDIO_PACKETS * dev->adev.max_pkt_size;
169 271
170 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) { 272 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
171 struct urb *urb; 273 struct urb *urb;
@@ -176,7 +278,7 @@ static int cx231xx_init_audio_isoc(struct cx231xx *dev)
176 return -ENOMEM; 278 return -ENOMEM;
177 279
178 memset(dev->adev.transfer_buffer[i], 0x80, sb_size); 280 memset(dev->adev.transfer_buffer[i], 0x80, sb_size);
179 urb = usb_alloc_urb(CX231XX_NUM_AUDIO_PACKETS, GFP_ATOMIC); 281 urb = usb_alloc_urb(CX231XX_ISO_NUM_AUDIO_PACKETS, GFP_ATOMIC);
180 if (!urb) { 282 if (!urb) {
181 cx231xx_errdev("usb_alloc_urb failed!\n"); 283 cx231xx_errdev("usb_alloc_urb failed!\n");
182 for (j = 0; j < i; j++) { 284 for (j = 0; j < i; j++) {
@@ -194,10 +296,10 @@ static int cx231xx_init_audio_isoc(struct cx231xx *dev)
194 urb->transfer_buffer = dev->adev.transfer_buffer[i]; 296 urb->transfer_buffer = dev->adev.transfer_buffer[i];
195 urb->interval = 1; 297 urb->interval = 1;
196 urb->complete = cx231xx_audio_isocirq; 298 urb->complete = cx231xx_audio_isocirq;
197 urb->number_of_packets = CX231XX_NUM_AUDIO_PACKETS; 299 urb->number_of_packets = CX231XX_ISO_NUM_AUDIO_PACKETS;
198 urb->transfer_buffer_length = sb_size; 300 urb->transfer_buffer_length = sb_size;
199 301
200 for (j = k = 0; j < CX231XX_NUM_AUDIO_PACKETS; 302 for (j = k = 0; j < CX231XX_ISO_NUM_AUDIO_PACKETS;
201 j++, k += dev->adev.max_pkt_size) { 303 j++, k += dev->adev.max_pkt_size) {
202 urb->iso_frame_desc[j].offset = k; 304 urb->iso_frame_desc[j].offset = k;
203 urb->iso_frame_desc[j].length = dev->adev.max_pkt_size; 305 urb->iso_frame_desc[j].length = dev->adev.max_pkt_size;
@@ -216,6 +318,59 @@ static int cx231xx_init_audio_isoc(struct cx231xx *dev)
216 return errCode; 318 return errCode;
217} 319}
218 320
321static int cx231xx_init_audio_bulk(struct cx231xx *dev)
322{
323 int i, errCode;
324 int sb_size;
325
326 cx231xx_info("%s: Starting BULK AUDIO transfers\n", __func__);
327
328 sb_size = CX231XX_NUM_AUDIO_PACKETS * dev->adev.max_pkt_size;
329
330 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
331 struct urb *urb;
332 int j;
333
334 dev->adev.transfer_buffer[i] = kmalloc(sb_size, GFP_ATOMIC);
335 if (!dev->adev.transfer_buffer[i])
336 return -ENOMEM;
337
338 memset(dev->adev.transfer_buffer[i], 0x80, sb_size);
339 urb = usb_alloc_urb(CX231XX_NUM_AUDIO_PACKETS, GFP_ATOMIC);
340 if (!urb) {
341 cx231xx_errdev("usb_alloc_urb failed!\n");
342 for (j = 0; j < i; j++) {
343 usb_free_urb(dev->adev.urb[j]);
344 kfree(dev->adev.transfer_buffer[j]);
345 }
346 return -ENOMEM;
347 }
348
349 urb->dev = dev->udev;
350 urb->context = dev;
351 urb->pipe = usb_rcvbulkpipe(dev->udev,
352 dev->adev.end_point_addr);
353 urb->transfer_flags = 0;
354 urb->transfer_buffer = dev->adev.transfer_buffer[i];
355 urb->complete = cx231xx_audio_bulkirq;
356 urb->transfer_buffer_length = sb_size;
357
358 dev->adev.urb[i] = urb;
359
360 }
361
362 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
363 errCode = usb_submit_urb(dev->adev.urb[i], GFP_ATOMIC);
364 if (errCode < 0) {
365 cx231xx_bulk_audio_deinit(dev);
366 return errCode;
367 }
368 }
369
370 return errCode;
371}
372
373
219static int cx231xx_cmd(struct cx231xx *dev, int cmd, int arg) 374static int cx231xx_cmd(struct cx231xx *dev, int cmd, int arg)
220{ 375{
221 dprintk("%s transfer\n", (dev->adev.capture_stream == STREAM_ON) ? 376 dprintk("%s transfer\n", (dev->adev.capture_stream == STREAM_ON) ?
@@ -225,7 +380,12 @@ static int cx231xx_cmd(struct cx231xx *dev, int cmd, int arg)
225 case CX231XX_CAPTURE_STREAM_EN: 380 case CX231XX_CAPTURE_STREAM_EN:
226 if (dev->adev.capture_stream == STREAM_OFF && arg == 1) { 381 if (dev->adev.capture_stream == STREAM_OFF && arg == 1) {
227 dev->adev.capture_stream = STREAM_ON; 382 dev->adev.capture_stream = STREAM_ON;
228 cx231xx_init_audio_isoc(dev); 383 if (is_fw_load(dev) == 0)
384 cx25840_call(dev, core, load_fw);
385 if (dev->USE_ISO)
386 cx231xx_init_audio_isoc(dev);
387 else
388 cx231xx_init_audio_bulk(dev);
229 } else if (dev->adev.capture_stream == STREAM_ON && arg == 0) { 389 } else if (dev->adev.capture_stream == STREAM_ON && arg == 0) {
230 dev->adev.capture_stream = STREAM_OFF; 390 dev->adev.capture_stream = STREAM_OFF;
231 cx231xx_isoc_audio_deinit(dev); 391 cx231xx_isoc_audio_deinit(dev);
@@ -300,7 +460,10 @@ static int snd_cx231xx_capture_open(struct snd_pcm_substream *substream)
300 460
301 /* set alternate setting for audio interface */ 461 /* set alternate setting for audio interface */
302 /* 1 - 48000 samples per sec */ 462 /* 1 - 48000 samples per sec */
303 ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 1); 463 if (dev->USE_ISO)
464 ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 1);
465 else
466 ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 0);
304 if (ret < 0) { 467 if (ret < 0) {
305 cx231xx_errdev("failed to set alternate setting !\n"); 468 cx231xx_errdev("failed to set alternate setting !\n");
306 469
@@ -330,6 +493,9 @@ static int snd_cx231xx_pcm_close(struct snd_pcm_substream *substream)
330 493
331 dprintk("closing device\n"); 494 dprintk("closing device\n");
332 495
496 /* inform hardware to start streaming */
497 ret = cx231xx_capture_start(dev, 0, Audio);
498
333 /* set alternate setting for audio interface */ 499 /* set alternate setting for audio interface */
334 /* 1 - 48000 samples per sec */ 500 /* 1 - 48000 samples per sec */
335 ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 0); 501 ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 0);
@@ -339,9 +505,6 @@ static int snd_cx231xx_pcm_close(struct snd_pcm_substream *substream)
339 return ret; 505 return ret;
340 } 506 }
341 507
342 /* inform hardware to start streaming */
343 ret = cx231xx_capture_start(dev, 0, Audio);
344
345 dev->mute = 1; 508 dev->mute = 1;
346 mutex_lock(&dev->lock); 509 mutex_lock(&dev->lock);
347 dev->adev.users--; 510 dev->adev.users--;
@@ -391,6 +554,11 @@ static int snd_cx231xx_hw_capture_free(struct snd_pcm_substream *substream)
391 554
392static int snd_cx231xx_prepare(struct snd_pcm_substream *substream) 555static int snd_cx231xx_prepare(struct snd_pcm_substream *substream)
393{ 556{
557 struct cx231xx *dev = snd_pcm_substream_chip(substream);
558
559 dev->adev.hwptr_done_capture = 0;
560 dev->adev.capture_transfer_done = 0;
561
394 return 0; 562 return 0;
395} 563}
396 564
@@ -495,6 +663,7 @@ static int cx231xx_audio_init(struct cx231xx *dev)
495 pcm->info_flags = 0; 663 pcm->info_flags = 0;
496 pcm->private_data = dev; 664 pcm->private_data = dev;
497 strcpy(pcm->name, "Conexant cx231xx Capture"); 665 strcpy(pcm->name, "Conexant cx231xx Capture");
666 snd_card_set_dev(card, &dev->udev->dev);
498 strcpy(card->driver, "Cx231xx-Audio"); 667 strcpy(card->driver, "Cx231xx-Audio");
499 strcpy(card->shortname, "Cx231xx Audio"); 668 strcpy(card->shortname, "Cx231xx Audio");
500 strcpy(card->longname, "Conexant cx231xx Audio"); 669 strcpy(card->longname, "Conexant cx231xx Audio");
diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c
index c2174413ab29..3e467ce1b06f 100644
--- a/drivers/media/video/cx231xx/cx231xx-avcore.c
+++ b/drivers/media/video/cx231xx/cx231xx-avcore.c
@@ -31,13 +31,16 @@
31#include <linux/i2c.h> 31#include <linux/i2c.h>
32#include <linux/mm.h> 32#include <linux/mm.h>
33#include <linux/mutex.h> 33#include <linux/mutex.h>
34#include <media/tuner.h>
34 35
35#include <media/v4l2-common.h> 36#include <media/v4l2-common.h>
36#include <media/v4l2-ioctl.h> 37#include <media/v4l2-ioctl.h>
37#include <media/v4l2-chip-ident.h> 38#include <media/v4l2-chip-ident.h>
38 39
39#include "cx231xx.h" 40#include "cx231xx.h"
41#include "cx231xx-dif.h"
40 42
43#define TUNER_MODE_FM_RADIO 0
41/****************************************************************************** 44/******************************************************************************
42 -: BLOCK ARRANGEMENT :- 45 -: BLOCK ARRANGEMENT :-
43 I2S block ----------------------| 46 I2S block ----------------------|
@@ -50,6 +53,57 @@
50 [Video] 53 [Video]
51 54
52*******************************************************************************/ 55*******************************************************************************/
56/******************************************************************************
57 * VERVE REGISTER *
58 * *
59 ******************************************************************************/
60static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
61{
62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
63 saddr, 1, data, 1);
64}
65
66static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
67{
68 int status;
69 u32 temp = 0;
70
71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
72 saddr, 1, &temp, 1);
73 *data = (u8) temp;
74 return status;
75}
76void initGPIO(struct cx231xx *dev)
77{
78 u32 _gpio_direction = 0;
79 u32 value = 0;
80 u8 val = 0;
81
82 _gpio_direction = _gpio_direction & 0xFC0003FF;
83 _gpio_direction = _gpio_direction | 0x03FDFC00;
84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
85
86 verve_read_byte(dev, 0x07, &val);
87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
88 verve_write_byte(dev, 0x07, 0xF4);
89 verve_read_byte(dev, 0x07, &val);
90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
91
92 cx231xx_capture_start(dev, 1, 2);
93
94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
96
97}
98void uninitGPIO(struct cx231xx *dev)
99{
100 u8 value[4] = { 0, 0, 0, 0 };
101
102 cx231xx_capture_start(dev, 0, 2);
103 verve_write_byte(dev, 0x07, 0x14);
104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
105 0x68, value, 4);
106}
53 107
54/****************************************************************************** 108/******************************************************************************
55 * A F E - B L O C K C O N T R O L functions * 109 * A F E - B L O C K C O N T R O L functions *
@@ -258,7 +312,7 @@ int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
258 312
259 switch (mode) { 313 switch (mode) {
260 case AFE_MODE_LOW_IF: 314 case AFE_MODE_LOW_IF:
261 /* SetupAFEforLowIF(); */ 315 cx231xx_Setup_AFE_for_LowIF(dev);
262 break; 316 break;
263 case AFE_MODE_BASEBAND: 317 case AFE_MODE_BASEBAND:
264 status = cx231xx_afe_setup_AFE_for_baseband(dev); 318 status = cx231xx_afe_setup_AFE_for_baseband(dev);
@@ -291,8 +345,13 @@ int cx231xx_afe_update_power_control(struct cx231xx *dev,
291 int status = 0; 345 int status = 0;
292 346
293 switch (dev->model) { 347 switch (dev->model) {
348 case CX231XX_BOARD_CNXT_CARRAERA:
294 case CX231XX_BOARD_CNXT_RDE_250: 349 case CX231XX_BOARD_CNXT_RDE_250:
350 case CX231XX_BOARD_CNXT_SHELBY:
295 case CX231XX_BOARD_CNXT_RDU_250: 351 case CX231XX_BOARD_CNXT_RDU_250:
352 case CX231XX_BOARD_CNXT_RDE_253S:
353 case CX231XX_BOARD_CNXT_RDU_253S:
354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
296 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 355 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
297 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 356 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
298 FLD_PWRDN_ENABLE_PLL)) { 357 FLD_PWRDN_ENABLE_PLL)) {
@@ -483,6 +542,17 @@ static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
483 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 542 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
484 saddr, 2, data, 4); 543 saddr, 2, data, 4);
485} 544}
545int cx231xx_check_fw(struct cx231xx *dev)
546{
547 u8 temp = 0;
548 int status = 0;
549 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
550 if (status < 0)
551 return status;
552 else
553 return temp;
554
555}
486 556
487int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 557int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
488{ 558{
@@ -521,9 +591,15 @@ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
521 return status; 591 return status;
522 } 592 }
523 } 593 }
524 status = cx231xx_set_decoder_video_input(dev, 594 if (dev->tuner_type == TUNER_NXP_TDA18271)
595 status = cx231xx_set_decoder_video_input(dev,
596 CX231XX_VMUX_TELEVISION,
597 INPUT(input)->vmux);
598 else
599 status = cx231xx_set_decoder_video_input(dev,
525 CX231XX_VMUX_COMPOSITE1, 600 CX231XX_VMUX_COMPOSITE1,
526 INPUT(input)->vmux); 601 INPUT(input)->vmux);
602
527 break; 603 break;
528 default: 604 default:
529 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", 605 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
@@ -681,7 +757,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
681 case CX231XX_VMUX_CABLE: 757 case CX231XX_VMUX_CABLE:
682 default: 758 default:
683 switch (dev->model) { 759 switch (dev->model) {
760 case CX231XX_BOARD_CNXT_CARRAERA:
684 case CX231XX_BOARD_CNXT_RDE_250: 761 case CX231XX_BOARD_CNXT_RDE_250:
762 case CX231XX_BOARD_CNXT_SHELBY:
685 case CX231XX_BOARD_CNXT_RDU_250: 763 case CX231XX_BOARD_CNXT_RDU_250:
686 /* Disable the use of DIF */ 764 /* Disable the use of DIF */
687 765
@@ -816,9 +894,21 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
816 /* Set VGA_SEL (for audio control) (bit 7-8) */ 894 /* Set VGA_SEL (for audio control) (bit 7-8) */
817 status = vid_blk_read_word(dev, AFE_CTRL, &value); 895 status = vid_blk_read_word(dev, AFE_CTRL, &value);
818 896
897 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
898 value &= (~(FLD_FUNC_MODE));
899 value |= 0x800000;
900
819 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 901 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
820 902
821 status = vid_blk_write_word(dev, AFE_CTRL, value); 903 status = vid_blk_write_word(dev, AFE_CTRL, value);
904
905 if (dev->tuner_type == TUNER_NXP_TDA18271) {
906 status = vid_blk_read_word(dev, PIN_CTRL,
907 &value);
908 status = vid_blk_write_word(dev, PIN_CTRL,
909 (value & 0xFFFFFFEF));
910 }
911
822 break; 912 break;
823 913
824 } 914 }
@@ -840,6 +930,39 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
840 return status; 930 return status;
841} 931}
842 932
933void cx231xx_enable656(struct cx231xx *dev)
934{
935 u8 temp = 0;
936 int status;
937 /*enable TS1 data[0:7] as output to export 656*/
938
939 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
940
941 /*enable TS1 clock as output to export 656*/
942
943 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
944 temp = temp|0x04;
945
946 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
947
948}
949EXPORT_SYMBOL_GPL(cx231xx_enable656);
950
951void cx231xx_disable656(struct cx231xx *dev)
952{
953 u8 temp = 0;
954 int status;
955
956
957 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
958
959 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
960 temp = temp&0xFB;
961
962 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
963}
964EXPORT_SYMBOL_GPL(cx231xx_disable656);
965
843/* 966/*
844 * Handle any video-mode specific overrides that are different 967 * Handle any video-mode specific overrides that are different
845 * on a per video standards basis after touching the MODE_CTRL 968 * on a per video standards basis after touching the MODE_CTRL
@@ -873,7 +996,7 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
873 VID_BLK_I2C_ADDRESS, 996 VID_BLK_I2C_ADDRESS,
874 VERT_TIM_CTRL, 997 VERT_TIM_CTRL,
875 FLD_V656BLANK_CNT, 998 FLD_V656BLANK_CNT,
876 0x1E000000); 999 0x1C000000);
877 1000
878 status = cx231xx_read_modify_write_i2c_dword(dev, 1001 status = cx231xx_read_modify_write_i2c_dword(dev,
879 VID_BLK_I2C_ADDRESS, 1002 VID_BLK_I2C_ADDRESS,
@@ -881,12 +1004,20 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
881 FLD_HBLANK_CNT, 1004 FLD_HBLANK_CNT,
882 cx231xx_set_field 1005 cx231xx_set_field
883 (FLD_HBLANK_CNT, 0x79)); 1006 (FLD_HBLANK_CNT, 0x79));
1007
884 } else if (dev->norm & V4L2_STD_SECAM) { 1008 } else if (dev->norm & V4L2_STD_SECAM) {
885 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 1009 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
886 status = cx231xx_read_modify_write_i2c_dword(dev, 1010 status = cx231xx_read_modify_write_i2c_dword(dev,
887 VID_BLK_I2C_ADDRESS, 1011 VID_BLK_I2C_ADDRESS,
888 VERT_TIM_CTRL, 1012 VERT_TIM_CTRL,
889 FLD_VBLANK_CNT, 0x24); 1013 FLD_VBLANK_CNT, 0x24);
1014 status = cx231xx_read_modify_write_i2c_dword(dev,
1015 VID_BLK_I2C_ADDRESS,
1016 VERT_TIM_CTRL,
1017 FLD_V656BLANK_CNT,
1018 cx231xx_set_field
1019 (FLD_V656BLANK_CNT,
1020 0x28));
890 /* Adjust the active video horizontal start point */ 1021 /* Adjust the active video horizontal start point */
891 status = cx231xx_read_modify_write_i2c_dword(dev, 1022 status = cx231xx_read_modify_write_i2c_dword(dev,
892 VID_BLK_I2C_ADDRESS, 1023 VID_BLK_I2C_ADDRESS,
@@ -900,6 +1031,13 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
900 VID_BLK_I2C_ADDRESS, 1031 VID_BLK_I2C_ADDRESS,
901 VERT_TIM_CTRL, 1032 VERT_TIM_CTRL,
902 FLD_VBLANK_CNT, 0x24); 1033 FLD_VBLANK_CNT, 0x24);
1034 status = cx231xx_read_modify_write_i2c_dword(dev,
1035 VID_BLK_I2C_ADDRESS,
1036 VERT_TIM_CTRL,
1037 FLD_V656BLANK_CNT,
1038 cx231xx_set_field
1039 (FLD_V656BLANK_CNT,
1040 0x28));
903 /* Adjust the active video horizontal start point */ 1041 /* Adjust the active video horizontal start point */
904 status = cx231xx_read_modify_write_i2c_dword(dev, 1042 status = cx231xx_read_modify_write_i2c_dword(dev,
905 VID_BLK_I2C_ADDRESS, 1043 VID_BLK_I2C_ADDRESS,
@@ -907,11 +1045,28 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
907 FLD_HBLANK_CNT, 1045 FLD_HBLANK_CNT,
908 cx231xx_set_field 1046 cx231xx_set_field
909 (FLD_HBLANK_CNT, 0x85)); 1047 (FLD_HBLANK_CNT, 0x85));
1048
910 } 1049 }
911 1050
912 return status; 1051 return status;
913} 1052}
914 1053
1054int cx231xx_unmute_audio(struct cx231xx *dev)
1055{
1056 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1057}
1058EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1059
1060int stopAudioFirmware(struct cx231xx *dev)
1061{
1062 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1063}
1064
1065int restartAudioFirmware(struct cx231xx *dev)
1066{
1067 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1068}
1069
915int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1070int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
916{ 1071{
917 int status = 0; 1072 int status = 0;
@@ -970,6 +1125,7 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
970 1125
971 /* unmute all, AC97 in, independence mode 1126 /* unmute all, AC97 in, independence mode
972 adr 08d0, data 0x00063073 */ 1127 adr 08d0, data 0x00063073 */
1128 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
973 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1129 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
974 1130
975 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1131 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
@@ -985,7 +1141,7 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
985 1141
986 case AUDIO_INPUT_TUNER_TV: 1142 case AUDIO_INPUT_TUNER_TV:
987 default: 1143 default:
988 1144 status = stopAudioFirmware(dev);
989 /* Setup SRC sources and clocks */ 1145 /* Setup SRC sources and clocks */
990 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1146 status = vid_blk_write_word(dev, BAND_OUT_SEL,
991 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1147 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
@@ -1013,17 +1169,30 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1013 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1169 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1014 1170
1015 /* setAudioStandard(_audio_standard); */ 1171 /* setAudioStandard(_audio_standard); */
1016
1017 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1172 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1173
1174 status = restartAudioFirmware(dev);
1175
1018 switch (dev->model) { 1176 switch (dev->model) {
1177 case CX231XX_BOARD_CNXT_CARRAERA:
1019 case CX231XX_BOARD_CNXT_RDE_250: 1178 case CX231XX_BOARD_CNXT_RDE_250:
1179 case CX231XX_BOARD_CNXT_SHELBY:
1020 case CX231XX_BOARD_CNXT_RDU_250: 1180 case CX231XX_BOARD_CNXT_RDU_250:
1181 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1021 status = cx231xx_read_modify_write_i2c_dword(dev, 1182 status = cx231xx_read_modify_write_i2c_dword(dev,
1022 VID_BLK_I2C_ADDRESS, 1183 VID_BLK_I2C_ADDRESS,
1023 CHIP_CTRL, 1184 CHIP_CTRL,
1024 FLD_SIF_EN, 1185 FLD_SIF_EN,
1025 cx231xx_set_field(FLD_SIF_EN, 1)); 1186 cx231xx_set_field(FLD_SIF_EN, 1));
1026 break; 1187 break;
1188 case CX231XX_BOARD_CNXT_RDE_253S:
1189 case CX231XX_BOARD_CNXT_RDU_253S:
1190 status = cx231xx_read_modify_write_i2c_dword(dev,
1191 VID_BLK_I2C_ADDRESS,
1192 CHIP_CTRL,
1193 FLD_SIF_EN,
1194 cx231xx_set_field(FLD_SIF_EN, 0));
1195 break;
1027 default: 1196 default:
1028 break; 1197 break;
1029 } 1198 }
@@ -1058,7 +1227,9 @@ int cx231xx_resolution_set(struct cx231xx *dev)
1058 return status; 1227 return status;
1059 1228
1060 /* set vertical scale */ 1229 /* set vertical scale */
1061 return vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale); 1230 status = vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale);
1231
1232 return status;
1062} 1233}
1063 1234
1064/****************************************************************************** 1235/******************************************************************************
@@ -1123,6 +1294,346 @@ int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1123 return status; 1294 return status;
1124 1295
1125} 1296}
1297EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_for_tuner);
1298void update_HH_register_after_set_DIF(struct cx231xx *dev)
1299{
1300/*
1301 u8 status = 0;
1302 u32 value = 0;
1303
1304 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1305 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1306 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1307
1308 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1309 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1310 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1311*/
1312}
1313
1314void cx231xx_dump_HH_reg(struct cx231xx *dev)
1315{
1316 u8 status = 0;
1317 u32 value = 0;
1318 u16 i = 0;
1319
1320 value = 0x45005390;
1321 status = vid_blk_write_word(dev, 0x104, value);
1322
1323 for (i = 0x100; i < 0x140; i++) {
1324 status = vid_blk_read_word(dev, i, &value);
1325 cx231xx_info("reg0x%x=0x%x\n", i, value);
1326 i = i+3;
1327 }
1328
1329 for (i = 0x300; i < 0x400; i++) {
1330 status = vid_blk_read_word(dev, i, &value);
1331 cx231xx_info("reg0x%x=0x%x\n", i, value);
1332 i = i+3;
1333 }
1334
1335 for (i = 0x400; i < 0x440; i++) {
1336 status = vid_blk_read_word(dev, i, &value);
1337 cx231xx_info("reg0x%x=0x%x\n", i, value);
1338 i = i+3;
1339 }
1340
1341 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1342 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1343 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1344 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1345 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1346
1347}
1348void cx231xx_dump_SC_reg(struct cx231xx *dev)
1349{
1350 u8 value[4] = { 0, 0, 0, 0 };
1351 int status = 0;
1352 cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1353
1354 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1355 value, 4);
1356 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1357 value[1], value[2], value[3]);
1358 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1359 value, 4);
1360 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1361 value[1], value[2], value[3]);
1362 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1363 value, 4);
1364 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1365 value[1], value[2], value[3]);
1366 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1367 value, 4);
1368 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1369 value[1], value[2], value[3]);
1370
1371 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1372 value, 4);
1373 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1374 value[1], value[2], value[3]);
1375 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1376 value, 4);
1377 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1378 value[1], value[2], value[3]);
1379 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1380 value, 4);
1381 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1382 value[1], value[2], value[3]);
1383 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1384 value, 4);
1385 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1386 value[1], value[2], value[3]);
1387
1388 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1389 value, 4);
1390 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1391 value[1], value[2], value[3]);
1392 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1393 value, 4);
1394 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1395 value[1], value[2], value[3]);
1396 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1397 value, 4);
1398 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1399 value[1], value[2], value[3]);
1400 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1401 value, 4);
1402 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1403 value[1], value[2], value[3]);
1404
1405 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1406 value, 4);
1407 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1408 value[1], value[2], value[3]);
1409 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1410 value, 4);
1411 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1412 value[1], value[2], value[3]);
1413 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1414 value, 4);
1415 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1416 value[1], value[2], value[3]);
1417 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1418 value, 4);
1419 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1420 value[1], value[2], value[3]);
1421
1422 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1423 value, 4);
1424 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1425 value[1], value[2], value[3]);
1426 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1427 value, 4);
1428 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1429 value[1], value[2], value[3]);
1430
1431
1432}
1433
1434void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1435
1436{
1437 u8 status = 0;
1438 u8 value = 0;
1439
1440
1441
1442 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1443 value = (value & 0xFE)|0x01;
1444 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1445
1446 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1447 value = (value & 0xFE)|0x00;
1448 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1449
1450
1451/*
1452 config colibri to lo-if mode
1453
1454 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1455 the diff IF input by half,
1456
1457 for low-if agc defect
1458*/
1459
1460 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1461 value = (value & 0xFC)|0x00;
1462 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1463
1464 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1465 value = (value & 0xF9)|0x02;
1466 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1467
1468 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1469 value = (value & 0xFB)|0x04;
1470 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1471
1472 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1473 value = (value & 0xFC)|0x03;
1474 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1475
1476 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1477 value = (value & 0xFB)|0x04;
1478 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1479
1480 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1481 value = (value & 0xF8)|0x06;
1482 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1483
1484 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1485 value = (value & 0x8F)|0x40;
1486 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1487
1488 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1489 value = (value & 0xDF)|0x20;
1490 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1491}
1492
1493void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1494 u8 spectral_invert, u32 mode)
1495{
1496
1497 u32 colibri_carrier_offset = 0;
1498 u8 status = 0;
1499 u32 func_mode = 0;
1500 u32 standard = 0;
1501 u8 value[4] = { 0, 0, 0, 0 };
1502
1503 switch (dev->model) {
1504 case CX231XX_BOARD_CNXT_CARRAERA:
1505 case CX231XX_BOARD_CNXT_RDE_250:
1506 case CX231XX_BOARD_CNXT_SHELBY:
1507 case CX231XX_BOARD_CNXT_RDU_250:
1508 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1509 func_mode = 0x03;
1510 break;
1511 case CX231XX_BOARD_CNXT_RDE_253S:
1512 case CX231XX_BOARD_CNXT_RDU_253S:
1513 func_mode = 0x01;
1514 break;
1515
1516 default:
1517 func_mode = 0x01;
1518 }
1519
1520 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1521 value[0] = (u8) 0x6F;
1522 value[1] = (u8) 0x6F;
1523 value[2] = (u8) 0x6F;
1524 value[3] = (u8) 0x6F;
1525 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1526 PWR_CTL_EN, value, 4);
1527 if (1) {
1528
1529 /*Set colibri for low IF*/
1530 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1531
1532
1533 /* Set C2HH for low IF operation.*/
1534 standard = dev->norm;
1535 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1536 func_mode, standard);
1537
1538
1539 /* Get colibri offsets.*/
1540 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1541 standard);
1542
1543 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1544 colibri_carrier_offset, standard);
1545
1546 /* Set the band Pass filter for DIF*/
1547 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset)
1548 , spectral_invert, mode);
1549 }
1550}
1551
1552u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1553{
1554 u32 colibri_carrier_offset = 0;
1555
1556
1557 if (mode == TUNER_MODE_FM_RADIO) {
1558 colibri_carrier_offset = 1100000;
1559 } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1560 colibri_carrier_offset = 4832000; /*4.83MHz */
1561 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1562 colibri_carrier_offset = 2700000; /*2.70MHz */
1563 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1564 | V4L2_STD_SECAM)) {
1565 colibri_carrier_offset = 2100000; /*2.10MHz */
1566 }
1567
1568
1569 return colibri_carrier_offset;
1570}
1571
1572void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1573 u8 spectral_invert, u32 mode)
1574{
1575
1576 unsigned long pll_freq_word;
1577 int status = 0;
1578 u32 dif_misc_ctrl_value = 0;
1579 u64 pll_freq_u64 = 0;
1580 u32 i = 0;
1581
1582
1583 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1584 if_freq, spectral_invert, mode);
1585
1586
1587 if (mode == TUNER_MODE_FM_RADIO) {
1588 pll_freq_word = 0x905A1CAC;
1589 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1590
1591 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1592 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1593 pll_freq_word = if_freq;
1594 pll_freq_u64 = (u64)pll_freq_word << 28L;
1595 do_div(pll_freq_u64, 50000000);
1596 pll_freq_word = (u32)pll_freq_u64;
1597 /*pll_freq_word = 0x3463497;*/
1598 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1599
1600 if (spectral_invert) {
1601 if_freq -= 400000;
1602 /* Enable Spectral Invert*/
1603 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1604 &dif_misc_ctrl_value);
1605 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1606 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1607 dif_misc_ctrl_value);
1608 } else {
1609 if_freq += 400000;
1610 /* Disable Spectral Invert*/
1611 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1612 &dif_misc_ctrl_value);
1613 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1614 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1615 dif_misc_ctrl_value);
1616 }
1617
1618 if_freq = (if_freq/100000)*100000;
1619
1620 if (if_freq < 3000000)
1621 if_freq = 3000000;
1622
1623 if (if_freq > 16000000)
1624 if_freq = 16000000;
1625 }
1626
1627 cx231xx_info("Enter IF=%d\n",
1628 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1629 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1630 if (Dif_set_array[i].if_freq == if_freq) {
1631 status = vid_blk_write_word(dev,
1632 Dif_set_array[i].register_address, Dif_set_array[i].value);
1633 }
1634 }
1635
1636}
1126 1637
1127/****************************************************************************** 1638/******************************************************************************
1128 * D I F - B L O C K C O N T R O L functions * 1639 * D I F - B L O C K C O N T R O L functions *
@@ -1132,6 +1643,7 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1132{ 1643{
1133 int status = 0; 1644 int status = 0;
1134 1645
1646
1135 if (mode == V4L2_TUNER_RADIO) { 1647 if (mode == V4L2_TUNER_RADIO) {
1136 /* C2HH */ 1648 /* C2HH */
1137 /* lo if big signal */ 1649 /* lo if big signal */
@@ -1174,6 +1686,7 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1174 VID_BLK_I2C_ADDRESS, 32, 1686 VID_BLK_I2C_ADDRESS, 32,
1175 AUD_IO_CTRL, 0, 31, 0x00000003); 1687 AUD_IO_CTRL, 0, 31, 0x00000003);
1176 } else if ((standard == V4L2_STD_PAL_I) | 1688 } else if ((standard == V4L2_STD_PAL_I) |
1689 (standard & V4L2_STD_PAL_D) |
1177 (standard & V4L2_STD_SECAM)) { 1690 (standard & V4L2_STD_SECAM)) {
1178 /* C2HH setup */ 1691 /* C2HH setup */
1179 /* lo if big signal */ 1692 /* lo if big signal */
@@ -1232,10 +1745,17 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1232 dev->norm = standard; 1745 dev->norm = standard;
1233 1746
1234 switch (dev->model) { 1747 switch (dev->model) {
1748 case CX231XX_BOARD_CNXT_CARRAERA:
1235 case CX231XX_BOARD_CNXT_RDE_250: 1749 case CX231XX_BOARD_CNXT_RDE_250:
1750 case CX231XX_BOARD_CNXT_SHELBY:
1236 case CX231XX_BOARD_CNXT_RDU_250: 1751 case CX231XX_BOARD_CNXT_RDU_250:
1752 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1237 func_mode = 0x03; 1753 func_mode = 0x03;
1238 break; 1754 break;
1755 case CX231XX_BOARD_CNXT_RDE_253S:
1756 case CX231XX_BOARD_CNXT_RDU_253S:
1757 func_mode = 0x01;
1758 break;
1239 default: 1759 default:
1240 func_mode = 0x01; 1760 func_mode = 0x01;
1241 } 1761 }
@@ -1617,17 +2137,27 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1617{ 2137{
1618 int status = 0; 2138 int status = 0;
1619 u32 dwval; 2139 u32 dwval;
1620 2140 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2141 dev->tuner_type);
1621 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2142 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1622 * SECAM L/B/D standards */ 2143 * SECAM L/B/D standards */
1623 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2144 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1624 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2145 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1625 2146
1626 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 2147 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
1627 V4L2_STD_SECAM_D)) 2148 V4L2_STD_SECAM_D)) {
1628 dwval |= 0x88000000; 2149 if (dev->tuner_type == TUNER_NXP_TDA18271) {
1629 else 2150 dwval &= ~FLD_DIF_IF_REF;
1630 dwval |= 0x44000000; 2151 dwval |= 0x88000300;
2152 } else
2153 dwval |= 0x88000000;
2154 } else {
2155 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2156 dwval &= ~FLD_DIF_IF_REF;
2157 dwval |= 0xCC000300;
2158 } else
2159 dwval |= 0x44000000;
2160 }
1631 2161
1632 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2162 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1633 2163
@@ -1714,8 +2244,6 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1714 return 0; 2244 return 0;
1715 } 2245 }
1716 2246
1717 cx231xx_info(" setPowerMode::mode = %d\n", mode);
1718
1719 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2247 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1720 4); 2248 4);
1721 if (status < 0) 2249 if (status < 0)
@@ -1761,7 +2289,7 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1761 2289
1762 case POLARIS_AVMODE_ANALOGT_TV: 2290 case POLARIS_AVMODE_ANALOGT_TV:
1763 2291
1764 tmp &= (~PWR_DEMOD_EN); 2292 tmp |= PWR_DEMOD_EN;
1765 tmp |= (I2C_DEMOD_EN); 2293 tmp |= (I2C_DEMOD_EN);
1766 value[0] = (u8) tmp; 2294 value[0] = (u8) tmp;
1767 value[1] = (u8) (tmp >> 8); 2295 value[1] = (u8) (tmp >> 8);
@@ -1814,14 +2342,27 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1814 msleep(PWR_SLEEP_INTERVAL); 2342 msleep(PWR_SLEEP_INTERVAL);
1815 } 2343 }
1816 2344
1817 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || 2345 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2346 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2347 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
1818 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { 2348 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1819 /* tuner path to channel 1 from port 3 */ 2349 /* tuner path to channel 1 from port 3 */
1820 cx231xx_enable_i2c_for_tuner(dev, I2C_3); 2350 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1821 2351
2352 /* reset the Tuner */
2353 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2354
2355 if (dev->cx231xx_reset_analog_tuner)
2356 dev->cx231xx_reset_analog_tuner(dev);
2357 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2358 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2359 (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2360 /* tuner path to channel 1 from port 3 */
2361 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1822 if (dev->cx231xx_reset_analog_tuner) 2362 if (dev->cx231xx_reset_analog_tuner)
1823 dev->cx231xx_reset_analog_tuner(dev); 2363 dev->cx231xx_reset_analog_tuner(dev);
1824 } 2364 }
2365
1825 break; 2366 break;
1826 2367
1827 case POLARIS_AVMODE_DIGITAL: 2368 case POLARIS_AVMODE_DIGITAL:
@@ -1876,14 +2417,27 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1876 msleep(PWR_SLEEP_INTERVAL); 2417 msleep(PWR_SLEEP_INTERVAL);
1877 } 2418 }
1878 2419
1879 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || 2420 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2421 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2422 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
1880 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { 2423 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1881 /* tuner path to channel 1 from port 3 */ 2424 /* tuner path to channel 1 from port 3 */
1882 cx231xx_enable_i2c_for_tuner(dev, I2C_3); 2425 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1883 2426
2427 /* reset the Tuner */
2428 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2429
2430 if (dev->cx231xx_reset_analog_tuner)
2431 dev->cx231xx_reset_analog_tuner(dev);
2432 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2433 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2434 (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2435 /* tuner path to channel 1 from port 3 */
2436 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1884 if (dev->cx231xx_reset_analog_tuner) 2437 if (dev->cx231xx_reset_analog_tuner)
1885 dev->cx231xx_reset_analog_tuner(dev); 2438 dev->cx231xx_reset_analog_tuner(dev);
1886 } 2439 }
2440
1887 break; 2441 break;
1888 2442
1889 default: 2443 default:
@@ -1913,9 +2467,6 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1913 2467
1914 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2468 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1915 4); 2469 4);
1916 cx231xx_info(" The data of PWR_CTL_EN register 0x74"
1917 "=0x%0x,0x%0x,0x%0x,0x%0x\n",
1918 value[0], value[1], value[2], value[3]);
1919 2470
1920 return status; 2471 return status;
1921} 2472}
@@ -2000,6 +2551,8 @@ int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2000int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 2551int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2001{ 2552{
2002 int status = 0; 2553 int status = 0;
2554 u32 value = 0;
2555 u8 val[4] = { 0, 0, 0, 0 };
2003 2556
2004 if (dev->udev->speed == USB_SPEED_HIGH) { 2557 if (dev->udev->speed == USB_SPEED_HIGH) {
2005 switch (media_type) { 2558 switch (media_type) {
@@ -2026,10 +2579,36 @@ int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2026 break; 2579 break;
2027 2580
2028 case 4: /* ts1 */ 2581 case 4: /* ts1 */
2029 cx231xx_info("%s: set ts1 registers\n", __func__); 2582 cx231xx_info("%s: set ts1 registers", __func__);
2583
2584 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2585 cx231xx_info(" MPEG\n");
2586 value &= 0xFFFFFFFC;
2587 value |= 0x3;
2588
2589 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2590
2591 val[0] = 0x04;
2592 val[1] = 0xA3;
2593 val[2] = 0x3B;
2594 val[3] = 0x00;
2595 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2596 TS1_CFG_REG, val, 4);
2597
2598 val[0] = 0x00;
2599 val[1] = 0x08;
2600 val[2] = 0x00;
2601 val[3] = 0x08;
2602 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2603 TS1_LENGTH_REG, val, 4);
2604
2605 } else {
2606 cx231xx_info(" BDA\n");
2030 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2607 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2031 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2608 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2609 }
2032 break; 2610 break;
2611
2033 case 6: /* ts1 parallel mode */ 2612 case 6: /* ts1 parallel mode */
2034 cx231xx_info("%s: set ts1 parrallel mode registers\n", 2613 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2035 __func__); 2614 __func__);
@@ -2128,7 +2707,7 @@ EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2128/***************************************************************************** 2707/*****************************************************************************
2129* G P I O B I T control functions * 2708* G P I O B I T control functions *
2130******************************************************************************/ 2709******************************************************************************/
2131int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) 2710int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2132{ 2711{
2133 int status = 0; 2712 int status = 0;
2134 2713
@@ -2137,7 +2716,7 @@ int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2137 return status; 2716 return status;
2138} 2717}
2139 2718
2140int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) 2719int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2141{ 2720{
2142 int status = 0; 2721 int status = 0;
2143 2722
@@ -2344,7 +2923,7 @@ int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2344 return status; 2923 return status;
2345} 2924}
2346 2925
2347int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf) 2926int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2348{ 2927{
2349 u8 value = 0; 2928 u8 value = 0;
2350 int status = 0; 2929 int status = 0;
@@ -2494,7 +3073,7 @@ int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2494/* cx231xx_gpio_i2c_read 3073/* cx231xx_gpio_i2c_read
2495 * Function to read data from gpio based I2C interface 3074 * Function to read data from gpio based I2C interface
2496 */ 3075 */
2497int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len) 3076int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
2498{ 3077{
2499 int status = 0; 3078 int status = 0;
2500 int i = 0; 3079 int i = 0;
@@ -2538,7 +3117,7 @@ int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2538/* cx231xx_gpio_i2c_write 3117/* cx231xx_gpio_i2c_write
2539 * Function to write data to gpio based I2C interface 3118 * Function to write data to gpio based I2C interface
2540 */ 3119 */
2541int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len) 3120int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
2542{ 3121{
2543 int status = 0; 3122 int status = 0;
2544 int i = 0; 3123 int i = 0;
diff --git a/drivers/media/video/cx231xx/cx231xx-cards.c b/drivers/media/video/cx231xx/cx231xx-cards.c
index f2a4900014bc..59e273324f5a 100644
--- a/drivers/media/video/cx231xx/cx231xx-cards.c
+++ b/drivers/media/video/cx231xx/cx231xx-cards.c
@@ -41,6 +41,10 @@ static int tuner = -1;
41module_param(tuner, int, 0444); 41module_param(tuner, int, 0444);
42MODULE_PARM_DESC(tuner, "tuner type"); 42MODULE_PARM_DESC(tuner, "tuner type");
43 43
44static int transfer_mode = 1;
45module_param(transfer_mode, int, 0444);
46MODULE_PARM_DESC(transfer_mode, "transfer mode (1-ISO or 0-BULK)");
47
44static unsigned int disable_ir; 48static unsigned int disable_ir;
45module_param(disable_ir, int, 0444); 49module_param(disable_ir, int, 0444);
46MODULE_PARM_DESC(disable_ir, "disable infrared remote support"); 50MODULE_PARM_DESC(disable_ir, "disable infrared remote support");
@@ -86,8 +90,8 @@ struct cx231xx_board cx231xx_boards[] = {
86 } 90 }
87 }, 91 },
88 }, 92 },
89 [CX231XX_BOARD_CNXT_RDE_250] = { 93 [CX231XX_BOARD_CNXT_CARRAERA] = {
90 .name = "Conexant Hybrid TV - RDE250", 94 .name = "Conexant Hybrid TV - CARRAERA",
91 .tuner_type = TUNER_XC5000, 95 .tuner_type = TUNER_XC5000,
92 .tuner_addr = 0x61, 96 .tuner_addr = 0x61,
93 .tuner_gpio = RDE250_XCV_TUNER, 97 .tuner_gpio = RDE250_XCV_TUNER,
@@ -125,9 +129,8 @@ struct cx231xx_board cx231xx_boards[] = {
125 } 129 }
126 }, 130 },
127 }, 131 },
128 132 [CX231XX_BOARD_CNXT_SHELBY] = {
129 [CX231XX_BOARD_CNXT_RDU_250] = { 133 .name = "Conexant Hybrid TV - SHELBY",
130 .name = "Conexant Hybrid TV - RDU250",
131 .tuner_type = TUNER_XC5000, 134 .tuner_type = TUNER_XC5000,
132 .tuner_addr = 0x61, 135 .tuner_addr = 0x61,
133 .tuner_gpio = RDE250_XCV_TUNER, 136 .tuner_gpio = RDE250_XCV_TUNER,
@@ -165,6 +168,183 @@ struct cx231xx_board cx231xx_boards[] = {
165 } 168 }
166 }, 169 },
167 }, 170 },
171 [CX231XX_BOARD_CNXT_RDE_253S] = {
172 .name = "Conexant Hybrid TV - RDE253S",
173 .tuner_type = TUNER_NXP_TDA18271,
174 .tuner_addr = 0x60,
175 .tuner_gpio = RDE250_XCV_TUNER,
176 .tuner_sif_gpio = 0x05,
177 .tuner_scl_gpio = 0x1a,
178 .tuner_sda_gpio = 0x1b,
179 .decoder = CX231XX_AVDECODER,
180 .demod_xfer_mode = 0,
181 .ctl_pin_status_mask = 0xFFFFFFC4,
182 .agc_analog_digital_select_gpio = 0x1c,
183 .gpio_pin_status_mask = 0x4001000,
184 .tuner_i2c_master = 1,
185 .demod_i2c_master = 2,
186 .has_dvb = 1,
187 .demod_addr = 0x02,
188 .norm = V4L2_STD_PAL,
189
190 .input = {{
191 .type = CX231XX_VMUX_TELEVISION,
192 .vmux = CX231XX_VIN_3_1,
193 .amux = CX231XX_AMUX_VIDEO,
194 .gpio = NULL,
195 }, {
196 .type = CX231XX_VMUX_COMPOSITE1,
197 .vmux = CX231XX_VIN_2_1,
198 .amux = CX231XX_AMUX_LINE_IN,
199 .gpio = NULL,
200 }, {
201 .type = CX231XX_VMUX_SVIDEO,
202 .vmux = CX231XX_VIN_1_1 |
203 (CX231XX_VIN_1_2 << 8) |
204 CX25840_SVIDEO_ON,
205 .amux = CX231XX_AMUX_LINE_IN,
206 .gpio = NULL,
207 }
208 },
209 },
210
211 [CX231XX_BOARD_CNXT_RDU_253S] = {
212 .name = "Conexant Hybrid TV - RDU253S",
213 .tuner_type = TUNER_NXP_TDA18271,
214 .tuner_addr = 0x60,
215 .tuner_gpio = RDE250_XCV_TUNER,
216 .tuner_sif_gpio = 0x05,
217 .tuner_scl_gpio = 0x1a,
218 .tuner_sda_gpio = 0x1b,
219 .decoder = CX231XX_AVDECODER,
220 .demod_xfer_mode = 0,
221 .ctl_pin_status_mask = 0xFFFFFFC4,
222 .agc_analog_digital_select_gpio = 0x1c,
223 .gpio_pin_status_mask = 0x4001000,
224 .tuner_i2c_master = 1,
225 .demod_i2c_master = 2,
226 .has_dvb = 1,
227 .demod_addr = 0x02,
228 .norm = V4L2_STD_PAL,
229
230 .input = {{
231 .type = CX231XX_VMUX_TELEVISION,
232 .vmux = CX231XX_VIN_3_1,
233 .amux = CX231XX_AMUX_VIDEO,
234 .gpio = NULL,
235 }, {
236 .type = CX231XX_VMUX_COMPOSITE1,
237 .vmux = CX231XX_VIN_2_1,
238 .amux = CX231XX_AMUX_LINE_IN,
239 .gpio = NULL,
240 }, {
241 .type = CX231XX_VMUX_SVIDEO,
242 .vmux = CX231XX_VIN_1_1 |
243 (CX231XX_VIN_1_2 << 8) |
244 CX25840_SVIDEO_ON,
245 .amux = CX231XX_AMUX_LINE_IN,
246 .gpio = NULL,
247 }
248 },
249 },
250 [CX231XX_BOARD_CNXT_VIDEO_GRABBER] = {
251 .name = "Conexant VIDEO GRABBER",
252 .tuner_type = TUNER_NXP_TDA18271,
253 .tuner_addr = 0x60,
254 .tuner_gpio = RDE250_XCV_TUNER,
255 .tuner_sif_gpio = 0x05,
256 .tuner_scl_gpio = 0x1a,
257 .tuner_sda_gpio = 0x1b,
258 .decoder = CX231XX_AVDECODER,
259 .demod_xfer_mode = 0,
260 .ctl_pin_status_mask = 0xFFFFFFC4,
261 .agc_analog_digital_select_gpio = 0x1c,
262 .gpio_pin_status_mask = 0x4001000,
263 .tuner_i2c_master = 1,
264 .demod_i2c_master = 2,
265 .has_dvb = 0,
266 .demod_addr = 0x02,
267 .norm = V4L2_STD_PAL,
268
269 .input = {{
270 .type = CX231XX_VMUX_COMPOSITE1,
271 .vmux = CX231XX_VIN_2_1,
272 .amux = CX231XX_AMUX_LINE_IN,
273 .gpio = NULL,
274 }, {
275 .type = CX231XX_VMUX_SVIDEO,
276 .vmux = CX231XX_VIN_1_1 |
277 (CX231XX_VIN_1_2 << 8) |
278 CX25840_SVIDEO_ON,
279 .amux = CX231XX_AMUX_LINE_IN,
280 .gpio = NULL,
281 }, {
282 .type = CX231XX_VMUX_TELEVISION,
283 .vmux = CX231XX_VIN_3_1,
284 .amux = CX231XX_AMUX_VIDEO,
285 .gpio = NULL,
286 }
287 },
288 },
289 [CX231XX_BOARD_CNXT_RDE_250] = {
290 .name = "Conexant Hybrid TV - rde 250",
291 .tuner_type = TUNER_XC5000,
292 .tuner_addr = 0x61,
293 .tuner_gpio = RDE250_XCV_TUNER,
294 .tuner_sif_gpio = 0x05,
295 .tuner_scl_gpio = 0x1a,
296 .tuner_sda_gpio = 0x1b,
297 .decoder = CX231XX_AVDECODER,
298 .demod_xfer_mode = 0,
299 .ctl_pin_status_mask = 0xFFFFFFC4,
300 .agc_analog_digital_select_gpio = 0x0c,
301 .gpio_pin_status_mask = 0x4001000,
302 .tuner_i2c_master = 1,
303 .demod_i2c_master = 2,
304 .has_dvb = 1,
305 .demod_addr = 0x02,
306 .norm = V4L2_STD_PAL,
307
308 .input = {{
309 .type = CX231XX_VMUX_TELEVISION,
310 .vmux = CX231XX_VIN_2_1,
311 .amux = CX231XX_AMUX_VIDEO,
312 .gpio = NULL,
313 }
314 },
315 },
316 [CX231XX_BOARD_CNXT_RDU_250] = {
317 .name = "Conexant Hybrid TV - RDU 250",
318 .tuner_type = TUNER_XC5000,
319 .tuner_addr = 0x61,
320 .tuner_gpio = RDE250_XCV_TUNER,
321 .tuner_sif_gpio = 0x05,
322 .tuner_scl_gpio = 0x1a,
323 .tuner_sda_gpio = 0x1b,
324 .decoder = CX231XX_AVDECODER,
325 .demod_xfer_mode = 0,
326 .ctl_pin_status_mask = 0xFFFFFFC4,
327 .agc_analog_digital_select_gpio = 0x0c,
328 .gpio_pin_status_mask = 0x4001000,
329 .tuner_i2c_master = 1,
330 .demod_i2c_master = 2,
331 .has_dvb = 1,
332 .demod_addr = 0x32,
333 .norm = V4L2_STD_NTSC,
334
335 .input = {{
336 .type = CX231XX_VMUX_TELEVISION,
337 .vmux = CX231XX_VIN_2_1,
338 .amux = CX231XX_AMUX_VIDEO,
339 .gpio = NULL,
340 }
341 },
342 },
343
344
345
346
347
168}; 348};
169const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards); 349const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards);
170 350
@@ -173,8 +353,18 @@ struct usb_device_id cx231xx_id_table[] = {
173 {USB_DEVICE(0x0572, 0x5A3C), 353 {USB_DEVICE(0x0572, 0x5A3C),
174 .driver_info = CX231XX_BOARD_UNKNOWN}, 354 .driver_info = CX231XX_BOARD_UNKNOWN},
175 {USB_DEVICE(0x0572, 0x58A2), 355 {USB_DEVICE(0x0572, 0x58A2),
176 .driver_info = CX231XX_BOARD_CNXT_RDE_250}, 356 .driver_info = CX231XX_BOARD_CNXT_CARRAERA},
177 {USB_DEVICE(0x0572, 0x58A1), 357 {USB_DEVICE(0x0572, 0x58A1),
358 .driver_info = CX231XX_BOARD_CNXT_SHELBY},
359 {USB_DEVICE(0x0572, 0x58A4),
360 .driver_info = CX231XX_BOARD_CNXT_RDE_253S},
361 {USB_DEVICE(0x0572, 0x58A5),
362 .driver_info = CX231XX_BOARD_CNXT_RDU_253S},
363 {USB_DEVICE(0x0572, 0x58A6),
364 .driver_info = CX231XX_BOARD_CNXT_VIDEO_GRABBER},
365 {USB_DEVICE(0x0572, 0x589E),
366 .driver_info = CX231XX_BOARD_CNXT_RDE_250},
367 {USB_DEVICE(0x0572, 0x58A0),
178 .driver_info = CX231XX_BOARD_CNXT_RDU_250}, 368 .driver_info = CX231XX_BOARD_CNXT_RDU_250},
179 {USB_DEVICE_VER(USB_VID_PIXELVIEW, USB_PID_PIXELVIEW_SBTVD, 0x4000,0x4fff), 369 {USB_DEVICE_VER(USB_VID_PIXELVIEW, USB_PID_PIXELVIEW_SBTVD, 0x4000,0x4fff),
180 .driver_info = CX231XX_BOARD_UNKNOWN}, 370 .driver_info = CX231XX_BOARD_UNKNOWN},
@@ -212,6 +402,23 @@ int cx231xx_tuner_callback(void *ptr, int component, int command, int arg)
212} 402}
213EXPORT_SYMBOL_GPL(cx231xx_tuner_callback); 403EXPORT_SYMBOL_GPL(cx231xx_tuner_callback);
214 404
405void cx231xx_reset_out(struct cx231xx *dev)
406{
407 cx231xx_set_gpio_value(dev, CX23417_RESET, 1);
408 msleep(200);
409 cx231xx_set_gpio_value(dev, CX23417_RESET, 0);
410 msleep(200);
411 cx231xx_set_gpio_value(dev, CX23417_RESET, 1);
412}
413void cx231xx_enable_OSC(struct cx231xx *dev)
414{
415 cx231xx_set_gpio_value(dev, CX23417_OSC_EN, 1);
416}
417void cx231xx_sleep_s5h1432(struct cx231xx *dev)
418{
419 cx231xx_set_gpio_value(dev, SLEEP_S5H1432, 0);
420}
421
215static inline void cx231xx_set_model(struct cx231xx *dev) 422static inline void cx231xx_set_model(struct cx231xx *dev)
216{ 423{
217 memcpy(&dev->board, &cx231xx_boards[dev->model], sizeof(dev->board)); 424 memcpy(&dev->board, &cx231xx_boards[dev->model], sizeof(dev->board));
@@ -235,9 +442,6 @@ void cx231xx_pre_card_setup(struct cx231xx *dev)
235 cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1); 442 cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
236 443
237 /* request some modules if any required */ 444 /* request some modules if any required */
238
239 /* reset the Tuner */
240 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
241 } 445 }
242 446
243 /* set the mode to Analog mode initially */ 447 /* set the mode to Analog mode initially */
@@ -297,10 +501,20 @@ void cx231xx_register_i2c_ir(struct cx231xx *dev)
297 /* detect & configure */ 501 /* detect & configure */
298 switch (dev->model) { 502 switch (dev->model) {
299 503
504 case CX231XX_BOARD_CNXT_CARRAERA:
505 break;
300 case CX231XX_BOARD_CNXT_RDE_250: 506 case CX231XX_BOARD_CNXT_RDE_250:
301 break; 507 break;
508 case CX231XX_BOARD_CNXT_SHELBY:
509 break;
302 case CX231XX_BOARD_CNXT_RDU_250: 510 case CX231XX_BOARD_CNXT_RDU_250:
303 break; 511 break;
512 case CX231XX_BOARD_CNXT_RDE_253S:
513 break;
514 case CX231XX_BOARD_CNXT_RDU_253S:
515 break;
516 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
517 break;
304 default: 518 default:
305 break; 519 break;
306 } 520 }
@@ -326,14 +540,38 @@ void cx231xx_card_setup(struct cx231xx *dev)
326 540
327 } 541 }
328 542
329 if (dev->board.tuner_type != TUNER_ABSENT) { 543 switch (dev->model) {
330 dev->sd_tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev, 544 case CX231XX_BOARD_CNXT_CARRAERA:
331 &dev->i2c_bus[1].i2c_adap, 545 case CX231XX_BOARD_CNXT_RDE_250:
332 "tuner", "tuner", 0xc2 >> 1, NULL); 546 case CX231XX_BOARD_CNXT_SHELBY:
333 if (dev->sd_tuner == NULL) 547 case CX231XX_BOARD_CNXT_RDU_250:
334 cx231xx_info("tuner subdev registration failure\n"); 548 if (dev->board.tuner_type != TUNER_ABSENT) {
335 549 dev->sd_tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev,
336 cx231xx_config_tuner(dev); 550 &dev->i2c_bus[1].i2c_adap,
551 "tuner", "tuner", 0xc2 >> 1, NULL);
552 if (dev->sd_tuner == NULL)
553 cx231xx_info(
554 "tuner subdev registration failure\n");
555
556 cx231xx_config_tuner(dev);
557 }
558 break;
559 case CX231XX_BOARD_CNXT_RDE_253S:
560 case CX231XX_BOARD_CNXT_RDU_253S:
561 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
562 if (dev->board.tuner_type != TUNER_ABSENT) {
563 dev->sd_tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev,
564 &dev->i2c_bus[1].i2c_adap,
565 "tuner", "tuner", 0xc0 >> 1, NULL);
566 if (dev->sd_tuner == NULL)
567 cx231xx_info(
568 "tuner subdev registration failure\n");
569
570 cx231xx_config_tuner(dev);
571 }
572 break;
573 default:
574 break;
337 } 575 }
338 576
339 cx231xx_config_tuner(dev); 577 cx231xx_config_tuner(dev);
@@ -409,6 +647,7 @@ static int cx231xx_init_dev(struct cx231xx **devhandle, struct usb_device *udev,
409 mutex_init(&dev->lock); 647 mutex_init(&dev->lock);
410 mutex_init(&dev->ctrl_urb_lock); 648 mutex_init(&dev->ctrl_urb_lock);
411 mutex_init(&dev->gpio_i2c_lock); 649 mutex_init(&dev->gpio_i2c_lock);
650 mutex_init(&dev->i2c_lock);
412 651
413 spin_lock_init(&dev->video_mode.slock); 652 spin_lock_init(&dev->video_mode.slock);
414 spin_lock_init(&dev->vbi_mode.slock); 653 spin_lock_init(&dev->vbi_mode.slock);
@@ -427,6 +666,12 @@ static int cx231xx_init_dev(struct cx231xx **devhandle, struct usb_device *udev,
427 /* Query cx231xx to find what pcb config it is related to */ 666 /* Query cx231xx to find what pcb config it is related to */
428 initialize_cx231xx(dev); 667 initialize_cx231xx(dev);
429 668
669 /*To workaround error number=-71 on EP0 for VideoGrabber,
670 need set alt here.*/
671 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
672 cx231xx_set_alt_setting(dev, INDEX_VIDEO, 3);
673 cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
674 }
430 /* Cx231xx pre card setup */ 675 /* Cx231xx pre card setup */
431 cx231xx_pre_card_setup(dev); 676 cx231xx_pre_card_setup(dev);
432 677
@@ -442,6 +687,7 @@ static int cx231xx_init_dev(struct cx231xx **devhandle, struct usb_device *udev,
442 /* register i2c bus */ 687 /* register i2c bus */
443 errCode = cx231xx_dev_init(dev); 688 errCode = cx231xx_dev_init(dev);
444 if (errCode < 0) { 689 if (errCode < 0) {
690 cx231xx_dev_uninit(dev);
445 cx231xx_errdev("%s: cx231xx_i2c_register - errCode [%d]!\n", 691 cx231xx_errdev("%s: cx231xx_i2c_register - errCode [%d]!\n",
446 __func__, errCode); 692 __func__, errCode);
447 return errCode; 693 return errCode;
@@ -480,9 +726,17 @@ static int cx231xx_init_dev(struct cx231xx **devhandle, struct usb_device *udev,
480 INIT_LIST_HEAD(&dev->vbi_mode.vidq.queued); 726 INIT_LIST_HEAD(&dev->vbi_mode.vidq.queued);
481 727
482 /* Reset other chips required if they are tied up with GPIO pins */ 728 /* Reset other chips required if they are tied up with GPIO pins */
483
484 cx231xx_add_into_devlist(dev); 729 cx231xx_add_into_devlist(dev);
485 730
731 printk(KERN_INFO "attach 417 %d\n", dev->model);
732 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
733 if (cx231xx_417_register(dev) < 0) {
734 printk(KERN_ERR
735 "%s() Failed to register 417 on VID_B\n",
736 __func__);
737 }
738 }
739
486 retval = cx231xx_register_analog_devices(dev); 740 retval = cx231xx_register_analog_devices(dev);
487 if (retval < 0) { 741 if (retval < 0) {
488 cx231xx_release_resources(dev); 742 cx231xx_release_resources(dev);
@@ -552,8 +806,8 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
552 cx231xx_devused |= 1 << nr; 806 cx231xx_devused |= 1 << nr;
553 807
554 if (nr >= CX231XX_MAXBOARDS) { 808 if (nr >= CX231XX_MAXBOARDS) {
555 cx231xx_err(DRIVER_NAME ": Supports only %i cx231xx boards.\n", 809 cx231xx_err(DRIVER_NAME
556 CX231XX_MAXBOARDS); 810 ": Supports only %i cx231xx boards.\n", CX231XX_MAXBOARDS);
557 cx231xx_devused &= ~(1 << nr); 811 cx231xx_devused &= ~(1 << nr);
558 return -ENOMEM; 812 return -ENOMEM;
559 } 813 }
@@ -578,6 +832,7 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
578 dev->xc_fw_load_done = 0; 832 dev->xc_fw_load_done = 0;
579 dev->has_alsa_audio = 1; 833 dev->has_alsa_audio = 1;
580 dev->power_mode = -1; 834 dev->power_mode = -1;
835 atomic_set(&dev->devlist_count, 0);
581 836
582 /* 0 - vbi ; 1 -sliced cc mode */ 837 /* 0 - vbi ; 1 -sliced cc mode */
583 dev->vbi_or_sliced_cc_mode = 0; 838 dev->vbi_or_sliced_cc_mode = 0;
@@ -591,6 +846,11 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
591 /* store the current interface */ 846 /* store the current interface */
592 lif = interface; 847 lif = interface;
593 848
849 /*mode_tv: digital=1 or analog=0*/
850 dev->mode_tv = 0;
851
852 dev->USE_ISO = transfer_mode;
853
594 switch (udev->speed) { 854 switch (udev->speed) {
595 case USB_SPEED_LOW: 855 case USB_SPEED_LOW:
596 speed = "1.5"; 856 speed = "1.5";
@@ -645,7 +905,7 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
645 * set skip interface, for all interfaces but 905 * set skip interface, for all interfaces but
646 * interface 1 and the last one 906 * interface 1 and the last one
647 */ 907 */
648 if ((ifnum != 1) && ((dev->interface_count - 1) 908 if ((ifnum != 1) && ((ifnum)
649 != dev->max_iad_interface_count)) 909 != dev->max_iad_interface_count))
650 skip_interface = 1; 910 skip_interface = 1;
651 911
@@ -667,7 +927,7 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
667 /* save our data pointer in this interface device */ 927 /* save our data pointer in this interface device */
668 usb_set_intfdata(lif, dev); 928 usb_set_intfdata(lif, dev);
669 929
670 if ((dev->interface_count - 1) != dev->max_iad_interface_count) 930 if ((ifnum) != dev->max_iad_interface_count)
671 return 0; 931 return 0;
672 932
673 /* 933 /*
@@ -680,15 +940,18 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
680 cx231xx_errdev("v4l2_device_register failed\n"); 940 cx231xx_errdev("v4l2_device_register failed\n");
681 cx231xx_devused &= ~(1 << nr); 941 cx231xx_devused &= ~(1 << nr);
682 kfree(dev); 942 kfree(dev);
943 dev = NULL;
683 return -EIO; 944 return -EIO;
684 } 945 }
685
686 /* allocate device struct */ 946 /* allocate device struct */
687 retval = cx231xx_init_dev(&dev, udev, nr); 947 retval = cx231xx_init_dev(&dev, udev, nr);
688 if (retval) { 948 if (retval) {
689 cx231xx_devused &= ~(1 << dev->devno); 949 cx231xx_devused &= ~(1 << dev->devno);
690 v4l2_device_unregister(&dev->v4l2_dev); 950 v4l2_device_unregister(&dev->v4l2_dev);
691 kfree(dev); 951 kfree(dev);
952 dev = NULL;
953 usb_set_intfdata(lif, NULL);
954
692 return retval; 955 return retval;
693 } 956 }
694 957
@@ -711,6 +974,7 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
711 cx231xx_devused &= ~(1 << nr); 974 cx231xx_devused &= ~(1 << nr);
712 v4l2_device_unregister(&dev->v4l2_dev); 975 v4l2_device_unregister(&dev->v4l2_dev);
713 kfree(dev); 976 kfree(dev);
977 dev = NULL;
714 return -ENOMEM; 978 return -ENOMEM;
715 } 979 }
716 980
@@ -744,6 +1008,7 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
744 cx231xx_devused &= ~(1 << nr); 1008 cx231xx_devused &= ~(1 << nr);
745 v4l2_device_unregister(&dev->v4l2_dev); 1009 v4l2_device_unregister(&dev->v4l2_dev);
746 kfree(dev); 1010 kfree(dev);
1011 dev = NULL;
747 return -ENOMEM; 1012 return -ENOMEM;
748 } 1013 }
749 1014
@@ -778,6 +1043,7 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
778 cx231xx_devused &= ~(1 << nr); 1043 cx231xx_devused &= ~(1 << nr);
779 v4l2_device_unregister(&dev->v4l2_dev); 1044 v4l2_device_unregister(&dev->v4l2_dev);
780 kfree(dev); 1045 kfree(dev);
1046 dev = NULL;
781 return -ENOMEM; 1047 return -ENOMEM;
782 } 1048 }
783 1049
@@ -813,6 +1079,7 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
813 cx231xx_devused &= ~(1 << nr); 1079 cx231xx_devused &= ~(1 << nr);
814 v4l2_device_unregister(&dev->v4l2_dev); 1080 v4l2_device_unregister(&dev->v4l2_dev);
815 kfree(dev); 1081 kfree(dev);
1082 dev = NULL;
816 return -ENOMEM; 1083 return -ENOMEM;
817 } 1084 }
818 1085
@@ -827,6 +1094,15 @@ static int cx231xx_usb_probe(struct usb_interface *interface,
827 } 1094 }
828 } 1095 }
829 1096
1097 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
1098 cx231xx_enable_OSC(dev);
1099 cx231xx_reset_out(dev);
1100 cx231xx_set_alt_setting(dev, INDEX_VIDEO, 3);
1101 }
1102
1103 if (dev->model == CX231XX_BOARD_CNXT_RDE_253S)
1104 cx231xx_sleep_s5h1432(dev);
1105
830 /* load other modules required */ 1106 /* load other modules required */
831 request_modules(dev); 1107 request_modules(dev);
832 1108
@@ -867,7 +1143,10 @@ static void cx231xx_usb_disconnect(struct usb_interface *interface)
867 video_device_node_name(dev->vdev)); 1143 video_device_node_name(dev->vdev));
868 1144
869 dev->state |= DEV_MISCONFIGURED; 1145 dev->state |= DEV_MISCONFIGURED;
870 cx231xx_uninit_isoc(dev); 1146 if (dev->USE_ISO)
1147 cx231xx_uninit_isoc(dev);
1148 else
1149 cx231xx_uninit_bulk(dev);
871 dev->state |= DEV_DISCONNECTED; 1150 dev->state |= DEV_DISCONNECTED;
872 wake_up_interruptible(&dev->wait_frame); 1151 wake_up_interruptible(&dev->wait_frame);
873 wake_up_interruptible(&dev->wait_stream); 1152 wake_up_interruptible(&dev->wait_stream);
@@ -886,6 +1165,7 @@ static void cx231xx_usb_disconnect(struct usb_interface *interface)
886 kfree(dev->sliced_cc_mode.alt_max_pkt_size); 1165 kfree(dev->sliced_cc_mode.alt_max_pkt_size);
887 kfree(dev->ts1_mode.alt_max_pkt_size); 1166 kfree(dev->ts1_mode.alt_max_pkt_size);
888 kfree(dev); 1167 kfree(dev);
1168 dev = NULL;
889 } 1169 }
890} 1170}
891 1171
diff --git a/drivers/media/video/cx231xx/cx231xx-conf-reg.h b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
index 31a8759f6e54..25593f212abf 100644
--- a/drivers/media/video/cx231xx/cx231xx-conf-reg.h
+++ b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
@@ -39,6 +39,7 @@
39#define CIR_CAR_REG 0x38 39#define CIR_CAR_REG 0x38
40#define CIR_OT_CFG1 0x40 40#define CIR_OT_CFG1 0x40
41#define CIR_OT_CFG2 0x44 41#define CIR_OT_CFG2 0x44
42#define GBULK_BIT_EN 0x68
42#define PWR_CTL_EN 0x74 43#define PWR_CTL_EN 0x74
43 44
44/* Polaris Endpoints capture mask for register EP_MODE_SET */ 45/* Polaris Endpoints capture mask for register EP_MODE_SET */
diff --git a/drivers/media/video/cx231xx/cx231xx-core.c b/drivers/media/video/cx231xx/cx231xx-core.c
index 912a4d740206..e258a6261ea4 100644
--- a/drivers/media/video/cx231xx/cx231xx-core.c
+++ b/drivers/media/video/cx231xx/cx231xx-core.c
@@ -27,6 +27,7 @@
27#include <linux/usb.h> 27#include <linux/usb.h>
28#include <linux/vmalloc.h> 28#include <linux/vmalloc.h>
29#include <media/v4l2-common.h> 29#include <media/v4l2-common.h>
30#include <media/tuner.h>
30 31
31#include "cx231xx.h" 32#include "cx231xx.h"
32#include "cx231xx-reg.h" 33#include "cx231xx-reg.h"
@@ -64,7 +65,7 @@ MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
64* Device control list functions * 65* Device control list functions *
65******************************************************************/ 66******************************************************************/
66 67
67static LIST_HEAD(cx231xx_devlist); 68LIST_HEAD(cx231xx_devlist);
68static DEFINE_MUTEX(cx231xx_devlist_mutex); 69static DEFINE_MUTEX(cx231xx_devlist_mutex);
69 70
70/* 71/*
@@ -74,15 +75,24 @@ static DEFINE_MUTEX(cx231xx_devlist_mutex);
74*/ 75*/
75void cx231xx_remove_from_devlist(struct cx231xx *dev) 76void cx231xx_remove_from_devlist(struct cx231xx *dev)
76{ 77{
77 mutex_lock(&cx231xx_devlist_mutex); 78 if (dev == NULL)
78 list_del(&dev->devlist); 79 return;
79 mutex_unlock(&cx231xx_devlist_mutex); 80 if (dev->udev == NULL)
81 return;
82
83 if (atomic_read(&dev->devlist_count) > 0) {
84 mutex_lock(&cx231xx_devlist_mutex);
85 list_del(&dev->devlist);
86 atomic_dec(&dev->devlist_count);
87 mutex_unlock(&cx231xx_devlist_mutex);
88 }
80}; 89};
81 90
82void cx231xx_add_into_devlist(struct cx231xx *dev) 91void cx231xx_add_into_devlist(struct cx231xx *dev)
83{ 92{
84 mutex_lock(&cx231xx_devlist_mutex); 93 mutex_lock(&cx231xx_devlist_mutex);
85 list_add_tail(&dev->devlist, &cx231xx_devlist); 94 list_add_tail(&dev->devlist, &cx231xx_devlist);
95 atomic_inc(&dev->devlist_count);
86 mutex_unlock(&cx231xx_devlist_mutex); 96 mutex_unlock(&cx231xx_devlist_mutex);
87}; 97};
88 98
@@ -114,6 +124,7 @@ void cx231xx_unregister_extension(struct cx231xx_ops *ops)
114 list_for_each_entry(dev, &cx231xx_devlist, devlist) 124 list_for_each_entry(dev, &cx231xx_devlist, devlist)
115 ops->fini(dev); 125 ops->fini(dev);
116 126
127
117 mutex_lock(&cx231xx_extension_devlist_lock); 128 mutex_lock(&cx231xx_extension_devlist_lock);
118 printk(KERN_INFO DRIVER_NAME ": %s removed\n", ops->name); 129 printk(KERN_INFO DRIVER_NAME ": %s removed\n", ops->name);
119 list_del(&ops->next); 130 list_del(&ops->next);
@@ -285,7 +296,7 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
285 val, reg, dev->urb_buf, len, HZ); 296 val, reg, dev->urb_buf, len, HZ);
286 if (ret < 0) { 297 if (ret < 0) {
287 cx231xx_isocdbg(" failed!\n"); 298 cx231xx_isocdbg(" failed!\n");
288 /* mutex_unlock(&dev->ctrl_urb_lock); */ 299 mutex_unlock(&dev->ctrl_urb_lock);
289 return ret; 300 return ret;
290 } 301 }
291 302
@@ -311,6 +322,8 @@ int cx231xx_send_vendor_cmd(struct cx231xx *dev,
311{ 322{
312 int ret; 323 int ret;
313 int pipe = 0; 324 int pipe = 0;
325 int unsend_size = 0;
326 u8 *pdata;
314 327
315 if (dev->state & DEV_DISCONNECTED) 328 if (dev->state & DEV_DISCONNECTED)
316 return -ENODEV; 329 return -ENODEV;
@@ -340,13 +353,86 @@ int cx231xx_send_vendor_cmd(struct cx231xx *dev,
340 cx231xx_isocdbg("\n"); 353 cx231xx_isocdbg("\n");
341 } 354 }
342 355
343 mutex_lock(&dev->ctrl_urb_lock); 356
344 ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest, 357/*
345 ven_req-> 358If the cx23102 read more than 4 bytes with i2c bus,
346 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 359need chop to 4 byte per request
347 ven_req->wValue, ven_req->wIndex, ven_req->pBuff, 360*/
348 ven_req->wLength, HZ); 361 if ((ven_req->wLength > 4) && ((ven_req->bRequest == 0x4) ||
349 mutex_unlock(&dev->ctrl_urb_lock); 362 (ven_req->bRequest == 0x5) ||
363 (ven_req->bRequest == 0x6))) {
364 unsend_size = 0;
365 pdata = ven_req->pBuff;
366
367
368 unsend_size = ven_req->wLength;
369
370 mutex_lock(&dev->ctrl_urb_lock);
371 /* the first package*/
372 ven_req->wValue = ven_req->wValue & 0xFFFB;
373 ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x2;
374 /*printk(KERN_INFO " !!!!! 0x%x 0x%x 0x%x 0x%x \n",
375 ven_req->bRequest,
376 ven_req->direction | USB_TYPE_VENDOR |
377 USB_RECIP_DEVICE,ven_req->wValue,ven_req->wIndex);*/
378 ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest,
379 ven_req->
380 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
381 ven_req->wValue, ven_req->wIndex, pdata,
382 0x0004, HZ);
383 unsend_size = unsend_size - 4;
384 mutex_unlock(&dev->ctrl_urb_lock);
385
386 /* the middle package*/
387 ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x42;
388 while (unsend_size - 4 > 0) {
389 pdata = pdata + 4;
390 /*printk(KERN_INFO " !!!!! 0x%x 0x%x 0x%x 0x%x \n",
391 ven_req->bRequest,
392 ven_req->direction | USB_TYPE_VENDOR |
393 USB_RECIP_DEVICE,
394 ven_req->wValue,ven_req->wIndex);*/
395 mutex_lock(&dev->ctrl_urb_lock);
396 ret = usb_control_msg(dev->udev, pipe,
397 ven_req->bRequest,
398 ven_req->
399 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
400 ven_req->wValue, ven_req->wIndex, pdata,
401 0x0004, HZ);
402 mutex_unlock(&dev->ctrl_urb_lock);
403 unsend_size = unsend_size - 4;
404 }
405
406
407 /* the last package*/
408 ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x40;
409 pdata = pdata + 4;
410 /*printk(KERN_INFO " !!!!! 0x%x 0x%x 0x%x 0x%x \n",
411 ven_req->bRequest,
412 ven_req->direction | USB_TYPE_VENDOR |
413 USB_RECIP_DEVICE,ven_req->wValue,ven_req->wIndex);*/
414 mutex_lock(&dev->ctrl_urb_lock);
415 ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest,
416 ven_req->
417 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
418 ven_req->wValue, ven_req->wIndex, pdata,
419 unsend_size, HZ);
420 mutex_unlock(&dev->ctrl_urb_lock);
421 /*printk(KERN_INFO " @@@@@ temp_buffer[0]=0x%x 0x%x 0x%x 0x%x
422 0x%x 0x%x\n",ven_req->pBuff[0],ven_req->pBuff[1],
423 ven_req->pBuff[2], ven_req->pBuff[3],ven_req->pBuff[4],
424 ven_req->pBuff[5]);*/
425
426 } else {
427 mutex_lock(&dev->ctrl_urb_lock);
428 ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest,
429 ven_req->
430 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
431 ven_req->wValue, ven_req->wIndex,
432 ven_req->pBuff, ven_req->wLength, HZ);
433 mutex_unlock(&dev->ctrl_urb_lock);
434
435 }
350 436
351 return ret; 437 return ret;
352} 438}
@@ -444,6 +530,11 @@ int cx231xx_set_video_alternate(struct cx231xx *dev)
444 dev->video_mode.alt = 0; 530 dev->video_mode.alt = 0;
445 } 531 }
446 532
533 if (dev->USE_ISO == 0)
534 dev->video_mode.alt = 0;
535
536 cx231xx_info("dev->video_mode.alt= %d\n", dev->video_mode.alt);
537
447 /* Get the correct video interface Index */ 538 /* Get the correct video interface Index */
448 usb_interface_index = 539 usb_interface_index =
449 dev->current_pcb_config.hs_config_info[0].interface_info. 540 dev->current_pcb_config.hs_config_info[0].interface_info.
@@ -452,8 +543,10 @@ int cx231xx_set_video_alternate(struct cx231xx *dev)
452 if (dev->video_mode.alt != prev_alt) { 543 if (dev->video_mode.alt != prev_alt) {
453 cx231xx_coredbg("minimum isoc packet size: %u (alt=%d)\n", 544 cx231xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
454 min_pkt_size, dev->video_mode.alt); 545 min_pkt_size, dev->video_mode.alt);
455 dev->video_mode.max_pkt_size = 546
456 dev->video_mode.alt_max_pkt_size[dev->video_mode.alt]; 547 if (dev->video_mode.alt_max_pkt_size != NULL)
548 dev->video_mode.max_pkt_size =
549 dev->video_mode.alt_max_pkt_size[dev->video_mode.alt];
457 cx231xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n", 550 cx231xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
458 dev->video_mode.alt, 551 dev->video_mode.alt,
459 dev->video_mode.max_pkt_size); 552 dev->video_mode.max_pkt_size);
@@ -485,7 +578,7 @@ int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt)
485 usb_interface_index = 578 usb_interface_index =
486 dev->current_pcb_config.hs_config_info[0].interface_info. 579 dev->current_pcb_config.hs_config_info[0].interface_info.
487 ts1_index + 1; 580 ts1_index + 1;
488 dev->video_mode.alt = alt; 581 dev->ts1_mode.alt = alt;
489 if (dev->ts1_mode.alt_max_pkt_size != NULL) 582 if (dev->ts1_mode.alt_max_pkt_size != NULL)
490 max_pkt_size = dev->ts1_mode.max_pkt_size = 583 max_pkt_size = dev->ts1_mode.max_pkt_size =
491 dev->ts1_mode.alt_max_pkt_size[dev->ts1_mode.alt]; 584 dev->ts1_mode.alt_max_pkt_size[dev->ts1_mode.alt];
@@ -542,7 +635,10 @@ int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt)
542 cx231xx_errdev 635 cx231xx_errdev
543 ("can't change interface %d alt no. to %d: Max. Pkt size = 0\n", 636 ("can't change interface %d alt no. to %d: Max. Pkt size = 0\n",
544 usb_interface_index, alt); 637 usb_interface_index, alt);
545 return -1; 638 /*To workaround error number=-71 on EP0 for videograbber,
639 need add following codes.*/
640 if (dev->model != CX231XX_BOARD_CNXT_VIDEO_GRABBER)
641 return -1;
546 } 642 }
547 643
548 cx231xx_info 644 cx231xx_info
@@ -584,8 +680,53 @@ int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio)
584 return rc; 680 return rc;
585} 681}
586 682
683int cx231xx_demod_reset(struct cx231xx *dev)
684{
685
686 u8 status = 0;
687 u8 value[4] = { 0, 0, 0, 0 };
688
689 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
690 value, 4);
691 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
692 value[1], value[2], value[3]);
693
694 cx231xx_info("Enter cx231xx_demod_reset()\n");
695 value[1] = (u8) 0x3;
696 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
697 PWR_CTL_EN, value, 4);
698 msleep(10);
699
700 value[1] = (u8) 0x0;
701 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
702 PWR_CTL_EN, value, 4);
703 msleep(10);
704
705 value[1] = (u8) 0x3;
706 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
707 PWR_CTL_EN, value, 4);
708 msleep(10);
709
710
711
712 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
713 value, 4);
714 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
715 value[1], value[2], value[3]);
716
717 return status;
718}
719EXPORT_SYMBOL_GPL(cx231xx_demod_reset);
720int is_fw_load(struct cx231xx *dev)
721{
722 return cx231xx_check_fw(dev);
723}
724EXPORT_SYMBOL_GPL(is_fw_load);
725
587int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode) 726int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode)
588{ 727{
728 int errCode = 0;
729
589 if (dev->mode == set_mode) 730 if (dev->mode == set_mode)
590 return 0; 731 return 0;
591 732
@@ -600,15 +741,70 @@ int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode)
600 741
601 dev->mode = set_mode; 742 dev->mode = set_mode;
602 743
603 if (dev->mode == CX231XX_DIGITAL_MODE) 744 if (dev->mode == CX231XX_DIGITAL_MODE)/* Set Digital power mode */ {
604 ;/* Set Digital power mode */ 745 /* set AGC mode to Digital */
605 else 746 switch (dev->model) {
606 ;/* Set Analog Power mode */ 747 case CX231XX_BOARD_CNXT_CARRAERA:
748 case CX231XX_BOARD_CNXT_RDE_250:
749 case CX231XX_BOARD_CNXT_SHELBY:
750 case CX231XX_BOARD_CNXT_RDU_250:
751 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 0);
752 break;
753 case CX231XX_BOARD_CNXT_RDE_253S:
754 case CX231XX_BOARD_CNXT_RDU_253S:
755 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1);
756 break;
757 default:
758 break;
759 }
760 } else/* Set Analog Power mode */ {
761 /* set AGC mode to Analog */
762 switch (dev->model) {
763 case CX231XX_BOARD_CNXT_CARRAERA:
764 case CX231XX_BOARD_CNXT_RDE_250:
765 case CX231XX_BOARD_CNXT_SHELBY:
766 case CX231XX_BOARD_CNXT_RDU_250:
767 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1);
768 break;
769 case CX231XX_BOARD_CNXT_RDE_253S:
770 case CX231XX_BOARD_CNXT_RDU_253S:
771 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 0);
772 break;
773 default:
774 break;
775 }
776 }
607 777
608 return 0; 778 return 0;
609} 779}
610EXPORT_SYMBOL_GPL(cx231xx_set_mode); 780EXPORT_SYMBOL_GPL(cx231xx_set_mode);
611 781
782int cx231xx_ep5_bulkout(struct cx231xx *dev, u8 *firmware, u16 size)
783{
784 int errCode = 0;
785 int actlen, ret = -ENOMEM;
786 u32 *buffer;
787
788buffer = kzalloc(4096, GFP_KERNEL);
789 if (buffer == NULL) {
790 cx231xx_info("out of mem\n");
791 return -ENOMEM;
792 }
793 memcpy(&buffer[0], firmware, 4096);
794
795 ret = usb_bulk_msg(dev->udev, usb_sndbulkpipe(dev->udev, 5),
796 buffer, 4096, &actlen, 2000);
797
798 if (ret)
799 cx231xx_info("bulk message failed: %d (%d/%d)", ret,
800 size, actlen);
801 else {
802 errCode = actlen != size ? -1 : 0;
803 }
804kfree(buffer);
805 return 0;
806}
807
612/***************************************************************** 808/*****************************************************************
613* URB Streaming functions * 809* URB Streaming functions *
614******************************************************************/ 810******************************************************************/
@@ -616,7 +812,7 @@ EXPORT_SYMBOL_GPL(cx231xx_set_mode);
616/* 812/*
617 * IRQ callback, called by URB callback 813 * IRQ callback, called by URB callback
618 */ 814 */
619static void cx231xx_irq_callback(struct urb *urb) 815static void cx231xx_isoc_irq_callback(struct urb *urb)
620{ 816{
621 struct cx231xx_dmaqueue *dma_q = urb->context; 817 struct cx231xx_dmaqueue *dma_q = urb->context;
622 struct cx231xx_video_mode *vmode = 818 struct cx231xx_video_mode *vmode =
@@ -655,12 +851,54 @@ static void cx231xx_irq_callback(struct urb *urb)
655 urb->status); 851 urb->status);
656 } 852 }
657} 853}
854/*****************************************************************
855* URB Streaming functions *
856******************************************************************/
658 857
659/* 858/*
859 * IRQ callback, called by URB callback
860 */
861static void cx231xx_bulk_irq_callback(struct urb *urb)
862{
863 struct cx231xx_dmaqueue *dma_q = urb->context;
864 struct cx231xx_video_mode *vmode =
865 container_of(dma_q, struct cx231xx_video_mode, vidq);
866 struct cx231xx *dev = container_of(vmode, struct cx231xx, video_mode);
867 int rc;
868
869 switch (urb->status) {
870 case 0: /* success */
871 case -ETIMEDOUT: /* NAK */
872 break;
873 case -ECONNRESET: /* kill */
874 case -ENOENT:
875 case -ESHUTDOWN:
876 return;
877 default: /* error */
878 cx231xx_isocdbg("urb completition error %d.\n", urb->status);
879 break;
880 }
881
882 /* Copy data from URB */
883 spin_lock(&dev->video_mode.slock);
884 rc = dev->video_mode.bulk_ctl.bulk_copy(dev, urb);
885 spin_unlock(&dev->video_mode.slock);
886
887 /* Reset urb buffers */
888 urb->status = 0;
889
890 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
891 if (urb->status) {
892 cx231xx_isocdbg("urb resubmit failed (error=%i)\n",
893 urb->status);
894 }
895}
896/*
660 * Stop and Deallocate URBs 897 * Stop and Deallocate URBs
661 */ 898 */
662void cx231xx_uninit_isoc(struct cx231xx *dev) 899void cx231xx_uninit_isoc(struct cx231xx *dev)
663{ 900{
901 struct cx231xx_dmaqueue *dma_q = &dev->video_mode.vidq;
664 struct urb *urb; 902 struct urb *urb;
665 int i; 903 int i;
666 904
@@ -690,16 +928,71 @@ void cx231xx_uninit_isoc(struct cx231xx *dev)
690 928
691 kfree(dev->video_mode.isoc_ctl.urb); 929 kfree(dev->video_mode.isoc_ctl.urb);
692 kfree(dev->video_mode.isoc_ctl.transfer_buffer); 930 kfree(dev->video_mode.isoc_ctl.transfer_buffer);
931 kfree(dma_q->p_left_data);
693 932
694 dev->video_mode.isoc_ctl.urb = NULL; 933 dev->video_mode.isoc_ctl.urb = NULL;
695 dev->video_mode.isoc_ctl.transfer_buffer = NULL; 934 dev->video_mode.isoc_ctl.transfer_buffer = NULL;
696 dev->video_mode.isoc_ctl.num_bufs = 0; 935 dev->video_mode.isoc_ctl.num_bufs = 0;
936 dma_q->p_left_data = NULL;
937
938 if (dev->mode_tv == 0)
939 cx231xx_capture_start(dev, 0, Raw_Video);
940 else
941 cx231xx_capture_start(dev, 0, TS1_serial_mode);
942
697 943
698 cx231xx_capture_start(dev, 0, Raw_Video);
699} 944}
700EXPORT_SYMBOL_GPL(cx231xx_uninit_isoc); 945EXPORT_SYMBOL_GPL(cx231xx_uninit_isoc);
701 946
702/* 947/*
948 * Stop and Deallocate URBs
949 */
950void cx231xx_uninit_bulk(struct cx231xx *dev)
951{
952 struct urb *urb;
953 int i;
954
955 cx231xx_isocdbg("cx231xx: called cx231xx_uninit_bulk\n");
956
957 dev->video_mode.bulk_ctl.nfields = -1;
958 for (i = 0; i < dev->video_mode.bulk_ctl.num_bufs; i++) {
959 urb = dev->video_mode.bulk_ctl.urb[i];
960 if (urb) {
961 if (!irqs_disabled())
962 usb_kill_urb(urb);
963 else
964 usb_unlink_urb(urb);
965
966 if (dev->video_mode.bulk_ctl.transfer_buffer[i]) {
967 usb_free_coherent(dev->udev,
968 urb->transfer_buffer_length,
969 dev->video_mode.isoc_ctl.
970 transfer_buffer[i],
971 urb->transfer_dma);
972 }
973 usb_free_urb(urb);
974 dev->video_mode.bulk_ctl.urb[i] = NULL;
975 }
976 dev->video_mode.bulk_ctl.transfer_buffer[i] = NULL;
977 }
978
979 kfree(dev->video_mode.bulk_ctl.urb);
980 kfree(dev->video_mode.bulk_ctl.transfer_buffer);
981
982 dev->video_mode.bulk_ctl.urb = NULL;
983 dev->video_mode.bulk_ctl.transfer_buffer = NULL;
984 dev->video_mode.bulk_ctl.num_bufs = 0;
985
986 if (dev->mode_tv == 0)
987 cx231xx_capture_start(dev, 0, Raw_Video);
988 else
989 cx231xx_capture_start(dev, 0, TS1_serial_mode);
990
991
992}
993EXPORT_SYMBOL_GPL(cx231xx_uninit_bulk);
994
995/*
703 * Allocate URBs and start IRQ 996 * Allocate URBs and start IRQ
704 */ 997 */
705int cx231xx_init_isoc(struct cx231xx *dev, int max_packets, 998int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
@@ -713,8 +1006,6 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
713 int j, k; 1006 int j, k;
714 int rc; 1007 int rc;
715 1008
716 cx231xx_isocdbg("cx231xx: called cx231xx_prepare_isoc\n");
717
718 dev->video_input = dev->video_input > 2 ? 2 : dev->video_input; 1009 dev->video_input = dev->video_input > 2 ? 2 : dev->video_input;
719 1010
720 cx231xx_info("Setting Video mux to %d\n", dev->video_input); 1011 cx231xx_info("Setting Video mux to %d\n", dev->video_input);
@@ -723,6 +1014,14 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
723 /* De-allocates all pending stuff */ 1014 /* De-allocates all pending stuff */
724 cx231xx_uninit_isoc(dev); 1015 cx231xx_uninit_isoc(dev);
725 1016
1017 dma_q->p_left_data = kzalloc(4096, GFP_KERNEL);
1018 if (dma_q->p_left_data == NULL) {
1019 cx231xx_info("out of mem\n");
1020 return -ENOMEM;
1021 }
1022
1023
1024
726 dev->video_mode.isoc_ctl.isoc_copy = isoc_copy; 1025 dev->video_mode.isoc_ctl.isoc_copy = isoc_copy;
727 dev->video_mode.isoc_ctl.num_bufs = num_bufs; 1026 dev->video_mode.isoc_ctl.num_bufs = num_bufs;
728 dma_q->pos = 0; 1027 dma_q->pos = 0;
@@ -733,6 +1032,14 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
733 dma_q->lines_per_field = dev->height / 2; 1032 dma_q->lines_per_field = dev->height / 2;
734 dma_q->bytes_left_in_line = dev->width << 1; 1033 dma_q->bytes_left_in_line = dev->width << 1;
735 dma_q->lines_completed = 0; 1034 dma_q->lines_completed = 0;
1035 dma_q->mpeg_buffer_done = 0;
1036 dma_q->left_data_count = 0;
1037 dma_q->mpeg_buffer_completed = 0;
1038 dma_q->add_ps_package_head = CX231XX_NEED_ADD_PS_PACKAGE_HEAD;
1039 dma_q->ps_head[0] = 0x00;
1040 dma_q->ps_head[1] = 0x00;
1041 dma_q->ps_head[2] = 0x01;
1042 dma_q->ps_head[3] = 0xBA;
736 for (i = 0; i < 8; i++) 1043 for (i = 0; i < 8; i++)
737 dma_q->partial_buf[i] = 0; 1044 dma_q->partial_buf[i] = 0;
738 1045
@@ -756,6 +1063,12 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
756 1063
757 sb_size = max_packets * dev->video_mode.isoc_ctl.max_pkt_size; 1064 sb_size = max_packets * dev->video_mode.isoc_ctl.max_pkt_size;
758 1065
1066 if (dev->mode_tv == 1)
1067 dev->video_mode.end_point_addr = 0x81;
1068 else
1069 dev->video_mode.end_point_addr = 0x84;
1070
1071
759 /* allocate urbs and transfer buffers */ 1072 /* allocate urbs and transfer buffers */
760 for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) { 1073 for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) {
761 urb = usb_alloc_urb(max_packets, GFP_KERNEL); 1074 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
@@ -784,7 +1097,7 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
784 1097
785 usb_fill_int_urb(urb, dev->udev, pipe, 1098 usb_fill_int_urb(urb, dev->udev, pipe,
786 dev->video_mode.isoc_ctl.transfer_buffer[i], 1099 dev->video_mode.isoc_ctl.transfer_buffer[i],
787 sb_size, cx231xx_irq_callback, dma_q, 1); 1100 sb_size, cx231xx_isoc_irq_callback, dma_q, 1);
788 1101
789 urb->number_of_packets = max_packets; 1102 urb->number_of_packets = max_packets;
790 urb->transfer_flags = URB_ISO_ASAP; 1103 urb->transfer_flags = URB_ISO_ASAP;
@@ -812,12 +1125,175 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
812 } 1125 }
813 } 1126 }
814 1127
815 cx231xx_capture_start(dev, 1, Raw_Video); 1128 if (dev->mode_tv == 0)
1129 cx231xx_capture_start(dev, 1, Raw_Video);
1130 else
1131 cx231xx_capture_start(dev, 1, TS1_serial_mode);
816 1132
817 return 0; 1133 return 0;
818} 1134}
819EXPORT_SYMBOL_GPL(cx231xx_init_isoc); 1135EXPORT_SYMBOL_GPL(cx231xx_init_isoc);
820 1136
1137/*
1138 * Allocate URBs and start IRQ
1139 */
1140int cx231xx_init_bulk(struct cx231xx *dev, int max_packets,
1141 int num_bufs, int max_pkt_size,
1142 int (*bulk_copy) (struct cx231xx *dev, struct urb *urb))
1143{
1144 struct cx231xx_dmaqueue *dma_q = &dev->video_mode.vidq;
1145 int i;
1146 int sb_size, pipe;
1147 struct urb *urb;
1148 int rc;
1149
1150 dev->video_input = dev->video_input > 2 ? 2 : dev->video_input;
1151
1152 cx231xx_info("Setting Video mux to %d\n", dev->video_input);
1153 video_mux(dev, dev->video_input);
1154
1155 /* De-allocates all pending stuff */
1156 cx231xx_uninit_bulk(dev);
1157
1158 dev->video_mode.bulk_ctl.bulk_copy = bulk_copy;
1159 dev->video_mode.bulk_ctl.num_bufs = num_bufs;
1160 dma_q->pos = 0;
1161 dma_q->is_partial_line = 0;
1162 dma_q->last_sav = 0;
1163 dma_q->current_field = -1;
1164 dma_q->field1_done = 0;
1165 dma_q->lines_per_field = dev->height / 2;
1166 dma_q->bytes_left_in_line = dev->width << 1;
1167 dma_q->lines_completed = 0;
1168 dma_q->mpeg_buffer_done = 0;
1169 dma_q->left_data_count = 0;
1170 dma_q->mpeg_buffer_completed = 0;
1171 dma_q->ps_head[0] = 0x00;
1172 dma_q->ps_head[1] = 0x00;
1173 dma_q->ps_head[2] = 0x01;
1174 dma_q->ps_head[3] = 0xBA;
1175 for (i = 0; i < 8; i++)
1176 dma_q->partial_buf[i] = 0;
1177
1178 dev->video_mode.bulk_ctl.urb =
1179 kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
1180 if (!dev->video_mode.bulk_ctl.urb) {
1181 cx231xx_errdev("cannot alloc memory for usb buffers\n");
1182 return -ENOMEM;
1183 }
1184
1185 dev->video_mode.bulk_ctl.transfer_buffer =
1186 kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
1187 if (!dev->video_mode.bulk_ctl.transfer_buffer) {
1188 cx231xx_errdev("cannot allocate memory for usbtransfer\n");
1189 kfree(dev->video_mode.bulk_ctl.urb);
1190 return -ENOMEM;
1191 }
1192
1193 dev->video_mode.bulk_ctl.max_pkt_size = max_pkt_size;
1194 dev->video_mode.bulk_ctl.buf = NULL;
1195
1196 sb_size = max_packets * dev->video_mode.bulk_ctl.max_pkt_size;
1197
1198 if (dev->mode_tv == 1)
1199 dev->video_mode.end_point_addr = 0x81;
1200 else
1201 dev->video_mode.end_point_addr = 0x84;
1202
1203
1204 /* allocate urbs and transfer buffers */
1205 for (i = 0; i < dev->video_mode.bulk_ctl.num_bufs; i++) {
1206 urb = usb_alloc_urb(0, GFP_KERNEL);
1207 if (!urb) {
1208 cx231xx_err("cannot alloc bulk_ctl.urb %i\n", i);
1209 cx231xx_uninit_bulk(dev);
1210 return -ENOMEM;
1211 }
1212 dev->video_mode.bulk_ctl.urb[i] = urb;
1213 urb->transfer_flags = 0;
1214
1215 dev->video_mode.bulk_ctl.transfer_buffer[i] =
1216 usb_alloc_coherent(dev->udev, sb_size, GFP_KERNEL,
1217 &urb->transfer_dma);
1218 if (!dev->video_mode.bulk_ctl.transfer_buffer[i]) {
1219 cx231xx_err("unable to allocate %i bytes for transfer"
1220 " buffer %i%s\n",
1221 sb_size, i,
1222 in_interrupt() ? " while in int" : "");
1223 cx231xx_uninit_bulk(dev);
1224 return -ENOMEM;
1225 }
1226 memset(dev->video_mode.bulk_ctl.transfer_buffer[i], 0, sb_size);
1227
1228 pipe = usb_rcvbulkpipe(dev->udev,
1229 dev->video_mode.end_point_addr);
1230 usb_fill_bulk_urb(urb, dev->udev, pipe,
1231 dev->video_mode.bulk_ctl.transfer_buffer[i],
1232 sb_size, cx231xx_bulk_irq_callback, dma_q);
1233 }
1234
1235 init_waitqueue_head(&dma_q->wq);
1236
1237 /* submit urbs and enables IRQ */
1238 for (i = 0; i < dev->video_mode.bulk_ctl.num_bufs; i++) {
1239 rc = usb_submit_urb(dev->video_mode.bulk_ctl.urb[i],
1240 GFP_ATOMIC);
1241 if (rc) {
1242 cx231xx_err("submit of urb %i failed (error=%i)\n", i,
1243 rc);
1244 cx231xx_uninit_bulk(dev);
1245 return rc;
1246 }
1247 }
1248
1249 if (dev->mode_tv == 0)
1250 cx231xx_capture_start(dev, 1, Raw_Video);
1251 else
1252 cx231xx_capture_start(dev, 1, TS1_serial_mode);
1253
1254 return 0;
1255}
1256EXPORT_SYMBOL_GPL(cx231xx_init_bulk);
1257void cx231xx_stop_TS1(struct cx231xx *dev)
1258{
1259 int status = 0;
1260 u8 val[4] = { 0, 0, 0, 0 };
1261
1262 val[0] = 0x00;
1263 val[1] = 0x03;
1264 val[2] = 0x00;
1265 val[3] = 0x00;
1266 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1267 TS_MODE_REG, val, 4);
1268
1269 val[0] = 0x00;
1270 val[1] = 0x70;
1271 val[2] = 0x04;
1272 val[3] = 0x00;
1273 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1274 TS1_CFG_REG, val, 4);
1275}
1276/* EXPORT_SYMBOL_GPL(cx231xx_stop_TS1); */
1277void cx231xx_start_TS1(struct cx231xx *dev)
1278{
1279 int status = 0;
1280 u8 val[4] = { 0, 0, 0, 0 };
1281
1282 val[0] = 0x03;
1283 val[1] = 0x03;
1284 val[2] = 0x00;
1285 val[3] = 0x00;
1286 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1287 TS_MODE_REG, val, 4);
1288
1289 val[0] = 0x04;
1290 val[1] = 0xA3;
1291 val[2] = 0x3B;
1292 val[3] = 0x00;
1293 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1294 TS1_CFG_REG, val, 4);
1295}
1296/* EXPORT_SYMBOL_GPL(cx231xx_start_TS1); */
821/***************************************************************** 1297/*****************************************************************
822* Device Init/UnInit functions * 1298* Device Init/UnInit functions *
823******************************************************************/ 1299******************************************************************/
@@ -856,14 +1332,33 @@ int cx231xx_dev_init(struct cx231xx *dev)
856 /* init hardware */ 1332 /* init hardware */
857 /* Note : with out calling set power mode function, 1333 /* Note : with out calling set power mode function,
858 afe can not be set up correctly */ 1334 afe can not be set up correctly */
859 errCode = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); 1335 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
860 if (errCode < 0) { 1336 errCode = cx231xx_set_power_mode(dev,
861 cx231xx_errdev 1337 POLARIS_AVMODE_ENXTERNAL_AV);
862 ("%s: Failed to set Power - errCode [%d]!\n", 1338 if (errCode < 0) {
863 __func__, errCode); 1339 cx231xx_errdev
864 return errCode; 1340 ("%s: Failed to set Power - errCode [%d]!\n",
1341 __func__, errCode);
1342 return errCode;
1343 }
1344 } else {
1345 errCode = cx231xx_set_power_mode(dev,
1346 POLARIS_AVMODE_ANALOGT_TV);
1347 if (errCode < 0) {
1348 cx231xx_errdev
1349 ("%s: Failed to set Power - errCode [%d]!\n",
1350 __func__, errCode);
1351 return errCode;
1352 }
865 } 1353 }
866 1354
1355 /* reset the Tuner */
1356 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
1357 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1358 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
1359 (dev->model == CX231XX_BOARD_CNXT_RDU_250))
1360 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
1361
867 /* initialize Colibri block */ 1362 /* initialize Colibri block */
868 errCode = cx231xx_afe_init_super_block(dev, 0x23c); 1363 errCode = cx231xx_afe_init_super_block(dev, 0x23c);
869 if (errCode < 0) { 1364 if (errCode < 0) {
@@ -907,7 +1402,20 @@ int cx231xx_dev_init(struct cx231xx *dev)
907 } 1402 }
908 1403
909 /* set AGC mode to Analog */ 1404 /* set AGC mode to Analog */
1405 switch (dev->model) {
1406 case CX231XX_BOARD_CNXT_CARRAERA:
1407 case CX231XX_BOARD_CNXT_RDE_250:
1408 case CX231XX_BOARD_CNXT_SHELBY:
1409 case CX231XX_BOARD_CNXT_RDU_250:
910 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1); 1410 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1);
1411 break;
1412 case CX231XX_BOARD_CNXT_RDE_253S:
1413 case CX231XX_BOARD_CNXT_RDU_253S:
1414 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 0);
1415 break;
1416 default:
1417 break;
1418 }
911 if (errCode < 0) { 1419 if (errCode < 0) {
912 cx231xx_errdev 1420 cx231xx_errdev
913 ("%s: cx231xx_AGC mode to Analog - errCode [%d]!\n", 1421 ("%s: cx231xx_AGC mode to Analog - errCode [%d]!\n",
@@ -923,7 +1431,8 @@ int cx231xx_dev_init(struct cx231xx *dev)
923 cx231xx_set_alt_setting(dev, INDEX_TS1, 0); 1431 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
924 1432
925 /* set the I2C master port to 3 on channel 1 */ 1433 /* set the I2C master port to 3 on channel 1 */
926 errCode = cx231xx_enable_i2c_for_tuner(dev, I2C_3); 1434 if (dev->model != CX231XX_BOARD_CNXT_VIDEO_GRABBER)
1435 errCode = cx231xx_enable_i2c_for_tuner(dev, I2C_3);
927 1436
928 return errCode; 1437 return errCode;
929} 1438}
@@ -941,7 +1450,7 @@ EXPORT_SYMBOL_GPL(cx231xx_dev_uninit);
941/***************************************************************** 1450/*****************************************************************
942* G P I O related functions * 1451* G P I O related functions *
943******************************************************************/ 1452******************************************************************/
944int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val, 1453int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val,
945 u8 len, u8 request, u8 direction) 1454 u8 len, u8 request, u8 direction)
946{ 1455{
947 int status = 0; 1456 int status = 0;
@@ -1026,6 +1535,91 @@ int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode)
1026/***************************************************************** 1535/*****************************************************************
1027 * I 2 C Internal C O N T R O L functions * 1536 * I 2 C Internal C O N T R O L functions *
1028 *****************************************************************/ 1537 *****************************************************************/
1538int cx231xx_read_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
1539 u8 saddr_len, u32 *data, u8 data_len, int master)
1540{
1541 int status = 0;
1542 struct cx231xx_i2c_xfer_data req_data;
1543 u8 value[64] = "0";
1544
1545 if (saddr_len == 0)
1546 saddr = 0;
1547 else if (saddr_len == 0)
1548 saddr &= 0xff;
1549
1550 /* prepare xfer_data struct */
1551 req_data.dev_addr = dev_addr >> 1;
1552 req_data.direction = I2C_M_RD;
1553 req_data.saddr_len = saddr_len;
1554 req_data.saddr_dat = saddr;
1555 req_data.buf_size = data_len;
1556 req_data.p_buffer = (u8 *) value;
1557
1558 /* usb send command */
1559 if (master == 0)
1560 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0],
1561 &req_data);
1562 else if (master == 1)
1563 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[1],
1564 &req_data);
1565 else if (master == 2)
1566 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[2],
1567 &req_data);
1568
1569 if (status >= 0) {
1570 /* Copy the data read back to main buffer */
1571 if (data_len == 1)
1572 *data = value[0];
1573 else if (data_len == 4)
1574 *data =
1575 value[0] | value[1] << 8 | value[2] << 16 | value[3]
1576 << 24;
1577 else if (data_len > 4)
1578 *data = value[saddr];
1579 }
1580
1581 return status;
1582}
1583
1584int cx231xx_write_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
1585 u8 saddr_len, u32 data, u8 data_len, int master)
1586{
1587 int status = 0;
1588 u8 value[4] = { 0, 0, 0, 0 };
1589 struct cx231xx_i2c_xfer_data req_data;
1590
1591 value[0] = (u8) data;
1592 value[1] = (u8) (data >> 8);
1593 value[2] = (u8) (data >> 16);
1594 value[3] = (u8) (data >> 24);
1595
1596 if (saddr_len == 0)
1597 saddr = 0;
1598 else if (saddr_len == 0)
1599 saddr &= 0xff;
1600
1601 /* prepare xfer_data struct */
1602 req_data.dev_addr = dev_addr >> 1;
1603 req_data.direction = 0;
1604 req_data.saddr_len = saddr_len;
1605 req_data.saddr_dat = saddr;
1606 req_data.buf_size = data_len;
1607 req_data.p_buffer = value;
1608
1609 /* usb send command */
1610 if (master == 0)
1611 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0],
1612 &req_data);
1613 else if (master == 1)
1614 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[1],
1615 &req_data);
1616 else if (master == 2)
1617 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[2],
1618 &req_data);
1619
1620 return status;
1621}
1622
1029int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr, u16 saddr, 1623int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr, u16 saddr,
1030 u8 saddr_len, u32 *data, u8 data_len) 1624 u8 saddr_len, u32 *data, u8 data_len)
1031{ 1625{
diff --git a/drivers/media/video/cx231xx/cx231xx-dif.h b/drivers/media/video/cx231xx/cx231xx-dif.h
new file mode 100644
index 000000000000..8187afcb0145
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-dif.h
@@ -0,0 +1,3178 @@
1/*
2 cx231xx-dif.h - driver for Conexant Cx23100/101/102 USB video capture devices
3
4 Copyright {C} 2009 <Bill.Liu@conexant.com>
5
6 This program is free software, you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY, without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program, if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef _CX231XX_DIF_H
22#define _CX231XX_DIF_H
23
24#include "cx231xx-reg.h"
25
26struct dif_settings{
27 u32 if_freq;
28 u32 register_address;
29 u32 value;
30};
31
32static struct dif_settings Dif_set_array[] = {
33
34/*case 3000000:*/
35/* BEGIN - DIF BPF register values from 30_quant.dat*/
36{3000000, DIF_BPF_COEFF01, 0x00000002},
37{3000000, DIF_BPF_COEFF23, 0x00080012},
38{3000000, DIF_BPF_COEFF45, 0x001e0024},
39{3000000, DIF_BPF_COEFF67, 0x001bfff8},
40{3000000, DIF_BPF_COEFF89, 0xffb4ff50},
41{3000000, DIF_BPF_COEFF1011, 0xfed8fe68},
42{3000000, DIF_BPF_COEFF1213, 0xfe24fe34},
43{3000000, DIF_BPF_COEFF1415, 0xfebaffc7},
44{3000000, DIF_BPF_COEFF1617, 0x014d031f},
45{3000000, DIF_BPF_COEFF1819, 0x04f0065d},
46{3000000, DIF_BPF_COEFF2021, 0x07010688},
47{3000000, DIF_BPF_COEFF2223, 0x04c901d6},
48{3000000, DIF_BPF_COEFF2425, 0xfe00f9d3},
49{3000000, DIF_BPF_COEFF2627, 0xf600f342},
50{3000000, DIF_BPF_COEFF2829, 0xf235f337},
51{3000000, DIF_BPF_COEFF3031, 0xf64efb22},
52{3000000, DIF_BPF_COEFF3233, 0x0105070f},
53{3000000, DIF_BPF_COEFF3435, 0x0c460fce},
54{3000000, DIF_BPF_COEFF36, 0x110d0000},
55/* END - DIF BPF register values from 30_quant.dat*/
56
57
58/*case 3100000:*/
59/* BEGIN - DIF BPF register values from 31_quant.dat*/
60{3100000, DIF_BPF_COEFF01, 0x00000001},
61{3100000, DIF_BPF_COEFF23, 0x00070012},
62{3100000, DIF_BPF_COEFF45, 0x00220032},
63{3100000, DIF_BPF_COEFF67, 0x00370026},
64{3100000, DIF_BPF_COEFF89, 0xfff0ff91},
65{3100000, DIF_BPF_COEFF1011, 0xff0efe7c},
66{3100000, DIF_BPF_COEFF1213, 0xfe01fdcc},
67{3100000, DIF_BPF_COEFF1415, 0xfe0afedb},
68{3100000, DIF_BPF_COEFF1617, 0x00440224},
69{3100000, DIF_BPF_COEFF1819, 0x0434060c},
70{3100000, DIF_BPF_COEFF2021, 0x0738074e},
71{3100000, DIF_BPF_COEFF2223, 0x06090361},
72{3100000, DIF_BPF_COEFF2425, 0xff99fb39},
73{3100000, DIF_BPF_COEFF2627, 0xf6fef3b6},
74{3100000, DIF_BPF_COEFF2829, 0xf21af2a5},
75{3100000, DIF_BPF_COEFF3031, 0xf573fa33},
76{3100000, DIF_BPF_COEFF3233, 0x0034067d},
77{3100000, DIF_BPF_COEFF3435, 0x0bfb0fb9},
78{3100000, DIF_BPF_COEFF36, 0x110d0000},
79/* END - DIF BPF register values from 31_quant.dat*/
80
81
82/*case 3200000:*/
83/* BEGIN - DIF BPF register values from 32_quant.dat*/
84{3200000, DIF_BPF_COEFF01, 0x00000000},
85{3200000, DIF_BPF_COEFF23, 0x0004000e},
86{3200000, DIF_BPF_COEFF45, 0x00200038},
87{3200000, DIF_BPF_COEFF67, 0x004c004f},
88{3200000, DIF_BPF_COEFF89, 0x002fffdf},
89{3200000, DIF_BPF_COEFF1011, 0xff5cfeb6},
90{3200000, DIF_BPF_COEFF1213, 0xfe0dfd92},
91{3200000, DIF_BPF_COEFF1415, 0xfd7ffe03},
92{3200000, DIF_BPF_COEFF1617, 0xff36010a},
93{3200000, DIF_BPF_COEFF1819, 0x03410575},
94{3200000, DIF_BPF_COEFF2021, 0x072607d2},
95{3200000, DIF_BPF_COEFF2223, 0x071804d5},
96{3200000, DIF_BPF_COEFF2425, 0x0134fcb7},
97{3200000, DIF_BPF_COEFF2627, 0xf81ff451},
98{3200000, DIF_BPF_COEFF2829, 0xf223f22e},
99{3200000, DIF_BPF_COEFF3031, 0xf4a7f94b},
100{3200000, DIF_BPF_COEFF3233, 0xff6405e8},
101{3200000, DIF_BPF_COEFF3435, 0x0bae0fa4},
102{3200000, DIF_BPF_COEFF36, 0x110d0000},
103/* END - DIF BPF register values from 32_quant.dat*/
104
105
106/*case 3300000:*/
107/* BEGIN - DIF BPF register values from 33_quant.dat*/
108{3300000, DIF_BPF_COEFF01, 0x0000ffff},
109{3300000, DIF_BPF_COEFF23, 0x00000008},
110{3300000, DIF_BPF_COEFF45, 0x001a0036},
111{3300000, DIF_BPF_COEFF67, 0x0056006d},
112{3300000, DIF_BPF_COEFF89, 0x00670030},
113{3300000, DIF_BPF_COEFF1011, 0xffbdff10},
114{3300000, DIF_BPF_COEFF1213, 0xfe46fd8d},
115{3300000, DIF_BPF_COEFF1415, 0xfd25fd4f},
116{3300000, DIF_BPF_COEFF1617, 0xfe35ffe0},
117{3300000, DIF_BPF_COEFF1819, 0x0224049f},
118{3300000, DIF_BPF_COEFF2021, 0x06c9080e},
119{3300000, DIF_BPF_COEFF2223, 0x07ef0627},
120{3300000, DIF_BPF_COEFF2425, 0x02c9fe45},
121{3300000, DIF_BPF_COEFF2627, 0xf961f513},
122{3300000, DIF_BPF_COEFF2829, 0xf250f1d2},
123{3300000, DIF_BPF_COEFF3031, 0xf3ecf869},
124{3300000, DIF_BPF_COEFF3233, 0xfe930552},
125{3300000, DIF_BPF_COEFF3435, 0x0b5f0f8f},
126{3300000, DIF_BPF_COEFF36, 0x110d0000},
127/* END - DIF BPF register values from 33_quant.dat*/
128
129
130/*case 3400000:*/
131/* BEGIN - DIF BPF register values from 34_quant.dat*/
132{3400000, DIF_BPF_COEFF01, 0xfffffffe},
133{3400000, DIF_BPF_COEFF23, 0xfffd0001},
134{3400000, DIF_BPF_COEFF45, 0x000f002c},
135{3400000, DIF_BPF_COEFF67, 0x0054007d},
136{3400000, DIF_BPF_COEFF89, 0x0093007c},
137{3400000, DIF_BPF_COEFF1011, 0x0024ff82},
138{3400000, DIF_BPF_COEFF1213, 0xfea6fdbb},
139{3400000, DIF_BPF_COEFF1415, 0xfd03fcca},
140{3400000, DIF_BPF_COEFF1617, 0xfd51feb9},
141{3400000, DIF_BPF_COEFF1819, 0x00eb0392},
142{3400000, DIF_BPF_COEFF2021, 0x06270802},
143{3400000, DIF_BPF_COEFF2223, 0x08880750},
144{3400000, DIF_BPF_COEFF2425, 0x044dffdb},
145{3400000, DIF_BPF_COEFF2627, 0xfabdf5f8},
146{3400000, DIF_BPF_COEFF2829, 0xf2a0f193},
147{3400000, DIF_BPF_COEFF3031, 0xf342f78f},
148{3400000, DIF_BPF_COEFF3233, 0xfdc404b9},
149{3400000, DIF_BPF_COEFF3435, 0x0b0e0f78},
150{3400000, DIF_BPF_COEFF36, 0x110d0000},
151/* END - DIF BPF register values from 34_quant.dat*/
152
153
154/*case 3500000:*/
155/* BEGIN - DIF BPF register values from 35_quant.dat*/
156{3500000, DIF_BPF_COEFF01, 0xfffffffd},
157{3500000, DIF_BPF_COEFF23, 0xfffafff9},
158{3500000, DIF_BPF_COEFF45, 0x0002001b},
159{3500000, DIF_BPF_COEFF67, 0x0046007d},
160{3500000, DIF_BPF_COEFF89, 0x00ad00ba},
161{3500000, DIF_BPF_COEFF1011, 0x00870000},
162{3500000, DIF_BPF_COEFF1213, 0xff26fe1a},
163{3500000, DIF_BPF_COEFF1415, 0xfd1bfc7e},
164{3500000, DIF_BPF_COEFF1617, 0xfc99fda4},
165{3500000, DIF_BPF_COEFF1819, 0xffa5025c},
166{3500000, DIF_BPF_COEFF2021, 0x054507ad},
167{3500000, DIF_BPF_COEFF2223, 0x08dd0847},
168{3500000, DIF_BPF_COEFF2425, 0x05b80172},
169{3500000, DIF_BPF_COEFF2627, 0xfc2ef6ff},
170{3500000, DIF_BPF_COEFF2829, 0xf313f170},
171{3500000, DIF_BPF_COEFF3031, 0xf2abf6bd},
172{3500000, DIF_BPF_COEFF3233, 0xfcf6041f},
173{3500000, DIF_BPF_COEFF3435, 0x0abc0f61},
174{3500000, DIF_BPF_COEFF36, 0x110d0000},
175/* END - DIF BPF register values from 35_quant.dat*/
176
177
178/*case 3600000:*/
179/* BEGIN - DIF BPF register values from 36_quant.dat*/
180{3600000, DIF_BPF_COEFF01, 0xfffffffd},
181{3600000, DIF_BPF_COEFF23, 0xfff8fff3},
182{3600000, DIF_BPF_COEFF45, 0xfff50006},
183{3600000, DIF_BPF_COEFF67, 0x002f006c},
184{3600000, DIF_BPF_COEFF89, 0x00b200e3},
185{3600000, DIF_BPF_COEFF1011, 0x00dc007e},
186{3600000, DIF_BPF_COEFF1213, 0xffb9fea0},
187{3600000, DIF_BPF_COEFF1415, 0xfd6bfc71},
188{3600000, DIF_BPF_COEFF1617, 0xfc17fcb1},
189{3600000, DIF_BPF_COEFF1819, 0xfe65010b},
190{3600000, DIF_BPF_COEFF2021, 0x042d0713},
191{3600000, DIF_BPF_COEFF2223, 0x08ec0906},
192{3600000, DIF_BPF_COEFF2425, 0x07020302},
193{3600000, DIF_BPF_COEFF2627, 0xfdaff823},
194{3600000, DIF_BPF_COEFF2829, 0xf3a7f16a},
195{3600000, DIF_BPF_COEFF3031, 0xf228f5f5},
196{3600000, DIF_BPF_COEFF3233, 0xfc2a0384},
197{3600000, DIF_BPF_COEFF3435, 0x0a670f4a},
198{3600000, DIF_BPF_COEFF36, 0x110d0000},
199/* END - DIF BPF register values from 36_quant.dat*/
200
201
202/*case 3700000:*/
203/* BEGIN - DIF BPF register values from 37_quant.dat*/
204{3700000, DIF_BPF_COEFF01, 0x0000fffd},
205{3700000, DIF_BPF_COEFF23, 0xfff7ffef},
206{3700000, DIF_BPF_COEFF45, 0xffe9fff1},
207{3700000, DIF_BPF_COEFF67, 0x0010004d},
208{3700000, DIF_BPF_COEFF89, 0x00a100f2},
209{3700000, DIF_BPF_COEFF1011, 0x011a00f0},
210{3700000, DIF_BPF_COEFF1213, 0x0053ff44},
211{3700000, DIF_BPF_COEFF1415, 0xfdedfca2},
212{3700000, DIF_BPF_COEFF1617, 0xfbd3fbef},
213{3700000, DIF_BPF_COEFF1819, 0xfd39ffae},
214{3700000, DIF_BPF_COEFF2021, 0x02ea0638},
215{3700000, DIF_BPF_COEFF2223, 0x08b50987},
216{3700000, DIF_BPF_COEFF2425, 0x08230483},
217{3700000, DIF_BPF_COEFF2627, 0xff39f960},
218{3700000, DIF_BPF_COEFF2829, 0xf45bf180},
219{3700000, DIF_BPF_COEFF3031, 0xf1b8f537},
220{3700000, DIF_BPF_COEFF3233, 0xfb6102e7},
221{3700000, DIF_BPF_COEFF3435, 0x0a110f32},
222{3700000, DIF_BPF_COEFF36, 0x110d0000},
223/* END - DIF BPF register values from 37_quant.dat*/
224
225
226/*case 3800000:*/
227/* BEGIN - DIF BPF register values from 38_quant.dat*/
228{3800000, DIF_BPF_COEFF01, 0x0000fffe},
229{3800000, DIF_BPF_COEFF23, 0xfff9ffee},
230{3800000, DIF_BPF_COEFF45, 0xffe1ffdd},
231{3800000, DIF_BPF_COEFF67, 0xfff00024},
232{3800000, DIF_BPF_COEFF89, 0x007c00e5},
233{3800000, DIF_BPF_COEFF1011, 0x013a014a},
234{3800000, DIF_BPF_COEFF1213, 0x00e6fff8},
235{3800000, DIF_BPF_COEFF1415, 0xfe98fd0f},
236{3800000, DIF_BPF_COEFF1617, 0xfbd3fb67},
237{3800000, DIF_BPF_COEFF1819, 0xfc32fe54},
238{3800000, DIF_BPF_COEFF2021, 0x01880525},
239{3800000, DIF_BPF_COEFF2223, 0x083909c7},
240{3800000, DIF_BPF_COEFF2425, 0x091505ee},
241{3800000, DIF_BPF_COEFF2627, 0x00c7fab3},
242{3800000, DIF_BPF_COEFF2829, 0xf52df1b4},
243{3800000, DIF_BPF_COEFF3031, 0xf15df484},
244{3800000, DIF_BPF_COEFF3233, 0xfa9b0249},
245{3800000, DIF_BPF_COEFF3435, 0x09ba0f19},
246{3800000, DIF_BPF_COEFF36, 0x110d0000},
247/* END - DIF BPF register values from 38_quant.dat*/
248
249
250/*case 3900000:*/
251/* BEGIN - DIF BPF register values from 39_quant.dat*/
252{3900000, DIF_BPF_COEFF01, 0x00000000},
253{3900000, DIF_BPF_COEFF23, 0xfffbfff0},
254{3900000, DIF_BPF_COEFF45, 0xffdeffcf},
255{3900000, DIF_BPF_COEFF67, 0xffd1fff6},
256{3900000, DIF_BPF_COEFF89, 0x004800be},
257{3900000, DIF_BPF_COEFF1011, 0x01390184},
258{3900000, DIF_BPF_COEFF1213, 0x016300ac},
259{3900000, DIF_BPF_COEFF1415, 0xff5efdb1},
260{3900000, DIF_BPF_COEFF1617, 0xfc17fb23},
261{3900000, DIF_BPF_COEFF1819, 0xfb5cfd0d},
262{3900000, DIF_BPF_COEFF2021, 0x001703e4},
263{3900000, DIF_BPF_COEFF2223, 0x077b09c4},
264{3900000, DIF_BPF_COEFF2425, 0x09d2073c},
265{3900000, DIF_BPF_COEFF2627, 0x0251fc18},
266{3900000, DIF_BPF_COEFF2829, 0xf61cf203},
267{3900000, DIF_BPF_COEFF3031, 0xf118f3dc},
268{3900000, DIF_BPF_COEFF3233, 0xf9d801aa},
269{3900000, DIF_BPF_COEFF3435, 0x09600eff},
270{3900000, DIF_BPF_COEFF36, 0x110d0000},
271/* END - DIF BPF register values from 39_quant.dat*/
272
273
274/*case 4000000:*/
275/* BEGIN - DIF BPF register values from 40_quant.dat*/
276{4000000, DIF_BPF_COEFF01, 0x00000001},
277{4000000, DIF_BPF_COEFF23, 0xfffefff4},
278{4000000, DIF_BPF_COEFF45, 0xffe1ffc8},
279{4000000, DIF_BPF_COEFF67, 0xffbaffca},
280{4000000, DIF_BPF_COEFF89, 0x000b0082},
281{4000000, DIF_BPF_COEFF1011, 0x01170198},
282{4000000, DIF_BPF_COEFF1213, 0x01c10152},
283{4000000, DIF_BPF_COEFF1415, 0x0030fe7b},
284{4000000, DIF_BPF_COEFF1617, 0xfc99fb24},
285{4000000, DIF_BPF_COEFF1819, 0xfac3fbe9},
286{4000000, DIF_BPF_COEFF2021, 0xfea5027f},
287{4000000, DIF_BPF_COEFF2223, 0x0683097f},
288{4000000, DIF_BPF_COEFF2425, 0x0a560867},
289{4000000, DIF_BPF_COEFF2627, 0x03d2fd89},
290{4000000, DIF_BPF_COEFF2829, 0xf723f26f},
291{4000000, DIF_BPF_COEFF3031, 0xf0e8f341},
292{4000000, DIF_BPF_COEFF3233, 0xf919010a},
293{4000000, DIF_BPF_COEFF3435, 0x09060ee5},
294{4000000, DIF_BPF_COEFF36, 0x110d0000},
295/* END - DIF BPF register values from 40_quant.dat*/
296
297
298/*case 4100000:*/
299/* BEGIN - DIF BPF register values from 41_quant.dat*/
300{4100000, DIF_BPF_COEFF01, 0x00010002},
301{4100000, DIF_BPF_COEFF23, 0x0002fffb},
302{4100000, DIF_BPF_COEFF45, 0xffe8ffca},
303{4100000, DIF_BPF_COEFF67, 0xffacffa4},
304{4100000, DIF_BPF_COEFF89, 0xffcd0036},
305{4100000, DIF_BPF_COEFF1011, 0x00d70184},
306{4100000, DIF_BPF_COEFF1213, 0x01f601dc},
307{4100000, DIF_BPF_COEFF1415, 0x00ffff60},
308{4100000, DIF_BPF_COEFF1617, 0xfd51fb6d},
309{4100000, DIF_BPF_COEFF1819, 0xfa6efaf5},
310{4100000, DIF_BPF_COEFF2021, 0xfd410103},
311{4100000, DIF_BPF_COEFF2223, 0x055708f9},
312{4100000, DIF_BPF_COEFF2425, 0x0a9e0969},
313{4100000, DIF_BPF_COEFF2627, 0x0543ff02},
314{4100000, DIF_BPF_COEFF2829, 0xf842f2f5},
315{4100000, DIF_BPF_COEFF3031, 0xf0cef2b2},
316{4100000, DIF_BPF_COEFF3233, 0xf85e006b},
317{4100000, DIF_BPF_COEFF3435, 0x08aa0ecb},
318{4100000, DIF_BPF_COEFF36, 0x110d0000},
319/* END - DIF BPF register values from 41_quant.dat*/
320
321
322/*case 4200000:*/
323/* BEGIN - DIF BPF register values from 42_quant.dat*/
324{4200000, DIF_BPF_COEFF01, 0x00010003},
325{4200000, DIF_BPF_COEFF23, 0x00050003},
326{4200000, DIF_BPF_COEFF45, 0xfff3ffd3},
327{4200000, DIF_BPF_COEFF67, 0xffaaff8b},
328{4200000, DIF_BPF_COEFF89, 0xff95ffe5},
329{4200000, DIF_BPF_COEFF1011, 0x0080014a},
330{4200000, DIF_BPF_COEFF1213, 0x01fe023f},
331{4200000, DIF_BPF_COEFF1415, 0x01ba0050},
332{4200000, DIF_BPF_COEFF1617, 0xfe35fbf8},
333{4200000, DIF_BPF_COEFF1819, 0xfa62fa3b},
334{4200000, DIF_BPF_COEFF2021, 0xfbf9ff7e},
335{4200000, DIF_BPF_COEFF2223, 0x04010836},
336{4200000, DIF_BPF_COEFF2425, 0x0aa90a3d},
337{4200000, DIF_BPF_COEFF2627, 0x069f007f},
338{4200000, DIF_BPF_COEFF2829, 0xf975f395},
339{4200000, DIF_BPF_COEFF3031, 0xf0cbf231},
340{4200000, DIF_BPF_COEFF3233, 0xf7a9ffcb},
341{4200000, DIF_BPF_COEFF3435, 0x084c0eaf},
342{4200000, DIF_BPF_COEFF36, 0x110d0000},
343/* END - DIF BPF register values from 42_quant.dat*/
344
345
346/*case 4300000:*/
347/* BEGIN - DIF BPF register values from 43_quant.dat*/
348{4300000, DIF_BPF_COEFF01, 0x00010003},
349{4300000, DIF_BPF_COEFF23, 0x0008000a},
350{4300000, DIF_BPF_COEFF45, 0x0000ffe4},
351{4300000, DIF_BPF_COEFF67, 0xffb4ff81},
352{4300000, DIF_BPF_COEFF89, 0xff6aff96},
353{4300000, DIF_BPF_COEFF1011, 0x001c00f0},
354{4300000, DIF_BPF_COEFF1213, 0x01d70271},
355{4300000, DIF_BPF_COEFF1415, 0x0254013b},
356{4300000, DIF_BPF_COEFF1617, 0xff36fcbd},
357{4300000, DIF_BPF_COEFF1819, 0xfa9ff9c5},
358{4300000, DIF_BPF_COEFF2021, 0xfadbfdfe},
359{4300000, DIF_BPF_COEFF2223, 0x028c073b},
360{4300000, DIF_BPF_COEFF2425, 0x0a750adf},
361{4300000, DIF_BPF_COEFF2627, 0x07e101fa},
362{4300000, DIF_BPF_COEFF2829, 0xfab8f44e},
363{4300000, DIF_BPF_COEFF3031, 0xf0ddf1be},
364{4300000, DIF_BPF_COEFF3233, 0xf6f9ff2b},
365{4300000, DIF_BPF_COEFF3435, 0x07ed0e94},
366{4300000, DIF_BPF_COEFF36, 0x110d0000},
367/* END - DIF BPF register values from 43_quant.dat*/
368
369
370/*case 4400000:*/
371/* BEGIN - DIF BPF register values from 44_quant.dat*/
372{4400000, DIF_BPF_COEFF01, 0x00000003},
373{4400000, DIF_BPF_COEFF23, 0x0009000f},
374{4400000, DIF_BPF_COEFF45, 0x000efff8},
375{4400000, DIF_BPF_COEFF67, 0xffc9ff87},
376{4400000, DIF_BPF_COEFF89, 0xff52ff54},
377{4400000, DIF_BPF_COEFF1011, 0xffb5007e},
378{4400000, DIF_BPF_COEFF1213, 0x01860270},
379{4400000, DIF_BPF_COEFF1415, 0x02c00210},
380{4400000, DIF_BPF_COEFF1617, 0x0044fdb2},
381{4400000, DIF_BPF_COEFF1819, 0xfb22f997},
382{4400000, DIF_BPF_COEFF2021, 0xf9f2fc90},
383{4400000, DIF_BPF_COEFF2223, 0x0102060f},
384{4400000, DIF_BPF_COEFF2425, 0x0a050b4c},
385{4400000, DIF_BPF_COEFF2627, 0x0902036e},
386{4400000, DIF_BPF_COEFF2829, 0xfc0af51e},
387{4400000, DIF_BPF_COEFF3031, 0xf106f15a},
388{4400000, DIF_BPF_COEFF3233, 0xf64efe8b},
389{4400000, DIF_BPF_COEFF3435, 0x078d0e77},
390{4400000, DIF_BPF_COEFF36, 0x110d0000},
391/* END - DIF BPF register values from 44_quant.dat*/
392
393
394/*case 4500000:*/
395/* BEGIN - DIF BPF register values from 45_quant.dat*/
396{4500000, DIF_BPF_COEFF01, 0x00000002},
397{4500000, DIF_BPF_COEFF23, 0x00080012},
398{4500000, DIF_BPF_COEFF45, 0x0019000e},
399{4500000, DIF_BPF_COEFF67, 0xffe5ff9e},
400{4500000, DIF_BPF_COEFF89, 0xff4fff25},
401{4500000, DIF_BPF_COEFF1011, 0xff560000},
402{4500000, DIF_BPF_COEFF1213, 0x0112023b},
403{4500000, DIF_BPF_COEFF1415, 0x02f702c0},
404{4500000, DIF_BPF_COEFF1617, 0x014dfec8},
405{4500000, DIF_BPF_COEFF1819, 0xfbe5f9b3},
406{4500000, DIF_BPF_COEFF2021, 0xf947fb41},
407{4500000, DIF_BPF_COEFF2223, 0xff7004b9},
408{4500000, DIF_BPF_COEFF2425, 0x095a0b81},
409{4500000, DIF_BPF_COEFF2627, 0x0a0004d8},
410{4500000, DIF_BPF_COEFF2829, 0xfd65f603},
411{4500000, DIF_BPF_COEFF3031, 0xf144f104},
412{4500000, DIF_BPF_COEFF3233, 0xf5aafdec},
413{4500000, DIF_BPF_COEFF3435, 0x072b0e5a},
414{4500000, DIF_BPF_COEFF36, 0x110d0000},
415/* END - DIF BPF register values from 45_quant.dat*/
416
417
418/*case 4600000:*/
419/* BEGIN - DIF BPF register values from 46_quant.dat*/
420{4600000, DIF_BPF_COEFF01, 0x00000001},
421{4600000, DIF_BPF_COEFF23, 0x00060012},
422{4600000, DIF_BPF_COEFF45, 0x00200022},
423{4600000, DIF_BPF_COEFF67, 0x0005ffc1},
424{4600000, DIF_BPF_COEFF89, 0xff61ff10},
425{4600000, DIF_BPF_COEFF1011, 0xff09ff82},
426{4600000, DIF_BPF_COEFF1213, 0x008601d7},
427{4600000, DIF_BPF_COEFF1415, 0x02f50340},
428{4600000, DIF_BPF_COEFF1617, 0x0241fff0},
429{4600000, DIF_BPF_COEFF1819, 0xfcddfa19},
430{4600000, DIF_BPF_COEFF2021, 0xf8e2fa1e},
431{4600000, DIF_BPF_COEFF2223, 0xfde30343},
432{4600000, DIF_BPF_COEFF2425, 0x08790b7f},
433{4600000, DIF_BPF_COEFF2627, 0x0ad50631},
434{4600000, DIF_BPF_COEFF2829, 0xfec7f6fc},
435{4600000, DIF_BPF_COEFF3031, 0xf198f0bd},
436{4600000, DIF_BPF_COEFF3233, 0xf50dfd4e},
437{4600000, DIF_BPF_COEFF3435, 0x06c90e3d},
438{4600000, DIF_BPF_COEFF36, 0x110d0000},
439/* END - DIF BPF register values from 46_quant.dat*/
440
441
442/*case 4700000:*/
443/* BEGIN - DIF BPF register values from 47_quant.dat*/
444{4700000, DIF_BPF_COEFF01, 0x0000ffff},
445{4700000, DIF_BPF_COEFF23, 0x0003000f},
446{4700000, DIF_BPF_COEFF45, 0x00220030},
447{4700000, DIF_BPF_COEFF67, 0x0025ffed},
448{4700000, DIF_BPF_COEFF89, 0xff87ff15},
449{4700000, DIF_BPF_COEFF1011, 0xfed6ff10},
450{4700000, DIF_BPF_COEFF1213, 0xffed014c},
451{4700000, DIF_BPF_COEFF1415, 0x02b90386},
452{4700000, DIF_BPF_COEFF1617, 0x03110119},
453{4700000, DIF_BPF_COEFF1819, 0xfdfefac4},
454{4700000, DIF_BPF_COEFF2021, 0xf8c6f92f},
455{4700000, DIF_BPF_COEFF2223, 0xfc6701b7},
456{4700000, DIF_BPF_COEFF2425, 0x07670b44},
457{4700000, DIF_BPF_COEFF2627, 0x0b7e0776},
458{4700000, DIF_BPF_COEFF2829, 0x002df807},
459{4700000, DIF_BPF_COEFF3031, 0xf200f086},
460{4700000, DIF_BPF_COEFF3233, 0xf477fcb1},
461{4700000, DIF_BPF_COEFF3435, 0x06650e1e},
462{4700000, DIF_BPF_COEFF36, 0x110d0000},
463/* END - DIF BPF register values from 47_quant.dat*/
464
465
466/*case 4800000:*/
467/* BEGIN - DIF BPF register values from 48_quant.dat*/
468{4800000, DIF_BPF_COEFF01, 0xfffffffe},
469{4800000, DIF_BPF_COEFF23, 0xffff0009},
470{4800000, DIF_BPF_COEFF45, 0x001e0038},
471{4800000, DIF_BPF_COEFF67, 0x003f001b},
472{4800000, DIF_BPF_COEFF89, 0xffbcff36},
473{4800000, DIF_BPF_COEFF1011, 0xfec2feb6},
474{4800000, DIF_BPF_COEFF1213, 0xff5600a5},
475{4800000, DIF_BPF_COEFF1415, 0x0248038d},
476{4800000, DIF_BPF_COEFF1617, 0x03b00232},
477{4800000, DIF_BPF_COEFF1819, 0xff39fbab},
478{4800000, DIF_BPF_COEFF2021, 0xf8f4f87f},
479{4800000, DIF_BPF_COEFF2223, 0xfb060020},
480{4800000, DIF_BPF_COEFF2425, 0x062a0ad2},
481{4800000, DIF_BPF_COEFF2627, 0x0bf908a3},
482{4800000, DIF_BPF_COEFF2829, 0x0192f922},
483{4800000, DIF_BPF_COEFF3031, 0xf27df05e},
484{4800000, DIF_BPF_COEFF3233, 0xf3e8fc14},
485{4800000, DIF_BPF_COEFF3435, 0x06000e00},
486{4800000, DIF_BPF_COEFF36, 0x110d0000},
487/* END - DIF BPF register values from 48_quant.dat*/
488
489
490/*case 4900000:*/
491/* BEGIN - DIF BPF register values from 49_quant.dat*/
492{4900000, DIF_BPF_COEFF01, 0xfffffffd},
493{4900000, DIF_BPF_COEFF23, 0xfffc0002},
494{4900000, DIF_BPF_COEFF45, 0x00160037},
495{4900000, DIF_BPF_COEFF67, 0x00510046},
496{4900000, DIF_BPF_COEFF89, 0xfff9ff6d},
497{4900000, DIF_BPF_COEFF1011, 0xfed0fe7c},
498{4900000, DIF_BPF_COEFF1213, 0xfecefff0},
499{4900000, DIF_BPF_COEFF1415, 0x01aa0356},
500{4900000, DIF_BPF_COEFF1617, 0x0413032b},
501{4900000, DIF_BPF_COEFF1819, 0x007ffcc5},
502{4900000, DIF_BPF_COEFF2021, 0xf96cf812},
503{4900000, DIF_BPF_COEFF2223, 0xf9cefe87},
504{4900000, DIF_BPF_COEFF2425, 0x04c90a2c},
505{4900000, DIF_BPF_COEFF2627, 0x0c4309b4},
506{4900000, DIF_BPF_COEFF2829, 0x02f3fa4a},
507{4900000, DIF_BPF_COEFF3031, 0xf30ef046},
508{4900000, DIF_BPF_COEFF3233, 0xf361fb7a},
509{4900000, DIF_BPF_COEFF3435, 0x059b0de0},
510{4900000, DIF_BPF_COEFF36, 0x110d0000},
511/* END - DIF BPF register values from 49_quant.dat*/
512
513
514/*case 5000000:*/
515/* BEGIN - DIF BPF register values from 50_quant.dat*/
516{5000000, DIF_BPF_COEFF01, 0xfffffffd},
517{5000000, DIF_BPF_COEFF23, 0xfff9fffa},
518{5000000, DIF_BPF_COEFF45, 0x000a002d},
519{5000000, DIF_BPF_COEFF67, 0x00570067},
520{5000000, DIF_BPF_COEFF89, 0x0037ffb5},
521{5000000, DIF_BPF_COEFF1011, 0xfefffe68},
522{5000000, DIF_BPF_COEFF1213, 0xfe62ff3d},
523{5000000, DIF_BPF_COEFF1415, 0x00ec02e3},
524{5000000, DIF_BPF_COEFF1617, 0x043503f6},
525{5000000, DIF_BPF_COEFF1819, 0x01befe05},
526{5000000, DIF_BPF_COEFF2021, 0xfa27f7ee},
527{5000000, DIF_BPF_COEFF2223, 0xf8c6fcf8},
528{5000000, DIF_BPF_COEFF2425, 0x034c0954},
529{5000000, DIF_BPF_COEFF2627, 0x0c5c0aa4},
530{5000000, DIF_BPF_COEFF2829, 0x044cfb7e},
531{5000000, DIF_BPF_COEFF3031, 0xf3b1f03f},
532{5000000, DIF_BPF_COEFF3233, 0xf2e2fae1},
533{5000000, DIF_BPF_COEFF3435, 0x05340dc0},
534{5000000, DIF_BPF_COEFF36, 0x110d0000},
535/* END - DIF BPF register values from 50_quant.dat*/
536
537
538/*case 5100000:*/
539/* BEGIN - DIF BPF register values from 51_quant.dat*/
540{5100000, DIF_BPF_COEFF01, 0x0000fffd},
541{5100000, DIF_BPF_COEFF23, 0xfff8fff4},
542{5100000, DIF_BPF_COEFF45, 0xfffd001e},
543{5100000, DIF_BPF_COEFF67, 0x0051007b},
544{5100000, DIF_BPF_COEFF89, 0x006e0006},
545{5100000, DIF_BPF_COEFF1011, 0xff48fe7c},
546{5100000, DIF_BPF_COEFF1213, 0xfe1bfe9a},
547{5100000, DIF_BPF_COEFF1415, 0x001d023e},
548{5100000, DIF_BPF_COEFF1617, 0x04130488},
549{5100000, DIF_BPF_COEFF1819, 0x02e6ff5b},
550{5100000, DIF_BPF_COEFF2021, 0xfb1ef812},
551{5100000, DIF_BPF_COEFF2223, 0xf7f7fb7f},
552{5100000, DIF_BPF_COEFF2425, 0x01bc084e},
553{5100000, DIF_BPF_COEFF2627, 0x0c430b72},
554{5100000, DIF_BPF_COEFF2829, 0x059afcba},
555{5100000, DIF_BPF_COEFF3031, 0xf467f046},
556{5100000, DIF_BPF_COEFF3233, 0xf26cfa4a},
557{5100000, DIF_BPF_COEFF3435, 0x04cd0da0},
558{5100000, DIF_BPF_COEFF36, 0x110d0000},
559/* END - DIF BPF register values from 51_quant.dat*/
560
561
562/*case 5200000:*/
563/* BEGIN - DIF BPF register values from 52_quant.dat*/
564{5200000, DIF_BPF_COEFF01, 0x0000fffe},
565{5200000, DIF_BPF_COEFF23, 0xfff8ffef},
566{5200000, DIF_BPF_COEFF45, 0xfff00009},
567{5200000, DIF_BPF_COEFF67, 0x003f007f},
568{5200000, DIF_BPF_COEFF89, 0x00980056},
569{5200000, DIF_BPF_COEFF1011, 0xffa5feb6},
570{5200000, DIF_BPF_COEFF1213, 0xfe00fe15},
571{5200000, DIF_BPF_COEFF1415, 0xff4b0170},
572{5200000, DIF_BPF_COEFF1617, 0x03b004d7},
573{5200000, DIF_BPF_COEFF1819, 0x03e800b9},
574{5200000, DIF_BPF_COEFF2021, 0xfc48f87f},
575{5200000, DIF_BPF_COEFF2223, 0xf768fa23},
576{5200000, DIF_BPF_COEFF2425, 0x0022071f},
577{5200000, DIF_BPF_COEFF2627, 0x0bf90c1b},
578{5200000, DIF_BPF_COEFF2829, 0x06dafdfd},
579{5200000, DIF_BPF_COEFF3031, 0xf52df05e},
580{5200000, DIF_BPF_COEFF3233, 0xf1fef9b5},
581{5200000, DIF_BPF_COEFF3435, 0x04640d7f},
582{5200000, DIF_BPF_COEFF36, 0x110d0000},
583/* END - DIF BPF register values from 52_quant.dat*/
584
585
586/*case 5300000:*/
587/* BEGIN - DIF BPF register values from 53_quant.dat*/
588{5300000, DIF_BPF_COEFF01, 0x0000ffff},
589{5300000, DIF_BPF_COEFF23, 0xfff9ffee},
590{5300000, DIF_BPF_COEFF45, 0xffe6fff3},
591{5300000, DIF_BPF_COEFF67, 0x00250072},
592{5300000, DIF_BPF_COEFF89, 0x00af009c},
593{5300000, DIF_BPF_COEFF1011, 0x000cff10},
594{5300000, DIF_BPF_COEFF1213, 0xfe13fdb8},
595{5300000, DIF_BPF_COEFF1415, 0xfe870089},
596{5300000, DIF_BPF_COEFF1617, 0x031104e1},
597{5300000, DIF_BPF_COEFF1819, 0x04b8020f},
598{5300000, DIF_BPF_COEFF2021, 0xfd98f92f},
599{5300000, DIF_BPF_COEFF2223, 0xf71df8f0},
600{5300000, DIF_BPF_COEFF2425, 0xfe8805ce},
601{5300000, DIF_BPF_COEFF2627, 0x0b7e0c9c},
602{5300000, DIF_BPF_COEFF2829, 0x0808ff44},
603{5300000, DIF_BPF_COEFF3031, 0xf603f086},
604{5300000, DIF_BPF_COEFF3233, 0xf19af922},
605{5300000, DIF_BPF_COEFF3435, 0x03fb0d5e},
606{5300000, DIF_BPF_COEFF36, 0x110d0000},
607/* END - DIF BPF register values from 53_quant.dat*/
608
609
610/*case 5400000:*/
611/* BEGIN - DIF BPF register values from 54_quant.dat*/
612{5400000, DIF_BPF_COEFF01, 0x00000001},
613{5400000, DIF_BPF_COEFF23, 0xfffcffef},
614{5400000, DIF_BPF_COEFF45, 0xffe0ffe0},
615{5400000, DIF_BPF_COEFF67, 0x00050056},
616{5400000, DIF_BPF_COEFF89, 0x00b000d1},
617{5400000, DIF_BPF_COEFF1011, 0x0071ff82},
618{5400000, DIF_BPF_COEFF1213, 0xfe53fd8c},
619{5400000, DIF_BPF_COEFF1415, 0xfddfff99},
620{5400000, DIF_BPF_COEFF1617, 0x024104a3},
621{5400000, DIF_BPF_COEFF1819, 0x054a034d},
622{5400000, DIF_BPF_COEFF2021, 0xff01fa1e},
623{5400000, DIF_BPF_COEFF2223, 0xf717f7ed},
624{5400000, DIF_BPF_COEFF2425, 0xfcf50461},
625{5400000, DIF_BPF_COEFF2627, 0x0ad50cf4},
626{5400000, DIF_BPF_COEFF2829, 0x0921008d},
627{5400000, DIF_BPF_COEFF3031, 0xf6e7f0bd},
628{5400000, DIF_BPF_COEFF3233, 0xf13ff891},
629{5400000, DIF_BPF_COEFF3435, 0x03920d3b},
630{5400000, DIF_BPF_COEFF36, 0x110d0000},
631/* END - DIF BPF register values from 54_quant.dat*/
632
633
634/*case 5500000:*/
635/* BEGIN - DIF BPF register values from 55_quant.dat*/
636{5500000, DIF_BPF_COEFF01, 0x00010002},
637{5500000, DIF_BPF_COEFF23, 0xfffffff3},
638{5500000, DIF_BPF_COEFF45, 0xffdeffd1},
639{5500000, DIF_BPF_COEFF67, 0xffe5002f},
640{5500000, DIF_BPF_COEFF89, 0x009c00ed},
641{5500000, DIF_BPF_COEFF1011, 0x00cb0000},
642{5500000, DIF_BPF_COEFF1213, 0xfebafd94},
643{5500000, DIF_BPF_COEFF1415, 0xfd61feb0},
644{5500000, DIF_BPF_COEFF1617, 0x014d0422},
645{5500000, DIF_BPF_COEFF1819, 0x05970464},
646{5500000, DIF_BPF_COEFF2021, 0x0074fb41},
647{5500000, DIF_BPF_COEFF2223, 0xf759f721},
648{5500000, DIF_BPF_COEFF2425, 0xfb7502de},
649{5500000, DIF_BPF_COEFF2627, 0x0a000d21},
650{5500000, DIF_BPF_COEFF2829, 0x0a2201d4},
651{5500000, DIF_BPF_COEFF3031, 0xf7d9f104},
652{5500000, DIF_BPF_COEFF3233, 0xf0edf804},
653{5500000, DIF_BPF_COEFF3435, 0x03280d19},
654{5500000, DIF_BPF_COEFF36, 0x110d0000},
655/* END - DIF BPF register values from 55_quant.dat*/
656
657
658/*case 5600000:*/
659/* BEGIN - DIF BPF register values from 56_quant.dat*/
660{5600000, DIF_BPF_COEFF01, 0x00010003},
661{5600000, DIF_BPF_COEFF23, 0x0003fffa},
662{5600000, DIF_BPF_COEFF45, 0xffe3ffc9},
663{5600000, DIF_BPF_COEFF67, 0xffc90002},
664{5600000, DIF_BPF_COEFF89, 0x007500ef},
665{5600000, DIF_BPF_COEFF1011, 0x010e007e},
666{5600000, DIF_BPF_COEFF1213, 0xff3dfdcf},
667{5600000, DIF_BPF_COEFF1415, 0xfd16fddd},
668{5600000, DIF_BPF_COEFF1617, 0x00440365},
669{5600000, DIF_BPF_COEFF1819, 0x059b0548},
670{5600000, DIF_BPF_COEFF2021, 0x01e3fc90},
671{5600000, DIF_BPF_COEFF2223, 0xf7dff691},
672{5600000, DIF_BPF_COEFF2425, 0xfa0f014d},
673{5600000, DIF_BPF_COEFF2627, 0x09020d23},
674{5600000, DIF_BPF_COEFF2829, 0x0b0a0318},
675{5600000, DIF_BPF_COEFF3031, 0xf8d7f15a},
676{5600000, DIF_BPF_COEFF3233, 0xf0a5f779},
677{5600000, DIF_BPF_COEFF3435, 0x02bd0cf6},
678{5600000, DIF_BPF_COEFF36, 0x110d0000},
679/* END - DIF BPF register values from 56_quant.dat*/
680
681
682/*case 5700000:*/
683/* BEGIN - DIF BPF register values from 57_quant.dat*/
684{5700000, DIF_BPF_COEFF01, 0x00010003},
685{5700000, DIF_BPF_COEFF23, 0x00060001},
686{5700000, DIF_BPF_COEFF45, 0xffecffc9},
687{5700000, DIF_BPF_COEFF67, 0xffb4ffd4},
688{5700000, DIF_BPF_COEFF89, 0x004000d5},
689{5700000, DIF_BPF_COEFF1011, 0x013600f0},
690{5700000, DIF_BPF_COEFF1213, 0xffd3fe39},
691{5700000, DIF_BPF_COEFF1415, 0xfd04fd31},
692{5700000, DIF_BPF_COEFF1617, 0xff360277},
693{5700000, DIF_BPF_COEFF1819, 0x055605ef},
694{5700000, DIF_BPF_COEFF2021, 0x033efdfe},
695{5700000, DIF_BPF_COEFF2223, 0xf8a5f642},
696{5700000, DIF_BPF_COEFF2425, 0xf8cbffb6},
697{5700000, DIF_BPF_COEFF2627, 0x07e10cfb},
698{5700000, DIF_BPF_COEFF2829, 0x0bd50456},
699{5700000, DIF_BPF_COEFF3031, 0xf9dff1be},
700{5700000, DIF_BPF_COEFF3233, 0xf067f6f2},
701{5700000, DIF_BPF_COEFF3435, 0x02520cd2},
702{5700000, DIF_BPF_COEFF36, 0x110d0000},
703/* END - DIF BPF register values from 57_quant.dat*/
704
705
706/*case 5800000:*/
707/* BEGIN - DIF BPF register values from 58_quant.dat*/
708{5800000, DIF_BPF_COEFF01, 0x00000003},
709{5800000, DIF_BPF_COEFF23, 0x00080009},
710{5800000, DIF_BPF_COEFF45, 0xfff8ffd2},
711{5800000, DIF_BPF_COEFF67, 0xffaaffac},
712{5800000, DIF_BPF_COEFF89, 0x000200a3},
713{5800000, DIF_BPF_COEFF1011, 0x013c014a},
714{5800000, DIF_BPF_COEFF1213, 0x006dfec9},
715{5800000, DIF_BPF_COEFF1415, 0xfd2bfcb7},
716{5800000, DIF_BPF_COEFF1617, 0xfe350165},
717{5800000, DIF_BPF_COEFF1819, 0x04cb0651},
718{5800000, DIF_BPF_COEFF2021, 0x0477ff7e},
719{5800000, DIF_BPF_COEFF2223, 0xf9a5f635},
720{5800000, DIF_BPF_COEFF2425, 0xf7b1fe20},
721{5800000, DIF_BPF_COEFF2627, 0x069f0ca8},
722{5800000, DIF_BPF_COEFF2829, 0x0c81058b},
723{5800000, DIF_BPF_COEFF3031, 0xfaf0f231},
724{5800000, DIF_BPF_COEFF3233, 0xf033f66d},
725{5800000, DIF_BPF_COEFF3435, 0x01e60cae},
726{5800000, DIF_BPF_COEFF36, 0x110d0000},
727/* END - DIF BPF register values from 58_quant.dat*/
728
729
730/*case 5900000:*/
731/* BEGIN - DIF BPF register values from 59_quant.dat*/
732{5900000, DIF_BPF_COEFF01, 0x00000002},
733{5900000, DIF_BPF_COEFF23, 0x0009000e},
734{5900000, DIF_BPF_COEFF45, 0x0005ffe1},
735{5900000, DIF_BPF_COEFF67, 0xffacff90},
736{5900000, DIF_BPF_COEFF89, 0xffc5005f},
737{5900000, DIF_BPF_COEFF1011, 0x01210184},
738{5900000, DIF_BPF_COEFF1213, 0x00fcff72},
739{5900000, DIF_BPF_COEFF1415, 0xfd8afc77},
740{5900000, DIF_BPF_COEFF1617, 0xfd51003f},
741{5900000, DIF_BPF_COEFF1819, 0x04020669},
742{5900000, DIF_BPF_COEFF2021, 0x05830103},
743{5900000, DIF_BPF_COEFF2223, 0xfad7f66b},
744{5900000, DIF_BPF_COEFF2425, 0xf6c8fc93},
745{5900000, DIF_BPF_COEFF2627, 0x05430c2b},
746{5900000, DIF_BPF_COEFF2829, 0x0d0d06b5},
747{5900000, DIF_BPF_COEFF3031, 0xfc08f2b2},
748{5900000, DIF_BPF_COEFF3233, 0xf00af5ec},
749{5900000, DIF_BPF_COEFF3435, 0x017b0c89},
750{5900000, DIF_BPF_COEFF36, 0x110d0000},
751/* END - DIF BPF register values from 59_quant.dat*/
752
753
754/*case 6000000:*/
755/* BEGIN - DIF BPF register values from 60_quant.dat*/
756{6000000, DIF_BPF_COEFF01, 0x00000001},
757{6000000, DIF_BPF_COEFF23, 0x00070012},
758{6000000, DIF_BPF_COEFF45, 0x0012fff5},
759{6000000, DIF_BPF_COEFF67, 0xffbaff82},
760{6000000, DIF_BPF_COEFF89, 0xff8e000f},
761{6000000, DIF_BPF_COEFF1011, 0x00e80198},
762{6000000, DIF_BPF_COEFF1213, 0x01750028},
763{6000000, DIF_BPF_COEFF1415, 0xfe18fc75},
764{6000000, DIF_BPF_COEFF1617, 0xfc99ff15},
765{6000000, DIF_BPF_COEFF1819, 0x03050636},
766{6000000, DIF_BPF_COEFF2021, 0x0656027f},
767{6000000, DIF_BPF_COEFF2223, 0xfc32f6e2},
768{6000000, DIF_BPF_COEFF2425, 0xf614fb17},
769{6000000, DIF_BPF_COEFF2627, 0x03d20b87},
770{6000000, DIF_BPF_COEFF2829, 0x0d7707d2},
771{6000000, DIF_BPF_COEFF3031, 0xfd26f341},
772{6000000, DIF_BPF_COEFF3233, 0xefeaf56f},
773{6000000, DIF_BPF_COEFF3435, 0x010f0c64},
774{6000000, DIF_BPF_COEFF36, 0x110d0000},
775/* END - DIF BPF register values from 60_quant.dat*/
776
777
778/*case 6100000:*/
779/* BEGIN - DIF BPF register values from 61_quant.dat*/
780{6100000, DIF_BPF_COEFF01, 0xffff0000},
781{6100000, DIF_BPF_COEFF23, 0x00050012},
782{6100000, DIF_BPF_COEFF45, 0x001c000b},
783{6100000, DIF_BPF_COEFF67, 0xffd1ff84},
784{6100000, DIF_BPF_COEFF89, 0xff66ffbe},
785{6100000, DIF_BPF_COEFF1011, 0x00960184},
786{6100000, DIF_BPF_COEFF1213, 0x01cd00da},
787{6100000, DIF_BPF_COEFF1415, 0xfeccfcb2},
788{6100000, DIF_BPF_COEFF1617, 0xfc17fdf9},
789{6100000, DIF_BPF_COEFF1819, 0x01e005bc},
790{6100000, DIF_BPF_COEFF2021, 0x06e703e4},
791{6100000, DIF_BPF_COEFF2223, 0xfdabf798},
792{6100000, DIF_BPF_COEFF2425, 0xf599f9b3},
793{6100000, DIF_BPF_COEFF2627, 0x02510abd},
794{6100000, DIF_BPF_COEFF2829, 0x0dbf08df},
795{6100000, DIF_BPF_COEFF3031, 0xfe48f3dc},
796{6100000, DIF_BPF_COEFF3233, 0xefd5f4f6},
797{6100000, DIF_BPF_COEFF3435, 0x00a20c3e},
798{6100000, DIF_BPF_COEFF36, 0x110d0000},
799/* END - DIF BPF register values from 61_quant.dat*/
800
801
802/*case 6200000:*/
803/* BEGIN - DIF BPF register values from 62_quant.dat*/
804{6200000, DIF_BPF_COEFF01, 0xfffffffe},
805{6200000, DIF_BPF_COEFF23, 0x0002000f},
806{6200000, DIF_BPF_COEFF45, 0x0021001f},
807{6200000, DIF_BPF_COEFF67, 0xfff0ff97},
808{6200000, DIF_BPF_COEFF89, 0xff50ff74},
809{6200000, DIF_BPF_COEFF1011, 0x0034014a},
810{6200000, DIF_BPF_COEFF1213, 0x01fa0179},
811{6200000, DIF_BPF_COEFF1415, 0xff97fd2a},
812{6200000, DIF_BPF_COEFF1617, 0xfbd3fcfa},
813{6200000, DIF_BPF_COEFF1819, 0x00a304fe},
814{6200000, DIF_BPF_COEFF2021, 0x07310525},
815{6200000, DIF_BPF_COEFF2223, 0xff37f886},
816{6200000, DIF_BPF_COEFF2425, 0xf55cf86e},
817{6200000, DIF_BPF_COEFF2627, 0x00c709d0},
818{6200000, DIF_BPF_COEFF2829, 0x0de209db},
819{6200000, DIF_BPF_COEFF3031, 0xff6df484},
820{6200000, DIF_BPF_COEFF3233, 0xefcbf481},
821{6200000, DIF_BPF_COEFF3435, 0x00360c18},
822{6200000, DIF_BPF_COEFF36, 0x110d0000},
823/* END - DIF BPF register values from 62_quant.dat*/
824
825
826/*case 6300000:*/
827/* BEGIN - DIF BPF register values from 63_quant.dat*/
828{6300000, DIF_BPF_COEFF01, 0xfffffffd},
829{6300000, DIF_BPF_COEFF23, 0xfffe000a},
830{6300000, DIF_BPF_COEFF45, 0x0021002f},
831{6300000, DIF_BPF_COEFF67, 0x0010ffb8},
832{6300000, DIF_BPF_COEFF89, 0xff50ff3b},
833{6300000, DIF_BPF_COEFF1011, 0xffcc00f0},
834{6300000, DIF_BPF_COEFF1213, 0x01fa01fa},
835{6300000, DIF_BPF_COEFF1415, 0x0069fdd4},
836{6300000, DIF_BPF_COEFF1617, 0xfbd3fc26},
837{6300000, DIF_BPF_COEFF1819, 0xff5d0407},
838{6300000, DIF_BPF_COEFF2021, 0x07310638},
839{6300000, DIF_BPF_COEFF2223, 0x00c9f9a8},
840{6300000, DIF_BPF_COEFF2425, 0xf55cf74e},
841{6300000, DIF_BPF_COEFF2627, 0xff3908c3},
842{6300000, DIF_BPF_COEFF2829, 0x0de20ac3},
843{6300000, DIF_BPF_COEFF3031, 0x0093f537},
844{6300000, DIF_BPF_COEFF3233, 0xefcbf410},
845{6300000, DIF_BPF_COEFF3435, 0xffca0bf2},
846{6300000, DIF_BPF_COEFF36, 0x110d0000},
847/* END - DIF BPF register values from 63_quant.dat*/
848
849
850/*case 6400000:*/
851/* BEGIN - DIF BPF register values from 64_quant.dat*/
852{6400000, DIF_BPF_COEFF01, 0xfffffffd},
853{6400000, DIF_BPF_COEFF23, 0xfffb0003},
854{6400000, DIF_BPF_COEFF45, 0x001c0037},
855{6400000, DIF_BPF_COEFF67, 0x002fffe2},
856{6400000, DIF_BPF_COEFF89, 0xff66ff17},
857{6400000, DIF_BPF_COEFF1011, 0xff6a007e},
858{6400000, DIF_BPF_COEFF1213, 0x01cd0251},
859{6400000, DIF_BPF_COEFF1415, 0x0134fea5},
860{6400000, DIF_BPF_COEFF1617, 0xfc17fb8b},
861{6400000, DIF_BPF_COEFF1819, 0xfe2002e0},
862{6400000, DIF_BPF_COEFF2021, 0x06e70713},
863{6400000, DIF_BPF_COEFF2223, 0x0255faf5},
864{6400000, DIF_BPF_COEFF2425, 0xf599f658},
865{6400000, DIF_BPF_COEFF2627, 0xfdaf0799},
866{6400000, DIF_BPF_COEFF2829, 0x0dbf0b96},
867{6400000, DIF_BPF_COEFF3031, 0x01b8f5f5},
868{6400000, DIF_BPF_COEFF3233, 0xefd5f3a3},
869{6400000, DIF_BPF_COEFF3435, 0xff5e0bca},
870{6400000, DIF_BPF_COEFF36, 0x110d0000},
871/* END - DIF BPF register values from 64_quant.dat*/
872
873
874/*case 6500000:*/
875/* BEGIN - DIF BPF register values from 65_quant.dat*/
876{6500000, DIF_BPF_COEFF01, 0x0000fffd},
877{6500000, DIF_BPF_COEFF23, 0xfff9fffb},
878{6500000, DIF_BPF_COEFF45, 0x00120037},
879{6500000, DIF_BPF_COEFF67, 0x00460010},
880{6500000, DIF_BPF_COEFF89, 0xff8eff0f},
881{6500000, DIF_BPF_COEFF1011, 0xff180000},
882{6500000, DIF_BPF_COEFF1213, 0x01750276},
883{6500000, DIF_BPF_COEFF1415, 0x01e8ff8d},
884{6500000, DIF_BPF_COEFF1617, 0xfc99fb31},
885{6500000, DIF_BPF_COEFF1819, 0xfcfb0198},
886{6500000, DIF_BPF_COEFF2021, 0x065607ad},
887{6500000, DIF_BPF_COEFF2223, 0x03cefc64},
888{6500000, DIF_BPF_COEFF2425, 0xf614f592},
889{6500000, DIF_BPF_COEFF2627, 0xfc2e0656},
890{6500000, DIF_BPF_COEFF2829, 0x0d770c52},
891{6500000, DIF_BPF_COEFF3031, 0x02daf6bd},
892{6500000, DIF_BPF_COEFF3233, 0xefeaf33b},
893{6500000, DIF_BPF_COEFF3435, 0xfef10ba3},
894{6500000, DIF_BPF_COEFF36, 0x110d0000},
895/* END - DIF BPF register values from 65_quant.dat*/
896
897
898/*case 6600000:*/
899/* BEGIN - DIF BPF register values from 66_quant.dat*/
900{6600000, DIF_BPF_COEFF01, 0x0000fffe},
901{6600000, DIF_BPF_COEFF23, 0xfff7fff5},
902{6600000, DIF_BPF_COEFF45, 0x0005002f},
903{6600000, DIF_BPF_COEFF67, 0x0054003c},
904{6600000, DIF_BPF_COEFF89, 0xffc5ff22},
905{6600000, DIF_BPF_COEFF1011, 0xfedfff82},
906{6600000, DIF_BPF_COEFF1213, 0x00fc0267},
907{6600000, DIF_BPF_COEFF1415, 0x0276007e},
908{6600000, DIF_BPF_COEFF1617, 0xfd51fb1c},
909{6600000, DIF_BPF_COEFF1819, 0xfbfe003e},
910{6600000, DIF_BPF_COEFF2021, 0x05830802},
911{6600000, DIF_BPF_COEFF2223, 0x0529fdec},
912{6600000, DIF_BPF_COEFF2425, 0xf6c8f4fe},
913{6600000, DIF_BPF_COEFF2627, 0xfabd04ff},
914{6600000, DIF_BPF_COEFF2829, 0x0d0d0cf6},
915{6600000, DIF_BPF_COEFF3031, 0x03f8f78f},
916{6600000, DIF_BPF_COEFF3233, 0xf00af2d7},
917{6600000, DIF_BPF_COEFF3435, 0xfe850b7b},
918{6600000, DIF_BPF_COEFF36, 0x110d0000},
919/* END - DIF BPF register values from 66_quant.dat*/
920
921
922/*case 6700000:*/
923/* BEGIN - DIF BPF register values from 67_quant.dat*/
924{6700000, DIF_BPF_COEFF01, 0x0000ffff},
925{6700000, DIF_BPF_COEFF23, 0xfff8fff0},
926{6700000, DIF_BPF_COEFF45, 0xfff80020},
927{6700000, DIF_BPF_COEFF67, 0x00560060},
928{6700000, DIF_BPF_COEFF89, 0x0002ff4e},
929{6700000, DIF_BPF_COEFF1011, 0xfec4ff10},
930{6700000, DIF_BPF_COEFF1213, 0x006d0225},
931{6700000, DIF_BPF_COEFF1415, 0x02d50166},
932{6700000, DIF_BPF_COEFF1617, 0xfe35fb4e},
933{6700000, DIF_BPF_COEFF1819, 0xfb35fee1},
934{6700000, DIF_BPF_COEFF2021, 0x0477080e},
935{6700000, DIF_BPF_COEFF2223, 0x065bff82},
936{6700000, DIF_BPF_COEFF2425, 0xf7b1f4a0},
937{6700000, DIF_BPF_COEFF2627, 0xf9610397},
938{6700000, DIF_BPF_COEFF2829, 0x0c810d80},
939{6700000, DIF_BPF_COEFF3031, 0x0510f869},
940{6700000, DIF_BPF_COEFF3233, 0xf033f278},
941{6700000, DIF_BPF_COEFF3435, 0xfe1a0b52},
942{6700000, DIF_BPF_COEFF36, 0x110d0000},
943/* END - DIF BPF register values from 67_quant.dat*/
944
945
946/*case 6800000:*/
947/* BEGIN - DIF BPF register values from 68_quant.dat*/
948{6800000, DIF_BPF_COEFF01, 0x00010000},
949{6800000, DIF_BPF_COEFF23, 0xfffaffee},
950{6800000, DIF_BPF_COEFF45, 0xffec000c},
951{6800000, DIF_BPF_COEFF67, 0x004c0078},
952{6800000, DIF_BPF_COEFF89, 0x0040ff8e},
953{6800000, DIF_BPF_COEFF1011, 0xfecafeb6},
954{6800000, DIF_BPF_COEFF1213, 0xffd301b6},
955{6800000, DIF_BPF_COEFF1415, 0x02fc0235},
956{6800000, DIF_BPF_COEFF1617, 0xff36fbc5},
957{6800000, DIF_BPF_COEFF1819, 0xfaaafd90},
958{6800000, DIF_BPF_COEFF2021, 0x033e07d2},
959{6800000, DIF_BPF_COEFF2223, 0x075b011b},
960{6800000, DIF_BPF_COEFF2425, 0xf8cbf47a},
961{6800000, DIF_BPF_COEFF2627, 0xf81f0224},
962{6800000, DIF_BPF_COEFF2829, 0x0bd50def},
963{6800000, DIF_BPF_COEFF3031, 0x0621f94b},
964{6800000, DIF_BPF_COEFF3233, 0xf067f21e},
965{6800000, DIF_BPF_COEFF3435, 0xfdae0b29},
966{6800000, DIF_BPF_COEFF36, 0x110d0000},
967/* END - DIF BPF register values from 68_quant.dat*/
968
969
970/*case 6900000:*/
971/* BEGIN - DIF BPF register values from 69_quant.dat*/
972{6900000, DIF_BPF_COEFF01, 0x00010001},
973{6900000, DIF_BPF_COEFF23, 0xfffdffef},
974{6900000, DIF_BPF_COEFF45, 0xffe3fff6},
975{6900000, DIF_BPF_COEFF67, 0x0037007f},
976{6900000, DIF_BPF_COEFF89, 0x0075ffdc},
977{6900000, DIF_BPF_COEFF1011, 0xfef2fe7c},
978{6900000, DIF_BPF_COEFF1213, 0xff3d0122},
979{6900000, DIF_BPF_COEFF1415, 0x02ea02dd},
980{6900000, DIF_BPF_COEFF1617, 0x0044fc79},
981{6900000, DIF_BPF_COEFF1819, 0xfa65fc5d},
982{6900000, DIF_BPF_COEFF2021, 0x01e3074e},
983{6900000, DIF_BPF_COEFF2223, 0x082102ad},
984{6900000, DIF_BPF_COEFF2425, 0xfa0ff48c},
985{6900000, DIF_BPF_COEFF2627, 0xf6fe00a9},
986{6900000, DIF_BPF_COEFF2829, 0x0b0a0e43},
987{6900000, DIF_BPF_COEFF3031, 0x0729fa33},
988{6900000, DIF_BPF_COEFF3233, 0xf0a5f1c9},
989{6900000, DIF_BPF_COEFF3435, 0xfd430b00},
990{6900000, DIF_BPF_COEFF36, 0x110d0000},
991/* END - DIF BPF register values from 69_quant.dat*/
992
993
994/*case 7000000:*/
995/* BEGIN - DIF BPF register values from 70_quant.dat*/
996{7000000, DIF_BPF_COEFF01, 0x00010002},
997{7000000, DIF_BPF_COEFF23, 0x0001fff3},
998{7000000, DIF_BPF_COEFF45, 0xffdeffe2},
999{7000000, DIF_BPF_COEFF67, 0x001b0076},
1000{7000000, DIF_BPF_COEFF89, 0x009c002d},
1001{7000000, DIF_BPF_COEFF1011, 0xff35fe68},
1002{7000000, DIF_BPF_COEFF1213, 0xfeba0076},
1003{7000000, DIF_BPF_COEFF1415, 0x029f0352},
1004{7000000, DIF_BPF_COEFF1617, 0x014dfd60},
1005{7000000, DIF_BPF_COEFF1819, 0xfa69fb53},
1006{7000000, DIF_BPF_COEFF2021, 0x00740688},
1007{7000000, DIF_BPF_COEFF2223, 0x08a7042d},
1008{7000000, DIF_BPF_COEFF2425, 0xfb75f4d6},
1009{7000000, DIF_BPF_COEFF2627, 0xf600ff2d},
1010{7000000, DIF_BPF_COEFF2829, 0x0a220e7a},
1011{7000000, DIF_BPF_COEFF3031, 0x0827fb22},
1012{7000000, DIF_BPF_COEFF3233, 0xf0edf17a},
1013{7000000, DIF_BPF_COEFF3435, 0xfcd80ad6},
1014{7000000, DIF_BPF_COEFF36, 0x110d0000},
1015/* END - DIF BPF register values from 70_quant.dat*/
1016
1017
1018/*case 7100000:*/
1019/* BEGIN - DIF BPF register values from 71_quant.dat*/
1020{7100000, DIF_BPF_COEFF01, 0x00000003},
1021{7100000, DIF_BPF_COEFF23, 0x0004fff9},
1022{7100000, DIF_BPF_COEFF45, 0xffe0ffd2},
1023{7100000, DIF_BPF_COEFF67, 0xfffb005e},
1024{7100000, DIF_BPF_COEFF89, 0x00b0007a},
1025{7100000, DIF_BPF_COEFF1011, 0xff8ffe7c},
1026{7100000, DIF_BPF_COEFF1213, 0xfe53ffc1},
1027{7100000, DIF_BPF_COEFF1415, 0x0221038c},
1028{7100000, DIF_BPF_COEFF1617, 0x0241fe6e},
1029{7100000, DIF_BPF_COEFF1819, 0xfab6fa80},
1030{7100000, DIF_BPF_COEFF2021, 0xff010587},
1031{7100000, DIF_BPF_COEFF2223, 0x08e90590},
1032{7100000, DIF_BPF_COEFF2425, 0xfcf5f556},
1033{7100000, DIF_BPF_COEFF2627, 0xf52bfdb3},
1034{7100000, DIF_BPF_COEFF2829, 0x09210e95},
1035{7100000, DIF_BPF_COEFF3031, 0x0919fc15},
1036{7100000, DIF_BPF_COEFF3233, 0xf13ff12f},
1037{7100000, DIF_BPF_COEFF3435, 0xfc6e0aab},
1038{7100000, DIF_BPF_COEFF36, 0x110d0000},
1039/* END - DIF BPF register values from 71_quant.dat*/
1040
1041
1042/*case 7200000:*/
1043/* BEGIN - DIF BPF register values from 72_quant.dat*/
1044{7200000, DIF_BPF_COEFF01, 0x00000003},
1045{7200000, DIF_BPF_COEFF23, 0x00070000},
1046{7200000, DIF_BPF_COEFF45, 0xffe6ffc9},
1047{7200000, DIF_BPF_COEFF67, 0xffdb0039},
1048{7200000, DIF_BPF_COEFF89, 0x00af00b8},
1049{7200000, DIF_BPF_COEFF1011, 0xfff4feb6},
1050{7200000, DIF_BPF_COEFF1213, 0xfe13ff10},
1051{7200000, DIF_BPF_COEFF1415, 0x01790388},
1052{7200000, DIF_BPF_COEFF1617, 0x0311ff92},
1053{7200000, DIF_BPF_COEFF1819, 0xfb48f9ed},
1054{7200000, DIF_BPF_COEFF2021, 0xfd980453},
1055{7200000, DIF_BPF_COEFF2223, 0x08e306cd},
1056{7200000, DIF_BPF_COEFF2425, 0xfe88f60a},
1057{7200000, DIF_BPF_COEFF2627, 0xf482fc40},
1058{7200000, DIF_BPF_COEFF2829, 0x08080e93},
1059{7200000, DIF_BPF_COEFF3031, 0x09fdfd0c},
1060{7200000, DIF_BPF_COEFF3233, 0xf19af0ea},
1061{7200000, DIF_BPF_COEFF3435, 0xfc050a81},
1062{7200000, DIF_BPF_COEFF36, 0x110d0000},
1063/* END - DIF BPF register values from 72_quant.dat*/
1064
1065
1066/*case 7300000:*/
1067/* BEGIN - DIF BPF register values from 73_quant.dat*/
1068{7300000, DIF_BPF_COEFF01, 0x00000002},
1069{7300000, DIF_BPF_COEFF23, 0x00080008},
1070{7300000, DIF_BPF_COEFF45, 0xfff0ffc9},
1071{7300000, DIF_BPF_COEFF67, 0xffc1000d},
1072{7300000, DIF_BPF_COEFF89, 0x009800e2},
1073{7300000, DIF_BPF_COEFF1011, 0x005bff10},
1074{7300000, DIF_BPF_COEFF1213, 0xfe00fe74},
1075{7300000, DIF_BPF_COEFF1415, 0x00b50345},
1076{7300000, DIF_BPF_COEFF1617, 0x03b000bc},
1077{7300000, DIF_BPF_COEFF1819, 0xfc18f9a1},
1078{7300000, DIF_BPF_COEFF2021, 0xfc4802f9},
1079{7300000, DIF_BPF_COEFF2223, 0x089807dc},
1080{7300000, DIF_BPF_COEFF2425, 0x0022f6f0},
1081{7300000, DIF_BPF_COEFF2627, 0xf407fada},
1082{7300000, DIF_BPF_COEFF2829, 0x06da0e74},
1083{7300000, DIF_BPF_COEFF3031, 0x0ad3fe06},
1084{7300000, DIF_BPF_COEFF3233, 0xf1fef0ab},
1085{7300000, DIF_BPF_COEFF3435, 0xfb9c0a55},
1086{7300000, DIF_BPF_COEFF36, 0x110d0000},
1087/* END - DIF BPF register values from 73_quant.dat*/
1088
1089
1090/*case 7400000:*/
1091/* BEGIN - DIF BPF register values from 74_quant.dat*/
1092{7400000, DIF_BPF_COEFF01, 0x00000001},
1093{7400000, DIF_BPF_COEFF23, 0x0008000e},
1094{7400000, DIF_BPF_COEFF45, 0xfffdffd0},
1095{7400000, DIF_BPF_COEFF67, 0xffafffdf},
1096{7400000, DIF_BPF_COEFF89, 0x006e00f2},
1097{7400000, DIF_BPF_COEFF1011, 0x00b8ff82},
1098{7400000, DIF_BPF_COEFF1213, 0xfe1bfdf8},
1099{7400000, DIF_BPF_COEFF1415, 0xffe302c8},
1100{7400000, DIF_BPF_COEFF1617, 0x041301dc},
1101{7400000, DIF_BPF_COEFF1819, 0xfd1af99e},
1102{7400000, DIF_BPF_COEFF2021, 0xfb1e0183},
1103{7400000, DIF_BPF_COEFF2223, 0x080908b5},
1104{7400000, DIF_BPF_COEFF2425, 0x01bcf801},
1105{7400000, DIF_BPF_COEFF2627, 0xf3bdf985},
1106{7400000, DIF_BPF_COEFF2829, 0x059a0e38},
1107{7400000, DIF_BPF_COEFF3031, 0x0b99ff03},
1108{7400000, DIF_BPF_COEFF3233, 0xf26cf071},
1109{7400000, DIF_BPF_COEFF3435, 0xfb330a2a},
1110{7400000, DIF_BPF_COEFF36, 0x110d0000},
1111/* END - DIF BPF register values from 74_quant.dat*/
1112
1113
1114/*case 7500000:*/
1115/* BEGIN - DIF BPF register values from 75_quant.dat*/
1116{7500000, DIF_BPF_COEFF01, 0xffff0000},
1117{7500000, DIF_BPF_COEFF23, 0x00070011},
1118{7500000, DIF_BPF_COEFF45, 0x000affdf},
1119{7500000, DIF_BPF_COEFF67, 0xffa9ffb5},
1120{7500000, DIF_BPF_COEFF89, 0x003700e6},
1121{7500000, DIF_BPF_COEFF1011, 0x01010000},
1122{7500000, DIF_BPF_COEFF1213, 0xfe62fda8},
1123{7500000, DIF_BPF_COEFF1415, 0xff140219},
1124{7500000, DIF_BPF_COEFF1617, 0x043502e1},
1125{7500000, DIF_BPF_COEFF1819, 0xfe42f9e6},
1126{7500000, DIF_BPF_COEFF2021, 0xfa270000},
1127{7500000, DIF_BPF_COEFF2223, 0x073a0953},
1128{7500000, DIF_BPF_COEFF2425, 0x034cf939},
1129{7500000, DIF_BPF_COEFF2627, 0xf3a4f845},
1130{7500000, DIF_BPF_COEFF2829, 0x044c0de1},
1131{7500000, DIF_BPF_COEFF3031, 0x0c4f0000},
1132{7500000, DIF_BPF_COEFF3233, 0xf2e2f03c},
1133{7500000, DIF_BPF_COEFF3435, 0xfacc09fe},
1134{7500000, DIF_BPF_COEFF36, 0x110d0000},
1135/* END - DIF BPF register values from 75_quant.dat*/
1136
1137
1138/*case 7600000:*/
1139/* BEGIN - DIF BPF register values from 76_quant.dat*/
1140{7600000, DIF_BPF_COEFF01, 0xffffffff},
1141{7600000, DIF_BPF_COEFF23, 0x00040012},
1142{7600000, DIF_BPF_COEFF45, 0x0016fff3},
1143{7600000, DIF_BPF_COEFF67, 0xffafff95},
1144{7600000, DIF_BPF_COEFF89, 0xfff900c0},
1145{7600000, DIF_BPF_COEFF1011, 0x0130007e},
1146{7600000, DIF_BPF_COEFF1213, 0xfecefd89},
1147{7600000, DIF_BPF_COEFF1415, 0xfe560146},
1148{7600000, DIF_BPF_COEFF1617, 0x041303bc},
1149{7600000, DIF_BPF_COEFF1819, 0xff81fa76},
1150{7600000, DIF_BPF_COEFF2021, 0xf96cfe7d},
1151{7600000, DIF_BPF_COEFF2223, 0x063209b1},
1152{7600000, DIF_BPF_COEFF2425, 0x04c9fa93},
1153{7600000, DIF_BPF_COEFF2627, 0xf3bdf71e},
1154{7600000, DIF_BPF_COEFF2829, 0x02f30d6e},
1155{7600000, DIF_BPF_COEFF3031, 0x0cf200fd},
1156{7600000, DIF_BPF_COEFF3233, 0xf361f00e},
1157{7600000, DIF_BPF_COEFF3435, 0xfa6509d1},
1158{7600000, DIF_BPF_COEFF36, 0x110d0000},
1159/* END - DIF BPF register values from 76_quant.dat*/
1160
1161
1162/*case 7700000:*/
1163/* BEGIN - DIF BPF register values from 77_quant.dat*/
1164{7700000, DIF_BPF_COEFF01, 0xfffffffe},
1165{7700000, DIF_BPF_COEFF23, 0x00010010},
1166{7700000, DIF_BPF_COEFF45, 0x001e0008},
1167{7700000, DIF_BPF_COEFF67, 0xffc1ff84},
1168{7700000, DIF_BPF_COEFF89, 0xffbc0084},
1169{7700000, DIF_BPF_COEFF1011, 0x013e00f0},
1170{7700000, DIF_BPF_COEFF1213, 0xff56fd9f},
1171{7700000, DIF_BPF_COEFF1415, 0xfdb8005c},
1172{7700000, DIF_BPF_COEFF1617, 0x03b00460},
1173{7700000, DIF_BPF_COEFF1819, 0x00c7fb45},
1174{7700000, DIF_BPF_COEFF2021, 0xf8f4fd07},
1175{7700000, DIF_BPF_COEFF2223, 0x04fa09ce},
1176{7700000, DIF_BPF_COEFF2425, 0x062afc07},
1177{7700000, DIF_BPF_COEFF2627, 0xf407f614},
1178{7700000, DIF_BPF_COEFF2829, 0x01920ce0},
1179{7700000, DIF_BPF_COEFF3031, 0x0d8301fa},
1180{7700000, DIF_BPF_COEFF3233, 0xf3e8efe5},
1181{7700000, DIF_BPF_COEFF3435, 0xfa0009a4},
1182{7700000, DIF_BPF_COEFF36, 0x110d0000},
1183/* END - DIF BPF register values from 77_quant.dat*/
1184
1185
1186/*case 7800000:*/
1187/* BEGIN - DIF BPF register values from 78_quant.dat*/
1188{7800000, DIF_BPF_COEFF01, 0x0000fffd},
1189{7800000, DIF_BPF_COEFF23, 0xfffd000b},
1190{7800000, DIF_BPF_COEFF45, 0x0022001d},
1191{7800000, DIF_BPF_COEFF67, 0xffdbff82},
1192{7800000, DIF_BPF_COEFF89, 0xff870039},
1193{7800000, DIF_BPF_COEFF1011, 0x012a014a},
1194{7800000, DIF_BPF_COEFF1213, 0xffedfde7},
1195{7800000, DIF_BPF_COEFF1415, 0xfd47ff6b},
1196{7800000, DIF_BPF_COEFF1617, 0x031104c6},
1197{7800000, DIF_BPF_COEFF1819, 0x0202fc4c},
1198{7800000, DIF_BPF_COEFF2021, 0xf8c6fbad},
1199{7800000, DIF_BPF_COEFF2223, 0x039909a7},
1200{7800000, DIF_BPF_COEFF2425, 0x0767fd8e},
1201{7800000, DIF_BPF_COEFF2627, 0xf482f52b},
1202{7800000, DIF_BPF_COEFF2829, 0x002d0c39},
1203{7800000, DIF_BPF_COEFF3031, 0x0e0002f4},
1204{7800000, DIF_BPF_COEFF3233, 0xf477efc2},
1205{7800000, DIF_BPF_COEFF3435, 0xf99b0977},
1206{7800000, DIF_BPF_COEFF36, 0x110d0000},
1207/* END - DIF BPF register values from 78_quant.dat*/
1208
1209
1210/*case 7900000:*/
1211/* BEGIN - DIF BPF register values from 79_quant.dat*/
1212{7900000, DIF_BPF_COEFF01, 0x0000fffd},
1213{7900000, DIF_BPF_COEFF23, 0xfffa0004},
1214{7900000, DIF_BPF_COEFF45, 0x0020002d},
1215{7900000, DIF_BPF_COEFF67, 0xfffbff91},
1216{7900000, DIF_BPF_COEFF89, 0xff61ffe8},
1217{7900000, DIF_BPF_COEFF1011, 0x00f70184},
1218{7900000, DIF_BPF_COEFF1213, 0x0086fe5c},
1219{7900000, DIF_BPF_COEFF1415, 0xfd0bfe85},
1220{7900000, DIF_BPF_COEFF1617, 0x024104e5},
1221{7900000, DIF_BPF_COEFF1819, 0x0323fd7d},
1222{7900000, DIF_BPF_COEFF2021, 0xf8e2fa79},
1223{7900000, DIF_BPF_COEFF2223, 0x021d093f},
1224{7900000, DIF_BPF_COEFF2425, 0x0879ff22},
1225{7900000, DIF_BPF_COEFF2627, 0xf52bf465},
1226{7900000, DIF_BPF_COEFF2829, 0xfec70b79},
1227{7900000, DIF_BPF_COEFF3031, 0x0e6803eb},
1228{7900000, DIF_BPF_COEFF3233, 0xf50defa5},
1229{7900000, DIF_BPF_COEFF3435, 0xf937094a},
1230{7900000, DIF_BPF_COEFF36, 0x110d0000},
1231/* END - DIF BPF register values from 79_quant.dat*/
1232
1233
1234/*case 8000000:*/
1235/* BEGIN - DIF BPF register values from 80_quant.dat*/
1236{8000000, DIF_BPF_COEFF01, 0x0000fffe},
1237{8000000, DIF_BPF_COEFF23, 0xfff8fffd},
1238{8000000, DIF_BPF_COEFF45, 0x00190036},
1239{8000000, DIF_BPF_COEFF67, 0x001bffaf},
1240{8000000, DIF_BPF_COEFF89, 0xff4fff99},
1241{8000000, DIF_BPF_COEFF1011, 0x00aa0198},
1242{8000000, DIF_BPF_COEFF1213, 0x0112fef3},
1243{8000000, DIF_BPF_COEFF1415, 0xfd09fdb9},
1244{8000000, DIF_BPF_COEFF1617, 0x014d04be},
1245{8000000, DIF_BPF_COEFF1819, 0x041bfecc},
1246{8000000, DIF_BPF_COEFF2021, 0xf947f978},
1247{8000000, DIF_BPF_COEFF2223, 0x00900897},
1248{8000000, DIF_BPF_COEFF2425, 0x095a00b9},
1249{8000000, DIF_BPF_COEFF2627, 0xf600f3c5},
1250{8000000, DIF_BPF_COEFF2829, 0xfd650aa3},
1251{8000000, DIF_BPF_COEFF3031, 0x0ebc04de},
1252{8000000, DIF_BPF_COEFF3233, 0xf5aaef8e},
1253{8000000, DIF_BPF_COEFF3435, 0xf8d5091c},
1254{8000000, DIF_BPF_COEFF36, 0x110d0000},
1255/* END - DIF BPF register values from 80_quant.dat*/
1256
1257
1258/*case 8100000:*/
1259/* BEGIN - DIF BPF register values from 81_quant.dat*/
1260{8100000, DIF_BPF_COEFF01, 0x0000ffff},
1261{8100000, DIF_BPF_COEFF23, 0xfff7fff6},
1262{8100000, DIF_BPF_COEFF45, 0x000e0038},
1263{8100000, DIF_BPF_COEFF67, 0x0037ffd7},
1264{8100000, DIF_BPF_COEFF89, 0xff52ff56},
1265{8100000, DIF_BPF_COEFF1011, 0x004b0184},
1266{8100000, DIF_BPF_COEFF1213, 0x0186ffa1},
1267{8100000, DIF_BPF_COEFF1415, 0xfd40fd16},
1268{8100000, DIF_BPF_COEFF1617, 0x00440452},
1269{8100000, DIF_BPF_COEFF1819, 0x04de0029},
1270{8100000, DIF_BPF_COEFF2021, 0xf9f2f8b2},
1271{8100000, DIF_BPF_COEFF2223, 0xfefe07b5},
1272{8100000, DIF_BPF_COEFF2425, 0x0a05024d},
1273{8100000, DIF_BPF_COEFF2627, 0xf6fef34d},
1274{8100000, DIF_BPF_COEFF2829, 0xfc0a09b8},
1275{8100000, DIF_BPF_COEFF3031, 0x0efa05cd},
1276{8100000, DIF_BPF_COEFF3233, 0xf64eef7d},
1277{8100000, DIF_BPF_COEFF3435, 0xf87308ed},
1278{8100000, DIF_BPF_COEFF36, 0x110d0000},
1279/* END - DIF BPF register values from 81_quant.dat*/
1280
1281
1282/*case 8200000:*/
1283/* BEGIN - DIF BPF register values from 82_quant.dat*/
1284{8200000, DIF_BPF_COEFF01, 0x00010000},
1285{8200000, DIF_BPF_COEFF23, 0xfff8fff0},
1286{8200000, DIF_BPF_COEFF45, 0x00000031},
1287{8200000, DIF_BPF_COEFF67, 0x004c0005},
1288{8200000, DIF_BPF_COEFF89, 0xff6aff27},
1289{8200000, DIF_BPF_COEFF1011, 0xffe4014a},
1290{8200000, DIF_BPF_COEFF1213, 0x01d70057},
1291{8200000, DIF_BPF_COEFF1415, 0xfdacfca6},
1292{8200000, DIF_BPF_COEFF1617, 0xff3603a7},
1293{8200000, DIF_BPF_COEFF1819, 0x05610184},
1294{8200000, DIF_BPF_COEFF2021, 0xfadbf82e},
1295{8200000, DIF_BPF_COEFF2223, 0xfd74069f},
1296{8200000, DIF_BPF_COEFF2425, 0x0a7503d6},
1297{8200000, DIF_BPF_COEFF2627, 0xf81ff2ff},
1298{8200000, DIF_BPF_COEFF2829, 0xfab808b9},
1299{8200000, DIF_BPF_COEFF3031, 0x0f2306b5},
1300{8200000, DIF_BPF_COEFF3233, 0xf6f9ef72},
1301{8200000, DIF_BPF_COEFF3435, 0xf81308bf},
1302{8200000, DIF_BPF_COEFF36, 0x110d0000},
1303/* END - DIF BPF register values from 82_quant.dat*/
1304
1305
1306/*case 8300000:*/
1307/* BEGIN - DIF BPF register values from 83_quant.dat*/
1308{8300000, DIF_BPF_COEFF01, 0x00010001},
1309{8300000, DIF_BPF_COEFF23, 0xfffbffee},
1310{8300000, DIF_BPF_COEFF45, 0xfff30022},
1311{8300000, DIF_BPF_COEFF67, 0x00560032},
1312{8300000, DIF_BPF_COEFF89, 0xff95ff10},
1313{8300000, DIF_BPF_COEFF1011, 0xff8000f0},
1314{8300000, DIF_BPF_COEFF1213, 0x01fe0106},
1315{8300000, DIF_BPF_COEFF1415, 0xfe46fc71},
1316{8300000, DIF_BPF_COEFF1617, 0xfe3502c7},
1317{8300000, DIF_BPF_COEFF1819, 0x059e02ce},
1318{8300000, DIF_BPF_COEFF2021, 0xfbf9f7f2},
1319{8300000, DIF_BPF_COEFF2223, 0xfbff055b},
1320{8300000, DIF_BPF_COEFF2425, 0x0aa9054c},
1321{8300000, DIF_BPF_COEFF2627, 0xf961f2db},
1322{8300000, DIF_BPF_COEFF2829, 0xf97507aa},
1323{8300000, DIF_BPF_COEFF3031, 0x0f350797},
1324{8300000, DIF_BPF_COEFF3233, 0xf7a9ef6d},
1325{8300000, DIF_BPF_COEFF3435, 0xf7b40890},
1326{8300000, DIF_BPF_COEFF36, 0x110d0000},
1327/* END - DIF BPF register values from 83_quant.dat*/
1328
1329
1330/*case 8400000:*/
1331/* BEGIN - DIF BPF register values from 84_quant.dat*/
1332{8400000, DIF_BPF_COEFF01, 0x00010002},
1333{8400000, DIF_BPF_COEFF23, 0xfffeffee},
1334{8400000, DIF_BPF_COEFF45, 0xffe8000f},
1335{8400000, DIF_BPF_COEFF67, 0x00540058},
1336{8400000, DIF_BPF_COEFF89, 0xffcdff14},
1337{8400000, DIF_BPF_COEFF1011, 0xff29007e},
1338{8400000, DIF_BPF_COEFF1213, 0x01f6019e},
1339{8400000, DIF_BPF_COEFF1415, 0xff01fc7c},
1340{8400000, DIF_BPF_COEFF1617, 0xfd5101bf},
1341{8400000, DIF_BPF_COEFF1819, 0x059203f6},
1342{8400000, DIF_BPF_COEFF2021, 0xfd41f7fe},
1343{8400000, DIF_BPF_COEFF2223, 0xfaa903f3},
1344{8400000, DIF_BPF_COEFF2425, 0x0a9e06a9},
1345{8400000, DIF_BPF_COEFF2627, 0xfabdf2e2},
1346{8400000, DIF_BPF_COEFF2829, 0xf842068b},
1347{8400000, DIF_BPF_COEFF3031, 0x0f320871},
1348{8400000, DIF_BPF_COEFF3233, 0xf85eef6e},
1349{8400000, DIF_BPF_COEFF3435, 0xf7560860},
1350{8400000, DIF_BPF_COEFF36, 0x110d0000},
1351/* END - DIF BPF register values from 84_quant.dat*/
1352
1353
1354/*case 8500000:*/
1355/* BEGIN - DIF BPF register values from 85_quant.dat*/
1356{8500000, DIF_BPF_COEFF01, 0x00000003},
1357{8500000, DIF_BPF_COEFF23, 0x0002fff2},
1358{8500000, DIF_BPF_COEFF45, 0xffe1fff9},
1359{8500000, DIF_BPF_COEFF67, 0x00460073},
1360{8500000, DIF_BPF_COEFF89, 0x000bff34},
1361{8500000, DIF_BPF_COEFF1011, 0xfee90000},
1362{8500000, DIF_BPF_COEFF1213, 0x01c10215},
1363{8500000, DIF_BPF_COEFF1415, 0xffd0fcc5},
1364{8500000, DIF_BPF_COEFF1617, 0xfc99009d},
1365{8500000, DIF_BPF_COEFF1819, 0x053d04f1},
1366{8500000, DIF_BPF_COEFF2021, 0xfea5f853},
1367{8500000, DIF_BPF_COEFF2223, 0xf97d0270},
1368{8500000, DIF_BPF_COEFF2425, 0x0a5607e4},
1369{8500000, DIF_BPF_COEFF2627, 0xfc2ef314},
1370{8500000, DIF_BPF_COEFF2829, 0xf723055f},
1371{8500000, DIF_BPF_COEFF3031, 0x0f180943},
1372{8500000, DIF_BPF_COEFF3233, 0xf919ef75},
1373{8500000, DIF_BPF_COEFF3435, 0xf6fa0830},
1374{8500000, DIF_BPF_COEFF36, 0x110d0000},
1375/* END - DIF BPF register values from 85_quant.dat*/
1376
1377
1378/*case 8600000:*/
1379/* BEGIN - DIF BPF register values from 86_quant.dat*/
1380{8600000, DIF_BPF_COEFF01, 0x00000003},
1381{8600000, DIF_BPF_COEFF23, 0x0005fff8},
1382{8600000, DIF_BPF_COEFF45, 0xffdeffe4},
1383{8600000, DIF_BPF_COEFF67, 0x002f007f},
1384{8600000, DIF_BPF_COEFF89, 0x0048ff6b},
1385{8600000, DIF_BPF_COEFF1011, 0xfec7ff82},
1386{8600000, DIF_BPF_COEFF1213, 0x0163025f},
1387{8600000, DIF_BPF_COEFF1415, 0x00a2fd47},
1388{8600000, DIF_BPF_COEFF1617, 0xfc17ff73},
1389{8600000, DIF_BPF_COEFF1819, 0x04a405b2},
1390{8600000, DIF_BPF_COEFF2021, 0x0017f8ed},
1391{8600000, DIF_BPF_COEFF2223, 0xf88500dc},
1392{8600000, DIF_BPF_COEFF2425, 0x09d208f9},
1393{8600000, DIF_BPF_COEFF2627, 0xfdaff370},
1394{8600000, DIF_BPF_COEFF2829, 0xf61c0429},
1395{8600000, DIF_BPF_COEFF3031, 0x0ee80a0b},
1396{8600000, DIF_BPF_COEFF3233, 0xf9d8ef82},
1397{8600000, DIF_BPF_COEFF3435, 0xf6a00800},
1398{8600000, DIF_BPF_COEFF36, 0x110d0000},
1399/* END - DIF BPF register values from 86_quant.dat*/
1400
1401
1402/*case 8700000:*/
1403/* BEGIN - DIF BPF register values from 87_quant.dat*/
1404{8700000, DIF_BPF_COEFF01, 0x00000003},
1405{8700000, DIF_BPF_COEFF23, 0x0007ffff},
1406{8700000, DIF_BPF_COEFF45, 0xffe1ffd4},
1407{8700000, DIF_BPF_COEFF67, 0x0010007a},
1408{8700000, DIF_BPF_COEFF89, 0x007cffb2},
1409{8700000, DIF_BPF_COEFF1011, 0xfec6ff10},
1410{8700000, DIF_BPF_COEFF1213, 0x00e60277},
1411{8700000, DIF_BPF_COEFF1415, 0x0168fdf9},
1412{8700000, DIF_BPF_COEFF1617, 0xfbd3fe50},
1413{8700000, DIF_BPF_COEFF1819, 0x03ce0631},
1414{8700000, DIF_BPF_COEFF2021, 0x0188f9c8},
1415{8700000, DIF_BPF_COEFF2223, 0xf7c7ff43},
1416{8700000, DIF_BPF_COEFF2425, 0x091509e3},
1417{8700000, DIF_BPF_COEFF2627, 0xff39f3f6},
1418{8700000, DIF_BPF_COEFF2829, 0xf52d02ea},
1419{8700000, DIF_BPF_COEFF3031, 0x0ea30ac9},
1420{8700000, DIF_BPF_COEFF3233, 0xfa9bef95},
1421{8700000, DIF_BPF_COEFF3435, 0xf64607d0},
1422{8700000, DIF_BPF_COEFF36, 0x110d0000},
1423/* END - DIF BPF register values from 87_quant.dat*/
1424
1425
1426/*case 8800000:*/
1427/* BEGIN - DIF BPF register values from 88_quant.dat*/
1428{8800000, DIF_BPF_COEFF01, 0x00000002},
1429{8800000, DIF_BPF_COEFF23, 0x00090007},
1430{8800000, DIF_BPF_COEFF45, 0xffe9ffca},
1431{8800000, DIF_BPF_COEFF67, 0xfff00065},
1432{8800000, DIF_BPF_COEFF89, 0x00a10003},
1433{8800000, DIF_BPF_COEFF1011, 0xfee6feb6},
1434{8800000, DIF_BPF_COEFF1213, 0x0053025b},
1435{8800000, DIF_BPF_COEFF1415, 0x0213fed0},
1436{8800000, DIF_BPF_COEFF1617, 0xfbd3fd46},
1437{8800000, DIF_BPF_COEFF1819, 0x02c70668},
1438{8800000, DIF_BPF_COEFF2021, 0x02eafadb},
1439{8800000, DIF_BPF_COEFF2223, 0xf74bfdae},
1440{8800000, DIF_BPF_COEFF2425, 0x08230a9c},
1441{8800000, DIF_BPF_COEFF2627, 0x00c7f4a3},
1442{8800000, DIF_BPF_COEFF2829, 0xf45b01a6},
1443{8800000, DIF_BPF_COEFF3031, 0x0e480b7c},
1444{8800000, DIF_BPF_COEFF3233, 0xfb61efae},
1445{8800000, DIF_BPF_COEFF3435, 0xf5ef079f},
1446{8800000, DIF_BPF_COEFF36, 0x110d0000},
1447/* END - DIF BPF register values from 88_quant.dat*/
1448
1449
1450/*case 8900000:*/
1451/* BEGIN - DIF BPF register values from 89_quant.dat*/
1452{8900000, DIF_BPF_COEFF01, 0xffff0000},
1453{8900000, DIF_BPF_COEFF23, 0x0008000d},
1454{8900000, DIF_BPF_COEFF45, 0xfff5ffc8},
1455{8900000, DIF_BPF_COEFF67, 0xffd10043},
1456{8900000, DIF_BPF_COEFF89, 0x00b20053},
1457{8900000, DIF_BPF_COEFF1011, 0xff24fe7c},
1458{8900000, DIF_BPF_COEFF1213, 0xffb9020c},
1459{8900000, DIF_BPF_COEFF1415, 0x0295ffbb},
1460{8900000, DIF_BPF_COEFF1617, 0xfc17fc64},
1461{8900000, DIF_BPF_COEFF1819, 0x019b0654},
1462{8900000, DIF_BPF_COEFF2021, 0x042dfc1c},
1463{8900000, DIF_BPF_COEFF2223, 0xf714fc2a},
1464{8900000, DIF_BPF_COEFF2425, 0x07020b21},
1465{8900000, DIF_BPF_COEFF2627, 0x0251f575},
1466{8900000, DIF_BPF_COEFF2829, 0xf3a7005e},
1467{8900000, DIF_BPF_COEFF3031, 0x0dd80c24},
1468{8900000, DIF_BPF_COEFF3233, 0xfc2aefcd},
1469{8900000, DIF_BPF_COEFF3435, 0xf599076e},
1470{8900000, DIF_BPF_COEFF36, 0x110d0000},
1471/* END - DIF BPF register values from 89_quant.dat*/
1472
1473
1474/*case 9000000:*/
1475/* BEGIN - DIF BPF register values from 90_quant.dat*/
1476{9000000, DIF_BPF_COEFF01, 0xffffffff},
1477{9000000, DIF_BPF_COEFF23, 0x00060011},
1478{9000000, DIF_BPF_COEFF45, 0x0002ffcf},
1479{9000000, DIF_BPF_COEFF67, 0xffba0018},
1480{9000000, DIF_BPF_COEFF89, 0x00ad009a},
1481{9000000, DIF_BPF_COEFF1011, 0xff79fe68},
1482{9000000, DIF_BPF_COEFF1213, 0xff260192},
1483{9000000, DIF_BPF_COEFF1415, 0x02e500ab},
1484{9000000, DIF_BPF_COEFF1617, 0xfc99fbb6},
1485{9000000, DIF_BPF_COEFF1819, 0x005b05f7},
1486{9000000, DIF_BPF_COEFF2021, 0x0545fd81},
1487{9000000, DIF_BPF_COEFF2223, 0xf723fabf},
1488{9000000, DIF_BPF_COEFF2425, 0x05b80b70},
1489{9000000, DIF_BPF_COEFF2627, 0x03d2f669},
1490{9000000, DIF_BPF_COEFF2829, 0xf313ff15},
1491{9000000, DIF_BPF_COEFF3031, 0x0d550cbf},
1492{9000000, DIF_BPF_COEFF3233, 0xfcf6eff2},
1493{9000000, DIF_BPF_COEFF3435, 0xf544073d},
1494{9000000, DIF_BPF_COEFF36, 0x110d0000},
1495/* END - DIF BPF register values from 90_quant.dat*/
1496
1497
1498/*case 9100000:*/
1499/* BEGIN - DIF BPF register values from 91_quant.dat*/
1500{9100000, DIF_BPF_COEFF01, 0xfffffffe},
1501{9100000, DIF_BPF_COEFF23, 0x00030012},
1502{9100000, DIF_BPF_COEFF45, 0x000fffdd},
1503{9100000, DIF_BPF_COEFF67, 0xffacffea},
1504{9100000, DIF_BPF_COEFF89, 0x009300cf},
1505{9100000, DIF_BPF_COEFF1011, 0xffdcfe7c},
1506{9100000, DIF_BPF_COEFF1213, 0xfea600f7},
1507{9100000, DIF_BPF_COEFF1415, 0x02fd0190},
1508{9100000, DIF_BPF_COEFF1617, 0xfd51fb46},
1509{9100000, DIF_BPF_COEFF1819, 0xff150554},
1510{9100000, DIF_BPF_COEFF2021, 0x0627fefd},
1511{9100000, DIF_BPF_COEFF2223, 0xf778f978},
1512{9100000, DIF_BPF_COEFF2425, 0x044d0b87},
1513{9100000, DIF_BPF_COEFF2627, 0x0543f77d},
1514{9100000, DIF_BPF_COEFF2829, 0xf2a0fdcf},
1515{9100000, DIF_BPF_COEFF3031, 0x0cbe0d4e},
1516{9100000, DIF_BPF_COEFF3233, 0xfdc4f01d},
1517{9100000, DIF_BPF_COEFF3435, 0xf4f2070b},
1518{9100000, DIF_BPF_COEFF36, 0x110d0000},
1519/* END - DIF BPF register values from 91_quant.dat*/
1520
1521
1522/*case 9200000:*/
1523/* BEGIN - DIF BPF register values from 92_quant.dat*/
1524{9200000, DIF_BPF_COEFF01, 0x0000fffd},
1525{9200000, DIF_BPF_COEFF23, 0x00000010},
1526{9200000, DIF_BPF_COEFF45, 0x001afff0},
1527{9200000, DIF_BPF_COEFF67, 0xffaaffbf},
1528{9200000, DIF_BPF_COEFF89, 0x006700ed},
1529{9200000, DIF_BPF_COEFF1011, 0x0043feb6},
1530{9200000, DIF_BPF_COEFF1213, 0xfe460047},
1531{9200000, DIF_BPF_COEFF1415, 0x02db0258},
1532{9200000, DIF_BPF_COEFF1617, 0xfe35fb1b},
1533{9200000, DIF_BPF_COEFF1819, 0xfddc0473},
1534{9200000, DIF_BPF_COEFF2021, 0x06c90082},
1535{9200000, DIF_BPF_COEFF2223, 0xf811f85e},
1536{9200000, DIF_BPF_COEFF2425, 0x02c90b66},
1537{9200000, DIF_BPF_COEFF2627, 0x069ff8ad},
1538{9200000, DIF_BPF_COEFF2829, 0xf250fc8d},
1539{9200000, DIF_BPF_COEFF3031, 0x0c140dcf},
1540{9200000, DIF_BPF_COEFF3233, 0xfe93f04d},
1541{9200000, DIF_BPF_COEFF3435, 0xf4a106d9},
1542{9200000, DIF_BPF_COEFF36, 0x110d0000},
1543/* END - DIF BPF register values from 92_quant.dat*/
1544
1545
1546/*case 9300000:*/
1547/* BEGIN - DIF BPF register values from 93_quant.dat*/
1548{9300000, DIF_BPF_COEFF01, 0x0000fffd},
1549{9300000, DIF_BPF_COEFF23, 0xfffc000c},
1550{9300000, DIF_BPF_COEFF45, 0x00200006},
1551{9300000, DIF_BPF_COEFF67, 0xffb4ff9c},
1552{9300000, DIF_BPF_COEFF89, 0x002f00ef},
1553{9300000, DIF_BPF_COEFF1011, 0x00a4ff10},
1554{9300000, DIF_BPF_COEFF1213, 0xfe0dff92},
1555{9300000, DIF_BPF_COEFF1415, 0x028102f7},
1556{9300000, DIF_BPF_COEFF1617, 0xff36fb37},
1557{9300000, DIF_BPF_COEFF1819, 0xfcbf035e},
1558{9300000, DIF_BPF_COEFF2021, 0x07260202},
1559{9300000, DIF_BPF_COEFF2223, 0xf8e8f778},
1560{9300000, DIF_BPF_COEFF2425, 0x01340b0d},
1561{9300000, DIF_BPF_COEFF2627, 0x07e1f9f4},
1562{9300000, DIF_BPF_COEFF2829, 0xf223fb51},
1563{9300000, DIF_BPF_COEFF3031, 0x0b590e42},
1564{9300000, DIF_BPF_COEFF3233, 0xff64f083},
1565{9300000, DIF_BPF_COEFF3435, 0xf45206a7},
1566{9300000, DIF_BPF_COEFF36, 0x110d0000},
1567/* END - DIF BPF register values from 93_quant.dat*/
1568
1569
1570/*case 9400000:*/
1571/* BEGIN - DIF BPF register values from 94_quant.dat*/
1572{9400000, DIF_BPF_COEFF01, 0x0000fffd},
1573{9400000, DIF_BPF_COEFF23, 0xfff90005},
1574{9400000, DIF_BPF_COEFF45, 0x0022001a},
1575{9400000, DIF_BPF_COEFF67, 0xffc9ff86},
1576{9400000, DIF_BPF_COEFF89, 0xfff000d7},
1577{9400000, DIF_BPF_COEFF1011, 0x00f2ff82},
1578{9400000, DIF_BPF_COEFF1213, 0xfe01fee5},
1579{9400000, DIF_BPF_COEFF1415, 0x01f60362},
1580{9400000, DIF_BPF_COEFF1617, 0x0044fb99},
1581{9400000, DIF_BPF_COEFF1819, 0xfbcc0222},
1582{9400000, DIF_BPF_COEFF2021, 0x07380370},
1583{9400000, DIF_BPF_COEFF2223, 0xf9f7f6cc},
1584{9400000, DIF_BPF_COEFF2425, 0xff990a7e},
1585{9400000, DIF_BPF_COEFF2627, 0x0902fb50},
1586{9400000, DIF_BPF_COEFF2829, 0xf21afa1f},
1587{9400000, DIF_BPF_COEFF3031, 0x0a8d0ea6},
1588{9400000, DIF_BPF_COEFF3233, 0x0034f0bf},
1589{9400000, DIF_BPF_COEFF3435, 0xf4050675},
1590{9400000, DIF_BPF_COEFF36, 0x110d0000},
1591/* END - DIF BPF register values from 94_quant.dat*/
1592
1593
1594/*case 9500000:*/
1595/* BEGIN - DIF BPF register values from 95_quant.dat*/
1596{9500000, DIF_BPF_COEFF01, 0x0000fffe},
1597{9500000, DIF_BPF_COEFF23, 0xfff8fffe},
1598{9500000, DIF_BPF_COEFF45, 0x001e002b},
1599{9500000, DIF_BPF_COEFF67, 0xffe5ff81},
1600{9500000, DIF_BPF_COEFF89, 0xffb400a5},
1601{9500000, DIF_BPF_COEFF1011, 0x01280000},
1602{9500000, DIF_BPF_COEFF1213, 0xfe24fe50},
1603{9500000, DIF_BPF_COEFF1415, 0x01460390},
1604{9500000, DIF_BPF_COEFF1617, 0x014dfc3a},
1605{9500000, DIF_BPF_COEFF1819, 0xfb1000ce},
1606{9500000, DIF_BPF_COEFF2021, 0x070104bf},
1607{9500000, DIF_BPF_COEFF2223, 0xfb37f65f},
1608{9500000, DIF_BPF_COEFF2425, 0xfe0009bc},
1609{9500000, DIF_BPF_COEFF2627, 0x0a00fcbb},
1610{9500000, DIF_BPF_COEFF2829, 0xf235f8f8},
1611{9500000, DIF_BPF_COEFF3031, 0x09b20efc},
1612{9500000, DIF_BPF_COEFF3233, 0x0105f101},
1613{9500000, DIF_BPF_COEFF3435, 0xf3ba0642},
1614{9500000, DIF_BPF_COEFF36, 0x110d0000},
1615/* END - DIF BPF register values from 95_quant.dat*/
1616
1617
1618/*case 9600000:*/
1619/* BEGIN - DIF BPF register values from 96_quant.dat*/
1620{9600000, DIF_BPF_COEFF01, 0x0001ffff},
1621{9600000, DIF_BPF_COEFF23, 0xfff8fff7},
1622{9600000, DIF_BPF_COEFF45, 0x00150036},
1623{9600000, DIF_BPF_COEFF67, 0x0005ff8c},
1624{9600000, DIF_BPF_COEFF89, 0xff810061},
1625{9600000, DIF_BPF_COEFF1011, 0x013d007e},
1626{9600000, DIF_BPF_COEFF1213, 0xfe71fddf},
1627{9600000, DIF_BPF_COEFF1415, 0x007c0380},
1628{9600000, DIF_BPF_COEFF1617, 0x0241fd13},
1629{9600000, DIF_BPF_COEFF1819, 0xfa94ff70},
1630{9600000, DIF_BPF_COEFF2021, 0x068005e2},
1631{9600000, DIF_BPF_COEFF2223, 0xfc9bf633},
1632{9600000, DIF_BPF_COEFF2425, 0xfc7308ca},
1633{9600000, DIF_BPF_COEFF2627, 0x0ad5fe30},
1634{9600000, DIF_BPF_COEFF2829, 0xf274f7e0},
1635{9600000, DIF_BPF_COEFF3031, 0x08c90f43},
1636{9600000, DIF_BPF_COEFF3233, 0x01d4f147},
1637{9600000, DIF_BPF_COEFF3435, 0xf371060f},
1638{9600000, DIF_BPF_COEFF36, 0x110d0000},
1639/* END - DIF BPF register values from 96_quant.dat*/
1640
1641
1642/*case 9700000:*/
1643/* BEGIN - DIF BPF register values from 97_quant.dat*/
1644{9700000, DIF_BPF_COEFF01, 0x00010001},
1645{9700000, DIF_BPF_COEFF23, 0xfff9fff1},
1646{9700000, DIF_BPF_COEFF45, 0x00090038},
1647{9700000, DIF_BPF_COEFF67, 0x0025ffa7},
1648{9700000, DIF_BPF_COEFF89, 0xff5e0012},
1649{9700000, DIF_BPF_COEFF1011, 0x013200f0},
1650{9700000, DIF_BPF_COEFF1213, 0xfee3fd9b},
1651{9700000, DIF_BPF_COEFF1415, 0xffaa0331},
1652{9700000, DIF_BPF_COEFF1617, 0x0311fe15},
1653{9700000, DIF_BPF_COEFF1819, 0xfa60fe18},
1654{9700000, DIF_BPF_COEFF2021, 0x05bd06d1},
1655{9700000, DIF_BPF_COEFF2223, 0xfe1bf64a},
1656{9700000, DIF_BPF_COEFF2425, 0xfafa07ae},
1657{9700000, DIF_BPF_COEFF2627, 0x0b7effab},
1658{9700000, DIF_BPF_COEFF2829, 0xf2d5f6d7},
1659{9700000, DIF_BPF_COEFF3031, 0x07d30f7a},
1660{9700000, DIF_BPF_COEFF3233, 0x02a3f194},
1661{9700000, DIF_BPF_COEFF3435, 0xf32905dc},
1662{9700000, DIF_BPF_COEFF36, 0x110d0000},
1663/* END - DIF BPF register values from 97_quant.dat*/
1664
1665
1666/*case 9800000:*/
1667/* BEGIN - DIF BPF register values from 98_quant.dat*/
1668{9800000, DIF_BPF_COEFF01, 0x00010002},
1669{9800000, DIF_BPF_COEFF23, 0xfffcffee},
1670{9800000, DIF_BPF_COEFF45, 0xfffb0032},
1671{9800000, DIF_BPF_COEFF67, 0x003fffcd},
1672{9800000, DIF_BPF_COEFF89, 0xff4effc1},
1673{9800000, DIF_BPF_COEFF1011, 0x0106014a},
1674{9800000, DIF_BPF_COEFF1213, 0xff6efd8a},
1675{9800000, DIF_BPF_COEFF1415, 0xfedd02aa},
1676{9800000, DIF_BPF_COEFF1617, 0x03b0ff34},
1677{9800000, DIF_BPF_COEFF1819, 0xfa74fcd7},
1678{9800000, DIF_BPF_COEFF2021, 0x04bf0781},
1679{9800000, DIF_BPF_COEFF2223, 0xffaaf6a3},
1680{9800000, DIF_BPF_COEFF2425, 0xf99e066b},
1681{9800000, DIF_BPF_COEFF2627, 0x0bf90128},
1682{9800000, DIF_BPF_COEFF2829, 0xf359f5e1},
1683{9800000, DIF_BPF_COEFF3031, 0x06d20fa2},
1684{9800000, DIF_BPF_COEFF3233, 0x0370f1e5},
1685{9800000, DIF_BPF_COEFF3435, 0xf2e405a8},
1686{9800000, DIF_BPF_COEFF36, 0x110d0000},
1687/* END - DIF BPF register values from 98_quant.dat*/
1688
1689
1690/*case 9900000:*/
1691/* BEGIN - DIF BPF register values from 99_quant.dat*/
1692{9900000, DIF_BPF_COEFF01, 0x00000003},
1693{9900000, DIF_BPF_COEFF23, 0xffffffee},
1694{9900000, DIF_BPF_COEFF45, 0xffef0024},
1695{9900000, DIF_BPF_COEFF67, 0x0051fffa},
1696{9900000, DIF_BPF_COEFF89, 0xff54ff77},
1697{9900000, DIF_BPF_COEFF1011, 0x00be0184},
1698{9900000, DIF_BPF_COEFF1213, 0x0006fdad},
1699{9900000, DIF_BPF_COEFF1415, 0xfe2701f3},
1700{9900000, DIF_BPF_COEFF1617, 0x0413005e},
1701{9900000, DIF_BPF_COEFF1819, 0xfad1fbba},
1702{9900000, DIF_BPF_COEFF2021, 0x039007ee},
1703{9900000, DIF_BPF_COEFF2223, 0x013bf73d},
1704{9900000, DIF_BPF_COEFF2425, 0xf868050a},
1705{9900000, DIF_BPF_COEFF2627, 0x0c4302a1},
1706{9900000, DIF_BPF_COEFF2829, 0xf3fdf4fe},
1707{9900000, DIF_BPF_COEFF3031, 0x05c70fba},
1708{9900000, DIF_BPF_COEFF3233, 0x043bf23c},
1709{9900000, DIF_BPF_COEFF3435, 0xf2a10575},
1710{9900000, DIF_BPF_COEFF36, 0x110d0000},
1711/* END - DIF BPF register values from 99_quant.dat*/
1712
1713
1714/*case 10000000:*/
1715/* BEGIN - DIF BPF register values from 100_quant.dat*/
1716{10000000, DIF_BPF_COEFF01, 0x00000003},
1717{10000000, DIF_BPF_COEFF23, 0x0003fff1},
1718{10000000, DIF_BPF_COEFF45, 0xffe50011},
1719{10000000, DIF_BPF_COEFF67, 0x00570027},
1720{10000000, DIF_BPF_COEFF89, 0xff70ff3c},
1721{10000000, DIF_BPF_COEFF1011, 0x00620198},
1722{10000000, DIF_BPF_COEFF1213, 0x009efe01},
1723{10000000, DIF_BPF_COEFF1415, 0xfd95011a},
1724{10000000, DIF_BPF_COEFF1617, 0x04350183},
1725{10000000, DIF_BPF_COEFF1819, 0xfb71fad0},
1726{10000000, DIF_BPF_COEFF2021, 0x023c0812},
1727{10000000, DIF_BPF_COEFF2223, 0x02c3f811},
1728{10000000, DIF_BPF_COEFF2425, 0xf75e0390},
1729{10000000, DIF_BPF_COEFF2627, 0x0c5c0411},
1730{10000000, DIF_BPF_COEFF2829, 0xf4c1f432},
1731{10000000, DIF_BPF_COEFF3031, 0x04b30fc1},
1732{10000000, DIF_BPF_COEFF3233, 0x0503f297},
1733{10000000, DIF_BPF_COEFF3435, 0xf2610541},
1734{10000000, DIF_BPF_COEFF36, 0x110d0000},
1735/* END - DIF BPF register values from 100_quant.dat*/
1736
1737
1738/*case 10100000:*/
1739/* BEGIN - DIF BPF register values from 101_quant.dat*/
1740{10100000, DIF_BPF_COEFF01, 0x00000003},
1741{10100000, DIF_BPF_COEFF23, 0x0006fff7},
1742{10100000, DIF_BPF_COEFF45, 0xffdffffc},
1743{10100000, DIF_BPF_COEFF67, 0x00510050},
1744{10100000, DIF_BPF_COEFF89, 0xff9dff18},
1745{10100000, DIF_BPF_COEFF1011, 0xfffc0184},
1746{10100000, DIF_BPF_COEFF1213, 0x0128fe80},
1747{10100000, DIF_BPF_COEFF1415, 0xfd32002e},
1748{10100000, DIF_BPF_COEFF1617, 0x04130292},
1749{10100000, DIF_BPF_COEFF1819, 0xfc4dfa21},
1750{10100000, DIF_BPF_COEFF2021, 0x00d107ee},
1751{10100000, DIF_BPF_COEFF2223, 0x0435f91c},
1752{10100000, DIF_BPF_COEFF2425, 0xf6850205},
1753{10100000, DIF_BPF_COEFF2627, 0x0c430573},
1754{10100000, DIF_BPF_COEFF2829, 0xf5a1f37d},
1755{10100000, DIF_BPF_COEFF3031, 0x03990fba},
1756{10100000, DIF_BPF_COEFF3233, 0x05c7f2f8},
1757{10100000, DIF_BPF_COEFF3435, 0xf222050d},
1758{10100000, DIF_BPF_COEFF36, 0x110d0000},
1759/* END - DIF BPF register values from 101_quant.dat*/
1760
1761
1762/*case 10200000:*/
1763/* BEGIN - DIF BPF register values from 102_quant.dat*/
1764{10200000, DIF_BPF_COEFF01, 0x00000002},
1765{10200000, DIF_BPF_COEFF23, 0x0008fffe},
1766{10200000, DIF_BPF_COEFF45, 0xffdfffe7},
1767{10200000, DIF_BPF_COEFF67, 0x003f006e},
1768{10200000, DIF_BPF_COEFF89, 0xffd6ff0f},
1769{10200000, DIF_BPF_COEFF1011, 0xff96014a},
1770{10200000, DIF_BPF_COEFF1213, 0x0197ff1f},
1771{10200000, DIF_BPF_COEFF1415, 0xfd05ff3e},
1772{10200000, DIF_BPF_COEFF1617, 0x03b0037c},
1773{10200000, DIF_BPF_COEFF1819, 0xfd59f9b7},
1774{10200000, DIF_BPF_COEFF2021, 0xff5d0781},
1775{10200000, DIF_BPF_COEFF2223, 0x0585fa56},
1776{10200000, DIF_BPF_COEFF2425, 0xf5e4006f},
1777{10200000, DIF_BPF_COEFF2627, 0x0bf906c4},
1778{10200000, DIF_BPF_COEFF2829, 0xf69df2e0},
1779{10200000, DIF_BPF_COEFF3031, 0x02790fa2},
1780{10200000, DIF_BPF_COEFF3233, 0x0688f35d},
1781{10200000, DIF_BPF_COEFF3435, 0xf1e604d8},
1782{10200000, DIF_BPF_COEFF36, 0x110d0000},
1783/* END - DIF BPF register values from 102_quant.dat*/
1784
1785
1786/*case 10300000:*/
1787/* BEGIN - DIF BPF register values from 103_quant.dat*/
1788{10300000, DIF_BPF_COEFF01, 0xffff0001},
1789{10300000, DIF_BPF_COEFF23, 0x00090005},
1790{10300000, DIF_BPF_COEFF45, 0xffe4ffd6},
1791{10300000, DIF_BPF_COEFF67, 0x0025007e},
1792{10300000, DIF_BPF_COEFF89, 0x0014ff20},
1793{10300000, DIF_BPF_COEFF1011, 0xff3c00f0},
1794{10300000, DIF_BPF_COEFF1213, 0x01e1ffd0},
1795{10300000, DIF_BPF_COEFF1415, 0xfd12fe5c},
1796{10300000, DIF_BPF_COEFF1617, 0x03110433},
1797{10300000, DIF_BPF_COEFF1819, 0xfe88f996},
1798{10300000, DIF_BPF_COEFF2021, 0xfdf106d1},
1799{10300000, DIF_BPF_COEFF2223, 0x06aafbb7},
1800{10300000, DIF_BPF_COEFF2425, 0xf57efed8},
1801{10300000, DIF_BPF_COEFF2627, 0x0b7e07ff},
1802{10300000, DIF_BPF_COEFF2829, 0xf7b0f25e},
1803{10300000, DIF_BPF_COEFF3031, 0x01560f7a},
1804{10300000, DIF_BPF_COEFF3233, 0x0745f3c7},
1805{10300000, DIF_BPF_COEFF3435, 0xf1ac04a4},
1806{10300000, DIF_BPF_COEFF36, 0x110d0000},
1807/* END - DIF BPF register values from 103_quant.dat*/
1808
1809
1810/*case 10400000:*/
1811/* BEGIN - DIF BPF register values from 104_quant.dat*/
1812{10400000, DIF_BPF_COEFF01, 0xffffffff},
1813{10400000, DIF_BPF_COEFF23, 0x0008000c},
1814{10400000, DIF_BPF_COEFF45, 0xffedffcb},
1815{10400000, DIF_BPF_COEFF67, 0x0005007d},
1816{10400000, DIF_BPF_COEFF89, 0x0050ff4c},
1817{10400000, DIF_BPF_COEFF1011, 0xfef6007e},
1818{10400000, DIF_BPF_COEFF1213, 0x01ff0086},
1819{10400000, DIF_BPF_COEFF1415, 0xfd58fd97},
1820{10400000, DIF_BPF_COEFF1617, 0x024104ad},
1821{10400000, DIF_BPF_COEFF1819, 0xffcaf9c0},
1822{10400000, DIF_BPF_COEFF2021, 0xfc9905e2},
1823{10400000, DIF_BPF_COEFF2223, 0x079afd35},
1824{10400000, DIF_BPF_COEFF2425, 0xf555fd46},
1825{10400000, DIF_BPF_COEFF2627, 0x0ad50920},
1826{10400000, DIF_BPF_COEFF2829, 0xf8d9f1f6},
1827{10400000, DIF_BPF_COEFF3031, 0x00310f43},
1828{10400000, DIF_BPF_COEFF3233, 0x07fdf435},
1829{10400000, DIF_BPF_COEFF3435, 0xf174046f},
1830{10400000, DIF_BPF_COEFF36, 0x110d0000},
1831/* END - DIF BPF register values from 104_quant.dat*/
1832
1833
1834/*case 10500000:*/
1835/* BEGIN - DIF BPF register values from 105_quant.dat*/
1836{10500000, DIF_BPF_COEFF01, 0xfffffffe},
1837{10500000, DIF_BPF_COEFF23, 0x00050011},
1838{10500000, DIF_BPF_COEFF45, 0xfffaffc8},
1839{10500000, DIF_BPF_COEFF67, 0xffe5006b},
1840{10500000, DIF_BPF_COEFF89, 0x0082ff8c},
1841{10500000, DIF_BPF_COEFF1011, 0xfecc0000},
1842{10500000, DIF_BPF_COEFF1213, 0x01f00130},
1843{10500000, DIF_BPF_COEFF1415, 0xfdd2fcfc},
1844{10500000, DIF_BPF_COEFF1617, 0x014d04e3},
1845{10500000, DIF_BPF_COEFF1819, 0x010efa32},
1846{10500000, DIF_BPF_COEFF2021, 0xfb6404bf},
1847{10500000, DIF_BPF_COEFF2223, 0x084efec5},
1848{10500000, DIF_BPF_COEFF2425, 0xf569fbc2},
1849{10500000, DIF_BPF_COEFF2627, 0x0a000a23},
1850{10500000, DIF_BPF_COEFF2829, 0xfa15f1ab},
1851{10500000, DIF_BPF_COEFF3031, 0xff0b0efc},
1852{10500000, DIF_BPF_COEFF3233, 0x08b0f4a7},
1853{10500000, DIF_BPF_COEFF3435, 0xf13f043a},
1854{10500000, DIF_BPF_COEFF36, 0x110d0000},
1855/* END - DIF BPF register values from 105_quant.dat*/
1856
1857
1858/*case 10600000:*/
1859/* BEGIN - DIF BPF register values from 106_quant.dat*/
1860{10600000, DIF_BPF_COEFF01, 0x0000fffd},
1861{10600000, DIF_BPF_COEFF23, 0x00020012},
1862{10600000, DIF_BPF_COEFF45, 0x0007ffcd},
1863{10600000, DIF_BPF_COEFF67, 0xffc9004c},
1864{10600000, DIF_BPF_COEFF89, 0x00a4ffd9},
1865{10600000, DIF_BPF_COEFF1011, 0xfec3ff82},
1866{10600000, DIF_BPF_COEFF1213, 0x01b401c1},
1867{10600000, DIF_BPF_COEFF1415, 0xfe76fc97},
1868{10600000, DIF_BPF_COEFF1617, 0x004404d2},
1869{10600000, DIF_BPF_COEFF1819, 0x0245fae8},
1870{10600000, DIF_BPF_COEFF2021, 0xfa5f0370},
1871{10600000, DIF_BPF_COEFF2223, 0x08c1005f},
1872{10600000, DIF_BPF_COEFF2425, 0xf5bcfa52},
1873{10600000, DIF_BPF_COEFF2627, 0x09020b04},
1874{10600000, DIF_BPF_COEFF2829, 0xfb60f17b},
1875{10600000, DIF_BPF_COEFF3031, 0xfde70ea6},
1876{10600000, DIF_BPF_COEFF3233, 0x095df51e},
1877{10600000, DIF_BPF_COEFF3435, 0xf10c0405},
1878{10600000, DIF_BPF_COEFF36, 0x110d0000},
1879/* END - DIF BPF register values from 106_quant.dat*/
1880
1881
1882/*case 10700000:*/
1883/* BEGIN - DIF BPF register values from 107_quant.dat*/
1884{10700000, DIF_BPF_COEFF01, 0x0000fffd},
1885{10700000, DIF_BPF_COEFF23, 0xffff0011},
1886{10700000, DIF_BPF_COEFF45, 0x0014ffdb},
1887{10700000, DIF_BPF_COEFF67, 0xffb40023},
1888{10700000, DIF_BPF_COEFF89, 0x00b2002a},
1889{10700000, DIF_BPF_COEFF1011, 0xfedbff10},
1890{10700000, DIF_BPF_COEFF1213, 0x0150022d},
1891{10700000, DIF_BPF_COEFF1415, 0xff38fc6f},
1892{10700000, DIF_BPF_COEFF1617, 0xff36047b},
1893{10700000, DIF_BPF_COEFF1819, 0x035efbda},
1894{10700000, DIF_BPF_COEFF2021, 0xf9940202},
1895{10700000, DIF_BPF_COEFF2223, 0x08ee01f5},
1896{10700000, DIF_BPF_COEFF2425, 0xf649f8fe},
1897{10700000, DIF_BPF_COEFF2627, 0x07e10bc2},
1898{10700000, DIF_BPF_COEFF2829, 0xfcb6f169},
1899{10700000, DIF_BPF_COEFF3031, 0xfcc60e42},
1900{10700000, DIF_BPF_COEFF3233, 0x0a04f599},
1901{10700000, DIF_BPF_COEFF3435, 0xf0db03d0},
1902{10700000, DIF_BPF_COEFF36, 0x110d0000},
1903/* END - DIF BPF register values from 107_quant.dat*/
1904
1905
1906/*case 10800000:*/
1907/* BEGIN - DIF BPF register values from 108_quant.dat*/
1908{10800000, DIF_BPF_COEFF01, 0x0000fffd},
1909{10800000, DIF_BPF_COEFF23, 0xfffb000d},
1910{10800000, DIF_BPF_COEFF45, 0x001dffed},
1911{10800000, DIF_BPF_COEFF67, 0xffaafff5},
1912{10800000, DIF_BPF_COEFF89, 0x00aa0077},
1913{10800000, DIF_BPF_COEFF1011, 0xff13feb6},
1914{10800000, DIF_BPF_COEFF1213, 0x00ce026b},
1915{10800000, DIF_BPF_COEFF1415, 0x000afc85},
1916{10800000, DIF_BPF_COEFF1617, 0xfe3503e3},
1917{10800000, DIF_BPF_COEFF1819, 0x044cfcfb},
1918{10800000, DIF_BPF_COEFF2021, 0xf90c0082},
1919{10800000, DIF_BPF_COEFF2223, 0x08d5037f},
1920{10800000, DIF_BPF_COEFF2425, 0xf710f7cc},
1921{10800000, DIF_BPF_COEFF2627, 0x069f0c59},
1922{10800000, DIF_BPF_COEFF2829, 0xfe16f173},
1923{10800000, DIF_BPF_COEFF3031, 0xfbaa0dcf},
1924{10800000, DIF_BPF_COEFF3233, 0x0aa5f617},
1925{10800000, DIF_BPF_COEFF3435, 0xf0ad039b},
1926{10800000, DIF_BPF_COEFF36, 0x110d0000},
1927/* END - DIF BPF register values from 108_quant.dat*/
1928
1929
1930/*case 10900000:*/
1931/* BEGIN - DIF BPF register values from 109_quant.dat*/
1932{10900000, DIF_BPF_COEFF01, 0x0000fffe},
1933{10900000, DIF_BPF_COEFF23, 0xfff90006},
1934{10900000, DIF_BPF_COEFF45, 0x00210003},
1935{10900000, DIF_BPF_COEFF67, 0xffacffc8},
1936{10900000, DIF_BPF_COEFF89, 0x008e00b6},
1937{10900000, DIF_BPF_COEFF1011, 0xff63fe7c},
1938{10900000, DIF_BPF_COEFF1213, 0x003a0275},
1939{10900000, DIF_BPF_COEFF1415, 0x00dafcda},
1940{10900000, DIF_BPF_COEFF1617, 0xfd510313},
1941{10900000, DIF_BPF_COEFF1819, 0x0501fe40},
1942{10900000, DIF_BPF_COEFF2021, 0xf8cbfefd},
1943{10900000, DIF_BPF_COEFF2223, 0x087604f0},
1944{10900000, DIF_BPF_COEFF2425, 0xf80af6c2},
1945{10900000, DIF_BPF_COEFF2627, 0x05430cc8},
1946{10900000, DIF_BPF_COEFF2829, 0xff7af19a},
1947{10900000, DIF_BPF_COEFF3031, 0xfa940d4e},
1948{10900000, DIF_BPF_COEFF3233, 0x0b3ff699},
1949{10900000, DIF_BPF_COEFF3435, 0xf0810365},
1950{10900000, DIF_BPF_COEFF36, 0x110d0000},
1951/* END - DIF BPF register values from 109_quant.dat*/
1952
1953
1954/*case 11000000:*/
1955/* BEGIN - DIF BPF register values from 110_quant.dat*/
1956{11000000, DIF_BPF_COEFF01, 0x0001ffff},
1957{11000000, DIF_BPF_COEFF23, 0xfff8ffff},
1958{11000000, DIF_BPF_COEFF45, 0x00210018},
1959{11000000, DIF_BPF_COEFF67, 0xffbaffa3},
1960{11000000, DIF_BPF_COEFF89, 0x006000e1},
1961{11000000, DIF_BPF_COEFF1011, 0xffc4fe68},
1962{11000000, DIF_BPF_COEFF1213, 0xffa0024b},
1963{11000000, DIF_BPF_COEFF1415, 0x019afd66},
1964{11000000, DIF_BPF_COEFF1617, 0xfc990216},
1965{11000000, DIF_BPF_COEFF1819, 0x0575ff99},
1966{11000000, DIF_BPF_COEFF2021, 0xf8d4fd81},
1967{11000000, DIF_BPF_COEFF2223, 0x07d40640},
1968{11000000, DIF_BPF_COEFF2425, 0xf932f5e6},
1969{11000000, DIF_BPF_COEFF2627, 0x03d20d0d},
1970{11000000, DIF_BPF_COEFF2829, 0x00dff1de},
1971{11000000, DIF_BPF_COEFF3031, 0xf9860cbf},
1972{11000000, DIF_BPF_COEFF3233, 0x0bd1f71e},
1973{11000000, DIF_BPF_COEFF3435, 0xf058032f},
1974{11000000, DIF_BPF_COEFF36, 0x110d0000},
1975/* END - DIF BPF register values from 110_quant.dat*/
1976
1977
1978/*case 11100000:*/
1979/* BEGIN - DIF BPF register values from 111_quant.dat*/
1980{11100000, DIF_BPF_COEFF01, 0x00010000},
1981{11100000, DIF_BPF_COEFF23, 0xfff8fff8},
1982{11100000, DIF_BPF_COEFF45, 0x001b0029},
1983{11100000, DIF_BPF_COEFF67, 0xffd1ff8a},
1984{11100000, DIF_BPF_COEFF89, 0x002600f2},
1985{11100000, DIF_BPF_COEFF1011, 0x002cfe7c},
1986{11100000, DIF_BPF_COEFF1213, 0xff0f01f0},
1987{11100000, DIF_BPF_COEFF1415, 0x023bfe20},
1988{11100000, DIF_BPF_COEFF1617, 0xfc1700fa},
1989{11100000, DIF_BPF_COEFF1819, 0x05a200f7},
1990{11100000, DIF_BPF_COEFF2021, 0xf927fc1c},
1991{11100000, DIF_BPF_COEFF2223, 0x06f40765},
1992{11100000, DIF_BPF_COEFF2425, 0xfa82f53b},
1993{11100000, DIF_BPF_COEFF2627, 0x02510d27},
1994{11100000, DIF_BPF_COEFF2829, 0x0243f23d},
1995{11100000, DIF_BPF_COEFF3031, 0xf8810c24},
1996{11100000, DIF_BPF_COEFF3233, 0x0c5cf7a7},
1997{11100000, DIF_BPF_COEFF3435, 0xf03102fa},
1998{11100000, DIF_BPF_COEFF36, 0x110d0000},
1999/* END - DIF BPF register values from 111_quant.dat*/
2000
2001
2002/*case 11200000:*/
2003/* BEGIN - DIF BPF register values from 112_quant.dat*/
2004{11200000, DIF_BPF_COEFF01, 0x00010002},
2005{11200000, DIF_BPF_COEFF23, 0xfffafff2},
2006{11200000, DIF_BPF_COEFF45, 0x00110035},
2007{11200000, DIF_BPF_COEFF67, 0xfff0ff81},
2008{11200000, DIF_BPF_COEFF89, 0xffe700e7},
2009{11200000, DIF_BPF_COEFF1011, 0x008ffeb6},
2010{11200000, DIF_BPF_COEFF1213, 0xfe94016d},
2011{11200000, DIF_BPF_COEFF1415, 0x02b0fefb},
2012{11200000, DIF_BPF_COEFF1617, 0xfbd3ffd1},
2013{11200000, DIF_BPF_COEFF1819, 0x05850249},
2014{11200000, DIF_BPF_COEFF2021, 0xf9c1fadb},
2015{11200000, DIF_BPF_COEFF2223, 0x05de0858},
2016{11200000, DIF_BPF_COEFF2425, 0xfbf2f4c4},
2017{11200000, DIF_BPF_COEFF2627, 0x00c70d17},
2018{11200000, DIF_BPF_COEFF2829, 0x03a0f2b8},
2019{11200000, DIF_BPF_COEFF3031, 0xf7870b7c},
2020{11200000, DIF_BPF_COEFF3233, 0x0cdff833},
2021{11200000, DIF_BPF_COEFF3435, 0xf00d02c4},
2022{11200000, DIF_BPF_COEFF36, 0x110d0000},
2023/* END - DIF BPF register values from 112_quant.dat*/
2024
2025
2026/*case 11300000:*/
2027/* BEGIN - DIF BPF register values from 113_quant.dat*/
2028{11300000, DIF_BPF_COEFF01, 0x00000003},
2029{11300000, DIF_BPF_COEFF23, 0xfffdffee},
2030{11300000, DIF_BPF_COEFF45, 0x00040038},
2031{11300000, DIF_BPF_COEFF67, 0x0010ff88},
2032{11300000, DIF_BPF_COEFF89, 0xffac00c2},
2033{11300000, DIF_BPF_COEFF1011, 0x00e2ff10},
2034{11300000, DIF_BPF_COEFF1213, 0xfe3900cb},
2035{11300000, DIF_BPF_COEFF1415, 0x02f1ffe9},
2036{11300000, DIF_BPF_COEFF1617, 0xfbd3feaa},
2037{11300000, DIF_BPF_COEFF1819, 0x05210381},
2038{11300000, DIF_BPF_COEFF2021, 0xfa9cf9c8},
2039{11300000, DIF_BPF_COEFF2223, 0x04990912},
2040{11300000, DIF_BPF_COEFF2425, 0xfd7af484},
2041{11300000, DIF_BPF_COEFF2627, 0xff390cdb},
2042{11300000, DIF_BPF_COEFF2829, 0x04f4f34d},
2043{11300000, DIF_BPF_COEFF3031, 0xf69a0ac9},
2044{11300000, DIF_BPF_COEFF3233, 0x0d5af8c1},
2045{11300000, DIF_BPF_COEFF3435, 0xefec028e},
2046{11300000, DIF_BPF_COEFF36, 0x110d0000},
2047/* END - DIF BPF register values from 113_quant.dat*/
2048
2049
2050/*case 11400000:*/
2051/* BEGIN - DIF BPF register values from 114_quant.dat*/
2052{11400000, DIF_BPF_COEFF01, 0x00000003},
2053{11400000, DIF_BPF_COEFF23, 0x0000ffee},
2054{11400000, DIF_BPF_COEFF45, 0xfff60033},
2055{11400000, DIF_BPF_COEFF67, 0x002fff9f},
2056{11400000, DIF_BPF_COEFF89, 0xff7b0087},
2057{11400000, DIF_BPF_COEFF1011, 0x011eff82},
2058{11400000, DIF_BPF_COEFF1213, 0xfe080018},
2059{11400000, DIF_BPF_COEFF1415, 0x02f900d8},
2060{11400000, DIF_BPF_COEFF1617, 0xfc17fd96},
2061{11400000, DIF_BPF_COEFF1819, 0x04790490},
2062{11400000, DIF_BPF_COEFF2021, 0xfbadf8ed},
2063{11400000, DIF_BPF_COEFF2223, 0x032f098e},
2064{11400000, DIF_BPF_COEFF2425, 0xff10f47d},
2065{11400000, DIF_BPF_COEFF2627, 0xfdaf0c75},
2066{11400000, DIF_BPF_COEFF2829, 0x063cf3fc},
2067{11400000, DIF_BPF_COEFF3031, 0xf5ba0a0b},
2068{11400000, DIF_BPF_COEFF3233, 0x0dccf952},
2069{11400000, DIF_BPF_COEFF3435, 0xefcd0258},
2070{11400000, DIF_BPF_COEFF36, 0x110d0000},
2071/* END - DIF BPF register values from 114_quant.dat*/
2072
2073
2074/*case 11500000:*/
2075/* BEGIN - DIF BPF register values from 115_quant.dat*/
2076{11500000, DIF_BPF_COEFF01, 0x00000003},
2077{11500000, DIF_BPF_COEFF23, 0x0004fff1},
2078{11500000, DIF_BPF_COEFF45, 0xffea0026},
2079{11500000, DIF_BPF_COEFF67, 0x0046ffc3},
2080{11500000, DIF_BPF_COEFF89, 0xff5a003c},
2081{11500000, DIF_BPF_COEFF1011, 0x013b0000},
2082{11500000, DIF_BPF_COEFF1213, 0xfe04ff63},
2083{11500000, DIF_BPF_COEFF1415, 0x02c801b8},
2084{11500000, DIF_BPF_COEFF1617, 0xfc99fca6},
2085{11500000, DIF_BPF_COEFF1819, 0x0397056a},
2086{11500000, DIF_BPF_COEFF2021, 0xfcecf853},
2087{11500000, DIF_BPF_COEFF2223, 0x01ad09c9},
2088{11500000, DIF_BPF_COEFF2425, 0x00acf4ad},
2089{11500000, DIF_BPF_COEFF2627, 0xfc2e0be7},
2090{11500000, DIF_BPF_COEFF2829, 0x0773f4c2},
2091{11500000, DIF_BPF_COEFF3031, 0xf4e90943},
2092{11500000, DIF_BPF_COEFF3233, 0x0e35f9e6},
2093{11500000, DIF_BPF_COEFF3435, 0xefb10221},
2094{11500000, DIF_BPF_COEFF36, 0x110d0000},
2095/* END - DIF BPF register values from 115_quant.dat*/
2096
2097
2098/*case 11600000:*/
2099/* BEGIN - DIF BPF register values from 116_quant.dat*/
2100{11600000, DIF_BPF_COEFF01, 0x00000002},
2101{11600000, DIF_BPF_COEFF23, 0x0007fff6},
2102{11600000, DIF_BPF_COEFF45, 0xffe20014},
2103{11600000, DIF_BPF_COEFF67, 0x0054ffee},
2104{11600000, DIF_BPF_COEFF89, 0xff4effeb},
2105{11600000, DIF_BPF_COEFF1011, 0x0137007e},
2106{11600000, DIF_BPF_COEFF1213, 0xfe2efebb},
2107{11600000, DIF_BPF_COEFF1415, 0x0260027a},
2108{11600000, DIF_BPF_COEFF1617, 0xfd51fbe6},
2109{11600000, DIF_BPF_COEFF1819, 0x02870605},
2110{11600000, DIF_BPF_COEFF2021, 0xfe4af7fe},
2111{11600000, DIF_BPF_COEFF2223, 0x001d09c1},
2112{11600000, DIF_BPF_COEFF2425, 0x0243f515},
2113{11600000, DIF_BPF_COEFF2627, 0xfabd0b32},
2114{11600000, DIF_BPF_COEFF2829, 0x0897f59e},
2115{11600000, DIF_BPF_COEFF3031, 0xf4280871},
2116{11600000, DIF_BPF_COEFF3233, 0x0e95fa7c},
2117{11600000, DIF_BPF_COEFF3435, 0xef9701eb},
2118{11600000, DIF_BPF_COEFF36, 0x110d0000},
2119/* END - DIF BPF register values from 116_quant.dat*/
2120
2121
2122/*case 11700000:*/
2123/* BEGIN - DIF BPF register values from 117_quant.dat*/
2124{11700000, DIF_BPF_COEFF01, 0xffff0001},
2125{11700000, DIF_BPF_COEFF23, 0x0008fffd},
2126{11700000, DIF_BPF_COEFF45, 0xffdeffff},
2127{11700000, DIF_BPF_COEFF67, 0x0056001d},
2128{11700000, DIF_BPF_COEFF89, 0xff57ff9c},
2129{11700000, DIF_BPF_COEFF1011, 0x011300f0},
2130{11700000, DIF_BPF_COEFF1213, 0xfe82fe2e},
2131{11700000, DIF_BPF_COEFF1415, 0x01ca0310},
2132{11700000, DIF_BPF_COEFF1617, 0xfe35fb62},
2133{11700000, DIF_BPF_COEFF1819, 0x0155065a},
2134{11700000, DIF_BPF_COEFF2021, 0xffbaf7f2},
2135{11700000, DIF_BPF_COEFF2223, 0xfe8c0977},
2136{11700000, DIF_BPF_COEFF2425, 0x03cef5b2},
2137{11700000, DIF_BPF_COEFF2627, 0xf9610a58},
2138{11700000, DIF_BPF_COEFF2829, 0x09a5f68f},
2139{11700000, DIF_BPF_COEFF3031, 0xf3790797},
2140{11700000, DIF_BPF_COEFF3233, 0x0eebfb14},
2141{11700000, DIF_BPF_COEFF3435, 0xef8001b5},
2142{11700000, DIF_BPF_COEFF36, 0x110d0000},
2143/* END - DIF BPF register values from 117_quant.dat*/
2144
2145
2146/*case 11800000:*/
2147/* BEGIN - DIF BPF register values from 118_quant.dat*/
2148{11800000, DIF_BPF_COEFF01, 0xffff0000},
2149{11800000, DIF_BPF_COEFF23, 0x00080004},
2150{11800000, DIF_BPF_COEFF45, 0xffe0ffe9},
2151{11800000, DIF_BPF_COEFF67, 0x004c0047},
2152{11800000, DIF_BPF_COEFF89, 0xff75ff58},
2153{11800000, DIF_BPF_COEFF1011, 0x00d1014a},
2154{11800000, DIF_BPF_COEFF1213, 0xfef9fdc8},
2155{11800000, DIF_BPF_COEFF1415, 0x0111036f},
2156{11800000, DIF_BPF_COEFF1617, 0xff36fb21},
2157{11800000, DIF_BPF_COEFF1819, 0x00120665},
2158{11800000, DIF_BPF_COEFF2021, 0x012df82e},
2159{11800000, DIF_BPF_COEFF2223, 0xfd0708ec},
2160{11800000, DIF_BPF_COEFF2425, 0x0542f682},
2161{11800000, DIF_BPF_COEFF2627, 0xf81f095c},
2162{11800000, DIF_BPF_COEFF2829, 0x0a9af792},
2163{11800000, DIF_BPF_COEFF3031, 0xf2db06b5},
2164{11800000, DIF_BPF_COEFF3233, 0x0f38fbad},
2165{11800000, DIF_BPF_COEFF3435, 0xef6c017e},
2166{11800000, DIF_BPF_COEFF36, 0x110d0000},
2167/* END - DIF BPF register values from 118_quant.dat*/
2168
2169
2170/*case 11900000:*/
2171/* BEGIN - DIF BPF register values from 119_quant.dat*/
2172{11900000, DIF_BPF_COEFF01, 0xffffffff},
2173{11900000, DIF_BPF_COEFF23, 0x0007000b},
2174{11900000, DIF_BPF_COEFF45, 0xffe7ffd8},
2175{11900000, DIF_BPF_COEFF67, 0x00370068},
2176{11900000, DIF_BPF_COEFF89, 0xffa4ff28},
2177{11900000, DIF_BPF_COEFF1011, 0x00790184},
2178{11900000, DIF_BPF_COEFF1213, 0xff87fd91},
2179{11900000, DIF_BPF_COEFF1415, 0x00430392},
2180{11900000, DIF_BPF_COEFF1617, 0x0044fb26},
2181{11900000, DIF_BPF_COEFF1819, 0xfece0626},
2182{11900000, DIF_BPF_COEFF2021, 0x0294f8b2},
2183{11900000, DIF_BPF_COEFF2223, 0xfb990825},
2184{11900000, DIF_BPF_COEFF2425, 0x0698f77f},
2185{11900000, DIF_BPF_COEFF2627, 0xf6fe0842},
2186{11900000, DIF_BPF_COEFF2829, 0x0b73f8a7},
2187{11900000, DIF_BPF_COEFF3031, 0xf25105cd},
2188{11900000, DIF_BPF_COEFF3233, 0x0f7bfc48},
2189{11900000, DIF_BPF_COEFF3435, 0xef5a0148},
2190{11900000, DIF_BPF_COEFF36, 0x110d0000},
2191/* END - DIF BPF register values from 119_quant.dat*/
2192
2193
2194/*case 12000000:*/
2195/* BEGIN - DIF BPF register values from 120_quant.dat*/
2196{12000000, DIF_BPF_COEFF01, 0x0000fffe},
2197{12000000, DIF_BPF_COEFF23, 0x00050010},
2198{12000000, DIF_BPF_COEFF45, 0xfff2ffcc},
2199{12000000, DIF_BPF_COEFF67, 0x001b007b},
2200{12000000, DIF_BPF_COEFF89, 0xffdfff10},
2201{12000000, DIF_BPF_COEFF1011, 0x00140198},
2202{12000000, DIF_BPF_COEFF1213, 0x0020fd8e},
2203{12000000, DIF_BPF_COEFF1415, 0xff710375},
2204{12000000, DIF_BPF_COEFF1617, 0x014dfb73},
2205{12000000, DIF_BPF_COEFF1819, 0xfd9a059f},
2206{12000000, DIF_BPF_COEFF2021, 0x03e0f978},
2207{12000000, DIF_BPF_COEFF2223, 0xfa4e0726},
2208{12000000, DIF_BPF_COEFF2425, 0x07c8f8a7},
2209{12000000, DIF_BPF_COEFF2627, 0xf600070c},
2210{12000000, DIF_BPF_COEFF2829, 0x0c2ff9c9},
2211{12000000, DIF_BPF_COEFF3031, 0xf1db04de},
2212{12000000, DIF_BPF_COEFF3233, 0x0fb4fce5},
2213{12000000, DIF_BPF_COEFF3435, 0xef4b0111},
2214{12000000, DIF_BPF_COEFF36, 0x110d0000},
2215/* END - DIF BPF register values from 120_quant.dat*/
2216
2217
2218/*case 12100000:*/
2219/* BEGIN - DIF BPF register values from 121_quant.dat*/
2220{12100000, DIF_BPF_COEFF01, 0x0000fffd},
2221{12100000, DIF_BPF_COEFF23, 0x00010012},
2222{12100000, DIF_BPF_COEFF45, 0xffffffc8},
2223{12100000, DIF_BPF_COEFF67, 0xfffb007e},
2224{12100000, DIF_BPF_COEFF89, 0x001dff14},
2225{12100000, DIF_BPF_COEFF1011, 0xffad0184},
2226{12100000, DIF_BPF_COEFF1213, 0x00b7fdbe},
2227{12100000, DIF_BPF_COEFF1415, 0xfea9031b},
2228{12100000, DIF_BPF_COEFF1617, 0x0241fc01},
2229{12100000, DIF_BPF_COEFF1819, 0xfc8504d6},
2230{12100000, DIF_BPF_COEFF2021, 0x0504fa79},
2231{12100000, DIF_BPF_COEFF2223, 0xf93005f6},
2232{12100000, DIF_BPF_COEFF2425, 0x08caf9f2},
2233{12100000, DIF_BPF_COEFF2627, 0xf52b05c0},
2234{12100000, DIF_BPF_COEFF2829, 0x0ccbfaf9},
2235{12100000, DIF_BPF_COEFF3031, 0xf17903eb},
2236{12100000, DIF_BPF_COEFF3233, 0x0fe3fd83},
2237{12100000, DIF_BPF_COEFF3435, 0xef3f00db},
2238{12100000, DIF_BPF_COEFF36, 0x110d0000},
2239/* END - DIF BPF register values from 121_quant.dat*/
2240
2241
2242/*case 12200000:*/
2243/* BEGIN - DIF BPF register values from 122_quant.dat*/
2244{12200000, DIF_BPF_COEFF01, 0x0000fffd},
2245{12200000, DIF_BPF_COEFF23, 0xfffe0011},
2246{12200000, DIF_BPF_COEFF45, 0x000cffcc},
2247{12200000, DIF_BPF_COEFF67, 0xffdb0071},
2248{12200000, DIF_BPF_COEFF89, 0x0058ff32},
2249{12200000, DIF_BPF_COEFF1011, 0xff4f014a},
2250{12200000, DIF_BPF_COEFF1213, 0x013cfe1f},
2251{12200000, DIF_BPF_COEFF1415, 0xfdfb028a},
2252{12200000, DIF_BPF_COEFF1617, 0x0311fcc9},
2253{12200000, DIF_BPF_COEFF1819, 0xfb9d03d6},
2254{12200000, DIF_BPF_COEFF2021, 0x05f4fbad},
2255{12200000, DIF_BPF_COEFF2223, 0xf848049d},
2256{12200000, DIF_BPF_COEFF2425, 0x0999fb5b},
2257{12200000, DIF_BPF_COEFF2627, 0xf4820461},
2258{12200000, DIF_BPF_COEFF2829, 0x0d46fc32},
2259{12200000, DIF_BPF_COEFF3031, 0xf12d02f4},
2260{12200000, DIF_BPF_COEFF3233, 0x1007fe21},
2261{12200000, DIF_BPF_COEFF3435, 0xef3600a4},
2262{12200000, DIF_BPF_COEFF36, 0x110d0000},
2263/* END - DIF BPF register values from 122_quant.dat*/
2264
2265
2266/*case 12300000:*/
2267/* BEGIN - DIF BPF register values from 123_quant.dat*/
2268{12300000, DIF_BPF_COEFF01, 0x0000fffe},
2269{12300000, DIF_BPF_COEFF23, 0xfffa000e},
2270{12300000, DIF_BPF_COEFF45, 0x0017ffd9},
2271{12300000, DIF_BPF_COEFF67, 0xffc10055},
2272{12300000, DIF_BPF_COEFF89, 0x0088ff68},
2273{12300000, DIF_BPF_COEFF1011, 0xff0400f0},
2274{12300000, DIF_BPF_COEFF1213, 0x01a6fea7},
2275{12300000, DIF_BPF_COEFF1415, 0xfd7501cc},
2276{12300000, DIF_BPF_COEFF1617, 0x03b0fdc0},
2277{12300000, DIF_BPF_COEFF1819, 0xfaef02a8},
2278{12300000, DIF_BPF_COEFF2021, 0x06a7fd07},
2279{12300000, DIF_BPF_COEFF2223, 0xf79d0326},
2280{12300000, DIF_BPF_COEFF2425, 0x0a31fcda},
2281{12300000, DIF_BPF_COEFF2627, 0xf40702f3},
2282{12300000, DIF_BPF_COEFF2829, 0x0d9ffd72},
2283{12300000, DIF_BPF_COEFF3031, 0xf0f601fa},
2284{12300000, DIF_BPF_COEFF3233, 0x1021fec0},
2285{12300000, DIF_BPF_COEFF3435, 0xef2f006d},
2286{12300000, DIF_BPF_COEFF36, 0x110d0000},
2287/* END - DIF BPF register values from 123_quant.dat*/
2288
2289
2290/*case 12400000:*/
2291/* BEGIN - DIF BPF register values from 124_quant.dat*/
2292{12400000, DIF_BPF_COEFF01, 0x0001ffff},
2293{12400000, DIF_BPF_COEFF23, 0xfff80007},
2294{12400000, DIF_BPF_COEFF45, 0x001fffeb},
2295{12400000, DIF_BPF_COEFF67, 0xffaf002d},
2296{12400000, DIF_BPF_COEFF89, 0x00a8ffb0},
2297{12400000, DIF_BPF_COEFF1011, 0xfed3007e},
2298{12400000, DIF_BPF_COEFF1213, 0x01e9ff4c},
2299{12400000, DIF_BPF_COEFF1415, 0xfd2000ee},
2300{12400000, DIF_BPF_COEFF1617, 0x0413fed8},
2301{12400000, DIF_BPF_COEFF1819, 0xfa82015c},
2302{12400000, DIF_BPF_COEFF2021, 0x0715fe7d},
2303{12400000, DIF_BPF_COEFF2223, 0xf7340198},
2304{12400000, DIF_BPF_COEFF2425, 0x0a8dfe69},
2305{12400000, DIF_BPF_COEFF2627, 0xf3bd017c},
2306{12400000, DIF_BPF_COEFF2829, 0x0dd5feb8},
2307{12400000, DIF_BPF_COEFF3031, 0xf0d500fd},
2308{12400000, DIF_BPF_COEFF3233, 0x1031ff60},
2309{12400000, DIF_BPF_COEFF3435, 0xef2b0037},
2310{12400000, DIF_BPF_COEFF36, 0x110d0000},
2311/* END - DIF BPF register values from 124_quant.dat*/
2312
2313
2314/*case 12500000:*/
2315/* BEGIN - DIF BPF register values from 125_quant.dat*/
2316{12500000, DIF_BPF_COEFF01, 0x00010000},
2317{12500000, DIF_BPF_COEFF23, 0xfff70000},
2318{12500000, DIF_BPF_COEFF45, 0x00220000},
2319{12500000, DIF_BPF_COEFF67, 0xffa90000},
2320{12500000, DIF_BPF_COEFF89, 0x00b30000},
2321{12500000, DIF_BPF_COEFF1011, 0xfec20000},
2322{12500000, DIF_BPF_COEFF1213, 0x02000000},
2323{12500000, DIF_BPF_COEFF1415, 0xfd030000},
2324{12500000, DIF_BPF_COEFF1617, 0x04350000},
2325{12500000, DIF_BPF_COEFF1819, 0xfa5e0000},
2326{12500000, DIF_BPF_COEFF2021, 0x073b0000},
2327{12500000, DIF_BPF_COEFF2223, 0xf7110000},
2328{12500000, DIF_BPF_COEFF2425, 0x0aac0000},
2329{12500000, DIF_BPF_COEFF2627, 0xf3a40000},
2330{12500000, DIF_BPF_COEFF2829, 0x0de70000},
2331{12500000, DIF_BPF_COEFF3031, 0xf0c90000},
2332{12500000, DIF_BPF_COEFF3233, 0x10360000},
2333{12500000, DIF_BPF_COEFF3435, 0xef290000},
2334{12500000, DIF_BPF_COEFF36, 0x110d0000},
2335/* END - DIF BPF register values from 125_quant.dat*/
2336
2337
2338/*case 12600000:*/
2339/* BEGIN - DIF BPF register values from 126_quant.dat*/
2340{12600000, DIF_BPF_COEFF01, 0x00010001},
2341{12600000, DIF_BPF_COEFF23, 0xfff8fff9},
2342{12600000, DIF_BPF_COEFF45, 0x001f0015},
2343{12600000, DIF_BPF_COEFF67, 0xffafffd3},
2344{12600000, DIF_BPF_COEFF89, 0x00a80050},
2345{12600000, DIF_BPF_COEFF1011, 0xfed3ff82},
2346{12600000, DIF_BPF_COEFF1213, 0x01e900b4},
2347{12600000, DIF_BPF_COEFF1415, 0xfd20ff12},
2348{12600000, DIF_BPF_COEFF1617, 0x04130128},
2349{12600000, DIF_BPF_COEFF1819, 0xfa82fea4},
2350{12600000, DIF_BPF_COEFF2021, 0x07150183},
2351{12600000, DIF_BPF_COEFF2223, 0xf734fe68},
2352{12600000, DIF_BPF_COEFF2425, 0x0a8d0197},
2353{12600000, DIF_BPF_COEFF2627, 0xf3bdfe84},
2354{12600000, DIF_BPF_COEFF2829, 0x0dd50148},
2355{12600000, DIF_BPF_COEFF3031, 0xf0d5ff03},
2356{12600000, DIF_BPF_COEFF3233, 0x103100a0},
2357{12600000, DIF_BPF_COEFF3435, 0xef2bffc9},
2358{12600000, DIF_BPF_COEFF36, 0x110d0000},
2359/* END - DIF BPF register values from 126_quant.dat*/
2360
2361
2362/*case 12700000:*/
2363/* BEGIN - DIF BPF register values from 127_quant.dat*/
2364{12700000, DIF_BPF_COEFF01, 0x00000002},
2365{12700000, DIF_BPF_COEFF23, 0xfffafff2},
2366{12700000, DIF_BPF_COEFF45, 0x00170027},
2367{12700000, DIF_BPF_COEFF67, 0xffc1ffab},
2368{12700000, DIF_BPF_COEFF89, 0x00880098},
2369{12700000, DIF_BPF_COEFF1011, 0xff04ff10},
2370{12700000, DIF_BPF_COEFF1213, 0x01a60159},
2371{12700000, DIF_BPF_COEFF1415, 0xfd75fe34},
2372{12700000, DIF_BPF_COEFF1617, 0x03b00240},
2373{12700000, DIF_BPF_COEFF1819, 0xfaeffd58},
2374{12700000, DIF_BPF_COEFF2021, 0x06a702f9},
2375{12700000, DIF_BPF_COEFF2223, 0xf79dfcda},
2376{12700000, DIF_BPF_COEFF2425, 0x0a310326},
2377{12700000, DIF_BPF_COEFF2627, 0xf407fd0d},
2378{12700000, DIF_BPF_COEFF2829, 0x0d9f028e},
2379{12700000, DIF_BPF_COEFF3031, 0xf0f6fe06},
2380{12700000, DIF_BPF_COEFF3233, 0x10210140},
2381{12700000, DIF_BPF_COEFF3435, 0xef2fff93},
2382{12700000, DIF_BPF_COEFF36, 0x110d0000},
2383/* END - DIF BPF register values from 127_quant.dat*/
2384
2385
2386/*case 12800000:*/
2387/* BEGIN - DIF BPF register values from 128_quant.dat*/
2388{12800000, DIF_BPF_COEFF01, 0x00000003},
2389{12800000, DIF_BPF_COEFF23, 0xfffeffef},
2390{12800000, DIF_BPF_COEFF45, 0x000c0034},
2391{12800000, DIF_BPF_COEFF67, 0xffdbff8f},
2392{12800000, DIF_BPF_COEFF89, 0x005800ce},
2393{12800000, DIF_BPF_COEFF1011, 0xff4ffeb6},
2394{12800000, DIF_BPF_COEFF1213, 0x013c01e1},
2395{12800000, DIF_BPF_COEFF1415, 0xfdfbfd76},
2396{12800000, DIF_BPF_COEFF1617, 0x03110337},
2397{12800000, DIF_BPF_COEFF1819, 0xfb9dfc2a},
2398{12800000, DIF_BPF_COEFF2021, 0x05f40453},
2399{12800000, DIF_BPF_COEFF2223, 0xf848fb63},
2400{12800000, DIF_BPF_COEFF2425, 0x099904a5},
2401{12800000, DIF_BPF_COEFF2627, 0xf482fb9f},
2402{12800000, DIF_BPF_COEFF2829, 0x0d4603ce},
2403{12800000, DIF_BPF_COEFF3031, 0xf12dfd0c},
2404{12800000, DIF_BPF_COEFF3233, 0x100701df},
2405{12800000, DIF_BPF_COEFF3435, 0xef36ff5c},
2406{12800000, DIF_BPF_COEFF36, 0x110d0000},
2407/* END - DIF BPF register values from 128_quant.dat*/
2408
2409
2410/*case 12900000:*/
2411/* BEGIN - DIF BPF register values from 129_quant.dat*/
2412{12900000, DIF_BPF_COEFF01, 0x00000003},
2413{12900000, DIF_BPF_COEFF23, 0x0001ffee},
2414{12900000, DIF_BPF_COEFF45, 0xffff0038},
2415{12900000, DIF_BPF_COEFF67, 0xfffbff82},
2416{12900000, DIF_BPF_COEFF89, 0x001d00ec},
2417{12900000, DIF_BPF_COEFF1011, 0xffadfe7c},
2418{12900000, DIF_BPF_COEFF1213, 0x00b70242},
2419{12900000, DIF_BPF_COEFF1415, 0xfea9fce5},
2420{12900000, DIF_BPF_COEFF1617, 0x024103ff},
2421{12900000, DIF_BPF_COEFF1819, 0xfc85fb2a},
2422{12900000, DIF_BPF_COEFF2021, 0x05040587},
2423{12900000, DIF_BPF_COEFF2223, 0xf930fa0a},
2424{12900000, DIF_BPF_COEFF2425, 0x08ca060e},
2425{12900000, DIF_BPF_COEFF2627, 0xf52bfa40},
2426{12900000, DIF_BPF_COEFF2829, 0x0ccb0507},
2427{12900000, DIF_BPF_COEFF3031, 0xf179fc15},
2428{12900000, DIF_BPF_COEFF3233, 0x0fe3027d},
2429{12900000, DIF_BPF_COEFF3435, 0xef3fff25},
2430{12900000, DIF_BPF_COEFF36, 0x110d0000},
2431/* END - DIF BPF register values from 129_quant.dat*/
2432
2433
2434/*case 113000000:*/
2435/* BEGIN - DIF BPF register values from 130_quant.dat*/
2436{13000000, DIF_BPF_COEFF01, 0x00000002},
2437{13000000, DIF_BPF_COEFF23, 0x0005fff0},
2438{13000000, DIF_BPF_COEFF45, 0xfff20034},
2439{13000000, DIF_BPF_COEFF67, 0x001bff85},
2440{13000000, DIF_BPF_COEFF89, 0xffdf00f0},
2441{13000000, DIF_BPF_COEFF1011, 0x0014fe68},
2442{13000000, DIF_BPF_COEFF1213, 0x00200272},
2443{13000000, DIF_BPF_COEFF1415, 0xff71fc8b},
2444{13000000, DIF_BPF_COEFF1617, 0x014d048d},
2445{13000000, DIF_BPF_COEFF1819, 0xfd9afa61},
2446{13000000, DIF_BPF_COEFF2021, 0x03e00688},
2447{13000000, DIF_BPF_COEFF2223, 0xfa4ef8da},
2448{13000000, DIF_BPF_COEFF2425, 0x07c80759},
2449{13000000, DIF_BPF_COEFF2627, 0xf600f8f4},
2450{13000000, DIF_BPF_COEFF2829, 0x0c2f0637},
2451{13000000, DIF_BPF_COEFF3031, 0xf1dbfb22},
2452{13000000, DIF_BPF_COEFF3233, 0x0fb4031b},
2453{13000000, DIF_BPF_COEFF3435, 0xef4bfeef},
2454{13000000, DIF_BPF_COEFF36, 0x110d0000},
2455/* END - DIF BPF register values from 130_quant.dat*/
2456
2457
2458/*case 13100000:*/
2459/* BEGIN - DIF BPF register values from 131_quant.dat*/
2460{13100000, DIF_BPF_COEFF01, 0xffff0001},
2461{13100000, DIF_BPF_COEFF23, 0x0007fff5},
2462{13100000, DIF_BPF_COEFF45, 0xffe70028},
2463{13100000, DIF_BPF_COEFF67, 0x0037ff98},
2464{13100000, DIF_BPF_COEFF89, 0xffa400d8},
2465{13100000, DIF_BPF_COEFF1011, 0x0079fe7c},
2466{13100000, DIF_BPF_COEFF1213, 0xff87026f},
2467{13100000, DIF_BPF_COEFF1415, 0x0043fc6e},
2468{13100000, DIF_BPF_COEFF1617, 0x004404da},
2469{13100000, DIF_BPF_COEFF1819, 0xfecef9da},
2470{13100000, DIF_BPF_COEFF2021, 0x0294074e},
2471{13100000, DIF_BPF_COEFF2223, 0xfb99f7db},
2472{13100000, DIF_BPF_COEFF2425, 0x06980881},
2473{13100000, DIF_BPF_COEFF2627, 0xf6fef7be},
2474{13100000, DIF_BPF_COEFF2829, 0x0b730759},
2475{13100000, DIF_BPF_COEFF3031, 0xf251fa33},
2476{13100000, DIF_BPF_COEFF3233, 0x0f7b03b8},
2477{13100000, DIF_BPF_COEFF3435, 0xef5afeb8},
2478{13100000, DIF_BPF_COEFF36, 0x110d0000},
2479/* END - DIF BPF register values from 131_quant.dat*/
2480
2481
2482/*case 13200000:*/
2483/* BEGIN - DIF BPF register values from 132_quant.dat*/
2484{13200000, DIF_BPF_COEFF01, 0xffff0000},
2485{13200000, DIF_BPF_COEFF23, 0x0008fffc},
2486{13200000, DIF_BPF_COEFF45, 0xffe00017},
2487{13200000, DIF_BPF_COEFF67, 0x004cffb9},
2488{13200000, DIF_BPF_COEFF89, 0xff7500a8},
2489{13200000, DIF_BPF_COEFF1011, 0x00d1feb6},
2490{13200000, DIF_BPF_COEFF1213, 0xfef90238},
2491{13200000, DIF_BPF_COEFF1415, 0x0111fc91},
2492{13200000, DIF_BPF_COEFF1617, 0xff3604df},
2493{13200000, DIF_BPF_COEFF1819, 0x0012f99b},
2494{13200000, DIF_BPF_COEFF2021, 0x012d07d2},
2495{13200000, DIF_BPF_COEFF2223, 0xfd07f714},
2496{13200000, DIF_BPF_COEFF2425, 0x0542097e},
2497{13200000, DIF_BPF_COEFF2627, 0xf81ff6a4},
2498{13200000, DIF_BPF_COEFF2829, 0x0a9a086e},
2499{13200000, DIF_BPF_COEFF3031, 0xf2dbf94b},
2500{13200000, DIF_BPF_COEFF3233, 0x0f380453},
2501{13200000, DIF_BPF_COEFF3435, 0xef6cfe82},
2502{13200000, DIF_BPF_COEFF36, 0x110d0000},
2503/* END - DIF BPF register values from 132_quant.dat*/
2504
2505
2506/*case 13300000:*/
2507/* BEGIN - DIF BPF register values from 133_quant.dat*/
2508{13300000, DIF_BPF_COEFF01, 0xffffffff},
2509{13300000, DIF_BPF_COEFF23, 0x00080003},
2510{13300000, DIF_BPF_COEFF45, 0xffde0001},
2511{13300000, DIF_BPF_COEFF67, 0x0056ffe3},
2512{13300000, DIF_BPF_COEFF89, 0xff570064},
2513{13300000, DIF_BPF_COEFF1011, 0x0113ff10},
2514{13300000, DIF_BPF_COEFF1213, 0xfe8201d2},
2515{13300000, DIF_BPF_COEFF1415, 0x01cafcf0},
2516{13300000, DIF_BPF_COEFF1617, 0xfe35049e},
2517{13300000, DIF_BPF_COEFF1819, 0x0155f9a6},
2518{13300000, DIF_BPF_COEFF2021, 0xffba080e},
2519{13300000, DIF_BPF_COEFF2223, 0xfe8cf689},
2520{13300000, DIF_BPF_COEFF2425, 0x03ce0a4e},
2521{13300000, DIF_BPF_COEFF2627, 0xf961f5a8},
2522{13300000, DIF_BPF_COEFF2829, 0x09a50971},
2523{13300000, DIF_BPF_COEFF3031, 0xf379f869},
2524{13300000, DIF_BPF_COEFF3233, 0x0eeb04ec},
2525{13300000, DIF_BPF_COEFF3435, 0xef80fe4b},
2526{13300000, DIF_BPF_COEFF36, 0x110d0000},
2527/* END - DIF BPF register values from 133_quant.dat*/
2528
2529
2530/*case 13400000:*/
2531/* BEGIN - DIF BPF register values from 134_quant.dat*/
2532{13400000, DIF_BPF_COEFF01, 0x0000fffe},
2533{13400000, DIF_BPF_COEFF23, 0x0007000a},
2534{13400000, DIF_BPF_COEFF45, 0xffe2ffec},
2535{13400000, DIF_BPF_COEFF67, 0x00540012},
2536{13400000, DIF_BPF_COEFF89, 0xff4e0015},
2537{13400000, DIF_BPF_COEFF1011, 0x0137ff82},
2538{13400000, DIF_BPF_COEFF1213, 0xfe2e0145},
2539{13400000, DIF_BPF_COEFF1415, 0x0260fd86},
2540{13400000, DIF_BPF_COEFF1617, 0xfd51041a},
2541{13400000, DIF_BPF_COEFF1819, 0x0287f9fb},
2542{13400000, DIF_BPF_COEFF2021, 0xfe4a0802},
2543{13400000, DIF_BPF_COEFF2223, 0x001df63f},
2544{13400000, DIF_BPF_COEFF2425, 0x02430aeb},
2545{13400000, DIF_BPF_COEFF2627, 0xfabdf4ce},
2546{13400000, DIF_BPF_COEFF2829, 0x08970a62},
2547{13400000, DIF_BPF_COEFF3031, 0xf428f78f},
2548{13400000, DIF_BPF_COEFF3233, 0x0e950584},
2549{13400000, DIF_BPF_COEFF3435, 0xef97fe15},
2550{13400000, DIF_BPF_COEFF36, 0x110d0000},
2551/* END - DIF BPF register values from 134_quant.dat*/
2552
2553
2554/*case 13500000:*/
2555/* BEGIN - DIF BPF register values from 135_quant.dat*/
2556{13500000, DIF_BPF_COEFF01, 0x0000fffd},
2557{13500000, DIF_BPF_COEFF23, 0x0004000f},
2558{13500000, DIF_BPF_COEFF45, 0xffeaffda},
2559{13500000, DIF_BPF_COEFF67, 0x0046003d},
2560{13500000, DIF_BPF_COEFF89, 0xff5affc4},
2561{13500000, DIF_BPF_COEFF1011, 0x013b0000},
2562{13500000, DIF_BPF_COEFF1213, 0xfe04009d},
2563{13500000, DIF_BPF_COEFF1415, 0x02c8fe48},
2564{13500000, DIF_BPF_COEFF1617, 0xfc99035a},
2565{13500000, DIF_BPF_COEFF1819, 0x0397fa96},
2566{13500000, DIF_BPF_COEFF2021, 0xfcec07ad},
2567{13500000, DIF_BPF_COEFF2223, 0x01adf637},
2568{13500000, DIF_BPF_COEFF2425, 0x00ac0b53},
2569{13500000, DIF_BPF_COEFF2627, 0xfc2ef419},
2570{13500000, DIF_BPF_COEFF2829, 0x07730b3e},
2571{13500000, DIF_BPF_COEFF3031, 0xf4e9f6bd},
2572{13500000, DIF_BPF_COEFF3233, 0x0e35061a},
2573{13500000, DIF_BPF_COEFF3435, 0xefb1fddf},
2574{13500000, DIF_BPF_COEFF36, 0x110d0000},
2575/* END - DIF BPF register values from 135_quant.dat*/
2576
2577
2578/*case 13600000:*/
2579/* BEGIN - DIF BPF register values from 136_quant.dat*/
2580{13600000, DIF_BPF_COEFF01, 0x0000fffd},
2581{13600000, DIF_BPF_COEFF23, 0x00000012},
2582{13600000, DIF_BPF_COEFF45, 0xfff6ffcd},
2583{13600000, DIF_BPF_COEFF67, 0x002f0061},
2584{13600000, DIF_BPF_COEFF89, 0xff7bff79},
2585{13600000, DIF_BPF_COEFF1011, 0x011e007e},
2586{13600000, DIF_BPF_COEFF1213, 0xfe08ffe8},
2587{13600000, DIF_BPF_COEFF1415, 0x02f9ff28},
2588{13600000, DIF_BPF_COEFF1617, 0xfc17026a},
2589{13600000, DIF_BPF_COEFF1819, 0x0479fb70},
2590{13600000, DIF_BPF_COEFF2021, 0xfbad0713},
2591{13600000, DIF_BPF_COEFF2223, 0x032ff672},
2592{13600000, DIF_BPF_COEFF2425, 0xff100b83},
2593{13600000, DIF_BPF_COEFF2627, 0xfdaff38b},
2594{13600000, DIF_BPF_COEFF2829, 0x063c0c04},
2595{13600000, DIF_BPF_COEFF3031, 0xf5baf5f5},
2596{13600000, DIF_BPF_COEFF3233, 0x0dcc06ae},
2597{13600000, DIF_BPF_COEFF3435, 0xefcdfda8},
2598{13600000, DIF_BPF_COEFF36, 0x110d0000},
2599/* END - DIF BPF register values from 136_quant.dat*/
2600
2601
2602/*case 13700000:*/
2603/* BEGIN - DIF BPF register values from 137_quant.dat*/
2604{13700000, DIF_BPF_COEFF01, 0x0000fffd},
2605{13700000, DIF_BPF_COEFF23, 0xfffd0012},
2606{13700000, DIF_BPF_COEFF45, 0x0004ffc8},
2607{13700000, DIF_BPF_COEFF67, 0x00100078},
2608{13700000, DIF_BPF_COEFF89, 0xffacff3e},
2609{13700000, DIF_BPF_COEFF1011, 0x00e200f0},
2610{13700000, DIF_BPF_COEFF1213, 0xfe39ff35},
2611{13700000, DIF_BPF_COEFF1415, 0x02f10017},
2612{13700000, DIF_BPF_COEFF1617, 0xfbd30156},
2613{13700000, DIF_BPF_COEFF1819, 0x0521fc7f},
2614{13700000, DIF_BPF_COEFF2021, 0xfa9c0638},
2615{13700000, DIF_BPF_COEFF2223, 0x0499f6ee},
2616{13700000, DIF_BPF_COEFF2425, 0xfd7a0b7c},
2617{13700000, DIF_BPF_COEFF2627, 0xff39f325},
2618{13700000, DIF_BPF_COEFF2829, 0x04f40cb3},
2619{13700000, DIF_BPF_COEFF3031, 0xf69af537},
2620{13700000, DIF_BPF_COEFF3233, 0x0d5a073f},
2621{13700000, DIF_BPF_COEFF3435, 0xefecfd72},
2622{13700000, DIF_BPF_COEFF36, 0x110d0000},
2623/* END - DIF BPF register values from 137_quant.dat*/
2624
2625
2626/*case 13800000:*/
2627/* BEGIN - DIF BPF register values from 138_quant.dat*/
2628{13800000, DIF_BPF_COEFF01, 0x0001fffe},
2629{13800000, DIF_BPF_COEFF23, 0xfffa000e},
2630{13800000, DIF_BPF_COEFF45, 0x0011ffcb},
2631{13800000, DIF_BPF_COEFF67, 0xfff0007f},
2632{13800000, DIF_BPF_COEFF89, 0xffe7ff19},
2633{13800000, DIF_BPF_COEFF1011, 0x008f014a},
2634{13800000, DIF_BPF_COEFF1213, 0xfe94fe93},
2635{13800000, DIF_BPF_COEFF1415, 0x02b00105},
2636{13800000, DIF_BPF_COEFF1617, 0xfbd3002f},
2637{13800000, DIF_BPF_COEFF1819, 0x0585fdb7},
2638{13800000, DIF_BPF_COEFF2021, 0xf9c10525},
2639{13800000, DIF_BPF_COEFF2223, 0x05def7a8},
2640{13800000, DIF_BPF_COEFF2425, 0xfbf20b3c},
2641{13800000, DIF_BPF_COEFF2627, 0x00c7f2e9},
2642{13800000, DIF_BPF_COEFF2829, 0x03a00d48},
2643{13800000, DIF_BPF_COEFF3031, 0xf787f484},
2644{13800000, DIF_BPF_COEFF3233, 0x0cdf07cd},
2645{13800000, DIF_BPF_COEFF3435, 0xf00dfd3c},
2646{13800000, DIF_BPF_COEFF36, 0x110d0000},
2647/* END - DIF BPF register values from 138_quant.dat*/
2648
2649
2650/*case 13900000:*/
2651/* BEGIN - DIF BPF register values from 139_quant.dat*/
2652{13900000, DIF_BPF_COEFF01, 0x00010000},
2653{13900000, DIF_BPF_COEFF23, 0xfff80008},
2654{13900000, DIF_BPF_COEFF45, 0x001bffd7},
2655{13900000, DIF_BPF_COEFF67, 0xffd10076},
2656{13900000, DIF_BPF_COEFF89, 0x0026ff0e},
2657{13900000, DIF_BPF_COEFF1011, 0x002c0184},
2658{13900000, DIF_BPF_COEFF1213, 0xff0ffe10},
2659{13900000, DIF_BPF_COEFF1415, 0x023b01e0},
2660{13900000, DIF_BPF_COEFF1617, 0xfc17ff06},
2661{13900000, DIF_BPF_COEFF1819, 0x05a2ff09},
2662{13900000, DIF_BPF_COEFF2021, 0xf92703e4},
2663{13900000, DIF_BPF_COEFF2223, 0x06f4f89b},
2664{13900000, DIF_BPF_COEFF2425, 0xfa820ac5},
2665{13900000, DIF_BPF_COEFF2627, 0x0251f2d9},
2666{13900000, DIF_BPF_COEFF2829, 0x02430dc3},
2667{13900000, DIF_BPF_COEFF3031, 0xf881f3dc},
2668{13900000, DIF_BPF_COEFF3233, 0x0c5c0859},
2669{13900000, DIF_BPF_COEFF3435, 0xf031fd06},
2670{13900000, DIF_BPF_COEFF36, 0x110d0000},
2671/* END - DIF BPF register values from 139_quant.dat*/
2672
2673
2674/*case 14000000:*/
2675/* BEGIN - DIF BPF register values from 140_quant.dat*/
2676{14000000, DIF_BPF_COEFF01, 0x00010001},
2677{14000000, DIF_BPF_COEFF23, 0xfff80001},
2678{14000000, DIF_BPF_COEFF45, 0x0021ffe8},
2679{14000000, DIF_BPF_COEFF67, 0xffba005d},
2680{14000000, DIF_BPF_COEFF89, 0x0060ff1f},
2681{14000000, DIF_BPF_COEFF1011, 0xffc40198},
2682{14000000, DIF_BPF_COEFF1213, 0xffa0fdb5},
2683{14000000, DIF_BPF_COEFF1415, 0x019a029a},
2684{14000000, DIF_BPF_COEFF1617, 0xfc99fdea},
2685{14000000, DIF_BPF_COEFF1819, 0x05750067},
2686{14000000, DIF_BPF_COEFF2021, 0xf8d4027f},
2687{14000000, DIF_BPF_COEFF2223, 0x07d4f9c0},
2688{14000000, DIF_BPF_COEFF2425, 0xf9320a1a},
2689{14000000, DIF_BPF_COEFF2627, 0x03d2f2f3},
2690{14000000, DIF_BPF_COEFF2829, 0x00df0e22},
2691{14000000, DIF_BPF_COEFF3031, 0xf986f341},
2692{14000000, DIF_BPF_COEFF3233, 0x0bd108e2},
2693{14000000, DIF_BPF_COEFF3435, 0xf058fcd1},
2694{14000000, DIF_BPF_COEFF36, 0x110d0000},
2695/* END - DIF BPF register values from 140_quant.dat*/
2696
2697
2698/*case 14100000:*/
2699/* BEGIN - DIF BPF register values from 141_quant.dat*/
2700{14100000, DIF_BPF_COEFF01, 0x00000002},
2701{14100000, DIF_BPF_COEFF23, 0xfff9fffa},
2702{14100000, DIF_BPF_COEFF45, 0x0021fffd},
2703{14100000, DIF_BPF_COEFF67, 0xffac0038},
2704{14100000, DIF_BPF_COEFF89, 0x008eff4a},
2705{14100000, DIF_BPF_COEFF1011, 0xff630184},
2706{14100000, DIF_BPF_COEFF1213, 0x003afd8b},
2707{14100000, DIF_BPF_COEFF1415, 0x00da0326},
2708{14100000, DIF_BPF_COEFF1617, 0xfd51fced},
2709{14100000, DIF_BPF_COEFF1819, 0x050101c0},
2710{14100000, DIF_BPF_COEFF2021, 0xf8cb0103},
2711{14100000, DIF_BPF_COEFF2223, 0x0876fb10},
2712{14100000, DIF_BPF_COEFF2425, 0xf80a093e},
2713{14100000, DIF_BPF_COEFF2627, 0x0543f338},
2714{14100000, DIF_BPF_COEFF2829, 0xff7a0e66},
2715{14100000, DIF_BPF_COEFF3031, 0xfa94f2b2},
2716{14100000, DIF_BPF_COEFF3233, 0x0b3f0967},
2717{14100000, DIF_BPF_COEFF3435, 0xf081fc9b},
2718{14100000, DIF_BPF_COEFF36, 0x110d0000},
2719/* END - DIF BPF register values from 141_quant.dat*/
2720
2721
2722/*case 14200000:*/
2723/* BEGIN - DIF BPF register values from 142_quant.dat*/
2724{14200000, DIF_BPF_COEFF01, 0x00000003},
2725{14200000, DIF_BPF_COEFF23, 0xfffbfff3},
2726{14200000, DIF_BPF_COEFF45, 0x001d0013},
2727{14200000, DIF_BPF_COEFF67, 0xffaa000b},
2728{14200000, DIF_BPF_COEFF89, 0x00aaff89},
2729{14200000, DIF_BPF_COEFF1011, 0xff13014a},
2730{14200000, DIF_BPF_COEFF1213, 0x00cefd95},
2731{14200000, DIF_BPF_COEFF1415, 0x000a037b},
2732{14200000, DIF_BPF_COEFF1617, 0xfe35fc1d},
2733{14200000, DIF_BPF_COEFF1819, 0x044c0305},
2734{14200000, DIF_BPF_COEFF2021, 0xf90cff7e},
2735{14200000, DIF_BPF_COEFF2223, 0x08d5fc81},
2736{14200000, DIF_BPF_COEFF2425, 0xf7100834},
2737{14200000, DIF_BPF_COEFF2627, 0x069ff3a7},
2738{14200000, DIF_BPF_COEFF2829, 0xfe160e8d},
2739{14200000, DIF_BPF_COEFF3031, 0xfbaaf231},
2740{14200000, DIF_BPF_COEFF3233, 0x0aa509e9},
2741{14200000, DIF_BPF_COEFF3435, 0xf0adfc65},
2742{14200000, DIF_BPF_COEFF36, 0x110d0000},
2743/* END - DIF BPF register values from 142_quant.dat*/
2744
2745
2746/*case 14300000:*/
2747/* BEGIN - DIF BPF register values from 143_quant.dat*/
2748{14300000, DIF_BPF_COEFF01, 0x00000003},
2749{14300000, DIF_BPF_COEFF23, 0xffffffef},
2750{14300000, DIF_BPF_COEFF45, 0x00140025},
2751{14300000, DIF_BPF_COEFF67, 0xffb4ffdd},
2752{14300000, DIF_BPF_COEFF89, 0x00b2ffd6},
2753{14300000, DIF_BPF_COEFF1011, 0xfedb00f0},
2754{14300000, DIF_BPF_COEFF1213, 0x0150fdd3},
2755{14300000, DIF_BPF_COEFF1415, 0xff380391},
2756{14300000, DIF_BPF_COEFF1617, 0xff36fb85},
2757{14300000, DIF_BPF_COEFF1819, 0x035e0426},
2758{14300000, DIF_BPF_COEFF2021, 0xf994fdfe},
2759{14300000, DIF_BPF_COEFF2223, 0x08eefe0b},
2760{14300000, DIF_BPF_COEFF2425, 0xf6490702},
2761{14300000, DIF_BPF_COEFF2627, 0x07e1f43e},
2762{14300000, DIF_BPF_COEFF2829, 0xfcb60e97},
2763{14300000, DIF_BPF_COEFF3031, 0xfcc6f1be},
2764{14300000, DIF_BPF_COEFF3233, 0x0a040a67},
2765{14300000, DIF_BPF_COEFF3435, 0xf0dbfc30},
2766{14300000, DIF_BPF_COEFF36, 0x110d0000},
2767/* END - DIF BPF register values from 143_quant.dat*/
2768
2769
2770/*case 14400000:*/
2771/* BEGIN - DIF BPF register values from 144_quant.dat*/
2772{14400000, DIF_BPF_COEFF01, 0x00000003},
2773{14400000, DIF_BPF_COEFF23, 0x0002ffee},
2774{14400000, DIF_BPF_COEFF45, 0x00070033},
2775{14400000, DIF_BPF_COEFF67, 0xffc9ffb4},
2776{14400000, DIF_BPF_COEFF89, 0x00a40027},
2777{14400000, DIF_BPF_COEFF1011, 0xfec3007e},
2778{14400000, DIF_BPF_COEFF1213, 0x01b4fe3f},
2779{14400000, DIF_BPF_COEFF1415, 0xfe760369},
2780{14400000, DIF_BPF_COEFF1617, 0x0044fb2e},
2781{14400000, DIF_BPF_COEFF1819, 0x02450518},
2782{14400000, DIF_BPF_COEFF2021, 0xfa5ffc90},
2783{14400000, DIF_BPF_COEFF2223, 0x08c1ffa1},
2784{14400000, DIF_BPF_COEFF2425, 0xf5bc05ae},
2785{14400000, DIF_BPF_COEFF2627, 0x0902f4fc},
2786{14400000, DIF_BPF_COEFF2829, 0xfb600e85},
2787{14400000, DIF_BPF_COEFF3031, 0xfde7f15a},
2788{14400000, DIF_BPF_COEFF3233, 0x095d0ae2},
2789{14400000, DIF_BPF_COEFF3435, 0xf10cfbfb},
2790{14400000, DIF_BPF_COEFF36, 0x110d0000},
2791/* END - DIF BPF register values from 144_quant.dat*/
2792
2793
2794/*case 14500000:*/
2795/* BEGIN - DIF BPF register values from 145_quant.dat*/
2796{14500000, DIF_BPF_COEFF01, 0xffff0002},
2797{14500000, DIF_BPF_COEFF23, 0x0005ffef},
2798{14500000, DIF_BPF_COEFF45, 0xfffa0038},
2799{14500000, DIF_BPF_COEFF67, 0xffe5ff95},
2800{14500000, DIF_BPF_COEFF89, 0x00820074},
2801{14500000, DIF_BPF_COEFF1011, 0xfecc0000},
2802{14500000, DIF_BPF_COEFF1213, 0x01f0fed0},
2803{14500000, DIF_BPF_COEFF1415, 0xfdd20304},
2804{14500000, DIF_BPF_COEFF1617, 0x014dfb1d},
2805{14500000, DIF_BPF_COEFF1819, 0x010e05ce},
2806{14500000, DIF_BPF_COEFF2021, 0xfb64fb41},
2807{14500000, DIF_BPF_COEFF2223, 0x084e013b},
2808{14500000, DIF_BPF_COEFF2425, 0xf569043e},
2809{14500000, DIF_BPF_COEFF2627, 0x0a00f5dd},
2810{14500000, DIF_BPF_COEFF2829, 0xfa150e55},
2811{14500000, DIF_BPF_COEFF3031, 0xff0bf104},
2812{14500000, DIF_BPF_COEFF3233, 0x08b00b59},
2813{14500000, DIF_BPF_COEFF3435, 0xf13ffbc6},
2814{14500000, DIF_BPF_COEFF36, 0x110d0000},
2815/* END - DIF BPF register values from 145_quant.dat*/
2816
2817
2818/*case 14600000:*/
2819/* BEGIN - DIF BPF register values from 146_quant.dat*/
2820{14600000, DIF_BPF_COEFF01, 0xffff0001},
2821{14600000, DIF_BPF_COEFF23, 0x0008fff4},
2822{14600000, DIF_BPF_COEFF45, 0xffed0035},
2823{14600000, DIF_BPF_COEFF67, 0x0005ff83},
2824{14600000, DIF_BPF_COEFF89, 0x005000b4},
2825{14600000, DIF_BPF_COEFF1011, 0xfef6ff82},
2826{14600000, DIF_BPF_COEFF1213, 0x01ffff7a},
2827{14600000, DIF_BPF_COEFF1415, 0xfd580269},
2828{14600000, DIF_BPF_COEFF1617, 0x0241fb53},
2829{14600000, DIF_BPF_COEFF1819, 0xffca0640},
2830{14600000, DIF_BPF_COEFF2021, 0xfc99fa1e},
2831{14600000, DIF_BPF_COEFF2223, 0x079a02cb},
2832{14600000, DIF_BPF_COEFF2425, 0xf55502ba},
2833{14600000, DIF_BPF_COEFF2627, 0x0ad5f6e0},
2834{14600000, DIF_BPF_COEFF2829, 0xf8d90e0a},
2835{14600000, DIF_BPF_COEFF3031, 0x0031f0bd},
2836{14600000, DIF_BPF_COEFF3233, 0x07fd0bcb},
2837{14600000, DIF_BPF_COEFF3435, 0xf174fb91},
2838{14600000, DIF_BPF_COEFF36, 0x110d0000},
2839/* END - DIF BPF register values from 146_quant.dat*/
2840
2841
2842/*case 14700000:*/
2843/* BEGIN - DIF BPF register values from 147_quant.dat*/
2844{14700000, DIF_BPF_COEFF01, 0xffffffff},
2845{14700000, DIF_BPF_COEFF23, 0x0009fffb},
2846{14700000, DIF_BPF_COEFF45, 0xffe4002a},
2847{14700000, DIF_BPF_COEFF67, 0x0025ff82},
2848{14700000, DIF_BPF_COEFF89, 0x001400e0},
2849{14700000, DIF_BPF_COEFF1011, 0xff3cff10},
2850{14700000, DIF_BPF_COEFF1213, 0x01e10030},
2851{14700000, DIF_BPF_COEFF1415, 0xfd1201a4},
2852{14700000, DIF_BPF_COEFF1617, 0x0311fbcd},
2853{14700000, DIF_BPF_COEFF1819, 0xfe88066a},
2854{14700000, DIF_BPF_COEFF2021, 0xfdf1f92f},
2855{14700000, DIF_BPF_COEFF2223, 0x06aa0449},
2856{14700000, DIF_BPF_COEFF2425, 0xf57e0128},
2857{14700000, DIF_BPF_COEFF2627, 0x0b7ef801},
2858{14700000, DIF_BPF_COEFF2829, 0xf7b00da2},
2859{14700000, DIF_BPF_COEFF3031, 0x0156f086},
2860{14700000, DIF_BPF_COEFF3233, 0x07450c39},
2861{14700000, DIF_BPF_COEFF3435, 0xf1acfb5c},
2862{14700000, DIF_BPF_COEFF36, 0x110d0000},
2863/* END - DIF BPF register values from 147_quant.dat*/
2864
2865
2866/*case 14800000:*/
2867/* BEGIN - DIF BPF register values from 148_quant.dat*/
2868{14800000, DIF_BPF_COEFF01, 0x0000fffe},
2869{14800000, DIF_BPF_COEFF23, 0x00080002},
2870{14800000, DIF_BPF_COEFF45, 0xffdf0019},
2871{14800000, DIF_BPF_COEFF67, 0x003fff92},
2872{14800000, DIF_BPF_COEFF89, 0xffd600f1},
2873{14800000, DIF_BPF_COEFF1011, 0xff96feb6},
2874{14800000, DIF_BPF_COEFF1213, 0x019700e1},
2875{14800000, DIF_BPF_COEFF1415, 0xfd0500c2},
2876{14800000, DIF_BPF_COEFF1617, 0x03b0fc84},
2877{14800000, DIF_BPF_COEFF1819, 0xfd590649},
2878{14800000, DIF_BPF_COEFF2021, 0xff5df87f},
2879{14800000, DIF_BPF_COEFF2223, 0x058505aa},
2880{14800000, DIF_BPF_COEFF2425, 0xf5e4ff91},
2881{14800000, DIF_BPF_COEFF2627, 0x0bf9f93c},
2882{14800000, DIF_BPF_COEFF2829, 0xf69d0d20},
2883{14800000, DIF_BPF_COEFF3031, 0x0279f05e},
2884{14800000, DIF_BPF_COEFF3233, 0x06880ca3},
2885{14800000, DIF_BPF_COEFF3435, 0xf1e6fb28},
2886{14800000, DIF_BPF_COEFF36, 0x110d0000},
2887/* END - DIF BPF register values from 148_quant.dat*/
2888
2889
2890/*case 14900000:*/
2891/* BEGIN - DIF BPF register values from 149_quant.dat*/
2892{14900000, DIF_BPF_COEFF01, 0x0000fffd},
2893{14900000, DIF_BPF_COEFF23, 0x00060009},
2894{14900000, DIF_BPF_COEFF45, 0xffdf0004},
2895{14900000, DIF_BPF_COEFF67, 0x0051ffb0},
2896{14900000, DIF_BPF_COEFF89, 0xff9d00e8},
2897{14900000, DIF_BPF_COEFF1011, 0xfffcfe7c},
2898{14900000, DIF_BPF_COEFF1213, 0x01280180},
2899{14900000, DIF_BPF_COEFF1415, 0xfd32ffd2},
2900{14900000, DIF_BPF_COEFF1617, 0x0413fd6e},
2901{14900000, DIF_BPF_COEFF1819, 0xfc4d05df},
2902{14900000, DIF_BPF_COEFF2021, 0x00d1f812},
2903{14900000, DIF_BPF_COEFF2223, 0x043506e4},
2904{14900000, DIF_BPF_COEFF2425, 0xf685fdfb},
2905{14900000, DIF_BPF_COEFF2627, 0x0c43fa8d},
2906{14900000, DIF_BPF_COEFF2829, 0xf5a10c83},
2907{14900000, DIF_BPF_COEFF3031, 0x0399f046},
2908{14900000, DIF_BPF_COEFF3233, 0x05c70d08},
2909{14900000, DIF_BPF_COEFF3435, 0xf222faf3},
2910{14900000, DIF_BPF_COEFF36, 0x110d0000},
2911/* END - DIF BPF register values from 149_quant.dat*/
2912
2913
2914/*case 15000000:*/
2915/* BEGIN - DIF BPF register values from 150_quant.dat*/
2916{15000000, DIF_BPF_COEFF01, 0x0000fffd},
2917{15000000, DIF_BPF_COEFF23, 0x0003000f},
2918{15000000, DIF_BPF_COEFF45, 0xffe5ffef},
2919{15000000, DIF_BPF_COEFF67, 0x0057ffd9},
2920{15000000, DIF_BPF_COEFF89, 0xff7000c4},
2921{15000000, DIF_BPF_COEFF1011, 0x0062fe68},
2922{15000000, DIF_BPF_COEFF1213, 0x009e01ff},
2923{15000000, DIF_BPF_COEFF1415, 0xfd95fee6},
2924{15000000, DIF_BPF_COEFF1617, 0x0435fe7d},
2925{15000000, DIF_BPF_COEFF1819, 0xfb710530},
2926{15000000, DIF_BPF_COEFF2021, 0x023cf7ee},
2927{15000000, DIF_BPF_COEFF2223, 0x02c307ef},
2928{15000000, DIF_BPF_COEFF2425, 0xf75efc70},
2929{15000000, DIF_BPF_COEFF2627, 0x0c5cfbef},
2930{15000000, DIF_BPF_COEFF2829, 0xf4c10bce},
2931{15000000, DIF_BPF_COEFF3031, 0x04b3f03f},
2932{15000000, DIF_BPF_COEFF3233, 0x05030d69},
2933{15000000, DIF_BPF_COEFF3435, 0xf261fabf},
2934{15000000, DIF_BPF_COEFF36, 0x110d0000},
2935/* END - DIF BPF register values from 150_quant.dat*/
2936
2937
2938/*case 15100000:*/
2939/* BEGIN - DIF BPF register values from 151_quant.dat*/
2940{15100000, DIF_BPF_COEFF01, 0x0000fffd},
2941{15100000, DIF_BPF_COEFF23, 0xffff0012},
2942{15100000, DIF_BPF_COEFF45, 0xffefffdc},
2943{15100000, DIF_BPF_COEFF67, 0x00510006},
2944{15100000, DIF_BPF_COEFF89, 0xff540089},
2945{15100000, DIF_BPF_COEFF1011, 0x00befe7c},
2946{15100000, DIF_BPF_COEFF1213, 0x00060253},
2947{15100000, DIF_BPF_COEFF1415, 0xfe27fe0d},
2948{15100000, DIF_BPF_COEFF1617, 0x0413ffa2},
2949{15100000, DIF_BPF_COEFF1819, 0xfad10446},
2950{15100000, DIF_BPF_COEFF2021, 0x0390f812},
2951{15100000, DIF_BPF_COEFF2223, 0x013b08c3},
2952{15100000, DIF_BPF_COEFF2425, 0xf868faf6},
2953{15100000, DIF_BPF_COEFF2627, 0x0c43fd5f},
2954{15100000, DIF_BPF_COEFF2829, 0xf3fd0b02},
2955{15100000, DIF_BPF_COEFF3031, 0x05c7f046},
2956{15100000, DIF_BPF_COEFF3233, 0x043b0dc4},
2957{15100000, DIF_BPF_COEFF3435, 0xf2a1fa8b},
2958{15100000, DIF_BPF_COEFF36, 0x110d0000},
2959/* END - DIF BPF register values from 151_quant.dat*/
2960
2961
2962/*case 15200000:*/
2963/* BEGIN - DIF BPF register values from 152_quant.dat*/
2964{15200000, DIF_BPF_COEFF01, 0x0001fffe},
2965{15200000, DIF_BPF_COEFF23, 0xfffc0012},
2966{15200000, DIF_BPF_COEFF45, 0xfffbffce},
2967{15200000, DIF_BPF_COEFF67, 0x003f0033},
2968{15200000, DIF_BPF_COEFF89, 0xff4e003f},
2969{15200000, DIF_BPF_COEFF1011, 0x0106feb6},
2970{15200000, DIF_BPF_COEFF1213, 0xff6e0276},
2971{15200000, DIF_BPF_COEFF1415, 0xfeddfd56},
2972{15200000, DIF_BPF_COEFF1617, 0x03b000cc},
2973{15200000, DIF_BPF_COEFF1819, 0xfa740329},
2974{15200000, DIF_BPF_COEFF2021, 0x04bff87f},
2975{15200000, DIF_BPF_COEFF2223, 0xffaa095d},
2976{15200000, DIF_BPF_COEFF2425, 0xf99ef995},
2977{15200000, DIF_BPF_COEFF2627, 0x0bf9fed8},
2978{15200000, DIF_BPF_COEFF2829, 0xf3590a1f},
2979{15200000, DIF_BPF_COEFF3031, 0x06d2f05e},
2980{15200000, DIF_BPF_COEFF3233, 0x03700e1b},
2981{15200000, DIF_BPF_COEFF3435, 0xf2e4fa58},
2982{15200000, DIF_BPF_COEFF36, 0x110d0000},
2983/* END - DIF BPF register values from 152_quant.dat*/
2984
2985
2986/*case 115300000:*/
2987/* BEGIN - DIF BPF register values from 153_quant.dat*/
2988{15300000, DIF_BPF_COEFF01, 0x0001ffff},
2989{15300000, DIF_BPF_COEFF23, 0xfff9000f},
2990{15300000, DIF_BPF_COEFF45, 0x0009ffc8},
2991{15300000, DIF_BPF_COEFF67, 0x00250059},
2992{15300000, DIF_BPF_COEFF89, 0xff5effee},
2993{15300000, DIF_BPF_COEFF1011, 0x0132ff10},
2994{15300000, DIF_BPF_COEFF1213, 0xfee30265},
2995{15300000, DIF_BPF_COEFF1415, 0xffaafccf},
2996{15300000, DIF_BPF_COEFF1617, 0x031101eb},
2997{15300000, DIF_BPF_COEFF1819, 0xfa6001e8},
2998{15300000, DIF_BPF_COEFF2021, 0x05bdf92f},
2999{15300000, DIF_BPF_COEFF2223, 0xfe1b09b6},
3000{15300000, DIF_BPF_COEFF2425, 0xfafaf852},
3001{15300000, DIF_BPF_COEFF2627, 0x0b7e0055},
3002{15300000, DIF_BPF_COEFF2829, 0xf2d50929},
3003{15300000, DIF_BPF_COEFF3031, 0x07d3f086},
3004{15300000, DIF_BPF_COEFF3233, 0x02a30e6c},
3005{15300000, DIF_BPF_COEFF3435, 0xf329fa24},
3006{15300000, DIF_BPF_COEFF36, 0x110d0000},
3007/* END - DIF BPF register values from 153_quant.dat*/
3008
3009
3010/*case 115400000:*/
3011/* BEGIN - DIF BPF register values from 154_quant.dat*/
3012{15400000, DIF_BPF_COEFF01, 0x00010001},
3013{15400000, DIF_BPF_COEFF23, 0xfff80009},
3014{15400000, DIF_BPF_COEFF45, 0x0015ffca},
3015{15400000, DIF_BPF_COEFF67, 0x00050074},
3016{15400000, DIF_BPF_COEFF89, 0xff81ff9f},
3017{15400000, DIF_BPF_COEFF1011, 0x013dff82},
3018{15400000, DIF_BPF_COEFF1213, 0xfe710221},
3019{15400000, DIF_BPF_COEFF1415, 0x007cfc80},
3020{15400000, DIF_BPF_COEFF1617, 0x024102ed},
3021{15400000, DIF_BPF_COEFF1819, 0xfa940090},
3022{15400000, DIF_BPF_COEFF2021, 0x0680fa1e},
3023{15400000, DIF_BPF_COEFF2223, 0xfc9b09cd},
3024{15400000, DIF_BPF_COEFF2425, 0xfc73f736},
3025{15400000, DIF_BPF_COEFF2627, 0x0ad501d0},
3026{15400000, DIF_BPF_COEFF2829, 0xf2740820},
3027{15400000, DIF_BPF_COEFF3031, 0x08c9f0bd},
3028{15400000, DIF_BPF_COEFF3233, 0x01d40eb9},
3029{15400000, DIF_BPF_COEFF3435, 0xf371f9f1},
3030{15400000, DIF_BPF_COEFF36, 0x110d0000},
3031/* END - DIF BPF register values from 154_quant.dat*/
3032
3033
3034/*case 115500000:*/
3035/* BEGIN - DIF BPF register values from 155_quant.dat*/
3036{15500000, DIF_BPF_COEFF01, 0x00000002},
3037{15500000, DIF_BPF_COEFF23, 0xfff80002},
3038{15500000, DIF_BPF_COEFF45, 0x001effd5},
3039{15500000, DIF_BPF_COEFF67, 0xffe5007f},
3040{15500000, DIF_BPF_COEFF89, 0xffb4ff5b},
3041{15500000, DIF_BPF_COEFF1011, 0x01280000},
3042{15500000, DIF_BPF_COEFF1213, 0xfe2401b0},
3043{15500000, DIF_BPF_COEFF1415, 0x0146fc70},
3044{15500000, DIF_BPF_COEFF1617, 0x014d03c6},
3045{15500000, DIF_BPF_COEFF1819, 0xfb10ff32},
3046{15500000, DIF_BPF_COEFF2021, 0x0701fb41},
3047{15500000, DIF_BPF_COEFF2223, 0xfb3709a1},
3048{15500000, DIF_BPF_COEFF2425, 0xfe00f644},
3049{15500000, DIF_BPF_COEFF2627, 0x0a000345},
3050{15500000, DIF_BPF_COEFF2829, 0xf2350708},
3051{15500000, DIF_BPF_COEFF3031, 0x09b2f104},
3052{15500000, DIF_BPF_COEFF3233, 0x01050eff},
3053{15500000, DIF_BPF_COEFF3435, 0xf3baf9be},
3054{15500000, DIF_BPF_COEFF36, 0x110d0000},
3055/* END - DIF BPF register values from 155_quant.dat*/
3056
3057
3058/*case 115600000:*/
3059/* BEGIN - DIF BPF register values from 156_quant.dat*/
3060{15600000, DIF_BPF_COEFF01, 0x00000003},
3061{15600000, DIF_BPF_COEFF23, 0xfff9fffb},
3062{15600000, DIF_BPF_COEFF45, 0x0022ffe6},
3063{15600000, DIF_BPF_COEFF67, 0xffc9007a},
3064{15600000, DIF_BPF_COEFF89, 0xfff0ff29},
3065{15600000, DIF_BPF_COEFF1011, 0x00f2007e},
3066{15600000, DIF_BPF_COEFF1213, 0xfe01011b},
3067{15600000, DIF_BPF_COEFF1415, 0x01f6fc9e},
3068{15600000, DIF_BPF_COEFF1617, 0x00440467},
3069{15600000, DIF_BPF_COEFF1819, 0xfbccfdde},
3070{15600000, DIF_BPF_COEFF2021, 0x0738fc90},
3071{15600000, DIF_BPF_COEFF2223, 0xf9f70934},
3072{15600000, DIF_BPF_COEFF2425, 0xff99f582},
3073{15600000, DIF_BPF_COEFF2627, 0x090204b0},
3074{15600000, DIF_BPF_COEFF2829, 0xf21a05e1},
3075{15600000, DIF_BPF_COEFF3031, 0x0a8df15a},
3076{15600000, DIF_BPF_COEFF3233, 0x00340f41},
3077{15600000, DIF_BPF_COEFF3435, 0xf405f98b},
3078{15600000, DIF_BPF_COEFF36, 0x110d0000},
3079/* END - DIF BPF register values from 156_quant.dat*/
3080
3081
3082/*case 115700000:*/
3083/* BEGIN - DIF BPF register values from 157_quant.dat*/
3084{15700000, DIF_BPF_COEFF01, 0x00000003},
3085{15700000, DIF_BPF_COEFF23, 0xfffcfff4},
3086{15700000, DIF_BPF_COEFF45, 0x0020fffa},
3087{15700000, DIF_BPF_COEFF67, 0xffb40064},
3088{15700000, DIF_BPF_COEFF89, 0x002fff11},
3089{15700000, DIF_BPF_COEFF1011, 0x00a400f0},
3090{15700000, DIF_BPF_COEFF1213, 0xfe0d006e},
3091{15700000, DIF_BPF_COEFF1415, 0x0281fd09},
3092{15700000, DIF_BPF_COEFF1617, 0xff3604c9},
3093{15700000, DIF_BPF_COEFF1819, 0xfcbffca2},
3094{15700000, DIF_BPF_COEFF2021, 0x0726fdfe},
3095{15700000, DIF_BPF_COEFF2223, 0xf8e80888},
3096{15700000, DIF_BPF_COEFF2425, 0x0134f4f3},
3097{15700000, DIF_BPF_COEFF2627, 0x07e1060c},
3098{15700000, DIF_BPF_COEFF2829, 0xf22304af},
3099{15700000, DIF_BPF_COEFF3031, 0x0b59f1be},
3100{15700000, DIF_BPF_COEFF3233, 0xff640f7d},
3101{15700000, DIF_BPF_COEFF3435, 0xf452f959},
3102{15700000, DIF_BPF_COEFF36, 0x110d0000},
3103/* END - DIF BPF register values from 157_quant.dat*/
3104
3105
3106/*case 115800000:*/
3107/* BEGIN - DIF BPF register values from 158_quant.dat*/
3108{15800000, DIF_BPF_COEFF01, 0x00000003},
3109{15800000, DIF_BPF_COEFF23, 0x0000fff0},
3110{15800000, DIF_BPF_COEFF45, 0x001a0010},
3111{15800000, DIF_BPF_COEFF67, 0xffaa0041},
3112{15800000, DIF_BPF_COEFF89, 0x0067ff13},
3113{15800000, DIF_BPF_COEFF1011, 0x0043014a},
3114{15800000, DIF_BPF_COEFF1213, 0xfe46ffb9},
3115{15800000, DIF_BPF_COEFF1415, 0x02dbfda8},
3116{15800000, DIF_BPF_COEFF1617, 0xfe3504e5},
3117{15800000, DIF_BPF_COEFF1819, 0xfddcfb8d},
3118{15800000, DIF_BPF_COEFF2021, 0x06c9ff7e},
3119{15800000, DIF_BPF_COEFF2223, 0xf81107a2},
3120{15800000, DIF_BPF_COEFF2425, 0x02c9f49a},
3121{15800000, DIF_BPF_COEFF2627, 0x069f0753},
3122{15800000, DIF_BPF_COEFF2829, 0xf2500373},
3123{15800000, DIF_BPF_COEFF3031, 0x0c14f231},
3124{15800000, DIF_BPF_COEFF3233, 0xfe930fb3},
3125{15800000, DIF_BPF_COEFF3435, 0xf4a1f927},
3126{15800000, DIF_BPF_COEFF36, 0x110d0000},
3127/* END - DIF BPF register values from 158_quant.dat*/
3128
3129
3130/*case 115900000:*/
3131/* BEGIN - DIF BPF register values from 159_quant.dat*/
3132{15900000, DIF_BPF_COEFF01, 0xffff0002},
3133{15900000, DIF_BPF_COEFF23, 0x0003ffee},
3134{15900000, DIF_BPF_COEFF45, 0x000f0023},
3135{15900000, DIF_BPF_COEFF67, 0xffac0016},
3136{15900000, DIF_BPF_COEFF89, 0x0093ff31},
3137{15900000, DIF_BPF_COEFF1011, 0xffdc0184},
3138{15900000, DIF_BPF_COEFF1213, 0xfea6ff09},
3139{15900000, DIF_BPF_COEFF1415, 0x02fdfe70},
3140{15900000, DIF_BPF_COEFF1617, 0xfd5104ba},
3141{15900000, DIF_BPF_COEFF1819, 0xff15faac},
3142{15900000, DIF_BPF_COEFF2021, 0x06270103},
3143{15900000, DIF_BPF_COEFF2223, 0xf7780688},
3144{15900000, DIF_BPF_COEFF2425, 0x044df479},
3145{15900000, DIF_BPF_COEFF2627, 0x05430883},
3146{15900000, DIF_BPF_COEFF2829, 0xf2a00231},
3147{15900000, DIF_BPF_COEFF3031, 0x0cbef2b2},
3148{15900000, DIF_BPF_COEFF3233, 0xfdc40fe3},
3149{15900000, DIF_BPF_COEFF3435, 0xf4f2f8f5},
3150{15900000, DIF_BPF_COEFF36, 0x110d0000},
3151/* END - DIF BPF register values from 159_quant.dat*/
3152
3153
3154/*case 116000000:*/
3155/* BEGIN - DIF BPF register values from 160_quant.dat*/
3156{16000000, DIF_BPF_COEFF01, 0xffff0001},
3157{16000000, DIF_BPF_COEFF23, 0x0006ffef},
3158{16000000, DIF_BPF_COEFF45, 0x00020031},
3159{16000000, DIF_BPF_COEFF67, 0xffbaffe8},
3160{16000000, DIF_BPF_COEFF89, 0x00adff66},
3161{16000000, DIF_BPF_COEFF1011, 0xff790198},
3162{16000000, DIF_BPF_COEFF1213, 0xff26fe6e},
3163{16000000, DIF_BPF_COEFF1415, 0x02e5ff55},
3164{16000000, DIF_BPF_COEFF1617, 0xfc99044a},
3165{16000000, DIF_BPF_COEFF1819, 0x005bfa09},
3166{16000000, DIF_BPF_COEFF2021, 0x0545027f},
3167{16000000, DIF_BPF_COEFF2223, 0xf7230541},
3168{16000000, DIF_BPF_COEFF2425, 0x05b8f490},
3169{16000000, DIF_BPF_COEFF2627, 0x03d20997},
3170{16000000, DIF_BPF_COEFF2829, 0xf31300eb},
3171{16000000, DIF_BPF_COEFF3031, 0x0d55f341},
3172{16000000, DIF_BPF_COEFF3233, 0xfcf6100e},
3173{16000000, DIF_BPF_COEFF3435, 0xf544f8c3},
3174{16000000, DIF_BPF_COEFF36, 0x110d0000},
3175/* END - DIF BPF register values from 160_quant.dat*/
3176};
3177
3178#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-dvb.c b/drivers/media/video/cx231xx/cx231xx-dvb.c
index 4ea3776b39fb..130794b971ce 100644
--- a/drivers/media/video/cx231xx/cx231xx-dvb.c
+++ b/drivers/media/video/cx231xx/cx231xx-dvb.c
@@ -29,6 +29,9 @@
29 29
30#include "xc5000.h" 30#include "xc5000.h"
31#include "dvb_dummy_fe.h" 31#include "dvb_dummy_fe.h"
32#include "s5h1432.h"
33#include "tda18271.h"
34#include "s5h1411.h"
32 35
33MODULE_DESCRIPTION("driver for cx231xx based DVB cards"); 36MODULE_DESCRIPTION("driver for cx231xx based DVB cards");
34MODULE_AUTHOR("Srinivasa Deevi <srinivasa.deevi@conexant.com>"); 37MODULE_AUTHOR("Srinivasa Deevi <srinivasa.deevi@conexant.com>");
@@ -65,6 +68,48 @@ struct cx231xx_dvb {
65 struct dvb_net net; 68 struct dvb_net net;
66}; 69};
67 70
71static struct s5h1432_config dvico_s5h1432_config = {
72 .output_mode = S5H1432_SERIAL_OUTPUT,
73 .gpio = S5H1432_GPIO_ON,
74 .qam_if = S5H1432_IF_4000,
75 .vsb_if = S5H1432_IF_4000,
76 .inversion = S5H1432_INVERSION_OFF,
77 .status_mode = S5H1432_DEMODLOCKING,
78 .mpeg_timing = S5H1432_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
79};
80
81static struct tda18271_std_map cnxt_rde253s_tda18271_std_map = {
82 .dvbt_6 = { .if_freq = 4000, .agc_mode = 3, .std = 4,
83 .if_lvl = 1, .rfagc_top = 0x37, },
84 .dvbt_7 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
85 .if_lvl = 1, .rfagc_top = 0x37, },
86 .dvbt_8 = { .if_freq = 4000, .agc_mode = 3, .std = 6,
87 .if_lvl = 1, .rfagc_top = 0x37, },
88};
89
90static struct tda18271_config cnxt_rde253s_tunerconfig = {
91 .std_map = &cnxt_rde253s_tda18271_std_map,
92 .gate = TDA18271_GATE_ANALOG,
93};
94
95static struct s5h1411_config tda18271_s5h1411_config = {
96 .output_mode = S5H1411_SERIAL_OUTPUT,
97 .gpio = S5H1411_GPIO_OFF,
98 .vsb_if = S5H1411_IF_3250,
99 .qam_if = S5H1411_IF_4000,
100 .inversion = S5H1411_INVERSION_ON,
101 .status_mode = S5H1411_DEMODLOCKING,
102 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
103};
104static struct s5h1411_config xc5000_s5h1411_config = {
105 .output_mode = S5H1411_SERIAL_OUTPUT,
106 .gpio = S5H1411_GPIO_OFF,
107 .vsb_if = S5H1411_IF_3250,
108 .qam_if = S5H1411_IF_3250,
109 .inversion = S5H1411_INVERSION_OFF,
110 .status_mode = S5H1411_DEMODLOCKING,
111 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
112};
68static inline void print_err_status(struct cx231xx *dev, int packet, int status) 113static inline void print_err_status(struct cx231xx *dev, int packet, int status)
69{ 114{
70 char *errmsg = "Unknown"; 115 char *errmsg = "Unknown";
@@ -128,34 +173,81 @@ static inline int dvb_isoc_copy(struct cx231xx *dev, struct urb *urb)
128 continue; 173 continue;
129 } 174 }
130 175
131 dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer + 176 dvb_dmx_swfilter(&dev->dvb->demux,
132 urb->iso_frame_desc[i].offset, 177 urb->transfer_buffer +
133 urb->iso_frame_desc[i].actual_length); 178 urb->iso_frame_desc[i].offset,
179 urb->iso_frame_desc[i].actual_length);
134 } 180 }
135 181
136 return 0; 182 return 0;
137} 183}
138 184
185static inline int dvb_bulk_copy(struct cx231xx *dev, struct urb *urb)
186{
187 int i;
188
189 if (!dev)
190 return 0;
191
192 if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED))
193 return 0;
194
195 if (urb->status < 0) {
196 print_err_status(dev, -1, urb->status);
197 if (urb->status == -ENOENT)
198 return 0;
199 }
200
201 /* Feed the transport payload into the kernel demux */
202 dvb_dmx_swfilter(&dev->dvb->demux,
203 urb->transfer_buffer, urb->actual_length);
204
205 return 0;
206}
207
139static int start_streaming(struct cx231xx_dvb *dvb) 208static int start_streaming(struct cx231xx_dvb *dvb)
140{ 209{
141 int rc; 210 int rc;
142 struct cx231xx *dev = dvb->adapter.priv; 211 struct cx231xx *dev = dvb->adapter.priv;
143 212
144 usb_set_interface(dev->udev, 0, 1); 213 if (dev->USE_ISO) {
145 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); 214 cx231xx_info("DVB transfer mode is ISO.\n");
146 if (rc < 0) 215mutex_lock(&dev->i2c_lock);
147 return rc; 216 cx231xx_enable_i2c_for_tuner(dev, I2C_1);
217 cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
218 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
219mutex_unlock(&dev->i2c_lock);
220 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
221 if (rc < 0)
222 return rc;
223 dev->mode_tv = 1;
224 return cx231xx_init_isoc(dev, CX231XX_DVB_MAX_PACKETS,
225 CX231XX_DVB_NUM_BUFS,
226 dev->ts1_mode.max_pkt_size,
227 dvb_isoc_copy);
228 } else {
229 cx231xx_info("DVB transfer mode is BULK.\n");
230 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
231 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
232 if (rc < 0)
233 return rc;
234 dev->mode_tv = 1;
235 return cx231xx_init_bulk(dev, CX231XX_DVB_MAX_PACKETS,
236 CX231XX_DVB_NUM_BUFS,
237 dev->ts1_mode.max_pkt_size,
238 dvb_bulk_copy);
239 }
148 240
149 return cx231xx_init_isoc(dev, CX231XX_DVB_MAX_PACKETS,
150 CX231XX_DVB_NUM_BUFS,
151 CX231XX_DVB_MAX_PACKETSIZE, dvb_isoc_copy);
152} 241}
153 242
154static int stop_streaming(struct cx231xx_dvb *dvb) 243static int stop_streaming(struct cx231xx_dvb *dvb)
155{ 244{
156 struct cx231xx *dev = dvb->adapter.priv; 245 struct cx231xx *dev = dvb->adapter.priv;
157 246
158 cx231xx_uninit_isoc(dev); 247 if (dev->USE_ISO)
248 cx231xx_uninit_isoc(dev);
249 else
250 cx231xx_uninit_bulk(dev);
159 251
160 cx231xx_set_mode(dev, CX231XX_SUSPEND); 252 cx231xx_set_mode(dev, CX231XX_SUSPEND);
161 253
@@ -216,7 +308,11 @@ static int cx231xx_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
216 308
217static struct xc5000_config cnxt_rde250_tunerconfig = { 309static struct xc5000_config cnxt_rde250_tunerconfig = {
218 .i2c_address = 0x61, 310 .i2c_address = 0x61,
219 .if_khz = 5380, 311 .if_khz = 4000,
312};
313static struct xc5000_config cnxt_rdu250_tunerconfig = {
314 .i2c_address = 0x61,
315 .if_khz = 3250,
220}; 316};
221 317
222/* ------------------------------------------------------------------ */ 318/* ------------------------------------------------------------------ */
@@ -268,7 +364,6 @@ int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq)
268 /*params.audmode = ; */ 364 /*params.audmode = ; */
269 365
270 /* Set the analog parameters to set the frequency */ 366 /* Set the analog parameters to set the frequency */
271 cx231xx_info("Setting Frequency for XC5000\n");
272 dops->set_analog_params(dev->dvb->frontend, &params); 367 dops->set_analog_params(dev->dvb->frontend, &params);
273 } 368 }
274 369
@@ -446,18 +541,19 @@ static int dvb_init(struct cx231xx *dev)
446 dev->cx231xx_reset_analog_tuner = cx231xx_reset_analog_tuner; 541 dev->cx231xx_reset_analog_tuner = cx231xx_reset_analog_tuner;
447 542
448 cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); 543 cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
544 cx231xx_demod_reset(dev);
449 /* init frontend */ 545 /* init frontend */
450 switch (dev->model) { 546 switch (dev->model) {
547 case CX231XX_BOARD_CNXT_CARRAERA:
451 case CX231XX_BOARD_CNXT_RDE_250: 548 case CX231XX_BOARD_CNXT_RDE_250:
452 549
453 /* dev->dvb->frontend = dvb_attach(s5h1411_attach, 550 dev->dvb->frontend = dvb_attach(s5h1432_attach,
454 &dvico_s5h1411_config, 551 &dvico_s5h1432_config,
455 &dev->i2c_bus[1].i2c_adap); */ 552 &dev->i2c_bus[2].i2c_adap);
456 dev->dvb->frontend = dvb_attach(dvb_dummy_fe_ofdm_attach);
457 553
458 if (dev->dvb->frontend == NULL) { 554 if (dev->dvb->frontend == NULL) {
459 printk(DRIVER_NAME 555 printk(DRIVER_NAME
460 ": Failed to attach dummy front end\n"); 556 ": Failed to attach s5h1432 front end\n");
461 result = -EINVAL; 557 result = -EINVAL;
462 goto out_free; 558 goto out_free;
463 } 559 }
@@ -473,9 +569,12 @@ static int dvb_init(struct cx231xx *dev)
473 } 569 }
474 570
475 break; 571 break;
572 case CX231XX_BOARD_CNXT_SHELBY:
476 case CX231XX_BOARD_CNXT_RDU_250: 573 case CX231XX_BOARD_CNXT_RDU_250:
477 574
478 dev->dvb->frontend = dvb_attach(dvb_dummy_fe_ofdm_attach); 575 dev->dvb->frontend = dvb_attach(s5h1411_attach,
576 &xc5000_s5h1411_config,
577 &dev->i2c_bus[2].i2c_adap);
479 578
480 if (dev->dvb->frontend == NULL) { 579 if (dev->dvb->frontend == NULL) {
481 printk(DRIVER_NAME 580 printk(DRIVER_NAME
@@ -489,7 +588,53 @@ static int dvb_init(struct cx231xx *dev)
489 588
490 if (!dvb_attach(xc5000_attach, dev->dvb->frontend, 589 if (!dvb_attach(xc5000_attach, dev->dvb->frontend,
491 &dev->i2c_bus[1].i2c_adap, 590 &dev->i2c_bus[1].i2c_adap,
492 &cnxt_rde250_tunerconfig)) { 591 &cnxt_rdu250_tunerconfig)) {
592 result = -EINVAL;
593 goto out_free;
594 }
595 break;
596 case CX231XX_BOARD_CNXT_RDE_253S:
597
598 dev->dvb->frontend = dvb_attach(s5h1432_attach,
599 &dvico_s5h1432_config,
600 &dev->i2c_bus[2].i2c_adap);
601
602 if (dev->dvb->frontend == NULL) {
603 printk(DRIVER_NAME
604 ": Failed to attach s5h1432 front end\n");
605 result = -EINVAL;
606 goto out_free;
607 }
608
609 /* define general-purpose callback pointer */
610 dvb->frontend->callback = cx231xx_tuner_callback;
611
612 if (!dvb_attach(tda18271_attach, dev->dvb->frontend,
613 0x60, &dev->i2c_bus[1].i2c_adap,
614 &cnxt_rde253s_tunerconfig)) {
615 result = -EINVAL;
616 goto out_free;
617 }
618 break;
619 case CX231XX_BOARD_CNXT_RDU_253S:
620
621 dev->dvb->frontend = dvb_attach(s5h1411_attach,
622 &tda18271_s5h1411_config,
623 &dev->i2c_bus[2].i2c_adap);
624
625 if (dev->dvb->frontend == NULL) {
626 printk(DRIVER_NAME
627 ": Failed to attach dummy front end\n");
628 result = -EINVAL;
629 goto out_free;
630 }
631
632 /* define general-purpose callback pointer */
633 dvb->frontend->callback = cx231xx_tuner_callback;
634
635 if (!dvb_attach(tda18271_attach, dev->dvb->frontend,
636 0x60, &dev->i2c_bus[1].i2c_adap,
637 &cnxt_rde253s_tunerconfig)) {
493 result = -EINVAL; 638 result = -EINVAL;
494 goto out_free; 639 goto out_free;
495 } 640 }
diff --git a/drivers/media/video/cx231xx/cx231xx-i2c.c b/drivers/media/video/cx231xx/cx231xx-i2c.c
index 58d9cc0867b9..d64bc7c21c20 100644
--- a/drivers/media/video/cx231xx/cx231xx-i2c.c
+++ b/drivers/media/video/cx231xx/cx231xx-i2c.c
@@ -359,7 +359,7 @@ static int cx231xx_i2c_xfer(struct i2c_adapter *i2c_adap,
359 359
360 if (num <= 0) 360 if (num <= 0)
361 return 0; 361 return 0;
362 362 mutex_lock(&dev->i2c_lock);
363 for (i = 0; i < num; i++) { 363 for (i = 0; i < num; i++) {
364 364
365 addr = msgs[i].addr >> 1; 365 addr = msgs[i].addr >> 1;
@@ -372,6 +372,7 @@ static int cx231xx_i2c_xfer(struct i2c_adapter *i2c_adap,
372 rc = cx231xx_i2c_check_for_device(i2c_adap, &msgs[i]); 372 rc = cx231xx_i2c_check_for_device(i2c_adap, &msgs[i]);
373 if (rc < 0) { 373 if (rc < 0) {
374 dprintk2(2, " no device\n"); 374 dprintk2(2, " no device\n");
375 mutex_lock(&dev->i2c_lock);
375 return rc; 376 return rc;
376 } 377 }
377 378
@@ -384,7 +385,7 @@ static int cx231xx_i2c_xfer(struct i2c_adapter *i2c_adap,
384 } 385 }
385 } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) && 386 } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) &&
386 msgs[i].addr == msgs[i + 1].addr 387 msgs[i].addr == msgs[i + 1].addr
387 && (msgs[i].len <= 2) && (bus->nr < 2)) { 388 && (msgs[i].len <= 2) && (bus->nr < 3)) {
388 /* read bytes */ 389 /* read bytes */
389 rc = cx231xx_i2c_recv_bytes_with_saddr(i2c_adap, 390 rc = cx231xx_i2c_recv_bytes_with_saddr(i2c_adap,
390 &msgs[i], 391 &msgs[i],
@@ -407,10 +408,11 @@ static int cx231xx_i2c_xfer(struct i2c_adapter *i2c_adap,
407 if (i2c_debug >= 2) 408 if (i2c_debug >= 2)
408 printk("\n"); 409 printk("\n");
409 } 410 }
410 411 mutex_unlock(&dev->i2c_lock);
411 return num; 412 return num;
412err: 413err:
413 dprintk2(2, " ERROR: %i\n", rc); 414 dprintk2(2, " ERROR: %i\n", rc);
415 mutex_unlock(&dev->i2c_lock);
414 return rc; 416 return rc;
415} 417}
416 418
diff --git a/drivers/media/video/cx231xx/cx231xx-input.c b/drivers/media/video/cx231xx/cx231xx-input.c
index fd099153b746..a0e8bb88d67e 100644
--- a/drivers/media/video/cx231xx/cx231xx-input.c
+++ b/drivers/media/video/cx231xx/cx231xx-input.c
@@ -61,6 +61,7 @@ struct cx231xx_ir_poll_result {
61struct cx231xx_IR { 61struct cx231xx_IR {
62 struct cx231xx *dev; 62 struct cx231xx *dev;
63 struct input_dev *input; 63 struct input_dev *input;
64 struct ir_input_state ir;
64 char name[32]; 65 char name[32];
65 char phys[32]; 66 char phys[32];
66 67
@@ -68,7 +69,9 @@ struct cx231xx_IR {
68 int polling; 69 int polling;
69 struct work_struct work; 70 struct work_struct work;
70 struct timer_list timer; 71 struct timer_list timer;
72 unsigned int last_toggle:1;
71 unsigned int last_readcount; 73 unsigned int last_readcount;
74 unsigned int repeat_interval;
72 75
73 int (*get_key) (struct cx231xx_IR *, struct cx231xx_ir_poll_result *); 76 int (*get_key) (struct cx231xx_IR *, struct cx231xx_ir_poll_result *);
74}; 77};
@@ -80,6 +83,7 @@ struct cx231xx_IR {
80static void cx231xx_ir_handle_key(struct cx231xx_IR *ir) 83static void cx231xx_ir_handle_key(struct cx231xx_IR *ir)
81{ 84{
82 int result; 85 int result;
86 int do_sendkey = 0;
83 struct cx231xx_ir_poll_result poll_result; 87 struct cx231xx_ir_poll_result poll_result;
84 88
85 /* read the registers containing the IR status */ 89 /* read the registers containing the IR status */
@@ -93,23 +97,44 @@ static void cx231xx_ir_handle_key(struct cx231xx_IR *ir)
93 poll_result.toggle_bit, poll_result.read_count, 97 poll_result.toggle_bit, poll_result.read_count,
94 ir->last_readcount, poll_result.rc_data[0]); 98 ir->last_readcount, poll_result.rc_data[0]);
95 99
96 if (poll_result.read_count > 0 && 100 if (ir->dev->chip_id == CHIP_ID_EM2874) {
97 poll_result.read_count != ir->last_readcount)
98 ir_keydown(ir->input,
99 poll_result.rc_data[0],
100 poll_result.toggle_bit);
101
102 if (ir->dev->chip_id == CHIP_ID_EM2874)
103 /* The em2874 clears the readcount field every time the 101 /* The em2874 clears the readcount field every time the
104 register is read. The em2860/2880 datasheet says that it 102 register is read. The em2860/2880 datasheet says that it
105 is supposed to clear the readcount, but it doesn't. So with 103 is supposed to clear the readcount, but it doesn't. So with
106 the em2874, we are looking for a non-zero read count as 104 the em2874, we are looking for a non-zero read count as
107 opposed to a readcount that is incrementing */ 105 opposed to a readcount that is incrementing */
108 ir->last_readcount = 0; 106 ir->last_readcount = 0;
109 else 107 }
110 ir->last_readcount = poll_result.read_count; 108
109 if (poll_result.read_count == 0) {
110 /* The button has not been pressed since the last read */
111 } else if (ir->last_toggle != poll_result.toggle_bit) {
112 /* A button has been pressed */
113 dprintk("button has been pressed\n");
114 ir->last_toggle = poll_result.toggle_bit;
115 ir->repeat_interval = 0;
116 do_sendkey = 1;
117 } else if (poll_result.toggle_bit == ir->last_toggle &&
118 poll_result.read_count > 0 &&
119 poll_result.read_count != ir->last_readcount) {
120 /* The button is still being held down */
121 dprintk("button being held down\n");
122
123 /* Debouncer for first keypress */
124 if (ir->repeat_interval++ > 9) {
125 /* Start repeating after 1 second */
126 do_sendkey = 1;
127 }
128 }
111 129
130 if (do_sendkey) {
131 dprintk("sending keypress\n");
132 ir_input_keydown(ir->input, &ir->ir, poll_result.rc_data[0]);
133 ir_input_nokey(ir->input, &ir->ir);
112 } 134 }
135
136 ir->last_readcount = poll_result.read_count;
137 return;
113} 138}
114 139
115static void ir_timer(unsigned long data) 140static void ir_timer(unsigned long data)
@@ -175,6 +200,10 @@ int cx231xx_ir_init(struct cx231xx *dev)
175 usb_make_path(dev->udev, ir->phys, sizeof(ir->phys)); 200 usb_make_path(dev->udev, ir->phys, sizeof(ir->phys));
176 strlcat(ir->phys, "/input0", sizeof(ir->phys)); 201 strlcat(ir->phys, "/input0", sizeof(ir->phys));
177 202
203 err = ir_input_init(input_dev, &ir->ir, IR_TYPE_OTHER);
204 if (err < 0)
205 goto err_out_free;
206
178 input_dev->name = ir->name; 207 input_dev->name = ir->name;
179 input_dev->phys = ir->phys; 208 input_dev->phys = ir->phys;
180 input_dev->id.bustype = BUS_USB; 209 input_dev->id.bustype = BUS_USB;
@@ -190,7 +219,7 @@ int cx231xx_ir_init(struct cx231xx *dev)
190 cx231xx_ir_start(ir); 219 cx231xx_ir_start(ir);
191 220
192 /* all done */ 221 /* all done */
193 err = __ir_input_register(ir->input, dev->board.ir_codes, 222 err = ir_input_register(ir->input, dev->board.ir_codes,
194 NULL, MODULE_NAME); 223 NULL, MODULE_NAME);
195 if (err) 224 if (err)
196 goto err_out_stop; 225 goto err_out_stop;
diff --git a/drivers/media/video/cx231xx/cx231xx-vbi.c b/drivers/media/video/cx231xx/cx231xx-vbi.c
index 689c5e25776c..d2147cadbfce 100644
--- a/drivers/media/video/cx231xx/cx231xx-vbi.c
+++ b/drivers/media/video/cx231xx/cx231xx-vbi.c
@@ -102,7 +102,7 @@ static inline int cx231xx_isoc_vbi_copy(struct cx231xx *dev, struct urb *urb)
102 return 0; 102 return 0;
103 } 103 }
104 104
105 buf = dev->vbi_mode.isoc_ctl.buf; 105 buf = dev->vbi_mode.bulk_ctl.buf;
106 106
107 /* get buffer pointer and length */ 107 /* get buffer pointer and length */
108 p_buffer = urb->transfer_buffer; 108 p_buffer = urb->transfer_buffer;
@@ -209,8 +209,8 @@ static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
209 VIDEOBUF_ACTIVE, it won't be, though. 209 VIDEOBUF_ACTIVE, it won't be, though.
210 */ 210 */
211 spin_lock_irqsave(&dev->vbi_mode.slock, flags); 211 spin_lock_irqsave(&dev->vbi_mode.slock, flags);
212 if (dev->vbi_mode.isoc_ctl.buf == buf) 212 if (dev->vbi_mode.bulk_ctl.buf == buf)
213 dev->vbi_mode.isoc_ctl.buf = NULL; 213 dev->vbi_mode.bulk_ctl.buf = NULL;
214 spin_unlock_irqrestore(&dev->vbi_mode.slock, flags); 214 spin_unlock_irqrestore(&dev->vbi_mode.slock, flags);
215 215
216 videobuf_vmalloc_free(&buf->vb); 216 videobuf_vmalloc_free(&buf->vb);
@@ -246,7 +246,7 @@ vbi_buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb,
246 goto fail; 246 goto fail;
247 } 247 }
248 248
249 if (!dev->vbi_mode.isoc_ctl.num_bufs) 249 if (!dev->vbi_mode.bulk_ctl.num_bufs)
250 urb_init = 1; 250 urb_init = 1;
251 251
252 if (urb_init) { 252 if (urb_init) {
@@ -328,7 +328,7 @@ static void cx231xx_irq_vbi_callback(struct urb *urb)
328 328
329 /* Copy data from URB */ 329 /* Copy data from URB */
330 spin_lock(&dev->vbi_mode.slock); 330 spin_lock(&dev->vbi_mode.slock);
331 rc = dev->vbi_mode.isoc_ctl.isoc_copy(dev, urb); 331 rc = dev->vbi_mode.bulk_ctl.bulk_copy(dev, urb);
332 spin_unlock(&dev->vbi_mode.slock); 332 spin_unlock(&dev->vbi_mode.slock);
333 333
334 /* Reset status */ 334 /* Reset status */
@@ -351,34 +351,34 @@ void cx231xx_uninit_vbi_isoc(struct cx231xx *dev)
351 351
352 cx231xx_info(DRIVER_NAME "cx231xx: called cx231xx_uninit_vbi_isoc\n"); 352 cx231xx_info(DRIVER_NAME "cx231xx: called cx231xx_uninit_vbi_isoc\n");
353 353
354 dev->vbi_mode.isoc_ctl.nfields = -1; 354 dev->vbi_mode.bulk_ctl.nfields = -1;
355 for (i = 0; i < dev->vbi_mode.isoc_ctl.num_bufs; i++) { 355 for (i = 0; i < dev->vbi_mode.bulk_ctl.num_bufs; i++) {
356 urb = dev->vbi_mode.isoc_ctl.urb[i]; 356 urb = dev->vbi_mode.bulk_ctl.urb[i];
357 if (urb) { 357 if (urb) {
358 if (!irqs_disabled()) 358 if (!irqs_disabled())
359 usb_kill_urb(urb); 359 usb_kill_urb(urb);
360 else 360 else
361 usb_unlink_urb(urb); 361 usb_unlink_urb(urb);
362 362
363 if (dev->vbi_mode.isoc_ctl.transfer_buffer[i]) { 363 if (dev->vbi_mode.bulk_ctl.transfer_buffer[i]) {
364 364
365 kfree(dev->vbi_mode.isoc_ctl. 365 kfree(dev->vbi_mode.bulk_ctl.
366 transfer_buffer[i]); 366 transfer_buffer[i]);
367 dev->vbi_mode.isoc_ctl.transfer_buffer[i] = 367 dev->vbi_mode.bulk_ctl.transfer_buffer[i] =
368 NULL; 368 NULL;
369 } 369 }
370 usb_free_urb(urb); 370 usb_free_urb(urb);
371 dev->vbi_mode.isoc_ctl.urb[i] = NULL; 371 dev->vbi_mode.bulk_ctl.urb[i] = NULL;
372 } 372 }
373 dev->vbi_mode.isoc_ctl.transfer_buffer[i] = NULL; 373 dev->vbi_mode.bulk_ctl.transfer_buffer[i] = NULL;
374 } 374 }
375 375
376 kfree(dev->vbi_mode.isoc_ctl.urb); 376 kfree(dev->vbi_mode.bulk_ctl.urb);
377 kfree(dev->vbi_mode.isoc_ctl.transfer_buffer); 377 kfree(dev->vbi_mode.bulk_ctl.transfer_buffer);
378 378
379 dev->vbi_mode.isoc_ctl.urb = NULL; 379 dev->vbi_mode.bulk_ctl.urb = NULL;
380 dev->vbi_mode.isoc_ctl.transfer_buffer = NULL; 380 dev->vbi_mode.bulk_ctl.transfer_buffer = NULL;
381 dev->vbi_mode.isoc_ctl.num_bufs = 0; 381 dev->vbi_mode.bulk_ctl.num_bufs = 0;
382 382
383 cx231xx_capture_start(dev, 0, Vbi); 383 cx231xx_capture_start(dev, 0, Vbi);
384} 384}
@@ -389,7 +389,7 @@ EXPORT_SYMBOL_GPL(cx231xx_uninit_vbi_isoc);
389 */ 389 */
390int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets, 390int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
391 int num_bufs, int max_pkt_size, 391 int num_bufs, int max_pkt_size,
392 int (*isoc_copy) (struct cx231xx *dev, 392 int (*bulk_copy) (struct cx231xx *dev,
393 struct urb *urb)) 393 struct urb *urb))
394{ 394{
395 struct cx231xx_dmaqueue *dma_q = &dev->vbi_mode.vidq; 395 struct cx231xx_dmaqueue *dma_q = &dev->vbi_mode.vidq;
@@ -408,8 +408,8 @@ int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
408 usb_rcvbulkpipe(dev->udev, 408 usb_rcvbulkpipe(dev->udev,
409 dev->vbi_mode.end_point_addr)); 409 dev->vbi_mode.end_point_addr));
410 410
411 dev->vbi_mode.isoc_ctl.isoc_copy = isoc_copy; 411 dev->vbi_mode.bulk_ctl.bulk_copy = bulk_copy;
412 dev->vbi_mode.isoc_ctl.num_bufs = num_bufs; 412 dev->vbi_mode.bulk_ctl.num_bufs = num_bufs;
413 dma_q->pos = 0; 413 dma_q->pos = 0;
414 dma_q->is_partial_line = 0; 414 dma_q->is_partial_line = 0;
415 dma_q->last_sav = 0; 415 dma_q->last_sav = 0;
@@ -421,42 +421,42 @@ int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
421 for (i = 0; i < 8; i++) 421 for (i = 0; i < 8; i++)
422 dma_q->partial_buf[i] = 0; 422 dma_q->partial_buf[i] = 0;
423 423
424 dev->vbi_mode.isoc_ctl.urb = kzalloc(sizeof(void *) * num_bufs, 424 dev->vbi_mode.bulk_ctl.urb = kzalloc(sizeof(void *) * num_bufs,
425 GFP_KERNEL); 425 GFP_KERNEL);
426 if (!dev->vbi_mode.isoc_ctl.urb) { 426 if (!dev->vbi_mode.bulk_ctl.urb) {
427 cx231xx_errdev("cannot alloc memory for usb buffers\n"); 427 cx231xx_errdev("cannot alloc memory for usb buffers\n");
428 return -ENOMEM; 428 return -ENOMEM;
429 } 429 }
430 430
431 dev->vbi_mode.isoc_ctl.transfer_buffer = 431 dev->vbi_mode.bulk_ctl.transfer_buffer =
432 kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL); 432 kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
433 if (!dev->vbi_mode.isoc_ctl.transfer_buffer) { 433 if (!dev->vbi_mode.bulk_ctl.transfer_buffer) {
434 cx231xx_errdev("cannot allocate memory for usbtransfer\n"); 434 cx231xx_errdev("cannot allocate memory for usbtransfer\n");
435 kfree(dev->vbi_mode.isoc_ctl.urb); 435 kfree(dev->vbi_mode.bulk_ctl.urb);
436 return -ENOMEM; 436 return -ENOMEM;
437 } 437 }
438 438
439 dev->vbi_mode.isoc_ctl.max_pkt_size = max_pkt_size; 439 dev->vbi_mode.bulk_ctl.max_pkt_size = max_pkt_size;
440 dev->vbi_mode.isoc_ctl.buf = NULL; 440 dev->vbi_mode.bulk_ctl.buf = NULL;
441 441
442 sb_size = max_packets * dev->vbi_mode.isoc_ctl.max_pkt_size; 442 sb_size = max_packets * dev->vbi_mode.bulk_ctl.max_pkt_size;
443 443
444 /* allocate urbs and transfer buffers */ 444 /* allocate urbs and transfer buffers */
445 for (i = 0; i < dev->vbi_mode.isoc_ctl.num_bufs; i++) { 445 for (i = 0; i < dev->vbi_mode.bulk_ctl.num_bufs; i++) {
446 446
447 urb = usb_alloc_urb(0, GFP_KERNEL); 447 urb = usb_alloc_urb(0, GFP_KERNEL);
448 if (!urb) { 448 if (!urb) {
449 cx231xx_err(DRIVER_NAME 449 cx231xx_err(DRIVER_NAME
450 ": cannot alloc isoc_ctl.urb %i\n", i); 450 ": cannot alloc bulk_ctl.urb %i\n", i);
451 cx231xx_uninit_vbi_isoc(dev); 451 cx231xx_uninit_vbi_isoc(dev);
452 return -ENOMEM; 452 return -ENOMEM;
453 } 453 }
454 dev->vbi_mode.isoc_ctl.urb[i] = urb; 454 dev->vbi_mode.bulk_ctl.urb[i] = urb;
455 urb->transfer_flags = 0; 455 urb->transfer_flags = 0;
456 456
457 dev->vbi_mode.isoc_ctl.transfer_buffer[i] = 457 dev->vbi_mode.bulk_ctl.transfer_buffer[i] =
458 kzalloc(sb_size, GFP_KERNEL); 458 kzalloc(sb_size, GFP_KERNEL);
459 if (!dev->vbi_mode.isoc_ctl.transfer_buffer[i]) { 459 if (!dev->vbi_mode.bulk_ctl.transfer_buffer[i]) {
460 cx231xx_err(DRIVER_NAME 460 cx231xx_err(DRIVER_NAME
461 ": unable to allocate %i bytes for transfer" 461 ": unable to allocate %i bytes for transfer"
462 " buffer %i%s\n", sb_size, i, 462 " buffer %i%s\n", sb_size, i,
@@ -467,15 +467,15 @@ int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
467 467
468 pipe = usb_rcvbulkpipe(dev->udev, dev->vbi_mode.end_point_addr); 468 pipe = usb_rcvbulkpipe(dev->udev, dev->vbi_mode.end_point_addr);
469 usb_fill_bulk_urb(urb, dev->udev, pipe, 469 usb_fill_bulk_urb(urb, dev->udev, pipe,
470 dev->vbi_mode.isoc_ctl.transfer_buffer[i], 470 dev->vbi_mode.bulk_ctl.transfer_buffer[i],
471 sb_size, cx231xx_irq_vbi_callback, dma_q); 471 sb_size, cx231xx_irq_vbi_callback, dma_q);
472 } 472 }
473 473
474 init_waitqueue_head(&dma_q->wq); 474 init_waitqueue_head(&dma_q->wq);
475 475
476 /* submit urbs and enables IRQ */ 476 /* submit urbs and enables IRQ */
477 for (i = 0; i < dev->vbi_mode.isoc_ctl.num_bufs; i++) { 477 for (i = 0; i < dev->vbi_mode.bulk_ctl.num_bufs; i++) {
478 rc = usb_submit_urb(dev->vbi_mode.isoc_ctl.urb[i], GFP_ATOMIC); 478 rc = usb_submit_urb(dev->vbi_mode.bulk_ctl.urb[i], GFP_ATOMIC);
479 if (rc) { 479 if (rc) {
480 cx231xx_err(DRIVER_NAME 480 cx231xx_err(DRIVER_NAME
481 ": submit of urb %i failed (error=%i)\n", i, 481 ": submit of urb %i failed (error=%i)\n", i,
@@ -536,7 +536,7 @@ static inline void vbi_buffer_filled(struct cx231xx *dev,
536 buf->vb.field_count++; 536 buf->vb.field_count++;
537 do_gettimeofday(&buf->vb.ts); 537 do_gettimeofday(&buf->vb.ts);
538 538
539 dev->vbi_mode.isoc_ctl.buf = NULL; 539 dev->vbi_mode.bulk_ctl.buf = NULL;
540 540
541 list_del(&buf->vb.queue); 541 list_del(&buf->vb.queue);
542 wake_up(&buf->vb.done); 542 wake_up(&buf->vb.done);
@@ -553,7 +553,7 @@ u32 cx231xx_copy_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
553 cx231xx_reset_vbi_buffer(dev, dma_q); 553 cx231xx_reset_vbi_buffer(dev, dma_q);
554 554
555 /* get the buffer pointer */ 555 /* get the buffer pointer */
556 buf = dev->vbi_mode.isoc_ctl.buf; 556 buf = dev->vbi_mode.bulk_ctl.buf;
557 557
558 /* Remember the field number for next time */ 558 /* Remember the field number for next time */
559 dma_q->current_field = field_number; 559 dma_q->current_field = field_number;
@@ -618,7 +618,7 @@ static inline void get_next_vbi_buf(struct cx231xx_dmaqueue *dma_q,
618 618
619 if (list_empty(&dma_q->active)) { 619 if (list_empty(&dma_q->active)) {
620 cx231xx_err(DRIVER_NAME ": No active queue to serve\n"); 620 cx231xx_err(DRIVER_NAME ": No active queue to serve\n");
621 dev->vbi_mode.isoc_ctl.buf = NULL; 621 dev->vbi_mode.bulk_ctl.buf = NULL;
622 *buf = NULL; 622 *buf = NULL;
623 return; 623 return;
624 } 624 }
@@ -630,7 +630,7 @@ static inline void get_next_vbi_buf(struct cx231xx_dmaqueue *dma_q,
630 outp = videobuf_to_vmalloc(&(*buf)->vb); 630 outp = videobuf_to_vmalloc(&(*buf)->vb);
631 memset(outp, 0, (*buf)->vb.size); 631 memset(outp, 0, (*buf)->vb.size);
632 632
633 dev->vbi_mode.isoc_ctl.buf = *buf; 633 dev->vbi_mode.bulk_ctl.buf = *buf;
634 634
635 return; 635 return;
636} 636}
@@ -640,7 +640,7 @@ void cx231xx_reset_vbi_buffer(struct cx231xx *dev,
640{ 640{
641 struct cx231xx_buffer *buf; 641 struct cx231xx_buffer *buf;
642 642
643 buf = dev->vbi_mode.isoc_ctl.buf; 643 buf = dev->vbi_mode.bulk_ctl.buf;
644 644
645 if (buf == NULL) { 645 if (buf == NULL) {
646 /* first try to get the buffer */ 646 /* first try to get the buffer */
@@ -664,7 +664,7 @@ int cx231xx_do_vbi_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
664 void *startwrite; 664 void *startwrite;
665 int offset, lencopy; 665 int offset, lencopy;
666 666
667 buf = dev->vbi_mode.isoc_ctl.buf; 667 buf = dev->vbi_mode.bulk_ctl.buf;
668 668
669 if (buf == NULL) 669 if (buf == NULL)
670 return -EINVAL; 670 return -EINVAL;
diff --git a/drivers/media/video/cx231xx/cx231xx-vbi.h b/drivers/media/video/cx231xx/cx231xx-vbi.h
index 89c7fe80b261..16c7d20a22a4 100644
--- a/drivers/media/video/cx231xx/cx231xx-vbi.h
+++ b/drivers/media/video/cx231xx/cx231xx-vbi.h
@@ -41,7 +41,7 @@ extern struct videobuf_queue_ops cx231xx_vbi_qops;
41/* stream functions */ 41/* stream functions */
42int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets, 42int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
43 int num_bufs, int max_pkt_size, 43 int num_bufs, int max_pkt_size,
44 int (*isoc_copy) (struct cx231xx *dev, 44 int (*bulk_copy) (struct cx231xx *dev,
45 struct urb *urb)); 45 struct urb *urb));
46 46
47void cx231xx_uninit_vbi_isoc(struct cx231xx *dev); 47void cx231xx_uninit_vbi_isoc(struct cx231xx *dev);
diff --git a/drivers/media/video/cx231xx/cx231xx-video.c b/drivers/media/video/cx231xx/cx231xx-video.c
index b638c4ed3f2e..9a42ccbcb46f 100644
--- a/drivers/media/video/cx231xx/cx231xx-video.c
+++ b/drivers/media/video/cx231xx/cx231xx-video.c
@@ -237,7 +237,10 @@ static inline void buffer_filled(struct cx231xx *dev,
237 buf->vb.field_count++; 237 buf->vb.field_count++;
238 do_gettimeofday(&buf->vb.ts); 238 do_gettimeofday(&buf->vb.ts);
239 239
240 dev->video_mode.isoc_ctl.buf = NULL; 240 if (dev->USE_ISO)
241 dev->video_mode.isoc_ctl.buf = NULL;
242 else
243 dev->video_mode.bulk_ctl.buf = NULL;
241 244
242 list_del(&buf->vb.queue); 245 list_del(&buf->vb.queue);
243 wake_up(&buf->vb.done); 246 wake_up(&buf->vb.done);
@@ -295,7 +298,10 @@ static inline void get_next_buf(struct cx231xx_dmaqueue *dma_q,
295 298
296 if (list_empty(&dma_q->active)) { 299 if (list_empty(&dma_q->active)) {
297 cx231xx_isocdbg("No active queue to serve\n"); 300 cx231xx_isocdbg("No active queue to serve\n");
298 dev->video_mode.isoc_ctl.buf = NULL; 301 if (dev->USE_ISO)
302 dev->video_mode.isoc_ctl.buf = NULL;
303 else
304 dev->video_mode.bulk_ctl.buf = NULL;
299 *buf = NULL; 305 *buf = NULL;
300 return; 306 return;
301 } 307 }
@@ -307,7 +313,10 @@ static inline void get_next_buf(struct cx231xx_dmaqueue *dma_q,
307 outp = videobuf_to_vmalloc(&(*buf)->vb); 313 outp = videobuf_to_vmalloc(&(*buf)->vb);
308 memset(outp, 0, (*buf)->vb.size); 314 memset(outp, 0, (*buf)->vb.size);
309 315
310 dev->video_mode.isoc_ctl.buf = *buf; 316 if (dev->USE_ISO)
317 dev->video_mode.isoc_ctl.buf = *buf;
318 else
319 dev->video_mode.bulk_ctl.buf = *buf;
311 320
312 return; 321 return;
313} 322}
@@ -418,6 +427,93 @@ static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
418 return rc; 427 return rc;
419} 428}
420 429
430static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
431{
432 struct cx231xx_buffer *buf;
433 struct cx231xx_dmaqueue *dma_q = urb->context;
434 unsigned char *outp = NULL;
435 int rc = 1;
436 unsigned char *p_buffer;
437 u32 bytes_parsed = 0, buffer_size = 0;
438 u8 sav_eav = 0;
439
440 if (!dev)
441 return 0;
442
443 if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED))
444 return 0;
445
446 if (urb->status < 0) {
447 print_err_status(dev, -1, urb->status);
448 if (urb->status == -ENOENT)
449 return 0;
450 }
451
452 buf = dev->video_mode.bulk_ctl.buf;
453 if (buf != NULL)
454 outp = videobuf_to_vmalloc(&buf->vb);
455
456 if (1) {
457
458 /* get buffer pointer and length */
459 p_buffer = urb->transfer_buffer;
460 buffer_size = urb->actual_length;
461 bytes_parsed = 0;
462
463 if (dma_q->is_partial_line) {
464 /* Handle the case of a partial line */
465 sav_eav = dma_q->last_sav;
466 } else {
467 /* Check for a SAV/EAV overlapping
468 the buffer boundary */
469 sav_eav =
470 cx231xx_find_boundary_SAV_EAV(p_buffer,
471 dma_q->partial_buf,
472 &bytes_parsed);
473 }
474
475 sav_eav &= 0xF0;
476 /* Get the first line if we have some portion of an SAV/EAV from
477 the last buffer or a partial line */
478 if (sav_eav) {
479 bytes_parsed += cx231xx_get_video_line(dev, dma_q,
480 sav_eav, /* SAV/EAV */
481 p_buffer + bytes_parsed, /* p_buffer */
482 buffer_size - bytes_parsed);/* buf size */
483 }
484
485 /* Now parse data that is completely in this buffer */
486 /* dma_q->is_partial_line = 0; */
487
488 while (bytes_parsed < buffer_size) {
489 u32 bytes_used = 0;
490
491 sav_eav = cx231xx_find_next_SAV_EAV(
492 p_buffer + bytes_parsed, /* p_buffer */
493 buffer_size - bytes_parsed, /* buf size */
494 &bytes_used);/* bytes used to get SAV/EAV */
495
496 bytes_parsed += bytes_used;
497
498 sav_eav &= 0xF0;
499 if (sav_eav && (bytes_parsed < buffer_size)) {
500 bytes_parsed += cx231xx_get_video_line(dev,
501 dma_q, sav_eav, /* SAV/EAV */
502 p_buffer + bytes_parsed,/* p_buffer */
503 buffer_size - bytes_parsed);/*buf size*/
504 }
505 }
506
507 /* Save the last four bytes of the buffer so we can check the
508 buffer boundary condition next time */
509 memcpy(dma_q->partial_buf, p_buffer + buffer_size - 4, 4);
510 bytes_parsed = 0;
511
512 }
513 return rc;
514}
515
516
421u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf, 517u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf,
422 u32 *p_bytes_used) 518 u32 *p_bytes_used)
423{ 519{
@@ -533,7 +629,10 @@ u32 cx231xx_copy_video_line(struct cx231xx *dev,
533 cx231xx_reset_video_buffer(dev, dma_q); 629 cx231xx_reset_video_buffer(dev, dma_q);
534 630
535 /* get the buffer pointer */ 631 /* get the buffer pointer */
536 buf = dev->video_mode.isoc_ctl.buf; 632 if (dev->USE_ISO)
633 buf = dev->video_mode.isoc_ctl.buf;
634 else
635 buf = dev->video_mode.bulk_ctl.buf;
537 636
538 /* Remember the field number for next time */ 637 /* Remember the field number for next time */
539 dma_q->current_field = field_number; 638 dma_q->current_field = field_number;
@@ -596,7 +695,10 @@ void cx231xx_reset_video_buffer(struct cx231xx *dev,
596 dma_q->field1_done = 0; 695 dma_q->field1_done = 0;
597 } 696 }
598 697
599 buf = dev->video_mode.isoc_ctl.buf; 698 if (dev->USE_ISO)
699 buf = dev->video_mode.isoc_ctl.buf;
700 else
701 buf = dev->video_mode.bulk_ctl.buf;
600 702
601 if (buf == NULL) { 703 if (buf == NULL) {
602 u8 *outp = NULL; 704 u8 *outp = NULL;
@@ -626,7 +728,10 @@ int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
626 void *startwrite; 728 void *startwrite;
627 int offset, lencopy; 729 int offset, lencopy;
628 730
629 buf = dev->video_mode.isoc_ctl.buf; 731 if (dev->USE_ISO)
732 buf = dev->video_mode.isoc_ctl.buf;
733 else
734 buf = dev->video_mode.bulk_ctl.buf;
630 735
631 if (buf == NULL) 736 if (buf == NULL)
632 return -1; 737 return -1;
@@ -691,7 +796,6 @@ buffer_setup(struct videobuf_queue *vq, unsigned int *count, unsigned int *size)
691{ 796{
692 struct cx231xx_fh *fh = vq->priv_data; 797 struct cx231xx_fh *fh = vq->priv_data;
693 struct cx231xx *dev = fh->dev; 798 struct cx231xx *dev = fh->dev;
694 struct v4l2_frequency f;
695 799
696 *size = (fh->dev->width * fh->dev->height * dev->format->depth + 7)>>3; 800 *size = (fh->dev->width * fh->dev->height * dev->format->depth + 7)>>3;
697 if (0 == *count) 801 if (0 == *count)
@@ -700,13 +804,6 @@ buffer_setup(struct videobuf_queue *vq, unsigned int *count, unsigned int *size)
700 if (*count < CX231XX_MIN_BUF) 804 if (*count < CX231XX_MIN_BUF)
701 *count = CX231XX_MIN_BUF; 805 *count = CX231XX_MIN_BUF;
702 806
703 /* Ask tuner to go to analog mode */
704 memset(&f, 0, sizeof(f));
705 f.frequency = dev->ctl_freq;
706 f.type = fh->radio ? V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
707
708 call_all(dev, tuner, s_frequency, &f);
709
710 return 0; 807 return 0;
711} 808}
712 809
@@ -730,8 +827,13 @@ static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
730 VIDEOBUF_ACTIVE, it won't be, though. 827 VIDEOBUF_ACTIVE, it won't be, though.
731 */ 828 */
732 spin_lock_irqsave(&dev->video_mode.slock, flags); 829 spin_lock_irqsave(&dev->video_mode.slock, flags);
733 if (dev->video_mode.isoc_ctl.buf == buf) 830 if (dev->USE_ISO) {
734 dev->video_mode.isoc_ctl.buf = NULL; 831 if (dev->video_mode.isoc_ctl.buf == buf)
832 dev->video_mode.isoc_ctl.buf = NULL;
833 } else {
834 if (dev->video_mode.bulk_ctl.buf == buf)
835 dev->video_mode.bulk_ctl.buf = NULL;
836 }
735 spin_unlock_irqrestore(&dev->video_mode.slock, flags); 837 spin_unlock_irqrestore(&dev->video_mode.slock, flags);
736 838
737 videobuf_vmalloc_free(&buf->vb); 839 videobuf_vmalloc_free(&buf->vb);
@@ -764,14 +866,27 @@ buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb,
764 goto fail; 866 goto fail;
765 } 867 }
766 868
767 if (!dev->video_mode.isoc_ctl.num_bufs) 869 if (dev->USE_ISO) {
768 urb_init = 1; 870 if (!dev->video_mode.isoc_ctl.num_bufs)
769 871 urb_init = 1;
872 } else {
873 if (!dev->video_mode.bulk_ctl.num_bufs)
874 urb_init = 1;
875 }
876 /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
877 urb_init, dev->video_mode.max_pkt_size);*/
770 if (urb_init) { 878 if (urb_init) {
771 rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS, 879 dev->mode_tv = 0;
880 if (dev->USE_ISO)
881 rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
772 CX231XX_NUM_BUFS, 882 CX231XX_NUM_BUFS,
773 dev->video_mode.max_pkt_size, 883 dev->video_mode.max_pkt_size,
774 cx231xx_isoc_copy); 884 cx231xx_isoc_copy);
885 else
886 rc = cx231xx_init_bulk(dev, CX231XX_NUM_PACKETS,
887 CX231XX_NUM_BUFS,
888 dev->video_mode.max_pkt_size,
889 cx231xx_bulk_copy);
775 if (rc < 0) 890 if (rc < 0)
776 goto fail; 891 goto fail;
777 } 892 }
@@ -1039,7 +1154,7 @@ out:
1039 return rc; 1154 return rc;
1040} 1155}
1041 1156
1042static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id * id) 1157static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id)
1043{ 1158{
1044 struct cx231xx_fh *fh = priv; 1159 struct cx231xx_fh *fh = priv;
1045 struct cx231xx *dev = fh->dev; 1160 struct cx231xx *dev = fh->dev;
@@ -1138,6 +1253,19 @@ static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1138 struct cx231xx *dev = fh->dev; 1253 struct cx231xx *dev = fh->dev;
1139 int rc; 1254 int rc;
1140 1255
1256 if (i == 10) {
1257 dev->USE_ISO = 0;
1258 cx231xx_info("trans-mode=BULK. USE_ISO = %d\n", dev->USE_ISO);
1259 return 0;
1260 }
1261
1262 if (i == 11) {
1263 dev->USE_ISO = 1;
1264 cx231xx_info("trans-mode=ISOC. USE_ISO = %d\n", dev->USE_ISO);
1265 return 0;
1266 }
1267
1268 dev->mode_tv = 0;
1141 rc = check_dev(dev); 1269 rc = check_dev(dev);
1142 if (rc < 0) 1270 if (rc < 0)
1143 return rc; 1271 return rc;
@@ -1337,6 +1465,11 @@ static int vidioc_s_frequency(struct file *file, void *priv,
1337 struct cx231xx_fh *fh = priv; 1465 struct cx231xx_fh *fh = priv;
1338 struct cx231xx *dev = fh->dev; 1466 struct cx231xx *dev = fh->dev;
1339 int rc; 1467 int rc;
1468 u32 if_frequency = 5400000;
1469
1470 cx231xx_info("Enter vidioc_s_frequency()f->frequency=%d;f->type=%d\n",
1471 f->frequency, f->type);
1472 /*cx231xx_info("f->type: 1-radio 2-analogTV 3-digitalTV\n");*/
1340 1473
1341 rc = check_dev(dev); 1474 rc = check_dev(dev);
1342 if (rc < 0) 1475 if (rc < 0)
@@ -1356,18 +1489,35 @@ static int vidioc_s_frequency(struct file *file, void *priv,
1356 mutex_lock(&dev->lock); 1489 mutex_lock(&dev->lock);
1357 1490
1358 dev->ctl_freq = f->frequency; 1491 dev->ctl_freq = f->frequency;
1359 1492 call_all(dev, tuner, s_frequency, f);
1360 if (dev->tuner_type == TUNER_XC5000) {
1361 if (dev->cx231xx_set_analog_freq != NULL)
1362 dev->cx231xx_set_analog_freq(dev, f->frequency);
1363 } else
1364 call_all(dev, tuner, s_frequency, f);
1365 1493
1366 mutex_unlock(&dev->lock); 1494 mutex_unlock(&dev->lock);
1367 1495
1368 /* set post channel change settings in DIF first */ 1496 /* set post channel change settings in DIF first */
1369 rc = cx231xx_tuner_post_channel_change(dev); 1497 rc = cx231xx_tuner_post_channel_change(dev);
1370 1498
1499 if (dev->tuner_type == TUNER_NXP_TDA18271) {
1500 if (dev->norm & (V4L2_STD_MN | V4L2_STD_NTSC_443))
1501 if_frequency = 5400000; /*5.4MHz */
1502 else if (dev->norm & V4L2_STD_B)
1503 if_frequency = 6000000; /*6.0MHz */
1504 else if (dev->norm & (V4L2_STD_PAL_DK | V4L2_STD_SECAM_DK))
1505 if_frequency = 6900000; /*6.9MHz */
1506 else if (dev->norm & V4L2_STD_GH)
1507 if_frequency = 7100000; /*7.1MHz */
1508 else if (dev->norm & V4L2_STD_PAL_I)
1509 if_frequency = 7250000; /*7.25MHz */
1510 else if (dev->norm & V4L2_STD_SECAM_L)
1511 if_frequency = 6900000; /*6.9MHz */
1512 else if (dev->norm & V4L2_STD_SECAM_LC)
1513 if_frequency = 1250000; /*1.25MHz */
1514
1515 cx231xx_info("if_frequency is set to %d\n", if_frequency);
1516 cx231xx_set_Colibri_For_LowIF(dev, if_frequency, 1, 1);
1517
1518 update_HH_register_after_set_DIF(dev);
1519 }
1520
1371 cx231xx_info("Set New FREQUENCY to %d\n", f->frequency); 1521 cx231xx_info("Set New FREQUENCY to %d\n", f->frequency);
1372 1522
1373 return rc; 1523 return rc;
@@ -1445,9 +1595,86 @@ static int vidioc_g_register(struct file *file, void *priv,
1445 case V4L2_CHIP_MATCH_I2C_DRIVER: 1595 case V4L2_CHIP_MATCH_I2C_DRIVER:
1446 call_all(dev, core, g_register, reg); 1596 call_all(dev, core, g_register, reg);
1447 return 0; 1597 return 0;
1448 case V4L2_CHIP_MATCH_I2C_ADDR: 1598 case V4L2_CHIP_MATCH_I2C_ADDR:/*for register debug*/
1449 /* Not supported yet */ 1599 switch (reg->match.addr) {
1450 return -EINVAL; 1600 case 0: /* Cx231xx - internal registers */
1601 ret = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1602 (u16)reg->reg, value, 4);
1603 reg->val = value[0] | value[1] << 8 |
1604 value[2] << 16 | value[3] << 24;
1605
1606 break;
1607 case 0x600:/* AFE - read byte */
1608 ret = cx231xx_read_i2c_master(dev, AFE_DEVICE_ADDRESS,
1609 (u16)reg->reg, 2,
1610 &data, 1 , 0);
1611 reg->val = le32_to_cpu(data & 0xff);
1612 break;
1613
1614 case 0x880:/* Video Block - read byte */
1615 if (reg->reg < 0x0b) {
1616 ret = cx231xx_read_i2c_master(dev,
1617 VID_BLK_I2C_ADDRESS,
1618 (u16)reg->reg, 2,
1619 &data, 1 , 0);
1620 reg->val = le32_to_cpu(data & 0xff);
1621 } else {
1622 ret = cx231xx_read_i2c_master(dev,
1623 VID_BLK_I2C_ADDRESS,
1624 (u16)reg->reg, 2,
1625 &data, 4 , 0);
1626 reg->val = le32_to_cpu(data);
1627 }
1628 break;
1629 case 0x980:
1630 ret = cx231xx_read_i2c_master(dev,
1631 I2S_BLK_DEVICE_ADDRESS,
1632 (u16)reg->reg, 1,
1633 &data, 1 , 0);
1634 reg->val = le32_to_cpu(data & 0xff);
1635 break;
1636 case 0x400:
1637 ret =
1638 cx231xx_read_i2c_master(dev, 0x40,
1639 (u16)reg->reg, 1,
1640 &data, 1 , 0);
1641 reg->val = le32_to_cpu(data & 0xff);
1642 break;
1643 case 0xc01:
1644 ret =
1645 cx231xx_read_i2c_master(dev, 0xc0,
1646 (u16)reg->reg, 2,
1647 &data, 38, 1);
1648 reg->val = le32_to_cpu(data);
1649 break;
1650 case 0x022:
1651 ret =
1652 cx231xx_read_i2c_master(dev, 0x02,
1653 (u16)reg->reg, 1,
1654 &data, 1, 2);
1655 reg->val = le32_to_cpu(data & 0xff);
1656 break;
1657 case 0x322:
1658 ret = cx231xx_read_i2c_master(dev,
1659 0x32,
1660 (u16)reg->reg, 1,
1661 &data, 4 , 2);
1662 reg->val = le32_to_cpu(data);
1663 break;
1664 case 0x342:
1665 ret = cx231xx_read_i2c_master(dev,
1666 0x34,
1667 (u16)reg->reg, 1,
1668 &data, 4 , 2);
1669 reg->val = le32_to_cpu(data);
1670 break;
1671
1672 default:
1673 cx231xx_info("no match device address!!\n");
1674 break;
1675 }
1676 return ret < 0 ? ret : 0;
1677 /*return -EINVAL;*/
1451 default: 1678 default:
1452 if (!v4l2_chip_match_host(&reg->match)) 1679 if (!v4l2_chip_match_host(&reg->match))
1453 return -EINVAL; 1680 return -EINVAL;
@@ -1531,7 +1758,91 @@ static int vidioc_s_register(struct file *file, void *priv,
1531 } 1758 }
1532 } 1759 }
1533 return ret < 0 ? ret : 0; 1760 return ret < 0 ? ret : 0;
1761 case V4L2_CHIP_MATCH_I2C_ADDR:
1762 {
1763 value = (u32) buf & 0xffffffff;
1534 1764
1765 switch (reg->match.addr) {
1766 case 0:/*cx231xx internal registers*/
1767 data[0] = (u8) value;
1768 data[1] = (u8) (value >> 8);
1769 data[2] = (u8) (value >> 16);
1770 data[3] = (u8) (value >> 24);
1771 ret = cx231xx_write_ctrl_reg(dev,
1772 VRT_SET_REGISTER,
1773 (u16)reg->reg, data,
1774 4);
1775 break;
1776 case 0x600:/* AFE - read byte */
1777 ret = cx231xx_write_i2c_master(dev,
1778 AFE_DEVICE_ADDRESS,
1779 (u16)reg->reg, 2,
1780 value, 1 , 0);
1781 break;
1782
1783 case 0x880:/* Video Block - read byte */
1784 if (reg->reg < 0x0b)
1785 cx231xx_write_i2c_master(dev,
1786 VID_BLK_I2C_ADDRESS,
1787 (u16)reg->reg, 2,
1788 value, 1, 0);
1789 else
1790 cx231xx_write_i2c_master(dev,
1791 VID_BLK_I2C_ADDRESS,
1792 (u16)reg->reg, 2,
1793 value, 4, 0);
1794 break;
1795 case 0x980:
1796 ret =
1797 cx231xx_write_i2c_master(dev,
1798 I2S_BLK_DEVICE_ADDRESS,
1799 (u16)reg->reg, 1,
1800 value, 1, 0);
1801 break;
1802 case 0x400:
1803 ret =
1804 cx231xx_write_i2c_master(dev,
1805 0x40,
1806 (u16)reg->reg, 1,
1807 value, 1, 0);
1808 break;
1809 case 0xc01:
1810 ret =
1811 cx231xx_write_i2c_master(dev,
1812 0xc0,
1813 (u16)reg->reg, 1,
1814 value, 1, 1);
1815 break;
1816
1817 case 0x022:
1818 ret =
1819 cx231xx_write_i2c_master(dev,
1820 0x02,
1821 (u16)reg->reg, 1,
1822 value, 1, 2);
1823 case 0x322:
1824 ret =
1825 cx231xx_write_i2c_master(dev,
1826 0x32,
1827 (u16)reg->reg, 1,
1828 value, 4, 2);
1829 break;
1830
1831 case 0x342:
1832 ret =
1833 cx231xx_write_i2c_master(dev,
1834 0x34,
1835 (u16)reg->reg, 1,
1836 value, 4, 2);
1837 break;
1838 default:
1839 cx231xx_info("no match device address, "
1840 "the value is %x\n", reg->match.addr);
1841 break;
1842
1843 }
1844
1845 }
1535 default: 1846 default:
1536 break; 1847 break;
1537 } 1848 }
@@ -1975,7 +2286,11 @@ static int cx231xx_v4l2_open(struct file *filp)
1975 dev->vscale = 0; 2286 dev->vscale = 0;
1976 2287
1977 /* Power up in Analog TV mode */ 2288 /* Power up in Analog TV mode */
1978 cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); 2289 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER)
2290 cx231xx_set_power_mode(dev,
2291 POLARIS_AVMODE_ENXTERNAL_AV);
2292 else
2293 cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV);
1979 2294
1980#if 0 2295#if 0
1981 cx231xx_set_mode(dev, CX231XX_ANALOG_MODE); 2296 cx231xx_set_mode(dev, CX231XX_ANALOG_MODE);
@@ -1991,7 +2306,6 @@ static int cx231xx_v4l2_open(struct file *filp)
1991 2306
1992 /* device needs to be initialized before isoc transfer */ 2307 /* device needs to be initialized before isoc transfer */
1993 dev->video_input = dev->video_input > 2 ? 2 : dev->video_input; 2308 dev->video_input = dev->video_input > 2 ? 2 : dev->video_input;
1994 video_mux(dev, dev->video_input);
1995 2309
1996 } 2310 }
1997 if (fh->radio) { 2311 if (fh->radio) {
@@ -2013,7 +2327,8 @@ static int cx231xx_v4l2_open(struct file *filp)
2013 if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) { 2327 if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
2014 /* Set the required alternate setting VBI interface works in 2328 /* Set the required alternate setting VBI interface works in
2015 Bulk mode only */ 2329 Bulk mode only */
2016 cx231xx_set_alt_setting(dev, INDEX_VANC, 0); 2330 if (dev->model != CX231XX_BOARD_CNXT_VIDEO_GRABBER)
2331 cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
2017 2332
2018 videobuf_queue_vmalloc_init(&fh->vb_vidq, &cx231xx_vbi_qops, 2333 videobuf_queue_vmalloc_init(&fh->vb_vidq, &cx231xx_vbi_qops,
2019 NULL, &dev->vbi_mode.slock, 2334 NULL, &dev->vbi_mode.slock,
@@ -2056,6 +2371,10 @@ void cx231xx_release_analog_resources(struct cx231xx *dev)
2056 if (dev->vdev) { 2371 if (dev->vdev) {
2057 cx231xx_info("V4L2 device %s deregistered\n", 2372 cx231xx_info("V4L2 device %s deregistered\n",
2058 video_device_node_name(dev->vdev)); 2373 video_device_node_name(dev->vdev));
2374
2375 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER)
2376 cx231xx_417_unregister(dev);
2377
2059 if (video_is_registered(dev->vdev)) 2378 if (video_is_registered(dev->vdev))
2060 video_unregister_device(dev->vdev); 2379 video_unregister_device(dev->vdev);
2061 else 2380 else
@@ -2077,39 +2396,47 @@ static int cx231xx_v4l2_close(struct file *filp)
2077 cx231xx_videodbg("users=%d\n", dev->users); 2396 cx231xx_videodbg("users=%d\n", dev->users);
2078 2397
2079 mutex_lock(&dev->lock); 2398 mutex_lock(&dev->lock);
2080 2399 cx231xx_videodbg("users=%d\n", dev->users);
2081 if (res_check(fh)) 2400 if (res_check(fh))
2082 res_free(fh); 2401 res_free(fh);
2083 2402
2084 if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) { 2403 /*To workaround error number=-71 on EP0 for VideoGrabber,
2085 videobuf_stop(&fh->vb_vidq); 2404 need exclude following.*/
2086 videobuf_mmap_free(&fh->vb_vidq); 2405 if (dev->model != CX231XX_BOARD_CNXT_VIDEO_GRABBER)
2406 if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
2407 videobuf_stop(&fh->vb_vidq);
2408 videobuf_mmap_free(&fh->vb_vidq);
2409
2410 /* the device is already disconnect,
2411 free the remaining resources */
2412 if (dev->state & DEV_DISCONNECTED) {
2413 if (atomic_read(&dev->devlist_count) > 0) {
2414 cx231xx_release_resources(dev);
2415 mutex_unlock(&dev->lock);
2416 kfree(dev);
2417 dev = NULL;
2418 return 0;
2419 }
2420 mutex_unlock(&dev->lock);
2421 return 0;
2422 }
2087 2423
2088 /* the device is already disconnect, 2424 /* do this before setting alternate! */
2089 free the remaining resources */ 2425 cx231xx_uninit_vbi_isoc(dev);
2090 if (dev->state & DEV_DISCONNECTED) { 2426
2091 cx231xx_release_resources(dev); 2427 /* set alternate 0 */
2428 if (!dev->vbi_or_sliced_cc_mode)
2429 cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
2430 else
2431 cx231xx_set_alt_setting(dev, INDEX_HANC, 0);
2432
2433 kfree(fh);
2434 dev->users--;
2435 wake_up_interruptible_nr(&dev->open, 1);
2092 mutex_unlock(&dev->lock); 2436 mutex_unlock(&dev->lock);
2093 kfree(dev);
2094 return 0; 2437 return 0;
2095 } 2438 }
2096 2439
2097 /* do this before setting alternate! */
2098 cx231xx_uninit_vbi_isoc(dev);
2099
2100 /* set alternate 0 */
2101 if (!dev->vbi_or_sliced_cc_mode)
2102 cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
2103 else
2104 cx231xx_set_alt_setting(dev, INDEX_HANC, 0);
2105
2106 kfree(fh);
2107 dev->users--;
2108 wake_up_interruptible_nr(&dev->open, 1);
2109 mutex_unlock(&dev->lock);
2110 return 0;
2111 }
2112
2113 if (dev->users == 1) { 2440 if (dev->users == 1) {
2114 videobuf_stop(&fh->vb_vidq); 2441 videobuf_stop(&fh->vb_vidq);
2115 videobuf_mmap_free(&fh->vb_vidq); 2442 videobuf_mmap_free(&fh->vb_vidq);
@@ -2120,6 +2447,7 @@ static int cx231xx_v4l2_close(struct file *filp)
2120 cx231xx_release_resources(dev); 2447 cx231xx_release_resources(dev);
2121 mutex_unlock(&dev->lock); 2448 mutex_unlock(&dev->lock);
2122 kfree(dev); 2449 kfree(dev);
2450 dev = NULL;
2123 return 0; 2451 return 0;
2124 } 2452 }
2125 2453
@@ -2127,7 +2455,10 @@ static int cx231xx_v4l2_close(struct file *filp)
2127 call_all(dev, core, s_power, 0); 2455 call_all(dev, core, s_power, 0);
2128 2456
2129 /* do this before setting alternate! */ 2457 /* do this before setting alternate! */
2130 cx231xx_uninit_isoc(dev); 2458 if (dev->USE_ISO)
2459 cx231xx_uninit_isoc(dev);
2460 else
2461 cx231xx_uninit_bulk(dev);
2131 cx231xx_set_mode(dev, CX231XX_SUSPEND); 2462 cx231xx_set_mode(dev, CX231XX_SUSPEND);
2132 2463
2133 /* set alternate 0 */ 2464 /* set alternate 0 */
@@ -2175,7 +2506,7 @@ cx231xx_v4l2_read(struct file *filp, char __user *buf, size_t count,
2175 * cx231xx_v4l2_poll() 2506 * cx231xx_v4l2_poll()
2176 * will allocate buffers when called for the first time 2507 * will allocate buffers when called for the first time
2177 */ 2508 */
2178static unsigned int cx231xx_v4l2_poll(struct file *filp, poll_table * wait) 2509static unsigned int cx231xx_v4l2_poll(struct file *filp, poll_table *wait)
2179{ 2510{
2180 struct cx231xx_fh *fh = filp->private_data; 2511 struct cx231xx_fh *fh = filp->private_data;
2181 struct cx231xx *dev = fh->dev; 2512 struct cx231xx *dev = fh->dev;
diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h
index 38d417191a65..d9a90c50aaa0 100644
--- a/drivers/media/video/cx231xx/cx231xx.h
+++ b/drivers/media/video/cx231xx/cx231xx.h
@@ -29,6 +29,7 @@
29#include <linux/i2c-algo-bit.h> 29#include <linux/i2c-algo-bit.h>
30#include <linux/mutex.h> 30#include <linux/mutex.h>
31 31
32#include <media/cx2341x.h>
32 33
33#include <media/videobuf-vmalloc.h> 34#include <media/videobuf-vmalloc.h>
34#include <media/v4l2-device.h> 35#include <media/v4l2-device.h>
@@ -49,12 +50,18 @@
49#define AFE_DEVICE_ADDRESS 0x60 50#define AFE_DEVICE_ADDRESS 0x60
50#define I2S_BLK_DEVICE_ADDRESS 0x98 51#define I2S_BLK_DEVICE_ADDRESS 0x98
51#define VID_BLK_I2C_ADDRESS 0x88 52#define VID_BLK_I2C_ADDRESS 0x88
53#define VERVE_I2C_ADDRESS 0x40
52#define DIF_USE_BASEBAND 0xFFFFFFFF 54#define DIF_USE_BASEBAND 0xFFFFFFFF
53 55
54/* Boards supported by driver */ 56/* Boards supported by driver */
55#define CX231XX_BOARD_UNKNOWN 0 57#define CX231XX_BOARD_UNKNOWN 0
56#define CX231XX_BOARD_CNXT_RDE_250 1 58#define CX231XX_BOARD_CNXT_CARRAERA 1
57#define CX231XX_BOARD_CNXT_RDU_250 2 59#define CX231XX_BOARD_CNXT_SHELBY 2
60#define CX231XX_BOARD_CNXT_RDE_253S 3
61#define CX231XX_BOARD_CNXT_RDU_253S 4
62#define CX231XX_BOARD_CNXT_VIDEO_GRABBER 5
63#define CX231XX_BOARD_CNXT_RDE_250 6
64#define CX231XX_BOARD_CNXT_RDU_250 7
58 65
59/* Limits minimum and default number of buffers */ 66/* Limits minimum and default number of buffers */
60#define CX231XX_MIN_BUF 4 67#define CX231XX_MIN_BUF 4
@@ -95,6 +102,24 @@
95#define CX231XX_URB_TIMEOUT \ 102#define CX231XX_URB_TIMEOUT \
96 msecs_to_jiffies(CX231XX_NUM_BUFS * CX231XX_NUM_PACKETS) 103 msecs_to_jiffies(CX231XX_NUM_BUFS * CX231XX_NUM_PACKETS)
97 104
105#define CX231xx_NORMS (\
106 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
107 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
108 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
109 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
110#define CX231xx_VERSION_CODE KERNEL_VERSION(0, 0, 2)
111
112#define SLEEP_S5H1432 30
113#define CX23417_OSC_EN 8
114#define CX23417_RESET 9
115
116struct cx23417_fmt {
117 char *name;
118 u32 fourcc; /* v4l2 format id */
119 int depth;
120 int flags;
121 u32 cxformat;
122};
98enum cx231xx_mode { 123enum cx231xx_mode {
99 CX231XX_SUSPEND, 124 CX231XX_SUSPEND,
100 CX231XX_ANALOG_MODE, 125 CX231XX_ANALOG_MODE,
@@ -114,7 +139,7 @@ enum cx231xx_stream_state {
114 139
115struct cx231xx; 140struct cx231xx;
116 141
117struct cx231xx_usb_isoc_ctl { 142struct cx231xx_isoc_ctl {
118 /* max packet size of isoc transaction */ 143 /* max packet size of isoc transaction */
119 int max_pkt_size; 144 int max_pkt_size;
120 145
@@ -148,6 +173,40 @@ struct cx231xx_usb_isoc_ctl {
148 int (*isoc_copy) (struct cx231xx *dev, struct urb *urb); 173 int (*isoc_copy) (struct cx231xx *dev, struct urb *urb);
149}; 174};
150 175
176struct cx231xx_bulk_ctl {
177 /* max packet size of bulk transaction */
178 int max_pkt_size;
179
180 /* number of allocated urbs */
181 int num_bufs;
182
183 /* urb for bulk transfers */
184 struct urb **urb;
185
186 /* transfer buffers for bulk transfer */
187 char **transfer_buffer;
188
189 /* Last buffer command and region */
190 u8 cmd;
191 int pos, size, pktsize;
192
193 /* Last field: ODD or EVEN? */
194 int field;
195
196 /* Stores incomplete commands */
197 u32 tmp_buf;
198 int tmp_buf_len;
199
200 /* Stores already requested buffers */
201 struct cx231xx_buffer *buf;
202
203 /* Stores the number of received fields */
204 int nfields;
205
206 /* bulk urb callback */
207 int (*bulk_copy) (struct cx231xx *dev, struct urb *urb);
208};
209
151struct cx231xx_fmt { 210struct cx231xx_fmt {
152 char *name; 211 char *name;
153 u32 fourcc; /* v4l2 format id */ 212 u32 fourcc; /* v4l2 format id */
@@ -165,6 +224,11 @@ struct cx231xx_buffer {
165 int receiving; 224 int receiving;
166}; 225};
167 226
227enum ps_package_head {
228 CX231XX_NEED_ADD_PS_PACKAGE_HEAD = 0,
229 CX231XX_NONEED_PS_PACKAGE_HEAD
230};
231
168struct cx231xx_dmaqueue { 232struct cx231xx_dmaqueue {
169 struct list_head active; 233 struct list_head active;
170 struct list_head queued; 234 struct list_head queued;
@@ -181,6 +245,14 @@ struct cx231xx_dmaqueue {
181 u32 lines_completed; 245 u32 lines_completed;
182 u8 field1_done; 246 u8 field1_done;
183 u32 lines_per_field; 247 u32 lines_per_field;
248
249 /*Mpeg2 control buffer*/
250 u8 *p_left_data;
251 u32 left_data_count;
252 u8 mpeg_buffer_done;
253 u32 mpeg_buffer_completed;
254 enum ps_package_head add_ps_package_head;
255 char ps_head[10];
184}; 256};
185 257
186/* inputs */ 258/* inputs */
@@ -309,7 +381,8 @@ enum AUDIO_INPUT {
309}; 381};
310 382
311#define CX231XX_AUDIO_BUFS 5 383#define CX231XX_AUDIO_BUFS 5
312#define CX231XX_NUM_AUDIO_PACKETS 64 384#define CX231XX_NUM_AUDIO_PACKETS 16
385#define CX231XX_ISO_NUM_AUDIO_PACKETS 64
313#define CX231XX_CAPTURE_STREAM_EN 1 386#define CX231XX_CAPTURE_STREAM_EN 1
314#define CX231XX_STOP_AUDIO 0 387#define CX231XX_STOP_AUDIO 0
315#define CX231XX_START_AUDIO 1 388#define CX231XX_START_AUDIO 1
@@ -331,6 +404,7 @@ struct cx231xx_audio {
331 404
332 int users, shutdown; 405 int users, shutdown;
333 enum cx231xx_stream_state capture_stream; 406 enum cx231xx_stream_state capture_stream;
407 /* locks */
334 spinlock_t slock; 408 spinlock_t slock;
335 409
336 int alt; /* alternate */ 410 int alt; /* alternate */
@@ -350,6 +424,28 @@ struct cx231xx_fh {
350 struct videobuf_queue vb_vidq; 424 struct videobuf_queue vb_vidq;
351 425
352 enum v4l2_buf_type type; 426 enum v4l2_buf_type type;
427
428
429
430/*following is copyed from cx23885.h*/
431 u32 resources;
432
433 /* video overlay */
434 struct v4l2_window win;
435 struct v4l2_clip *clips;
436 unsigned int nclips;
437
438 /* video capture */
439 struct cx23417_fmt *fmt;
440 unsigned int width, height;
441
442 /* vbi capture */
443 struct videobuf_queue vidq;
444 struct videobuf_queue vbiq;
445
446 /* MPEG Encoder specifics ONLY */
447
448 atomic_t v4l_reading;
353}; 449};
354 450
355/*****************************************************************/ 451/*****************************************************************/
@@ -403,6 +499,13 @@ struct VENDOR_REQUEST_IN {
403 u8 *pBuff; 499 u8 *pBuff;
404}; 500};
405 501
502struct cx231xx_tvnorm {
503 char *name;
504 v4l2_std_id id;
505 u32 cxiformat;
506 u32 cxoformat;
507};
508
406struct cx231xx_ctrl { 509struct cx231xx_ctrl {
407 struct v4l2_queryctrl v; 510 struct v4l2_queryctrl v;
408 u32 off; 511 u32 off;
@@ -424,7 +527,9 @@ enum TRANSFER_TYPE {
424struct cx231xx_video_mode { 527struct cx231xx_video_mode {
425 /* Isoc control struct */ 528 /* Isoc control struct */
426 struct cx231xx_dmaqueue vidq; 529 struct cx231xx_dmaqueue vidq;
427 struct cx231xx_usb_isoc_ctl isoc_ctl; 530 struct cx231xx_isoc_ctl isoc_ctl;
531 struct cx231xx_bulk_ctl bulk_ctl;
532 /* locks */
428 spinlock_t slock; 533 spinlock_t slock;
429 534
430 /* usb transfer */ 535 /* usb transfer */
@@ -434,6 +539,64 @@ struct cx231xx_video_mode {
434 unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */ 539 unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
435 u16 end_point_addr; 540 u16 end_point_addr;
436}; 541};
542/*
543struct cx23885_dmaqueue {
544 struct list_head active;
545 struct list_head queued;
546 struct timer_list timeout;
547 struct btcx_riscmem stopper;
548 u32 count;
549};
550*/
551struct cx231xx_tsport {
552 struct cx231xx *dev;
553
554 int nr;
555 int sram_chno;
556
557 struct videobuf_dvb_frontends frontends;
558
559 /* dma queues */
560
561 u32 ts_packet_size;
562 u32 ts_packet_count;
563
564 int width;
565 int height;
566
567 /* locks */
568 spinlock_t slock;
569
570 /* registers */
571 u32 reg_gpcnt;
572 u32 reg_gpcnt_ctl;
573 u32 reg_dma_ctl;
574 u32 reg_lngth;
575 u32 reg_hw_sop_ctrl;
576 u32 reg_gen_ctrl;
577 u32 reg_bd_pkt_status;
578 u32 reg_sop_status;
579 u32 reg_fifo_ovfl_stat;
580 u32 reg_vld_misc;
581 u32 reg_ts_clk_en;
582 u32 reg_ts_int_msk;
583 u32 reg_ts_int_stat;
584 u32 reg_src_sel;
585
586 /* Default register vals */
587 int pci_irqmask;
588 u32 dma_ctl_val;
589 u32 ts_int_msk_val;
590 u32 gen_ctrl_val;
591 u32 ts_clk_en_val;
592 u32 src_sel_val;
593 u32 vld_misc_val;
594 u32 hw_sop_ctrl_val;
595
596 /* Allow a single tsport to have multiple frontends */
597 u32 num_frontends;
598 void *port_priv;
599};
437 600
438/* main device struct */ 601/* main device struct */
439struct cx231xx { 602struct cx231xx {
@@ -465,7 +628,9 @@ struct cx231xx {
465 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ 628 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
466 struct cx231xx_i2c i2c_bus[3]; 629 struct cx231xx_i2c i2c_bus[3];
467 unsigned int xc_fw_load_done:1; 630 unsigned int xc_fw_load_done:1;
631 /* locks */
468 struct mutex gpio_i2c_lock; 632 struct mutex gpio_i2c_lock;
633 struct mutex i2c_lock;
469 634
470 /* video for linux */ 635 /* video for linux */
471 int users; /* user count for exclusive use */ 636 int users; /* user count for exclusive use */
@@ -505,6 +670,8 @@ struct cx231xx {
505 struct cx231xx_video_mode sliced_cc_mode; 670 struct cx231xx_video_mode sliced_cc_mode;
506 struct cx231xx_video_mode ts1_mode; 671 struct cx231xx_video_mode ts1_mode;
507 672
673 atomic_t devlist_count;
674
508 struct usb_device *udev; /* the usb device */ 675 struct usb_device *udev; /* the usb device */
509 char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */ 676 char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */
510 677
@@ -550,8 +717,24 @@ struct cx231xx {
550 u8 vbi_or_sliced_cc_mode; /* 0 - vbi ; 1 - sliced cc mode */ 717 u8 vbi_or_sliced_cc_mode; /* 0 - vbi ; 1 - sliced cc mode */
551 enum cx231xx_std_mode std_mode; /* 0 - Air; 1 - cable */ 718 enum cx231xx_std_mode std_mode; /* 0 - Air; 1 - cable */
552 719
720 /*mode: digital=1 or analog=0*/
721 u8 mode_tv;
722
723 u8 USE_ISO;
724 struct cx231xx_tvnorm encodernorm;
725 struct cx231xx_tsport ts1, ts2;
726 struct cx2341x_mpeg_params mpeg_params;
727 struct video_device *v4l_device;
728 atomic_t v4l_reader_count;
729 u32 freq;
730 unsigned int input;
731 u32 cx23417_mailbox;
732 u32 __iomem *lmmio;
733 u8 __iomem *bmmio;
553}; 734};
554 735
736extern struct list_head cx231xx_devlist;
737
555#define cx25840_call(cx231xx, o, f, args...) \ 738#define cx25840_call(cx231xx, o, f, args...) \
556 v4l2_subdev_call(cx231xx->sd_cx25840, o, f, ##args) 739 v4l2_subdev_call(cx231xx->sd_cx25840, o, f, ##args)
557#define tuner_call(cx231xx, o, f, args...) \ 740#define tuner_call(cx231xx, o, f, args...) \
@@ -577,6 +760,10 @@ int cx231xx_i2c_register(struct cx231xx_i2c *bus);
577int cx231xx_i2c_unregister(struct cx231xx_i2c *bus); 760int cx231xx_i2c_unregister(struct cx231xx_i2c *bus);
578 761
579/* Internal block control functions */ 762/* Internal block control functions */
763int cx231xx_read_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
764 u8 saddr_len, u32 *data, u8 data_len, int master);
765int cx231xx_write_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
766 u8 saddr_len, u32 data, u8 data_len, int master);
580int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr, 767int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr,
581 u16 saddr, u8 saddr_len, u32 *data, u8 data_len); 768 u16 saddr, u8 saddr_len, u32 *data, u8 data_len);
582int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr, 769int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr,
@@ -588,6 +775,9 @@ int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
588 u16 saddr, u32 mask, u32 value); 775 u16 saddr, u32 mask, u32 value);
589u32 cx231xx_set_field(u32 field_mask, u32 data); 776u32 cx231xx_set_field(u32 field_mask, u32 data);
590 777
778/*verve r/w*/
779void initGPIO(struct cx231xx *dev);
780void uninitGPIO(struct cx231xx *dev);
591/* afe related functions */ 781/* afe related functions */
592int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count); 782int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count);
593int cx231xx_afe_init_channels(struct cx231xx *dev); 783int cx231xx_afe_init_channels(struct cx231xx *dev);
@@ -607,6 +797,19 @@ int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input);
607/* DIF related functions */ 797/* DIF related functions */
608int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 798int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
609 u32 function_mode, u32 standard); 799 u32 function_mode, u32 standard);
800void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
801 u8 spectral_invert, u32 mode);
802u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd);
803void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
804 u8 spectral_invert, u32 mode);
805void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev);
806void reset_s5h1432_demod(struct cx231xx *dev);
807void cx231xx_dump_HH_reg(struct cx231xx *dev);
808void update_HH_register_after_set_DIF(struct cx231xx *dev);
809void cx231xx_dump_SC_reg(struct cx231xx *dev);
810
811
812
610int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard); 813int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard);
611int cx231xx_tuner_pre_channel_change(struct cx231xx *dev); 814int cx231xx_tuner_pre_channel_change(struct cx231xx *dev);
612int cx231xx_tuner_post_channel_change(struct cx231xx *dev); 815int cx231xx_tuner_post_channel_change(struct cx231xx *dev);
@@ -675,12 +878,26 @@ int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type);
675int cx231xx_resolution_set(struct cx231xx *dev); 878int cx231xx_resolution_set(struct cx231xx *dev);
676int cx231xx_set_video_alternate(struct cx231xx *dev); 879int cx231xx_set_video_alternate(struct cx231xx *dev);
677int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt); 880int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt);
881int is_fw_load(struct cx231xx *dev);
882int cx231xx_check_fw(struct cx231xx *dev);
678int cx231xx_init_isoc(struct cx231xx *dev, int max_packets, 883int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
679 int num_bufs, int max_pkt_size, 884 int num_bufs, int max_pkt_size,
680 int (*isoc_copy) (struct cx231xx *dev, 885 int (*isoc_copy) (struct cx231xx *dev,
681 struct urb *urb)); 886 struct urb *urb));
887int cx231xx_init_bulk(struct cx231xx *dev, int max_packets,
888 int num_bufs, int max_pkt_size,
889 int (*bulk_copy) (struct cx231xx *dev,
890 struct urb *urb));
891void cx231xx_stop_TS1(struct cx231xx *dev);
892void cx231xx_start_TS1(struct cx231xx *dev);
682void cx231xx_uninit_isoc(struct cx231xx *dev); 893void cx231xx_uninit_isoc(struct cx231xx *dev);
894void cx231xx_uninit_bulk(struct cx231xx *dev);
683int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode); 895int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode);
896int cx231xx_unmute_audio(struct cx231xx *dev);
897int cx231xx_ep5_bulkout(struct cx231xx *dev, u8 *firmware, u16 size);
898void cx231xx_disable656(struct cx231xx *dev);
899void cx231xx_enable656(struct cx231xx *dev);
900int cx231xx_demod_reset(struct cx231xx *dev);
684int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio); 901int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio);
685 902
686/* Device list functions */ 903/* Device list functions */
@@ -740,6 +957,10 @@ int cx231xx_tuner_callback(void *ptr, int component, int command, int arg);
740int cx231xx_ir_init(struct cx231xx *dev); 957int cx231xx_ir_init(struct cx231xx *dev);
741int cx231xx_ir_fini(struct cx231xx *dev); 958int cx231xx_ir_fini(struct cx231xx *dev);
742 959
960/* cx23885-417.c */
961extern int cx231xx_417_register(struct cx231xx *dev);
962extern void cx231xx_417_unregister(struct cx231xx *dev);
963
743/* printk macros */ 964/* printk macros */
744 965
745#define cx231xx_err(fmt, arg...) do {\ 966#define cx231xx_err(fmt, arg...) do {\