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authorEmil Velikov <emil.l.velikov@gmail.com>2013-07-02 09:44:12 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-07-25 17:07:42 -0400
commit64dd8fc12c34e39e82b77109bb5b328ad5b24268 (patch)
tree2c7e408cf36bde82ea42fed4efac6913704eba8f
parent3913338881a1e4898176da0008c3df80aabdc3dd (diff)
drm/nv50-/disp: Use output specific mask in interrupt
commit 378f2bcdf7c971453d11580936dc0ffe845f5880 upstream. The commit commit 476e84e126171d809f9c0b5d97137f5055f95ca8 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon Feb 11 09:24:23 2013 +1000 drm/nv50-/disp: initial supervisor support for off-chip encoders changed the write mask in one of the interrupt functions for on-chip encoders, causing a regression in certain VGA dual-head setups. This commit reintroduces the mask thus resolving the regression Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66129 Reported-and-Tested-by: Yves-Alexis <corsac@debian.org> CC: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 6a38402fa56c..5680d3eb11ca 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1107,6 +1107,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1107 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; 1107 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1108 u32 hval, hreg = 0x614200 + (head * 0x800); 1108 u32 hval, hreg = 0x614200 + (head * 0x800);
1109 u32 oval, oreg; 1109 u32 oval, oreg;
1110 u32 mask;
1110 u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp); 1111 u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
1111 if (conf != ~0) { 1112 if (conf != ~0) {
1112 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) { 1113 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
@@ -1133,6 +1134,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1133 oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800; 1134 oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
1134 oval = 0x00000000; 1135 oval = 0x00000000;
1135 hval = 0x00000000; 1136 hval = 0x00000000;
1137 mask = 0xffffffff;
1136 } else 1138 } else
1137 if (!outp.location) { 1139 if (!outp.location) {
1138 if (outp.type == DCB_OUTPUT_DP) 1140 if (outp.type == DCB_OUTPUT_DP)
@@ -1140,14 +1142,16 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1140 oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800; 1142 oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
1141 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; 1143 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
1142 hval = 0x00000000; 1144 hval = 0x00000000;
1145 mask = 0x00000707;
1143 } else { 1146 } else {
1144 oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800; 1147 oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
1145 oval = 0x00000001; 1148 oval = 0x00000001;
1146 hval = 0x00000001; 1149 hval = 0x00000001;
1150 mask = 0x00000707;
1147 } 1151 }
1148 1152
1149 nv_mask(priv, hreg, 0x0000000f, hval); 1153 nv_mask(priv, hreg, 0x0000000f, hval);
1150 nv_mask(priv, oreg, 0x00000707, oval); 1154 nv_mask(priv, oreg, mask, oval);
1151 } 1155 }
1152} 1156}
1153 1157