diff options
author | Eric Anholt <eric@anholt.net> | 2010-04-02 18:24:27 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-04-12 12:23:30 -0400 |
commit | 6443170f6d862a1cc89e61e4bb2410b714b875f4 (patch) | |
tree | 17767306f21c95f066163d1d7df9c2a2e35bbbc9 | |
parent | 335af9a235a82842854b394507ab5e310d88be42 (diff) |
drm/i915: Remove dead KMS encoder save/restore code.
This was brought over from UMS, and used for a while until we decided
that drm_helper_resume_force_mode was easier and more reliable, since
it didn't require duplicating all the code deleted here. We just
forgot to delete all that junk for a while.
-rw-r--r-- | drivers/gpu/drm/i915/dvo.h | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/dvo_ch7017.c | 46 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/dvo_ch7xxx.c | 44 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/dvo_ivch.c | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/dvo_sil164.c | 38 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/dvo_tfp410.c | 32 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 30 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dvo.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 24 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_lvds.c | 71 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_sdvo.c | 161 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_tv.c | 139 |
12 files changed, 4 insertions, 643 deletions
diff --git a/drivers/gpu/drm/i915/dvo.h b/drivers/gpu/drm/i915/dvo.h index 288fc50627e2..0d6ff640e1c6 100644 --- a/drivers/gpu/drm/i915/dvo.h +++ b/drivers/gpu/drm/i915/dvo.h | |||
@@ -70,16 +70,6 @@ struct intel_dvo_dev_ops { | |||
70 | void (*dpms)(struct intel_dvo_device *dvo, int mode); | 70 | void (*dpms)(struct intel_dvo_device *dvo, int mode); |
71 | 71 | ||
72 | /* | 72 | /* |
73 | * Saves the output's state for restoration on VT switch. | ||
74 | */ | ||
75 | void (*save)(struct intel_dvo_device *dvo); | ||
76 | |||
77 | /* | ||
78 | * Restore's the output's state at VT switch. | ||
79 | */ | ||
80 | void (*restore)(struct intel_dvo_device *dvo); | ||
81 | |||
82 | /* | ||
83 | * Callback for testing a video mode for a given output. | 73 | * Callback for testing a video mode for a given output. |
84 | * | 74 | * |
85 | * This function should only check for cases where a mode can't | 75 | * This function should only check for cases where a mode can't |
diff --git a/drivers/gpu/drm/i915/dvo_ch7017.c b/drivers/gpu/drm/i915/dvo_ch7017.c index 1184c14ba87d..14d59804acd7 100644 --- a/drivers/gpu/drm/i915/dvo_ch7017.c +++ b/drivers/gpu/drm/i915/dvo_ch7017.c | |||
@@ -159,16 +159,7 @@ | |||
159 | #define CH7017_BANG_LIMIT_CONTROL 0x7f | 159 | #define CH7017_BANG_LIMIT_CONTROL 0x7f |
160 | 160 | ||
161 | struct ch7017_priv { | 161 | struct ch7017_priv { |
162 | uint8_t save_hapi; | 162 | uint8_t dummy; |
163 | uint8_t save_vali; | ||
164 | uint8_t save_valo; | ||
165 | uint8_t save_ailo; | ||
166 | uint8_t save_lvds_pll_vco; | ||
167 | uint8_t save_feedback_div; | ||
168 | uint8_t save_lvds_control_2; | ||
169 | uint8_t save_outputs_enable; | ||
170 | uint8_t save_lvds_power_down; | ||
171 | uint8_t save_power_management; | ||
172 | }; | 163 | }; |
173 | 164 | ||
174 | static void ch7017_dump_regs(struct intel_dvo_device *dvo); | 165 | static void ch7017_dump_regs(struct intel_dvo_device *dvo); |
@@ -401,39 +392,6 @@ do { \ | |||
401 | DUMP(CH7017_LVDS_POWER_DOWN); | 392 | DUMP(CH7017_LVDS_POWER_DOWN); |
402 | } | 393 | } |
403 | 394 | ||
404 | static void ch7017_save(struct intel_dvo_device *dvo) | ||
405 | { | ||
406 | struct ch7017_priv *priv = dvo->dev_priv; | ||
407 | |||
408 | ch7017_read(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, &priv->save_hapi); | ||
409 | ch7017_read(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, &priv->save_valo); | ||
410 | ch7017_read(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, &priv->save_ailo); | ||
411 | ch7017_read(dvo, CH7017_LVDS_PLL_VCO_CONTROL, &priv->save_lvds_pll_vco); | ||
412 | ch7017_read(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, &priv->save_feedback_div); | ||
413 | ch7017_read(dvo, CH7017_LVDS_CONTROL_2, &priv->save_lvds_control_2); | ||
414 | ch7017_read(dvo, CH7017_OUTPUTS_ENABLE, &priv->save_outputs_enable); | ||
415 | ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &priv->save_lvds_power_down); | ||
416 | ch7017_read(dvo, CH7017_POWER_MANAGEMENT, &priv->save_power_management); | ||
417 | } | ||
418 | |||
419 | static void ch7017_restore(struct intel_dvo_device *dvo) | ||
420 | { | ||
421 | struct ch7017_priv *priv = dvo->dev_priv; | ||
422 | |||
423 | /* Power down before changing mode */ | ||
424 | ch7017_dpms(dvo, DRM_MODE_DPMS_OFF); | ||
425 | |||
426 | ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, priv->save_hapi); | ||
427 | ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, priv->save_valo); | ||
428 | ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, priv->save_ailo); | ||
429 | ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, priv->save_lvds_pll_vco); | ||
430 | ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, priv->save_feedback_div); | ||
431 | ch7017_write(dvo, CH7017_LVDS_CONTROL_2, priv->save_lvds_control_2); | ||
432 | ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, priv->save_outputs_enable); | ||
433 | ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, priv->save_lvds_power_down); | ||
434 | ch7017_write(dvo, CH7017_POWER_MANAGEMENT, priv->save_power_management); | ||
435 | } | ||
436 | |||
437 | static void ch7017_destroy(struct intel_dvo_device *dvo) | 395 | static void ch7017_destroy(struct intel_dvo_device *dvo) |
438 | { | 396 | { |
439 | struct ch7017_priv *priv = dvo->dev_priv; | 397 | struct ch7017_priv *priv = dvo->dev_priv; |
@@ -451,7 +409,5 @@ struct intel_dvo_dev_ops ch7017_ops = { | |||
451 | .mode_set = ch7017_mode_set, | 409 | .mode_set = ch7017_mode_set, |
452 | .dpms = ch7017_dpms, | 410 | .dpms = ch7017_dpms, |
453 | .dump_regs = ch7017_dump_regs, | 411 | .dump_regs = ch7017_dump_regs, |
454 | .save = ch7017_save, | ||
455 | .restore = ch7017_restore, | ||
456 | .destroy = ch7017_destroy, | 412 | .destroy = ch7017_destroy, |
457 | }; | 413 | }; |
diff --git a/drivers/gpu/drm/i915/dvo_ch7xxx.c b/drivers/gpu/drm/i915/dvo_ch7xxx.c index d56ff5cc22b2..6f1944b24441 100644 --- a/drivers/gpu/drm/i915/dvo_ch7xxx.c +++ b/drivers/gpu/drm/i915/dvo_ch7xxx.c | |||
@@ -92,21 +92,10 @@ static struct ch7xxx_id_struct { | |||
92 | { CH7301_VID, "CH7301" }, | 92 | { CH7301_VID, "CH7301" }, |
93 | }; | 93 | }; |
94 | 94 | ||
95 | struct ch7xxx_reg_state { | ||
96 | uint8_t regs[CH7xxx_NUM_REGS]; | ||
97 | }; | ||
98 | |||
99 | struct ch7xxx_priv { | 95 | struct ch7xxx_priv { |
100 | bool quiet; | 96 | bool quiet; |
101 | |||
102 | struct ch7xxx_reg_state save_reg; | ||
103 | struct ch7xxx_reg_state mode_reg; | ||
104 | uint8_t save_TCTL, save_TPCP, save_TPD, save_TPVT; | ||
105 | uint8_t save_TLPF, save_TCT, save_PM, save_IDF; | ||
106 | }; | 97 | }; |
107 | 98 | ||
108 | static void ch7xxx_save(struct intel_dvo_device *dvo); | ||
109 | |||
110 | static char *ch7xxx_get_id(uint8_t vid) | 99 | static char *ch7xxx_get_id(uint8_t vid) |
111 | { | 100 | { |
112 | int i; | 101 | int i; |
@@ -312,42 +301,17 @@ static void ch7xxx_dpms(struct intel_dvo_device *dvo, int mode) | |||
312 | 301 | ||
313 | static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) | 302 | static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) |
314 | { | 303 | { |
315 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; | ||
316 | int i; | 304 | int i; |
317 | 305 | ||
318 | for (i = 0; i < CH7xxx_NUM_REGS; i++) { | 306 | for (i = 0; i < CH7xxx_NUM_REGS; i++) { |
307 | uint8_t val; | ||
319 | if ((i % 8) == 0 ) | 308 | if ((i % 8) == 0 ) |
320 | DRM_LOG_KMS("\n %02X: ", i); | 309 | DRM_LOG_KMS("\n %02X: ", i); |
321 | DRM_LOG_KMS("%02X ", ch7xxx->mode_reg.regs[i]); | 310 | ch7xxx_readb(dvo, i, &val); |
311 | DRM_LOG_KMS("%02X ", val); | ||
322 | } | 312 | } |
323 | } | 313 | } |
324 | 314 | ||
325 | static void ch7xxx_save(struct intel_dvo_device *dvo) | ||
326 | { | ||
327 | struct ch7xxx_priv *ch7xxx= dvo->dev_priv; | ||
328 | |||
329 | ch7xxx_readb(dvo, CH7xxx_TCTL, &ch7xxx->save_TCTL); | ||
330 | ch7xxx_readb(dvo, CH7xxx_TPCP, &ch7xxx->save_TPCP); | ||
331 | ch7xxx_readb(dvo, CH7xxx_TPD, &ch7xxx->save_TPD); | ||
332 | ch7xxx_readb(dvo, CH7xxx_TPVT, &ch7xxx->save_TPVT); | ||
333 | ch7xxx_readb(dvo, CH7xxx_TLPF, &ch7xxx->save_TLPF); | ||
334 | ch7xxx_readb(dvo, CH7xxx_PM, &ch7xxx->save_PM); | ||
335 | ch7xxx_readb(dvo, CH7xxx_IDF, &ch7xxx->save_IDF); | ||
336 | } | ||
337 | |||
338 | static void ch7xxx_restore(struct intel_dvo_device *dvo) | ||
339 | { | ||
340 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; | ||
341 | |||
342 | ch7xxx_writeb(dvo, CH7xxx_TCTL, ch7xxx->save_TCTL); | ||
343 | ch7xxx_writeb(dvo, CH7xxx_TPCP, ch7xxx->save_TPCP); | ||
344 | ch7xxx_writeb(dvo, CH7xxx_TPD, ch7xxx->save_TPD); | ||
345 | ch7xxx_writeb(dvo, CH7xxx_TPVT, ch7xxx->save_TPVT); | ||
346 | ch7xxx_writeb(dvo, CH7xxx_TLPF, ch7xxx->save_TLPF); | ||
347 | ch7xxx_writeb(dvo, CH7xxx_IDF, ch7xxx->save_IDF); | ||
348 | ch7xxx_writeb(dvo, CH7xxx_PM, ch7xxx->save_PM); | ||
349 | } | ||
350 | |||
351 | static void ch7xxx_destroy(struct intel_dvo_device *dvo) | 315 | static void ch7xxx_destroy(struct intel_dvo_device *dvo) |
352 | { | 316 | { |
353 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; | 317 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
@@ -365,7 +329,5 @@ struct intel_dvo_dev_ops ch7xxx_ops = { | |||
365 | .mode_set = ch7xxx_mode_set, | 329 | .mode_set = ch7xxx_mode_set, |
366 | .dpms = ch7xxx_dpms, | 330 | .dpms = ch7xxx_dpms, |
367 | .dump_regs = ch7xxx_dump_regs, | 331 | .dump_regs = ch7xxx_dump_regs, |
368 | .save = ch7xxx_save, | ||
369 | .restore = ch7xxx_restore, | ||
370 | .destroy = ch7xxx_destroy, | 332 | .destroy = ch7xxx_destroy, |
371 | }; | 333 | }; |
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c index 24169e528f0f..a2ec3f487202 100644 --- a/drivers/gpu/drm/i915/dvo_ivch.c +++ b/drivers/gpu/drm/i915/dvo_ivch.c | |||
@@ -153,9 +153,6 @@ struct ivch_priv { | |||
153 | bool quiet; | 153 | bool quiet; |
154 | 154 | ||
155 | uint16_t width, height; | 155 | uint16_t width, height; |
156 | |||
157 | uint16_t save_VR01; | ||
158 | uint16_t save_VR40; | ||
159 | }; | 156 | }; |
160 | 157 | ||
161 | 158 | ||
@@ -405,22 +402,6 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo) | |||
405 | DRM_LOG_KMS("VR8F: 0x%04x\n", val); | 402 | DRM_LOG_KMS("VR8F: 0x%04x\n", val); |
406 | } | 403 | } |
407 | 404 | ||
408 | static void ivch_save(struct intel_dvo_device *dvo) | ||
409 | { | ||
410 | struct ivch_priv *priv = dvo->dev_priv; | ||
411 | |||
412 | ivch_read(dvo, VR01, &priv->save_VR01); | ||
413 | ivch_read(dvo, VR40, &priv->save_VR40); | ||
414 | } | ||
415 | |||
416 | static void ivch_restore(struct intel_dvo_device *dvo) | ||
417 | { | ||
418 | struct ivch_priv *priv = dvo->dev_priv; | ||
419 | |||
420 | ivch_write(dvo, VR01, priv->save_VR01); | ||
421 | ivch_write(dvo, VR40, priv->save_VR40); | ||
422 | } | ||
423 | |||
424 | static void ivch_destroy(struct intel_dvo_device *dvo) | 405 | static void ivch_destroy(struct intel_dvo_device *dvo) |
425 | { | 406 | { |
426 | struct ivch_priv *priv = dvo->dev_priv; | 407 | struct ivch_priv *priv = dvo->dev_priv; |
@@ -434,8 +415,6 @@ static void ivch_destroy(struct intel_dvo_device *dvo) | |||
434 | struct intel_dvo_dev_ops ivch_ops= { | 415 | struct intel_dvo_dev_ops ivch_ops= { |
435 | .init = ivch_init, | 416 | .init = ivch_init, |
436 | .dpms = ivch_dpms, | 417 | .dpms = ivch_dpms, |
437 | .save = ivch_save, | ||
438 | .restore = ivch_restore, | ||
439 | .mode_valid = ivch_mode_valid, | 418 | .mode_valid = ivch_mode_valid, |
440 | .mode_set = ivch_mode_set, | 419 | .mode_set = ivch_mode_set, |
441 | .detect = ivch_detect, | 420 | .detect = ivch_detect, |
diff --git a/drivers/gpu/drm/i915/dvo_sil164.c b/drivers/gpu/drm/i915/dvo_sil164.c index 0001c13f0a80..9b8e6765cf26 100644 --- a/drivers/gpu/drm/i915/dvo_sil164.c +++ b/drivers/gpu/drm/i915/dvo_sil164.c | |||
@@ -58,17 +58,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |||
58 | 58 | ||
59 | #define SIL164_REGC 0x0c | 59 | #define SIL164_REGC 0x0c |
60 | 60 | ||
61 | struct sil164_save_rec { | ||
62 | uint8_t reg8; | ||
63 | uint8_t reg9; | ||
64 | uint8_t regc; | ||
65 | }; | ||
66 | |||
67 | struct sil164_priv { | 61 | struct sil164_priv { |
68 | //I2CDevRec d; | 62 | //I2CDevRec d; |
69 | bool quiet; | 63 | bool quiet; |
70 | struct sil164_save_rec save_regs; | ||
71 | struct sil164_save_rec mode_regs; | ||
72 | }; | 64 | }; |
73 | 65 | ||
74 | #define SILPTR(d) ((SIL164Ptr)(d->DriverPrivate.ptr)) | 66 | #define SILPTR(d) ((SIL164Ptr)(d->DriverPrivate.ptr)) |
@@ -252,34 +244,6 @@ static void sil164_dump_regs(struct intel_dvo_device *dvo) | |||
252 | DRM_LOG_KMS("SIL164_REGC: 0x%02x\n", val); | 244 | DRM_LOG_KMS("SIL164_REGC: 0x%02x\n", val); |
253 | } | 245 | } |
254 | 246 | ||
255 | static void sil164_save(struct intel_dvo_device *dvo) | ||
256 | { | ||
257 | struct sil164_priv *sil= dvo->dev_priv; | ||
258 | |||
259 | if (!sil164_readb(dvo, SIL164_REG8, &sil->save_regs.reg8)) | ||
260 | return; | ||
261 | |||
262 | if (!sil164_readb(dvo, SIL164_REG9, &sil->save_regs.reg9)) | ||
263 | return; | ||
264 | |||
265 | if (!sil164_readb(dvo, SIL164_REGC, &sil->save_regs.regc)) | ||
266 | return; | ||
267 | |||
268 | return; | ||
269 | } | ||
270 | |||
271 | static void sil164_restore(struct intel_dvo_device *dvo) | ||
272 | { | ||
273 | struct sil164_priv *sil = dvo->dev_priv; | ||
274 | |||
275 | /* Restore it powered down initially */ | ||
276 | sil164_writeb(dvo, SIL164_REG8, sil->save_regs.reg8 & ~0x1); | ||
277 | |||
278 | sil164_writeb(dvo, SIL164_REG9, sil->save_regs.reg9); | ||
279 | sil164_writeb(dvo, SIL164_REGC, sil->save_regs.regc); | ||
280 | sil164_writeb(dvo, SIL164_REG8, sil->save_regs.reg8); | ||
281 | } | ||
282 | |||
283 | static void sil164_destroy(struct intel_dvo_device *dvo) | 247 | static void sil164_destroy(struct intel_dvo_device *dvo) |
284 | { | 248 | { |
285 | struct sil164_priv *sil = dvo->dev_priv; | 249 | struct sil164_priv *sil = dvo->dev_priv; |
@@ -297,7 +261,5 @@ struct intel_dvo_dev_ops sil164_ops = { | |||
297 | .mode_set = sil164_mode_set, | 261 | .mode_set = sil164_mode_set, |
298 | .dpms = sil164_dpms, | 262 | .dpms = sil164_dpms, |
299 | .dump_regs = sil164_dump_regs, | 263 | .dump_regs = sil164_dump_regs, |
300 | .save = sil164_save, | ||
301 | .restore = sil164_restore, | ||
302 | .destroy = sil164_destroy, | 264 | .destroy = sil164_destroy, |
303 | }; | 265 | }; |
diff --git a/drivers/gpu/drm/i915/dvo_tfp410.c b/drivers/gpu/drm/i915/dvo_tfp410.c index c7c391bc116a..66c697bc9b22 100644 --- a/drivers/gpu/drm/i915/dvo_tfp410.c +++ b/drivers/gpu/drm/i915/dvo_tfp410.c | |||
@@ -86,16 +86,8 @@ | |||
86 | #define TFP410_V_RES_LO 0x3C | 86 | #define TFP410_V_RES_LO 0x3C |
87 | #define TFP410_V_RES_HI 0x3D | 87 | #define TFP410_V_RES_HI 0x3D |
88 | 88 | ||
89 | struct tfp410_save_rec { | ||
90 | uint8_t ctl1; | ||
91 | uint8_t ctl2; | ||
92 | }; | ||
93 | |||
94 | struct tfp410_priv { | 89 | struct tfp410_priv { |
95 | bool quiet; | 90 | bool quiet; |
96 | |||
97 | struct tfp410_save_rec saved_reg; | ||
98 | struct tfp410_save_rec mode_reg; | ||
99 | }; | 91 | }; |
100 | 92 | ||
101 | static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) | 93 | static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) |
@@ -293,28 +285,6 @@ static void tfp410_dump_regs(struct intel_dvo_device *dvo) | |||
293 | DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val); | 285 | DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val); |
294 | } | 286 | } |
295 | 287 | ||
296 | static void tfp410_save(struct intel_dvo_device *dvo) | ||
297 | { | ||
298 | struct tfp410_priv *tfp = dvo->dev_priv; | ||
299 | |||
300 | if (!tfp410_readb(dvo, TFP410_CTL_1, &tfp->saved_reg.ctl1)) | ||
301 | return; | ||
302 | |||
303 | if (!tfp410_readb(dvo, TFP410_CTL_2, &tfp->saved_reg.ctl2)) | ||
304 | return; | ||
305 | } | ||
306 | |||
307 | static void tfp410_restore(struct intel_dvo_device *dvo) | ||
308 | { | ||
309 | struct tfp410_priv *tfp = dvo->dev_priv; | ||
310 | |||
311 | /* Restore it powered down initially */ | ||
312 | tfp410_writeb(dvo, TFP410_CTL_1, tfp->saved_reg.ctl1 & ~0x1); | ||
313 | |||
314 | tfp410_writeb(dvo, TFP410_CTL_2, tfp->saved_reg.ctl2); | ||
315 | tfp410_writeb(dvo, TFP410_CTL_1, tfp->saved_reg.ctl1); | ||
316 | } | ||
317 | |||
318 | static void tfp410_destroy(struct intel_dvo_device *dvo) | 288 | static void tfp410_destroy(struct intel_dvo_device *dvo) |
319 | { | 289 | { |
320 | struct tfp410_priv *tfp = dvo->dev_priv; | 290 | struct tfp410_priv *tfp = dvo->dev_priv; |
@@ -332,7 +302,5 @@ struct intel_dvo_dev_ops tfp410_ops = { | |||
332 | .mode_set = tfp410_mode_set, | 302 | .mode_set = tfp410_mode_set, |
333 | .dpms = tfp410_dpms, | 303 | .dpms = tfp410_dpms, |
334 | .dump_regs = tfp410_dump_regs, | 304 | .dump_regs = tfp410_dump_regs, |
335 | .save = tfp410_save, | ||
336 | .restore = tfp410_restore, | ||
337 | .destroy = tfp410_destroy, | 305 | .destroy = tfp410_destroy, |
338 | }; | 306 | }; |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6064fd70a424..8f2dd65abaca 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -47,8 +47,6 @@ struct intel_dp_priv { | |||
47 | uint32_t output_reg; | 47 | uint32_t output_reg; |
48 | uint32_t DP; | 48 | uint32_t DP; |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | 49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
50 | uint32_t save_DP; | ||
51 | uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE]; | ||
52 | bool has_audio; | 50 | bool has_audio; |
53 | int dpms_mode; | 51 | int dpms_mode; |
54 | uint8_t link_bw; | 52 | uint8_t link_bw; |
@@ -748,20 +746,6 @@ intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |||
748 | return link_status[r - DP_LANE0_1_STATUS]; | 746 | return link_status[r - DP_LANE0_1_STATUS]; |
749 | } | 747 | } |
750 | 748 | ||
751 | static void | ||
752 | intel_dp_save(struct drm_connector *connector) | ||
753 | { | ||
754 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
755 | struct drm_device *dev = intel_encoder->base.dev; | ||
756 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
757 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | ||
758 | |||
759 | dp_priv->save_DP = I915_READ(dp_priv->output_reg); | ||
760 | intel_dp_aux_native_read(intel_encoder, DP_LINK_BW_SET, | ||
761 | dp_priv->save_link_configuration, | ||
762 | sizeof (dp_priv->save_link_configuration)); | ||
763 | } | ||
764 | |||
765 | static uint8_t | 749 | static uint8_t |
766 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | 750 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], |
767 | int lane) | 751 | int lane) |
@@ -1101,18 +1085,6 @@ intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) | |||
1101 | POSTING_READ(dp_priv->output_reg); | 1085 | POSTING_READ(dp_priv->output_reg); |
1102 | } | 1086 | } |
1103 | 1087 | ||
1104 | static void | ||
1105 | intel_dp_restore(struct drm_connector *connector) | ||
1106 | { | ||
1107 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
1108 | struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; | ||
1109 | |||
1110 | if (dp_priv->save_DP & DP_PORT_EN) | ||
1111 | intel_dp_link_train(intel_encoder, dp_priv->save_DP, dp_priv->save_link_configuration); | ||
1112 | else | ||
1113 | intel_dp_link_down(intel_encoder, dp_priv->save_DP); | ||
1114 | } | ||
1115 | |||
1116 | /* | 1088 | /* |
1117 | * According to DP spec | 1089 | * According to DP spec |
1118 | * 5.1.2: | 1090 | * 5.1.2: |
@@ -1267,8 +1239,6 @@ static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { | |||
1267 | 1239 | ||
1268 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | 1240 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
1269 | .dpms = drm_helper_connector_dpms, | 1241 | .dpms = drm_helper_connector_dpms, |
1270 | .save = intel_dp_save, | ||
1271 | .restore = intel_dp_restore, | ||
1272 | .detect = intel_dp_detect, | 1242 | .detect = intel_dp_detect, |
1273 | .fill_modes = drm_helper_probe_single_connector_modes, | 1243 | .fill_modes = drm_helper_probe_single_connector_modes, |
1274 | .destroy = intel_dp_destroy, | 1244 | .destroy = intel_dp_destroy, |
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index a3e6efa38c75..1bf6697061bf 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c | |||
@@ -95,35 +95,6 @@ static void intel_dvo_dpms(struct drm_encoder *encoder, int mode) | |||
95 | } | 95 | } |
96 | } | 96 | } |
97 | 97 | ||
98 | static void intel_dvo_save(struct drm_connector *connector) | ||
99 | { | ||
100 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | ||
101 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
102 | struct intel_dvo_device *dvo = intel_encoder->dev_priv; | ||
103 | |||
104 | /* Each output should probably just save the registers it touches, | ||
105 | * but for now, use more overkill. | ||
106 | */ | ||
107 | dev_priv->saveDVOA = I915_READ(DVOA); | ||
108 | dev_priv->saveDVOB = I915_READ(DVOB); | ||
109 | dev_priv->saveDVOC = I915_READ(DVOC); | ||
110 | |||
111 | dvo->dev_ops->save(dvo); | ||
112 | } | ||
113 | |||
114 | static void intel_dvo_restore(struct drm_connector *connector) | ||
115 | { | ||
116 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | ||
117 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
118 | struct intel_dvo_device *dvo = intel_encoder->dev_priv; | ||
119 | |||
120 | dvo->dev_ops->restore(dvo); | ||
121 | |||
122 | I915_WRITE(DVOA, dev_priv->saveDVOA); | ||
123 | I915_WRITE(DVOB, dev_priv->saveDVOB); | ||
124 | I915_WRITE(DVOC, dev_priv->saveDVOC); | ||
125 | } | ||
126 | |||
127 | static int intel_dvo_mode_valid(struct drm_connector *connector, | 98 | static int intel_dvo_mode_valid(struct drm_connector *connector, |
128 | struct drm_display_mode *mode) | 99 | struct drm_display_mode *mode) |
129 | { | 100 | { |
@@ -317,8 +288,6 @@ static const struct drm_encoder_helper_funcs intel_dvo_helper_funcs = { | |||
317 | 288 | ||
318 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { | 289 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
319 | .dpms = drm_helper_connector_dpms, | 290 | .dpms = drm_helper_connector_dpms, |
320 | .save = intel_dvo_save, | ||
321 | .restore = intel_dvo_restore, | ||
322 | .detect = intel_dvo_detect, | 291 | .detect = intel_dvo_detect, |
323 | .destroy = intel_dvo_destroy, | 292 | .destroy = intel_dvo_destroy, |
324 | .fill_modes = drm_helper_probe_single_connector_modes, | 293 | .fill_modes = drm_helper_probe_single_connector_modes, |
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 74823e77b2fe..78cb775be4d7 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -38,7 +38,6 @@ | |||
38 | 38 | ||
39 | struct intel_hdmi_priv { | 39 | struct intel_hdmi_priv { |
40 | u32 sdvox_reg; | 40 | u32 sdvox_reg; |
41 | u32 save_SDVOX; | ||
42 | bool has_hdmi_sink; | 41 | bool has_hdmi_sink; |
43 | }; | 42 | }; |
44 | 43 | ||
@@ -105,27 +104,6 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |||
105 | } | 104 | } |
106 | } | 105 | } |
107 | 106 | ||
108 | static void intel_hdmi_save(struct drm_connector *connector) | ||
109 | { | ||
110 | struct drm_device *dev = connector->dev; | ||
111 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
112 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
113 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; | ||
114 | |||
115 | hdmi_priv->save_SDVOX = I915_READ(hdmi_priv->sdvox_reg); | ||
116 | } | ||
117 | |||
118 | static void intel_hdmi_restore(struct drm_connector *connector) | ||
119 | { | ||
120 | struct drm_device *dev = connector->dev; | ||
121 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
122 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
123 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; | ||
124 | |||
125 | I915_WRITE(hdmi_priv->sdvox_reg, hdmi_priv->save_SDVOX); | ||
126 | POSTING_READ(hdmi_priv->sdvox_reg); | ||
127 | } | ||
128 | |||
129 | static int intel_hdmi_mode_valid(struct drm_connector *connector, | 107 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
130 | struct drm_display_mode *mode) | 108 | struct drm_display_mode *mode) |
131 | { | 109 | { |
@@ -203,8 +181,6 @@ static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |||
203 | 181 | ||
204 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | 182 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
205 | .dpms = drm_helper_connector_dpms, | 183 | .dpms = drm_helper_connector_dpms, |
206 | .save = intel_hdmi_save, | ||
207 | .restore = intel_hdmi_restore, | ||
208 | .detect = intel_hdmi_detect, | 184 | .detect = intel_hdmi_detect, |
209 | .fill_modes = drm_helper_probe_single_connector_modes, | 185 | .fill_modes = drm_helper_probe_single_connector_modes, |
210 | .destroy = intel_hdmi_destroy, | 186 | .destroy = intel_hdmi_destroy, |
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index a3b82081e1a7..bc0ab7d57dbc 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
@@ -138,75 +138,6 @@ static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |||
138 | /* XXX: We never power down the LVDS pairs. */ | 138 | /* XXX: We never power down the LVDS pairs. */ |
139 | } | 139 | } |
140 | 140 | ||
141 | static void intel_lvds_save(struct drm_connector *connector) | ||
142 | { | ||
143 | struct drm_device *dev = connector->dev; | ||
144 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
145 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; | ||
146 | u32 pwm_ctl_reg; | ||
147 | |||
148 | if (HAS_PCH_SPLIT(dev)) { | ||
149 | pp_on_reg = PCH_PP_ON_DELAYS; | ||
150 | pp_off_reg = PCH_PP_OFF_DELAYS; | ||
151 | pp_ctl_reg = PCH_PP_CONTROL; | ||
152 | pp_div_reg = PCH_PP_DIVISOR; | ||
153 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | ||
154 | } else { | ||
155 | pp_on_reg = PP_ON_DELAYS; | ||
156 | pp_off_reg = PP_OFF_DELAYS; | ||
157 | pp_ctl_reg = PP_CONTROL; | ||
158 | pp_div_reg = PP_DIVISOR; | ||
159 | pwm_ctl_reg = BLC_PWM_CTL; | ||
160 | } | ||
161 | |||
162 | dev_priv->savePP_ON = I915_READ(pp_on_reg); | ||
163 | dev_priv->savePP_OFF = I915_READ(pp_off_reg); | ||
164 | dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg); | ||
165 | dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg); | ||
166 | dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg); | ||
167 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & | ||
168 | BACKLIGHT_DUTY_CYCLE_MASK); | ||
169 | |||
170 | /* | ||
171 | * If the light is off at server startup, just make it full brightness | ||
172 | */ | ||
173 | if (dev_priv->backlight_duty_cycle == 0) | ||
174 | dev_priv->backlight_duty_cycle = | ||
175 | intel_lvds_get_max_backlight(dev); | ||
176 | } | ||
177 | |||
178 | static void intel_lvds_restore(struct drm_connector *connector) | ||
179 | { | ||
180 | struct drm_device *dev = connector->dev; | ||
181 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
182 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; | ||
183 | u32 pwm_ctl_reg; | ||
184 | |||
185 | if (HAS_PCH_SPLIT(dev)) { | ||
186 | pp_on_reg = PCH_PP_ON_DELAYS; | ||
187 | pp_off_reg = PCH_PP_OFF_DELAYS; | ||
188 | pp_ctl_reg = PCH_PP_CONTROL; | ||
189 | pp_div_reg = PCH_PP_DIVISOR; | ||
190 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | ||
191 | } else { | ||
192 | pp_on_reg = PP_ON_DELAYS; | ||
193 | pp_off_reg = PP_OFF_DELAYS; | ||
194 | pp_ctl_reg = PP_CONTROL; | ||
195 | pp_div_reg = PP_DIVISOR; | ||
196 | pwm_ctl_reg = BLC_PWM_CTL; | ||
197 | } | ||
198 | |||
199 | I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL); | ||
200 | I915_WRITE(pp_on_reg, dev_priv->savePP_ON); | ||
201 | I915_WRITE(pp_off_reg, dev_priv->savePP_OFF); | ||
202 | I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR); | ||
203 | I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL); | ||
204 | if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) | ||
205 | intel_lvds_set_power(dev, true); | ||
206 | else | ||
207 | intel_lvds_set_power(dev, false); | ||
208 | } | ||
209 | |||
210 | static int intel_lvds_mode_valid(struct drm_connector *connector, | 141 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
211 | struct drm_display_mode *mode) | 142 | struct drm_display_mode *mode) |
212 | { | 143 | { |
@@ -778,8 +709,6 @@ static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs | |||
778 | 709 | ||
779 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | 710 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { |
780 | .dpms = drm_helper_connector_dpms, | 711 | .dpms = drm_helper_connector_dpms, |
781 | .save = intel_lvds_save, | ||
782 | .restore = intel_lvds_restore, | ||
783 | .detect = intel_lvds_detect, | 712 | .detect = intel_lvds_detect, |
784 | .fill_modes = drm_helper_probe_single_connector_modes, | 713 | .fill_modes = drm_helper_probe_single_connector_modes, |
785 | .set_property = intel_lvds_set_property, | 714 | .set_property = intel_lvds_set_property, |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 097819c51a15..5534704c151a 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -129,11 +129,6 @@ struct intel_sdvo_priv { | |||
129 | /* Mac mini hack -- use the same DDC as the analog connector */ | 129 | /* Mac mini hack -- use the same DDC as the analog connector */ |
130 | struct i2c_adapter *analog_ddc_bus; | 130 | struct i2c_adapter *analog_ddc_bus; |
131 | 131 | ||
132 | int save_sdvo_mult; | ||
133 | u16 save_active_outputs; | ||
134 | struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; | ||
135 | struct intel_sdvo_dtd save_output_dtd[16]; | ||
136 | u32 save_SDVOX; | ||
137 | /* add the property for the SDVO-TV */ | 132 | /* add the property for the SDVO-TV */ |
138 | struct drm_property *left_property; | 133 | struct drm_property *left_property; |
139 | struct drm_property *right_property; | 134 | struct drm_property *right_property; |
@@ -562,17 +557,6 @@ static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, b | |||
562 | return true; | 557 | return true; |
563 | } | 558 | } |
564 | 559 | ||
565 | static bool intel_sdvo_get_active_outputs(struct intel_encoder *intel_encoder, | ||
566 | u16 *outputs) | ||
567 | { | ||
568 | u8 status; | ||
569 | |||
570 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0); | ||
571 | status = intel_sdvo_read_response(intel_encoder, outputs, sizeof(*outputs)); | ||
572 | |||
573 | return (status == SDVO_CMD_STATUS_SUCCESS); | ||
574 | } | ||
575 | |||
576 | static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder, | 560 | static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder, |
577 | u16 outputs) | 561 | u16 outputs) |
578 | { | 562 | { |
@@ -645,40 +629,6 @@ static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder, | |||
645 | return (status == SDVO_CMD_STATUS_SUCCESS); | 629 | return (status == SDVO_CMD_STATUS_SUCCESS); |
646 | } | 630 | } |
647 | 631 | ||
648 | static bool intel_sdvo_get_timing(struct intel_encoder *intel_encoder, u8 cmd, | ||
649 | struct intel_sdvo_dtd *dtd) | ||
650 | { | ||
651 | u8 status; | ||
652 | |||
653 | intel_sdvo_write_cmd(intel_encoder, cmd, NULL, 0); | ||
654 | status = intel_sdvo_read_response(intel_encoder, &dtd->part1, | ||
655 | sizeof(dtd->part1)); | ||
656 | if (status != SDVO_CMD_STATUS_SUCCESS) | ||
657 | return false; | ||
658 | |||
659 | intel_sdvo_write_cmd(intel_encoder, cmd + 1, NULL, 0); | ||
660 | status = intel_sdvo_read_response(intel_encoder, &dtd->part2, | ||
661 | sizeof(dtd->part2)); | ||
662 | if (status != SDVO_CMD_STATUS_SUCCESS) | ||
663 | return false; | ||
664 | |||
665 | return true; | ||
666 | } | ||
667 | |||
668 | static bool intel_sdvo_get_input_timing(struct intel_encoder *intel_encoder, | ||
669 | struct intel_sdvo_dtd *dtd) | ||
670 | { | ||
671 | return intel_sdvo_get_timing(intel_encoder, | ||
672 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); | ||
673 | } | ||
674 | |||
675 | static bool intel_sdvo_get_output_timing(struct intel_encoder *intel_encoder, | ||
676 | struct intel_sdvo_dtd *dtd) | ||
677 | { | ||
678 | return intel_sdvo_get_timing(intel_encoder, | ||
679 | SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd); | ||
680 | } | ||
681 | |||
682 | static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd, | 632 | static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd, |
683 | struct intel_sdvo_dtd *dtd) | 633 | struct intel_sdvo_dtd *dtd) |
684 | { | 634 | { |
@@ -766,23 +716,6 @@ static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_en | |||
766 | return false; | 716 | return false; |
767 | } | 717 | } |
768 | 718 | ||
769 | static int intel_sdvo_get_clock_rate_mult(struct intel_encoder *intel_encoder) | ||
770 | { | ||
771 | u8 response, status; | ||
772 | |||
773 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0); | ||
774 | status = intel_sdvo_read_response(intel_encoder, &response, 1); | ||
775 | |||
776 | if (status != SDVO_CMD_STATUS_SUCCESS) { | ||
777 | DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n"); | ||
778 | return SDVO_CLOCK_RATE_MULT_1X; | ||
779 | } else { | ||
780 | DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response); | ||
781 | } | ||
782 | |||
783 | return response; | ||
784 | } | ||
785 | |||
786 | static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val) | 719 | static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val) |
787 | { | 720 | { |
788 | u8 status; | 721 | u8 status; |
@@ -1356,98 +1289,6 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) | |||
1356 | return; | 1289 | return; |
1357 | } | 1290 | } |
1358 | 1291 | ||
1359 | static void intel_sdvo_save(struct drm_connector *connector) | ||
1360 | { | ||
1361 | struct drm_device *dev = connector->dev; | ||
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
1363 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
1364 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; | ||
1365 | int o; | ||
1366 | |||
1367 | sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_encoder); | ||
1368 | intel_sdvo_get_active_outputs(intel_encoder, &sdvo_priv->save_active_outputs); | ||
1369 | |||
1370 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { | ||
1371 | intel_sdvo_set_target_input(intel_encoder, true, false); | ||
1372 | intel_sdvo_get_input_timing(intel_encoder, | ||
1373 | &sdvo_priv->save_input_dtd_1); | ||
1374 | } | ||
1375 | |||
1376 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { | ||
1377 | intel_sdvo_set_target_input(intel_encoder, false, true); | ||
1378 | intel_sdvo_get_input_timing(intel_encoder, | ||
1379 | &sdvo_priv->save_input_dtd_2); | ||
1380 | } | ||
1381 | |||
1382 | for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) | ||
1383 | { | ||
1384 | u16 this_output = (1 << o); | ||
1385 | if (sdvo_priv->caps.output_flags & this_output) | ||
1386 | { | ||
1387 | intel_sdvo_set_target_output(intel_encoder, this_output); | ||
1388 | intel_sdvo_get_output_timing(intel_encoder, | ||
1389 | &sdvo_priv->save_output_dtd[o]); | ||
1390 | } | ||
1391 | } | ||
1392 | if (sdvo_priv->is_tv) { | ||
1393 | /* XXX: Save TV format/enhancements. */ | ||
1394 | } | ||
1395 | |||
1396 | sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->sdvo_reg); | ||
1397 | } | ||
1398 | |||
1399 | static void intel_sdvo_restore(struct drm_connector *connector) | ||
1400 | { | ||
1401 | struct drm_device *dev = connector->dev; | ||
1402 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
1403 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; | ||
1404 | int o; | ||
1405 | int i; | ||
1406 | bool input1, input2; | ||
1407 | u8 status; | ||
1408 | |||
1409 | intel_sdvo_set_active_outputs(intel_encoder, 0); | ||
1410 | |||
1411 | for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) | ||
1412 | { | ||
1413 | u16 this_output = (1 << o); | ||
1414 | if (sdvo_priv->caps.output_flags & this_output) { | ||
1415 | intel_sdvo_set_target_output(intel_encoder, this_output); | ||
1416 | intel_sdvo_set_output_timing(intel_encoder, &sdvo_priv->save_output_dtd[o]); | ||
1417 | } | ||
1418 | } | ||
1419 | |||
1420 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { | ||
1421 | intel_sdvo_set_target_input(intel_encoder, true, false); | ||
1422 | intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_1); | ||
1423 | } | ||
1424 | |||
1425 | if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { | ||
1426 | intel_sdvo_set_target_input(intel_encoder, false, true); | ||
1427 | intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_2); | ||
1428 | } | ||
1429 | |||
1430 | intel_sdvo_set_clock_rate_mult(intel_encoder, sdvo_priv->save_sdvo_mult); | ||
1431 | |||
1432 | if (sdvo_priv->is_tv) { | ||
1433 | /* XXX: Restore TV format/enhancements. */ | ||
1434 | } | ||
1435 | |||
1436 | intel_sdvo_write_sdvox(intel_encoder, sdvo_priv->save_SDVOX); | ||
1437 | |||
1438 | if (sdvo_priv->save_SDVOX & SDVO_ENABLE) | ||
1439 | { | ||
1440 | for (i = 0; i < 2; i++) | ||
1441 | intel_wait_for_vblank(dev); | ||
1442 | status = intel_sdvo_get_trained_inputs(intel_encoder, &input1, &input2); | ||
1443 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) | ||
1444 | DRM_DEBUG_KMS("First %s output reported failure to " | ||
1445 | "sync\n", SDVO_NAME(sdvo_priv)); | ||
1446 | } | ||
1447 | |||
1448 | intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->save_active_outputs); | ||
1449 | } | ||
1450 | |||
1451 | static int intel_sdvo_mode_valid(struct drm_connector *connector, | 1292 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
1452 | struct drm_display_mode *mode) | 1293 | struct drm_display_mode *mode) |
1453 | { | 1294 | { |
@@ -2119,8 +1960,6 @@ static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { | |||
2119 | 1960 | ||
2120 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { | 1961 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
2121 | .dpms = drm_helper_connector_dpms, | 1962 | .dpms = drm_helper_connector_dpms, |
2122 | .save = intel_sdvo_save, | ||
2123 | .restore = intel_sdvo_restore, | ||
2124 | .detect = intel_sdvo_detect, | 1963 | .detect = intel_sdvo_detect, |
2125 | .fill_modes = drm_helper_probe_single_connector_modes, | 1964 | .fill_modes = drm_helper_probe_single_connector_modes, |
2126 | .set_property = intel_sdvo_set_property, | 1965 | .set_property = intel_sdvo_set_property, |
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index dd5e2e84b2b2..c8f67bfa22ed 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c | |||
@@ -916,143 +916,6 @@ intel_tv_dpms(struct drm_encoder *encoder, int mode) | |||
916 | } | 916 | } |
917 | } | 917 | } |
918 | 918 | ||
919 | static void | ||
920 | intel_tv_save(struct drm_connector *connector) | ||
921 | { | ||
922 | struct drm_device *dev = connector->dev; | ||
923 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
924 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
925 | struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; | ||
926 | int i; | ||
927 | |||
928 | tv_priv->save_TV_H_CTL_1 = I915_READ(TV_H_CTL_1); | ||
929 | tv_priv->save_TV_H_CTL_2 = I915_READ(TV_H_CTL_2); | ||
930 | tv_priv->save_TV_H_CTL_3 = I915_READ(TV_H_CTL_3); | ||
931 | tv_priv->save_TV_V_CTL_1 = I915_READ(TV_V_CTL_1); | ||
932 | tv_priv->save_TV_V_CTL_2 = I915_READ(TV_V_CTL_2); | ||
933 | tv_priv->save_TV_V_CTL_3 = I915_READ(TV_V_CTL_3); | ||
934 | tv_priv->save_TV_V_CTL_4 = I915_READ(TV_V_CTL_4); | ||
935 | tv_priv->save_TV_V_CTL_5 = I915_READ(TV_V_CTL_5); | ||
936 | tv_priv->save_TV_V_CTL_6 = I915_READ(TV_V_CTL_6); | ||
937 | tv_priv->save_TV_V_CTL_7 = I915_READ(TV_V_CTL_7); | ||
938 | tv_priv->save_TV_SC_CTL_1 = I915_READ(TV_SC_CTL_1); | ||
939 | tv_priv->save_TV_SC_CTL_2 = I915_READ(TV_SC_CTL_2); | ||
940 | tv_priv->save_TV_SC_CTL_3 = I915_READ(TV_SC_CTL_3); | ||
941 | |||
942 | tv_priv->save_TV_CSC_Y = I915_READ(TV_CSC_Y); | ||
943 | tv_priv->save_TV_CSC_Y2 = I915_READ(TV_CSC_Y2); | ||
944 | tv_priv->save_TV_CSC_U = I915_READ(TV_CSC_U); | ||
945 | tv_priv->save_TV_CSC_U2 = I915_READ(TV_CSC_U2); | ||
946 | tv_priv->save_TV_CSC_V = I915_READ(TV_CSC_V); | ||
947 | tv_priv->save_TV_CSC_V2 = I915_READ(TV_CSC_V2); | ||
948 | tv_priv->save_TV_CLR_KNOBS = I915_READ(TV_CLR_KNOBS); | ||
949 | tv_priv->save_TV_CLR_LEVEL = I915_READ(TV_CLR_LEVEL); | ||
950 | tv_priv->save_TV_WIN_POS = I915_READ(TV_WIN_POS); | ||
951 | tv_priv->save_TV_WIN_SIZE = I915_READ(TV_WIN_SIZE); | ||
952 | tv_priv->save_TV_FILTER_CTL_1 = I915_READ(TV_FILTER_CTL_1); | ||
953 | tv_priv->save_TV_FILTER_CTL_2 = I915_READ(TV_FILTER_CTL_2); | ||
954 | tv_priv->save_TV_FILTER_CTL_3 = I915_READ(TV_FILTER_CTL_3); | ||
955 | |||
956 | for (i = 0; i < 60; i++) | ||
957 | tv_priv->save_TV_H_LUMA[i] = I915_READ(TV_H_LUMA_0 + (i <<2)); | ||
958 | for (i = 0; i < 60; i++) | ||
959 | tv_priv->save_TV_H_CHROMA[i] = I915_READ(TV_H_CHROMA_0 + (i <<2)); | ||
960 | for (i = 0; i < 43; i++) | ||
961 | tv_priv->save_TV_V_LUMA[i] = I915_READ(TV_V_LUMA_0 + (i <<2)); | ||
962 | for (i = 0; i < 43; i++) | ||
963 | tv_priv->save_TV_V_CHROMA[i] = I915_READ(TV_V_CHROMA_0 + (i <<2)); | ||
964 | |||
965 | tv_priv->save_TV_DAC = I915_READ(TV_DAC); | ||
966 | tv_priv->save_TV_CTL = I915_READ(TV_CTL); | ||
967 | } | ||
968 | |||
969 | static void | ||
970 | intel_tv_restore(struct drm_connector *connector) | ||
971 | { | ||
972 | struct drm_device *dev = connector->dev; | ||
973 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
974 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); | ||
975 | struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; | ||
976 | struct drm_crtc *crtc = connector->encoder->crtc; | ||
977 | struct intel_crtc *intel_crtc; | ||
978 | int i; | ||
979 | |||
980 | /* FIXME: No CRTC? */ | ||
981 | if (!crtc) | ||
982 | return; | ||
983 | |||
984 | intel_crtc = to_intel_crtc(crtc); | ||
985 | I915_WRITE(TV_H_CTL_1, tv_priv->save_TV_H_CTL_1); | ||
986 | I915_WRITE(TV_H_CTL_2, tv_priv->save_TV_H_CTL_2); | ||
987 | I915_WRITE(TV_H_CTL_3, tv_priv->save_TV_H_CTL_3); | ||
988 | I915_WRITE(TV_V_CTL_1, tv_priv->save_TV_V_CTL_1); | ||
989 | I915_WRITE(TV_V_CTL_2, tv_priv->save_TV_V_CTL_2); | ||
990 | I915_WRITE(TV_V_CTL_3, tv_priv->save_TV_V_CTL_3); | ||
991 | I915_WRITE(TV_V_CTL_4, tv_priv->save_TV_V_CTL_4); | ||
992 | I915_WRITE(TV_V_CTL_5, tv_priv->save_TV_V_CTL_5); | ||
993 | I915_WRITE(TV_V_CTL_6, tv_priv->save_TV_V_CTL_6); | ||
994 | I915_WRITE(TV_V_CTL_7, tv_priv->save_TV_V_CTL_7); | ||
995 | I915_WRITE(TV_SC_CTL_1, tv_priv->save_TV_SC_CTL_1); | ||
996 | I915_WRITE(TV_SC_CTL_2, tv_priv->save_TV_SC_CTL_2); | ||
997 | I915_WRITE(TV_SC_CTL_3, tv_priv->save_TV_SC_CTL_3); | ||
998 | |||
999 | I915_WRITE(TV_CSC_Y, tv_priv->save_TV_CSC_Y); | ||
1000 | I915_WRITE(TV_CSC_Y2, tv_priv->save_TV_CSC_Y2); | ||
1001 | I915_WRITE(TV_CSC_U, tv_priv->save_TV_CSC_U); | ||
1002 | I915_WRITE(TV_CSC_U2, tv_priv->save_TV_CSC_U2); | ||
1003 | I915_WRITE(TV_CSC_V, tv_priv->save_TV_CSC_V); | ||
1004 | I915_WRITE(TV_CSC_V2, tv_priv->save_TV_CSC_V2); | ||
1005 | I915_WRITE(TV_CLR_KNOBS, tv_priv->save_TV_CLR_KNOBS); | ||
1006 | I915_WRITE(TV_CLR_LEVEL, tv_priv->save_TV_CLR_LEVEL); | ||
1007 | |||
1008 | { | ||
1009 | int pipeconf_reg = (intel_crtc->pipe == 0) ? | ||
1010 | PIPEACONF : PIPEBCONF; | ||
1011 | int dspcntr_reg = (intel_crtc->plane == 0) ? | ||
1012 | DSPACNTR : DSPBCNTR; | ||
1013 | int pipeconf = I915_READ(pipeconf_reg); | ||
1014 | int dspcntr = I915_READ(dspcntr_reg); | ||
1015 | int dspbase_reg = (intel_crtc->plane == 0) ? | ||
1016 | DSPAADDR : DSPBADDR; | ||
1017 | /* Pipe must be off here */ | ||
1018 | I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE); | ||
1019 | /* Flush the plane changes */ | ||
1020 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | ||
1021 | |||
1022 | if (!IS_I9XX(dev)) { | ||
1023 | /* Wait for vblank for the disable to take effect */ | ||
1024 | intel_wait_for_vblank(dev); | ||
1025 | } | ||
1026 | |||
1027 | I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE); | ||
1028 | /* Wait for vblank for the disable to take effect. */ | ||
1029 | intel_wait_for_vblank(dev); | ||
1030 | |||
1031 | /* Filter ctl must be set before TV_WIN_SIZE */ | ||
1032 | I915_WRITE(TV_FILTER_CTL_1, tv_priv->save_TV_FILTER_CTL_1); | ||
1033 | I915_WRITE(TV_FILTER_CTL_2, tv_priv->save_TV_FILTER_CTL_2); | ||
1034 | I915_WRITE(TV_FILTER_CTL_3, tv_priv->save_TV_FILTER_CTL_3); | ||
1035 | I915_WRITE(TV_WIN_POS, tv_priv->save_TV_WIN_POS); | ||
1036 | I915_WRITE(TV_WIN_SIZE, tv_priv->save_TV_WIN_SIZE); | ||
1037 | I915_WRITE(pipeconf_reg, pipeconf); | ||
1038 | I915_WRITE(dspcntr_reg, dspcntr); | ||
1039 | /* Flush the plane changes */ | ||
1040 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | ||
1041 | } | ||
1042 | |||
1043 | for (i = 0; i < 60; i++) | ||
1044 | I915_WRITE(TV_H_LUMA_0 + (i <<2), tv_priv->save_TV_H_LUMA[i]); | ||
1045 | for (i = 0; i < 60; i++) | ||
1046 | I915_WRITE(TV_H_CHROMA_0 + (i <<2), tv_priv->save_TV_H_CHROMA[i]); | ||
1047 | for (i = 0; i < 43; i++) | ||
1048 | I915_WRITE(TV_V_LUMA_0 + (i <<2), tv_priv->save_TV_V_LUMA[i]); | ||
1049 | for (i = 0; i < 43; i++) | ||
1050 | I915_WRITE(TV_V_CHROMA_0 + (i <<2), tv_priv->save_TV_V_CHROMA[i]); | ||
1051 | |||
1052 | I915_WRITE(TV_DAC, tv_priv->save_TV_DAC); | ||
1053 | I915_WRITE(TV_CTL, tv_priv->save_TV_CTL); | ||
1054 | } | ||
1055 | |||
1056 | static const struct tv_mode * | 919 | static const struct tv_mode * |
1057 | intel_tv_mode_lookup (char *tv_format) | 920 | intel_tv_mode_lookup (char *tv_format) |
1058 | { | 921 | { |
@@ -1687,8 +1550,6 @@ static const struct drm_encoder_helper_funcs intel_tv_helper_funcs = { | |||
1687 | 1550 | ||
1688 | static const struct drm_connector_funcs intel_tv_connector_funcs = { | 1551 | static const struct drm_connector_funcs intel_tv_connector_funcs = { |
1689 | .dpms = drm_helper_connector_dpms, | 1552 | .dpms = drm_helper_connector_dpms, |
1690 | .save = intel_tv_save, | ||
1691 | .restore = intel_tv_restore, | ||
1692 | .detect = intel_tv_detect, | 1553 | .detect = intel_tv_detect, |
1693 | .destroy = intel_tv_destroy, | 1554 | .destroy = intel_tv_destroy, |
1694 | .set_property = intel_tv_set_property, | 1555 | .set_property = intel_tv_set_property, |