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authorOlof Johansson <olof@lixom.net>2015-01-12 17:25:55 -0500
committerOlof Johansson <olof@lixom.net>2015-01-12 17:25:55 -0500
commit63bdaa9332dd8f582629b96bea44dd228231c64a (patch)
tree476f888d56db2e433496c548583fdd7005f9a082
parenteaa27f34e91a14cdceed26ed6c6793ec1d186115 (diff)
parent569dd56c9971c699472d3b270e988baf7f6de8c9 (diff)
Merge tag 'renesas-lager-board-removal-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Merge "Renesas ARM Based SoC Lager Board Removal for v3.20" from Simon Horman: "The serial port rename changes are not strictly related to lager board removal from a feature point of view. But the lager portion of this change depends on board removal to avoid a regression of booting using that code, And thus it seems to make sense to put here. And it seems best to put the koelsch and lager serial port rename changes in the same branch. Likewise the removal of bootargs from lager DT depends on removing lager board code to avoid a regression when using it and thus I have included it in the same branch." * Remove legacy r8a7790 SoC and its Lager board code * Update serial port names on koelsch and lager boards * Remove console bootargs parameter from lager DT * tag 'renesas-lager-board-removal-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: lager dts: Drop console= bootargs parameter ARM: shmobile: koelsch: Rename SCIF[01] serial ports to ttySC[01] ARM: shmobile: lager: Rename SCIFA[01] serial ports to ttySC[01] ARM: shmobile: r8a7790: Remove legacy code ARM: shmobile: lager: Remove legacy board support ARM: shmobile: lager-reference: DTS-only board support Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts6
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts4
-rw-r--r--arch/arm/configs/lager_defconfig150
-rw-r--r--arch/arm/configs/shmobile_defconfig1
-rw-r--r--arch/arm/mach-shmobile/Kconfig20
-rw-r--r--arch/arm/mach-shmobile/Makefile3
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-lager-reference.c39
-rw-r--r--arch/arm/mach-shmobile/board-lager.c827
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c459
-rw-r--r--arch/arm/mach-shmobile/r8a7790.h28
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c284
14 files changed, 6 insertions, 1818 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 3589d67437f8..b65b22b0ea3e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1395,7 +1395,6 @@ F: arch/arm/configs/ape6evm_defconfig
1395F: arch/arm/configs/armadillo800eva_defconfig 1395F: arch/arm/configs/armadillo800eva_defconfig
1396F: arch/arm/configs/bockw_defconfig 1396F: arch/arm/configs/bockw_defconfig
1397F: arch/arm/configs/kzm9g_defconfig 1397F: arch/arm/configs/kzm9g_defconfig
1398F: arch/arm/configs/lager_defconfig
1399F: arch/arm/configs/mackerel_defconfig 1398F: arch/arm/configs/mackerel_defconfig
1400F: arch/arm/configs/marzen_defconfig 1399F: arch/arm/configs/marzen_defconfig
1401F: arch/arm/configs/shmobile_defconfig 1400F: arch/arm/configs/shmobile_defconfig
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 91bd5bd62857..19cb6fcecf89 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -410,7 +410,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
410 r8a7778-bockw.dtb \ 410 r8a7778-bockw.dtb \
411 r8a7778-bockw-reference.dtb \ 411 r8a7778-bockw-reference.dtb \
412 r8a7779-marzen.dtb \ 412 r8a7779-marzen.dtb \
413 r8a7790-lager.dtb \
414 sh7372-mackerel.dtb \ 413 sh7372-mackerel.dtb \
415 sh73a0-kzm9g.dtb \ 414 sh73a0-kzm9g.dtb \
416 sh73a0-kzm9g-reference.dtb 415 sh73a0-kzm9g-reference.dtb
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 636d53bb87a2..4118030f366d 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -47,12 +47,12 @@
47 compatible = "renesas,lager", "renesas,r8a7790"; 47 compatible = "renesas,lager", "renesas,r8a7790";
48 48
49 aliases { 49 aliases {
50 serial6 = &scifa0; 50 serial0 = &scifa0;
51 serial7 = &scifa1; 51 serial1 = &scifa1;
52 }; 52 };
53 53
54 chosen { 54 chosen {
55 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 55 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
56 stdout-path = &scifa0; 56 stdout-path = &scifa0;
57 }; 57 };
58 58
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 990af167c551..bf58c79a6554 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -48,8 +48,8 @@
48 compatible = "renesas,koelsch", "renesas,r8a7791"; 48 compatible = "renesas,koelsch", "renesas,r8a7791";
49 49
50 aliases { 50 aliases {
51 serial6 = &scif0; 51 serial0 = &scif0;
52 serial7 = &scif1; 52 serial1 = &scif1;
53 }; 53 };
54 54
55 chosen { 55 chosen {
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
deleted file mode 100644
index a82afc916a89..000000000000
--- a/arch/arm/configs/lager_defconfig
+++ /dev/null
@@ -1,150 +0,0 @@
1CONFIG_SYSVIPC=y
2CONFIG_NO_HZ=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_CC_OPTIMIZE_FOR_SIZE=y
7CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y
9CONFIG_PERF_EVENTS=y
10CONFIG_SLAB=y
11# CONFIG_LBDAF is not set
12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set
15CONFIG_ARCH_SHMOBILE_LEGACY=y
16CONFIG_ARCH_R8A7790=y
17CONFIG_MACH_LAGER=y
18# CONFIG_SH_TIMER_TMU is not set
19# CONFIG_EM_TIMER_STI is not set
20CONFIG_ARM_ERRATA_430973=y
21CONFIG_ARM_ERRATA_458693=y
22CONFIG_ARM_ERRATA_460075=y
23CONFIG_ARM_ERRATA_743622=y
24CONFIG_ARM_ERRATA_754322=y
25CONFIG_PCI=y
26CONFIG_PCI_RCAR_GEN2=y
27CONFIG_PCI_RCAR_GEN2_PCIE=y
28CONFIG_HAVE_ARM_ARCH_TIMER=y
29CONFIG_AEABI=y
30# CONFIG_OABI_COMPAT is not set
31CONFIG_FORCE_MAX_ZONEORDER=13
32CONFIG_ZBOOT_ROM_TEXT=0x0
33CONFIG_ZBOOT_ROM_BSS=0x0
34CONFIG_ARM_APPENDED_DTB=y
35CONFIG_KEXEC=y
36CONFIG_AUTO_ZRELADDR=y
37CONFIG_VFP=y
38CONFIG_NEON=y
39# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
40CONFIG_PM=y
41CONFIG_NET=y
42CONFIG_PACKET=y
43CONFIG_UNIX=y
44CONFIG_INET=y
45CONFIG_IP_PNP=y
46CONFIG_IP_PNP_DHCP=y
47# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
48# CONFIG_INET_XFRM_MODE_TUNNEL is not set
49# CONFIG_INET_XFRM_MODE_BEET is not set
50# CONFIG_INET_LRO is not set
51# CONFIG_INET_DIAG is not set
52# CONFIG_IPV6 is not set
53# CONFIG_WIRELESS is not set
54CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
55CONFIG_DEVTMPFS=y
56CONFIG_DEVTMPFS_MOUNT=y
57CONFIG_MTD=y
58CONFIG_MTD_M25P80=y
59CONFIG_MTD_SPI_NOR=y
60CONFIG_BLK_DEV_SD=y
61CONFIG_ATA=y
62CONFIG_SATA_RCAR=y
63CONFIG_NETDEVICES=y
64# CONFIG_NET_CORE is not set
65# CONFIG_NET_VENDOR_ARC is not set
66# CONFIG_NET_CADENCE is not set
67# CONFIG_NET_VENDOR_BROADCOM is not set
68# CONFIG_NET_VENDOR_CIRRUS is not set
69# CONFIG_NET_VENDOR_FARADAY is not set
70# CONFIG_NET_VENDOR_INTEL is not set
71# CONFIG_NET_VENDOR_MARVELL is not set
72# CONFIG_NET_VENDOR_MICREL is not set
73# CONFIG_NET_VENDOR_NATSEMI is not set
74CONFIG_SH_ETH=y
75# CONFIG_NET_VENDOR_SEEQ is not set
76# CONFIG_NET_VENDOR_SMSC is not set
77# CONFIG_NET_VENDOR_STMICRO is not set
78# CONFIG_NET_VENDOR_VIA is not set
79# CONFIG_NET_VENDOR_WIZNET is not set
80# CONFIG_WLAN is not set
81# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
82CONFIG_INPUT_EVDEV=y
83# CONFIG_KEYBOARD_ATKBD is not set
84CONFIG_KEYBOARD_GPIO=y
85# CONFIG_INPUT_MOUSE is not set
86# CONFIG_SERIO is not set
87# CONFIG_LEGACY_PTYS is not set
88CONFIG_SERIAL_SH_SCI=y
89CONFIG_SERIAL_SH_SCI_NR_UARTS=10
90CONFIG_SERIAL_SH_SCI_CONSOLE=y
91# CONFIG_HW_RANDOM is not set
92CONFIG_I2C_GPIO=y
93CONFIG_I2C_SH_MOBILE=y
94CONFIG_I2C_RCAR=y
95CONFIG_SPI=y
96CONFIG_SPI_RSPI=y
97CONFIG_SPI_SH_MSIOF=y
98CONFIG_GPIO_SH_PFC=y
99CONFIG_GPIOLIB=y
100CONFIG_GPIO_RCAR=y
101# CONFIG_HWMON is not set
102CONFIG_THERMAL=y
103CONFIG_RCAR_THERMAL=y
104CONFIG_REGULATOR=y
105CONFIG_REGULATOR_FIXED_VOLTAGE=y
106CONFIG_REGULATOR_DA9210=y
107CONFIG_REGULATOR_GPIO=y
108CONFIG_MEDIA_SUPPORT=y
109CONFIG_MEDIA_CAMERA_SUPPORT=y
110CONFIG_V4L_PLATFORM_DRIVERS=y
111CONFIG_SOC_CAMERA=y
112CONFIG_SOC_CAMERA_PLATFORM=y
113CONFIG_VIDEO_RCAR_VIN=y
114# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
115CONFIG_VIDEO_ADV7180=y
116CONFIG_DRM=y
117CONFIG_DRM_RCAR_DU=y
118CONFIG_SOUND=y
119CONFIG_SND=y
120CONFIG_SND_SOC=y
121CONFIG_SND_SOC_RCAR=y
122# CONFIG_USB_SUPPORT is not set
123CONFIG_MMC=y
124CONFIG_MMC_SDHI=y
125CONFIG_MMC_SH_MMCIF=y
126CONFIG_NEW_LEDS=y
127CONFIG_LEDS_CLASS=y
128CONFIG_LEDS_GPIO=y
129CONFIG_RTC_CLASS=y
130CONFIG_DMADEVICES=y
131CONFIG_SH_DMAE=y
132# CONFIG_IOMMU_SUPPORT is not set
133# CONFIG_DNOTIFY is not set
134CONFIG_MSDOS_FS=y
135CONFIG_VFAT_FS=y
136CONFIG_TMPFS=y
137CONFIG_CONFIGFS_FS=y
138# CONFIG_MISC_FILESYSTEMS is not set
139CONFIG_NFS_FS=y
140CONFIG_NFS_V3_ACL=y
141CONFIG_NFS_V4=y
142CONFIG_NFS_V4_1=y
143CONFIG_ROOT_NFS=y
144CONFIG_NLS_CODEPAGE_437=y
145CONFIG_NLS_ISO8859_1=y
146# CONFIG_ENABLE_WARN_DEPRECATED is not set
147# CONFIG_ENABLE_MUST_CHECK is not set
148# CONFIG_ARM_UNWIND is not set
149# CONFIG_CRYPTO_ANSI_CPRNG is not set
150# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 3df6ca0c1d1f..e4a6c5e9174d 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_R8A7779=y
17CONFIG_ARCH_R8A7790=y 17CONFIG_ARCH_R8A7790=y
18CONFIG_ARCH_R8A7791=y 18CONFIG_ARCH_R8A7791=y
19CONFIG_ARCH_R8A7794=y 19CONFIG_ARCH_R8A7794=y
20CONFIG_MACH_LAGER=y
21CONFIG_MACH_MARZEN=y 20CONFIG_MACH_MARZEN=y
22# CONFIG_SWP_EMULATE is not set 21# CONFIG_SWP_EMULATE is not set
23CONFIG_CPU_BPREDICT_DISABLE=y 22CONFIG_CPU_BPREDICT_DISABLE=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1b4fafe524ff..bb3d07504d8b 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -74,11 +74,6 @@ config ARCH_R8A7794
74 74
75comment "Renesas ARM SoCs Board Type" 75comment "Renesas ARM SoCs Board Type"
76 76
77config MACH_LAGER
78 bool "Lager board"
79 depends on ARCH_R8A7790
80 select MICREL_PHY if SH_ETH
81
82config MACH_MARZEN 77config MACH_MARZEN
83 bool "MARZEN board" 78 bool "MARZEN board"
84 depends on ARCH_R8A7779 79 depends on ARCH_R8A7779
@@ -133,14 +128,6 @@ config ARCH_R8A7779
133 select ARCH_WANT_OPTIONAL_GPIOLIB 128 select ARCH_WANT_OPTIONAL_GPIOLIB
134 select ARM_GIC 129 select ARM_GIC
135 130
136config ARCH_R8A7790
137 bool "R-Car H2 (R8A77900)"
138 select ARCH_RCAR_GEN2
139 select ARCH_WANT_OPTIONAL_GPIOLIB
140 select ARM_GIC
141 select MIGHT_HAVE_PCI
142 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
143
144comment "Renesas ARM SoCs Board Type" 131comment "Renesas ARM SoCs Board Type"
145 132
146config MACH_APE6EVM 133config MACH_APE6EVM
@@ -208,13 +195,6 @@ config MACH_MARZEN
208 select REGULATOR_FIXED_VOLTAGE if REGULATOR 195 select REGULATOR_FIXED_VOLTAGE if REGULATOR
209 select USE_OF 196 select USE_OF
210 197
211config MACH_LAGER
212 bool "Lager board"
213 depends on ARCH_R8A7790
214 select USE_OF
215 select MICREL_PHY if SH_ETH
216 select SND_SOC_AK4642 if SND_SIMPLE_CARD
217
218config MACH_KZM9G 198config MACH_KZM9G
219 bool "KZM-A9-GT board" 199 bool "KZM-A9-GT board"
220 depends on ARCH_SH73A0 200 depends on ARCH_SH73A0
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index b55cac0e5b2b..d53996e6da97 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
27obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o 27obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o 29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
30obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
31endif 30endif
32 31
33# CPU reset vector handling objects 32# CPU reset vector handling objects
@@ -57,7 +56,6 @@ obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
57 56
58# Board objects 57# Board objects
59ifdef CONFIG_ARCH_SHMOBILE_MULTI 58ifdef CONFIG_ARCH_SHMOBILE_MULTI
60obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o
61obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o 59obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
62else 60else
63obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o 61obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
@@ -66,7 +64,6 @@ obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
66obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 64obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
67obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o 65obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
68obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 66obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
69obj-$(CONFIG_MACH_LAGER) += board-lager.o
70obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 67obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
71obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 68obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
72obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 69obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 57d00ed6ec0c..02532bea5300 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,7 +7,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
8loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 8loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
9loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 9loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
10loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
11loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 10loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
12loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 11loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
13 12
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
deleted file mode 100644
index fa06bdba61df..000000000000
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Lager board support - Reference DT implementation
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/init.h>
18#include <linux/of_platform.h>
19
20#include <asm/mach/arch.h>
21
22#include "common.h"
23#include "r8a7790.h"
24#include "rcar-gen2.h"
25
26static const char *lager_boards_compat_dt[] __initdata = {
27 "renesas,lager",
28 "renesas,lager-reference",
29 NULL,
30};
31
32DT_MACHINE_START(LAGER_DT, "lager")
33 .smp = smp_ops(r8a7790_smp_ops),
34 .init_early = shmobile_init_delay,
35 .init_time = rcar_gen2_timer_init,
36 .init_late = shmobile_init_late,
37 .reserve = rcar_gen2_reserve,
38 .dt_compat = lager_boards_compat_dt,
39MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
deleted file mode 100644
index f8197eb6e566..000000000000
--- a/arch/arm/mach-shmobile/board-lager.c
+++ /dev/null
@@ -1,827 +0,0 @@
1/*
2 * Lager board support
3 *
4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2014 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/gpio.h>
19#include <linux/gpio_keys.h>
20#include <linux/i2c.h>
21#include <linux/input.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/kernel.h>
25#include <linux/leds.h>
26#include <linux/mfd/tmio.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/sh_mmcif.h>
29#include <linux/mmc/sh_mobile_sdhi.h>
30#include <linux/mtd/partitions.h>
31#include <linux/mtd/mtd.h>
32#include <linux/pinctrl/machine.h>
33#include <linux/platform_data/camera-rcar.h>
34#include <linux/platform_data/gpio-rcar.h>
35#include <linux/platform_data/usb-rcar-gen2-phy.h>
36#include <linux/platform_device.h>
37#include <linux/phy.h>
38#include <linux/regulator/driver.h>
39#include <linux/regulator/fixed.h>
40#include <linux/regulator/gpio-regulator.h>
41#include <linux/regulator/machine.h>
42#include <linux/sh_eth.h>
43#include <linux/spi/flash.h>
44#include <linux/spi/rspi.h>
45#include <linux/spi/spi.h>
46#include <linux/usb/phy.h>
47#include <linux/usb/renesas_usbhs.h>
48
49#include <media/soc_camera.h>
50#include <asm/mach-types.h>
51#include <asm/mach/arch.h>
52#include <sound/rcar_snd.h>
53#include <sound/simple_card.h>
54
55#include "common.h"
56#include "irqs.h"
57#include "r8a7790.h"
58#include "rcar-gen2.h"
59
60/*
61 * SSI-AK4643
62 *
63 * SW1: 1: AK4643
64 * 2: CN22
65 * 3: ADV7511
66 *
67 * this command is required when playback.
68 *
69 * # amixer set "LINEOUT Mixer DACL" on
70 */
71
72/*
73 * SDHI0 (CN8)
74 *
75 * JP3: pin1
76 * SW20: pin1
77
78 * GP5_24: 1: VDD 3.3V (defult)
79 * 0: VDD 0.0V
80 * GP5_29: 1: VccQ 3.3V (defult)
81 * 0: VccQ 1.8V
82 *
83 */
84
85/* LEDS */
86static struct gpio_led lager_leds[] = {
87 {
88 .name = "led8",
89 .gpio = RCAR_GP_PIN(5, 17),
90 .default_state = LEDS_GPIO_DEFSTATE_ON,
91 }, {
92 .name = "led7",
93 .gpio = RCAR_GP_PIN(4, 23),
94 .default_state = LEDS_GPIO_DEFSTATE_ON,
95 }, {
96 .name = "led6",
97 .gpio = RCAR_GP_PIN(4, 22),
98 .default_state = LEDS_GPIO_DEFSTATE_ON,
99 },
100};
101
102static const struct gpio_led_platform_data lager_leds_pdata __initconst = {
103 .leds = lager_leds,
104 .num_leds = ARRAY_SIZE(lager_leds),
105};
106
107/* GPIO KEY */
108#define GPIO_KEY(c, g, d, ...) \
109 { .code = c, .gpio = g, .desc = d, .active_low = 1, \
110 .wakeup = 1, .debounce_interval = 20 }
111
112static struct gpio_keys_button gpio_buttons[] = {
113 GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"),
114 GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"),
115 GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"),
116 GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"),
117};
118
119static const struct gpio_keys_platform_data lager_keys_pdata __initconst = {
120 .buttons = gpio_buttons,
121 .nbuttons = ARRAY_SIZE(gpio_buttons),
122};
123
124/* Fixed 3.3V regulator to be used by MMCIF */
125static struct regulator_consumer_supply fixed3v3_power_consumers[] =
126{
127 REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
128};
129
130/*
131 * SDHI regulator macro
132 *
133 ** FIXME**
134 * Lager board vqmmc is provided via DA9063 PMIC chip,
135 * and we should use ${LINK}/drivers/mfd/da9063-* driver for it.
136 * but, it doesn't have regulator support at this point.
137 * It uses gpio-regulator for vqmmc as quick-hack.
138 */
139#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin) \
140static struct regulator_consumer_supply vcc_sdhi##idx##_consumer = \
141 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx); \
142 \
143static struct regulator_init_data vcc_sdhi##idx##_init_data = { \
144 .constraints = { \
145 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
146 }, \
147 .consumer_supplies = &vcc_sdhi##idx##_consumer, \
148 .num_consumer_supplies = 1, \
149}; \
150 \
151static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
152 .supply_name = "SDHI" #idx "Vcc", \
153 .microvolts = 3300000, \
154 .gpio = vdd_pin, \
155 .enable_high = 1, \
156 .init_data = &vcc_sdhi##idx##_init_data, \
157}; \
158 \
159static struct regulator_consumer_supply vccq_sdhi##idx##_consumer = \
160 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx); \
161 \
162static struct regulator_init_data vccq_sdhi##idx##_init_data = { \
163 .constraints = { \
164 .input_uV = 3300000, \
165 .min_uV = 1800000, \
166 .max_uV = 3300000, \
167 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
168 REGULATOR_CHANGE_STATUS, \
169 }, \
170 .consumer_supplies = &vccq_sdhi##idx##_consumer, \
171 .num_consumer_supplies = 1, \
172}; \
173 \
174static struct gpio vccq_sdhi##idx##_gpio = \
175 { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx }; \
176 \
177static struct gpio_regulator_state vccq_sdhi##idx##_states[] = { \
178 { .value = 1800000, .gpios = 0 }, \
179 { .value = 3300000, .gpios = 1 }, \
180}; \
181 \
182static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
183 .supply_name = "vqmmc", \
184 .gpios = &vccq_sdhi##idx##_gpio, \
185 .nr_gpios = 1, \
186 .states = vccq_sdhi##idx##_states, \
187 .nr_states = ARRAY_SIZE(vccq_sdhi##idx##_states), \
188 .type = REGULATOR_VOLTAGE, \
189 .init_data = &vccq_sdhi##idx##_init_data, \
190};
191
192SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29));
193SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30));
194
195/* MMCIF */
196static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
197 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
198 .clk_ctrl2_present = true,
199 .ccs_unsupported = true,
200};
201
202static const struct resource mmcif1_resources[] __initconst = {
203 DEFINE_RES_MEM(0xee220000, 0x80),
204 DEFINE_RES_IRQ(gic_spi(170)),
205};
206
207/* Ether */
208static const struct sh_eth_plat_data ether_pdata __initconst = {
209 .phy = 0x1,
210 .phy_irq = irq_pin(0),
211 .edmac_endian = EDMAC_LITTLE_ENDIAN,
212 .phy_interface = PHY_INTERFACE_MODE_RMII,
213 .ether_link_active_low = 1,
214};
215
216static const struct resource ether_resources[] __initconst = {
217 DEFINE_RES_MEM(0xee700000, 0x400),
218 DEFINE_RES_IRQ(gic_spi(162)),
219};
220
221static const struct platform_device_info ether_info __initconst = {
222 .name = "r8a7790-ether",
223 .id = -1,
224 .res = ether_resources,
225 .num_res = ARRAY_SIZE(ether_resources),
226 .data = &ether_pdata,
227 .size_data = sizeof(ether_pdata),
228 .dma_mask = DMA_BIT_MASK(32),
229};
230
231/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
232static struct mtd_partition spi_flash_part[] = {
233 /* Reserved for user loader program, read-only */
234 {
235 .name = "loader",
236 .offset = 0,
237 .size = SZ_256K,
238 .mask_flags = MTD_WRITEABLE,
239 },
240 /* Reserved for user program, read-only */
241 {
242 .name = "user",
243 .offset = MTDPART_OFS_APPEND,
244 .size = SZ_4M,
245 .mask_flags = MTD_WRITEABLE,
246 },
247 /* All else is writable (e.g. JFFS2) */
248 {
249 .name = "flash",
250 .offset = MTDPART_OFS_APPEND,
251 .size = MTDPART_SIZ_FULL,
252 .mask_flags = 0,
253 },
254};
255
256static const struct flash_platform_data spi_flash_data = {
257 .name = "m25p80",
258 .parts = spi_flash_part,
259 .nr_parts = ARRAY_SIZE(spi_flash_part),
260 .type = "s25fl512s",
261};
262
263static const struct rspi_plat_data qspi_pdata __initconst = {
264 .num_chipselect = 1,
265};
266
267static const struct spi_board_info spi_info[] __initconst = {
268 {
269 .modalias = "m25p80",
270 .platform_data = &spi_flash_data,
271 .mode = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
272 .max_speed_hz = 30000000,
273 .bus_num = 0,
274 .chip_select = 0,
275 },
276};
277
278/* QSPI resource */
279static const struct resource qspi_resources[] __initconst = {
280 DEFINE_RES_MEM(0xe6b10000, 0x1000),
281 DEFINE_RES_IRQ_NAMED(gic_spi(184), "mux"),
282};
283
284/* VIN */
285static const struct resource vin_resources[] __initconst = {
286 /* VIN0 */
287 DEFINE_RES_MEM(0xe6ef0000, 0x1000),
288 DEFINE_RES_IRQ(gic_spi(188)),
289 /* VIN1 */
290 DEFINE_RES_MEM(0xe6ef1000, 0x1000),
291 DEFINE_RES_IRQ(gic_spi(189)),
292};
293
294static void __init lager_add_vin_device(unsigned idx,
295 struct rcar_vin_platform_data *pdata)
296{
297 struct platform_device_info vin_info = {
298 .name = "r8a7790-vin",
299 .id = idx,
300 .res = &vin_resources[idx * 2],
301 .num_res = 2,
302 .dma_mask = DMA_BIT_MASK(32),
303 .data = pdata,
304 .size_data = sizeof(*pdata),
305 };
306
307 BUG_ON(idx > 1);
308
309 platform_device_register_full(&vin_info);
310}
311
312#define LAGER_CAMERA(idx, name, addr, pdata, flag) \
313static struct i2c_board_info i2c_cam##idx##_device = { \
314 I2C_BOARD_INFO(name, addr), \
315}; \
316 \
317static struct rcar_vin_platform_data vin##idx##_pdata = { \
318 .flags = flag, \
319}; \
320 \
321static struct soc_camera_link cam##idx##_link = { \
322 .bus_id = idx, \
323 .board_info = &i2c_cam##idx##_device, \
324 .i2c_adapter_id = 2, \
325 .module_name = name, \
326 .priv = pdata, \
327}
328
329/* Camera 0 is not currently supported due to adv7612 support missing */
330LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);
331
332static void __init lager_add_camera1_device(void)
333{
334 platform_device_register_data(NULL, "soc-camera-pdrv", 1,
335 &cam1_link, sizeof(cam1_link));
336 lager_add_vin_device(1, &vin1_pdata);
337}
338
339/* SATA1 */
340static const struct resource sata1_resources[] __initconst = {
341 DEFINE_RES_MEM(0xee500000, 0x2000),
342 DEFINE_RES_IRQ(gic_spi(106)),
343};
344
345static const struct platform_device_info sata1_info __initconst = {
346 .name = "sata-r8a7790",
347 .id = 1,
348 .res = sata1_resources,
349 .num_res = ARRAY_SIZE(sata1_resources),
350 .dma_mask = DMA_BIT_MASK(32),
351};
352
353/* USBHS */
354static const struct resource usbhs_resources[] __initconst = {
355 DEFINE_RES_MEM(0xe6590000, 0x100),
356 DEFINE_RES_IRQ(gic_spi(107)),
357};
358
359struct usbhs_private {
360 struct renesas_usbhs_platform_info info;
361 struct usb_phy *phy;
362};
363
364#define usbhs_get_priv(pdev) \
365 container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info)
366
367static int usbhs_power_ctrl(struct platform_device *pdev,
368 void __iomem *base, int enable)
369{
370 struct usbhs_private *priv = usbhs_get_priv(pdev);
371
372 if (!priv->phy)
373 return -ENODEV;
374
375 if (enable) {
376 int retval = usb_phy_init(priv->phy);
377
378 if (!retval)
379 retval = usb_phy_set_suspend(priv->phy, 0);
380 return retval;
381 }
382
383 usb_phy_set_suspend(priv->phy, 1);
384 usb_phy_shutdown(priv->phy);
385 return 0;
386}
387
388static int usbhs_hardware_init(struct platform_device *pdev)
389{
390 struct usbhs_private *priv = usbhs_get_priv(pdev);
391 struct usb_phy *phy;
392 int ret;
393
394 /* USB0 Function - use PWEN as GPIO input to detect DIP Switch SW5
395 * setting to avoid VBUS short circuit due to wrong cable.
396 * PWEN should be pulled up high if USB Function is selected by SW5
397 */
398 gpio_request_one(RCAR_GP_PIN(5, 18), GPIOF_IN, NULL); /* USB0_PWEN */
399 if (!gpio_get_value(RCAR_GP_PIN(5, 18))) {
400 pr_warn("Error: USB Function not selected - check SW5 + SW6\n");
401 ret = -ENOTSUPP;
402 goto error;
403 }
404
405 phy = usb_get_phy_dev(&pdev->dev, 0);
406 if (IS_ERR(phy)) {
407 ret = PTR_ERR(phy);
408 goto error;
409 }
410
411 priv->phy = phy;
412 return 0;
413 error:
414 gpio_free(RCAR_GP_PIN(5, 18));
415 return ret;
416}
417
418static int usbhs_hardware_exit(struct platform_device *pdev)
419{
420 struct usbhs_private *priv = usbhs_get_priv(pdev);
421
422 if (!priv->phy)
423 return 0;
424
425 usb_put_phy(priv->phy);
426 priv->phy = NULL;
427
428 gpio_free(RCAR_GP_PIN(5, 18));
429 return 0;
430}
431
432static int usbhs_get_id(struct platform_device *pdev)
433{
434 return USBHS_GADGET;
435}
436
437static u32 lager_usbhs_pipe_type[] = {
438 USB_ENDPOINT_XFER_CONTROL,
439 USB_ENDPOINT_XFER_ISOC,
440 USB_ENDPOINT_XFER_ISOC,
441 USB_ENDPOINT_XFER_BULK,
442 USB_ENDPOINT_XFER_BULK,
443 USB_ENDPOINT_XFER_BULK,
444 USB_ENDPOINT_XFER_INT,
445 USB_ENDPOINT_XFER_INT,
446 USB_ENDPOINT_XFER_INT,
447 USB_ENDPOINT_XFER_BULK,
448 USB_ENDPOINT_XFER_BULK,
449 USB_ENDPOINT_XFER_BULK,
450 USB_ENDPOINT_XFER_BULK,
451 USB_ENDPOINT_XFER_BULK,
452 USB_ENDPOINT_XFER_BULK,
453 USB_ENDPOINT_XFER_BULK,
454};
455
456static struct usbhs_private usbhs_priv __initdata = {
457 .info = {
458 .platform_callback = {
459 .power_ctrl = usbhs_power_ctrl,
460 .hardware_init = usbhs_hardware_init,
461 .hardware_exit = usbhs_hardware_exit,
462 .get_id = usbhs_get_id,
463 },
464 .driver_param = {
465 .buswait_bwait = 4,
466 .pipe_type = lager_usbhs_pipe_type,
467 .pipe_size = ARRAY_SIZE(lager_usbhs_pipe_type),
468 },
469 }
470};
471
472static void __init lager_register_usbhs(void)
473{
474 usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2");
475 platform_device_register_resndata(NULL,
476 "renesas_usbhs", -1,
477 usbhs_resources,
478 ARRAY_SIZE(usbhs_resources),
479 &usbhs_priv.info,
480 sizeof(usbhs_priv.info));
481}
482
483/* USBHS PHY */
484static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = {
485 .chan0_pci = 0, /* Channel 0 is USBHS */
486 .chan2_pci = 1, /* Channel 2 is PCI USB */
487};
488
489static const struct resource usbhs_phy_resources[] __initconst = {
490 DEFINE_RES_MEM(0xe6590100, 0x100),
491};
492
493/* I2C */
494static struct i2c_board_info i2c2_devices[] = {
495 {
496 I2C_BOARD_INFO("ak4643", 0x12),
497 }
498};
499
500/* Sound */
501static struct resource rsnd_resources[] __initdata = {
502 [RSND_GEN2_SCU] = DEFINE_RES_MEM(0xec500000, 0x1000),
503 [RSND_GEN2_ADG] = DEFINE_RES_MEM(0xec5a0000, 0x100),
504 [RSND_GEN2_SSIU] = DEFINE_RES_MEM(0xec540000, 0x1000),
505 [RSND_GEN2_SSI] = DEFINE_RES_MEM(0xec541000, 0x1280),
506};
507
508static struct rsnd_ssi_platform_info rsnd_ssi[] = {
509 RSND_SSI(0, gic_spi(370), 0),
510 RSND_SSI(0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE),
511};
512
513static struct rsnd_src_platform_info rsnd_src[2] = {
514 /* no member at this point */
515};
516
517static struct rsnd_dai_platform_info rsnd_dai = {
518 .playback = { .ssi = &rsnd_ssi[0], },
519 .capture = { .ssi = &rsnd_ssi[1], },
520};
521
522static struct rcar_snd_info rsnd_info = {
523 .flags = RSND_GEN2,
524 .ssi_info = rsnd_ssi,
525 .ssi_info_nr = ARRAY_SIZE(rsnd_ssi),
526 .src_info = rsnd_src,
527 .src_info_nr = ARRAY_SIZE(rsnd_src),
528 .dai_info = &rsnd_dai,
529 .dai_info_nr = 1,
530};
531
532static struct asoc_simple_card_info rsnd_card_info = {
533 .name = "AK4643",
534 .card = "SSI01-AK4643",
535 .codec = "ak4642-codec.2-0012",
536 .platform = "rcar_sound",
537 .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
538 .cpu_dai = {
539 .name = "rcar_sound",
540 },
541 .codec_dai = {
542 .name = "ak4642-hifi",
543 .sysclk = 11289600,
544 },
545};
546
547static void __init lager_add_rsnd_device(void)
548{
549 struct platform_device_info cardinfo = {
550 .name = "asoc-simple-card",
551 .id = -1,
552 .data = &rsnd_card_info,
553 .size_data = sizeof(struct asoc_simple_card_info),
554 .dma_mask = DMA_BIT_MASK(32),
555 };
556
557 i2c_register_board_info(2, i2c2_devices,
558 ARRAY_SIZE(i2c2_devices));
559
560 platform_device_register_resndata(
561 NULL, "rcar_sound", -1,
562 rsnd_resources, ARRAY_SIZE(rsnd_resources),
563 &rsnd_info, sizeof(rsnd_info));
564
565 platform_device_register_full(&cardinfo);
566}
567
568/* SDHI0 */
569static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
570 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
571 MMC_CAP_POWER_OFF_CARD,
572 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
573 TMIO_MMC_WRPROTECT_DISABLE,
574};
575
576static struct resource sdhi0_resources[] __initdata = {
577 DEFINE_RES_MEM(0xee100000, 0x200),
578 DEFINE_RES_IRQ(gic_spi(165)),
579};
580
581/* SDHI2 */
582static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
583 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
584 MMC_CAP_POWER_OFF_CARD,
585 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
586 TMIO_MMC_WRPROTECT_DISABLE,
587};
588
589static struct resource sdhi2_resources[] __initdata = {
590 DEFINE_RES_MEM(0xee140000, 0x100),
591 DEFINE_RES_IRQ(gic_spi(167)),
592};
593
594/* Internal PCI1 */
595static const struct resource pci1_resources[] __initconst = {
596 DEFINE_RES_MEM(0xee0b0000, 0x10000), /* CFG */
597 DEFINE_RES_MEM(0xee0a0000, 0x10000), /* MEM */
598 DEFINE_RES_IRQ(gic_spi(112)),
599};
600
601static const struct platform_device_info pci1_info __initconst = {
602 .name = "pci-rcar-gen2",
603 .id = 1,
604 .res = pci1_resources,
605 .num_res = ARRAY_SIZE(pci1_resources),
606 .dma_mask = DMA_BIT_MASK(32),
607};
608
609static void __init lager_add_usb1_device(void)
610{
611 platform_device_register_full(&pci1_info);
612}
613
614/* Internal PCI2 */
615static const struct resource pci2_resources[] __initconst = {
616 DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */
617 DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */
618 DEFINE_RES_IRQ(gic_spi(113)),
619};
620
621static const struct platform_device_info pci2_info __initconst = {
622 .name = "pci-rcar-gen2",
623 .id = 2,
624 .res = pci2_resources,
625 .num_res = ARRAY_SIZE(pci2_resources),
626 .dma_mask = DMA_BIT_MASK(32),
627};
628
629static void __init lager_add_usb2_device(void)
630{
631 platform_device_register_full(&pci2_info);
632}
633
634static const struct pinctrl_map lager_pinctrl_map[] = {
635 /* DU (CN10: ARGB0, CN13: LVDS) */
636 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
637 "du_rgb666", "du"),
638 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
639 "du_sync_1", "du"),
640 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
641 "du_clk_out_0", "du"),
642 /* I2C2 */
643 PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790",
644 "i2c2", "i2c2"),
645 /* QSPI */
646 PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
647 "qspi_ctrl", "qspi"),
648 PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
649 "qspi_data4", "qspi"),
650 /* SCIF0 (CN19: DEBUG SERIAL0) */
651 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
652 "scif0_data", "scif0"),
653 /* SCIF1 (CN20: DEBUG SERIAL1) */
654 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
655 "scif1_data", "scif1"),
656 /* SDHI0 */
657 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
658 "sdhi0_data4", "sdhi0"),
659 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
660 "sdhi0_ctrl", "sdhi0"),
661 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
662 "sdhi0_cd", "sdhi0"),
663 /* SDHI2 */
664 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
665 "sdhi2_data4", "sdhi2"),
666 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
667 "sdhi2_ctrl", "sdhi2"),
668 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
669 "sdhi2_cd", "sdhi2"),
670 /* SSI (CN17: sound) */
671 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
672 "ssi0129_ctrl", "ssi"),
673 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
674 "ssi0_data", "ssi"),
675 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
676 "ssi1_data", "ssi"),
677 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
678 "audio_clk_a", "audio_clk"),
679 /* MMCIF1 */
680 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
681 "mmc1_data8", "mmc1"),
682 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
683 "mmc1_ctrl", "mmc1"),
684 /* Ether */
685 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
686 "eth_link", "eth"),
687 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
688 "eth_mdio", "eth"),
689 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
690 "eth_rmii", "eth"),
691 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
692 "intc_irq0", "intc"),
693 /* VIN0 */
694 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
695 "vin0_data24", "vin0"),
696 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
697 "vin0_sync", "vin0"),
698 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
699 "vin0_field", "vin0"),
700 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
701 "vin0_clkenb", "vin0"),
702 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
703 "vin0_clk", "vin0"),
704 /* VIN1 */
705 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
706 "vin1_data8", "vin1"),
707 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
708 "vin1_clk", "vin1"),
709 /* USB0 */
710 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790",
711 "usb0_ovc_vbus", "usb0"),
712 /* USB1 */
713 PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.1", "pfc-r8a7790",
714 "usb1", "usb1"),
715 /* USB2 */
716 PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.2", "pfc-r8a7790",
717 "usb2", "usb2"),
718};
719
720static void __init lager_add_standard_devices(void)
721{
722 int fixed_regulator_idx = 0;
723 int gpio_regulator_idx = 0;
724
725 r8a7790_clock_init();
726
727 pinctrl_register_mappings(lager_pinctrl_map,
728 ARRAY_SIZE(lager_pinctrl_map));
729 r8a7790_pinmux_init();
730
731 r8a7790_add_standard_devices();
732 platform_device_register_data(NULL, "leds-gpio", -1,
733 &lager_leds_pdata,
734 sizeof(lager_leds_pdata));
735 platform_device_register_data(NULL, "gpio-keys", -1,
736 &lager_keys_pdata,
737 sizeof(lager_keys_pdata));
738 regulator_register_always_on(fixed_regulator_idx++,
739 "fixed-3.3V", fixed3v3_power_consumers,
740 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
741 platform_device_register_resndata(NULL, "sh_mmcif", 1,
742 mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
743 &mmcif1_pdata, sizeof(mmcif1_pdata));
744
745 platform_device_register_full(&ether_info);
746
747 platform_device_register_resndata(NULL, "qspi", 0,
748 qspi_resources,
749 ARRAY_SIZE(qspi_resources),
750 &qspi_pdata, sizeof(qspi_pdata));
751 spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
752
753 platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++,
754 &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
755 platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++,
756 &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
757
758 platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++,
759 &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
760 platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++,
761 &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
762
763 lager_add_camera1_device();
764
765 platform_device_register_full(&sata1_info);
766
767 platform_device_register_resndata(NULL, "usb_phy_rcar_gen2",
768 -1, usbhs_phy_resources,
769 ARRAY_SIZE(usbhs_phy_resources),
770 &usbhs_phy_pdata,
771 sizeof(usbhs_phy_pdata));
772 lager_register_usbhs();
773 lager_add_usb1_device();
774 lager_add_usb2_device();
775
776 lager_add_rsnd_device();
777
778 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
779 sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
780 &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
781 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 2,
782 sdhi2_resources, ARRAY_SIZE(sdhi2_resources),
783 &sdhi2_info, sizeof(struct sh_mobile_sdhi_info));
784}
785
786/*
787 * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
788 * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
789 * 14-15. We have to set them back to 01 from the default 00 value each time
790 * the PHY is reset. It's also important because the PHY's LED0 signal is
791 * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
792 * bounce on and off after each packet, which we apparently want to avoid.
793 */
794static int lager_ksz8041_fixup(struct phy_device *phydev)
795{
796 u16 phyctrl1 = phy_read(phydev, 0x1e);
797
798 phyctrl1 &= ~0xc000;
799 phyctrl1 |= 0x4000;
800 return phy_write(phydev, 0x1e, phyctrl1);
801}
802
803static void __init lager_init(void)
804{
805 lager_add_standard_devices();
806
807 irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW);
808
809 if (IS_ENABLED(CONFIG_PHYLIB))
810 phy_register_fixup_for_id("r8a7790-ether-ff:01",
811 lager_ksz8041_fixup);
812}
813
814static const char * const lager_boards_compat_dt[] __initconst = {
815 "renesas,lager",
816 NULL,
817};
818
819DT_MACHINE_START(LAGER_DT, "lager")
820 .smp = smp_ops(r8a7790_smp_ops),
821 .init_early = shmobile_init_delay,
822 .init_time = rcar_gen2_timer_init,
823 .init_machine = lager_init,
824 .init_late = shmobile_init_late,
825 .reserve = rcar_gen2_reserve,
826 .dt_compat = lager_boards_compat_dt,
827MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
deleted file mode 100644
index f9bbc5f0a9a1..000000000000
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ /dev/null
@@ -1,459 +0,0 @@
1/*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/sh_clk.h>
20#include <linux/clkdev.h>
21
22#include "clock.h"
23#include "common.h"
24#include "r8a7790.h"
25#include "rcar-gen2.h"
26
27/*
28 * MD EXTAL PLL0 PLL1 PLL3
29 * 14 13 19 (MHz) *1 *1
30 *---------------------------------------------------
31 * 0 0 0 15 x 1 x172/2 x208/2 x106
32 * 0 0 1 15 x 1 x172/2 x208/2 x88
33 * 0 1 0 20 x 1 x130/2 x156/2 x80
34 * 0 1 1 20 x 1 x130/2 x156/2 x66
35 * 1 0 0 26 / 2 x200/2 x240/2 x122
36 * 1 0 1 26 / 2 x200/2 x240/2 x102
37 * 1 1 0 30 / 2 x172/2 x208/2 x106
38 * 1 1 1 30 / 2 x172/2 x208/2 x88
39 *
40 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
41 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
42 */
43
44#define CPG_BASE 0xe6150000
45#define CPG_LEN 0x1000
46
47#define SMSTPCR1 0xe6150134
48#define SMSTPCR2 0xe6150138
49#define SMSTPCR3 0xe615013c
50#define SMSTPCR5 0xe6150144
51#define SMSTPCR7 0xe615014c
52#define SMSTPCR8 0xe6150990
53#define SMSTPCR9 0xe6150994
54#define SMSTPCR10 0xe6150998
55
56#define MSTPSR1 IOMEM(0xe6150038)
57#define MSTPSR2 IOMEM(0xe6150040)
58#define MSTPSR3 IOMEM(0xe6150048)
59#define MSTPSR5 IOMEM(0xe615003c)
60#define MSTPSR7 IOMEM(0xe61501c4)
61#define MSTPSR8 IOMEM(0xe61509a0)
62#define MSTPSR9 IOMEM(0xe61509a4)
63#define MSTPSR10 IOMEM(0xe61509a8)
64
65#define SDCKCR 0xE6150074
66#define SD2CKCR 0xE6150078
67#define SD3CKCR 0xE615026C
68#define MMC0CKCR 0xE6150240
69#define MMC1CKCR 0xE6150244
70#define SSPCKCR 0xE6150248
71#define SSPRSCKCR 0xE615024C
72
73static struct clk_mapping cpg_mapping = {
74 .phys = CPG_BASE,
75 .len = CPG_LEN,
76};
77
78static struct clk extal_clk = {
79 /* .rate will be updated on r8a7790_clock_init() */
80 .mapping = &cpg_mapping,
81};
82
83static struct sh_clk_ops followparent_clk_ops = {
84 .recalc = followparent_recalc,
85};
86
87static struct clk main_clk = {
88 /* .parent will be set r8a7790_clock_init */
89 .ops = &followparent_clk_ops,
90};
91
92static struct clk audio_clk_a = {
93};
94
95static struct clk audio_clk_b = {
96};
97
98static struct clk audio_clk_c = {
99};
100
101/*
102 * clock ratio of these clock will be updated
103 * on r8a7790_clock_init()
104 */
105SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
106SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
107SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
108SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
109
110/* fixed ratio clock */
111SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
112SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
113
114SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
115SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
116SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
117SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
118SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
119SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
120SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
121SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
122SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
123SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
124SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
125SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
126SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
127
128SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
129SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
130SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
131SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
132
133static struct clk *main_clks[] = {
134 &audio_clk_a,
135 &audio_clk_b,
136 &audio_clk_c,
137 &extal_clk,
138 &extal_div2_clk,
139 &main_clk,
140 &pll1_clk,
141 &pll1_div2_clk,
142 &pll3_clk,
143 &lb_clk,
144 &qspi_clk,
145 &zg_clk,
146 &zx_clk,
147 &zs_clk,
148 &hp_clk,
149 &i_clk,
150 &b_clk,
151 &p_clk,
152 &cl_clk,
153 &m2_clk,
154 &imp_clk,
155 &rclk_clk,
156 &oscclk_clk,
157 &zb3_clk,
158 &zb3d2_clk,
159 &ddr_clk,
160 &mp_clk,
161 &cp_clk,
162};
163
164/* SDHI (DIV4) clock */
165static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
166
167static struct clk_div_mult_table div4_div_mult_table = {
168 .divisors = divisors,
169 .nr_divisors = ARRAY_SIZE(divisors),
170};
171
172static struct clk_div4_table div4_table = {
173 .div_mult_table = &div4_div_mult_table,
174};
175
176enum {
177 DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
178};
179
180static struct clk div4_clks[DIV4_NR] = {
181 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
182 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
183 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
184};
185
186/* DIV6 clocks */
187enum {
188 DIV6_SD2, DIV6_SD3,
189 DIV6_MMC0, DIV6_MMC1,
190 DIV6_SSP, DIV6_SSPRS,
191 DIV6_NR
192};
193
194static struct clk div6_clks[DIV6_NR] = {
195 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
196 [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
197 [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
198 [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
199 [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
200 [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
201};
202
203/* MSTP */
204enum {
205 MSTP1017, /* parent of SCU */
206
207 MSTP1031, MSTP1030,
208 MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
209 MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
210 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
211 MSTP931, MSTP930, MSTP929, MSTP928,
212 MSTP917,
213 MSTP815, MSTP814,
214 MSTP813,
215 MSTP811, MSTP810, MSTP809, MSTP808,
216 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
217 MSTP717, MSTP716,
218 MSTP704, MSTP703,
219 MSTP522,
220 MSTP502, MSTP501,
221 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
222 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
223 MSTP124,
224 MSTP_NR
225};
226
227static struct clk mstp_clks[MSTP_NR] = {
228 [MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
229 [MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
230 [MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
231 [MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
232 [MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
233 [MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
234 [MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
235 [MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
236 [MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
237 [MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
238 [MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
239 [MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
240 [MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
241 [MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
242 [MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
243 [MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
244 [MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
245 [MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
246 [MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
247 [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
248 [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
249 [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
250 [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
251 [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
252 [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
253 [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
254 [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
255 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
256 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
257 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
258 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
259 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
260 [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
261 [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
262 [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
263 [MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
264 [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
265 [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
266 [MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
267 [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
268 [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
269 [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
270 [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
271 [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
272 [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
273 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
274 [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
275 [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
276 [MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
277 [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
278 [MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
279 [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
280 [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
281 [MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
282 [MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
283 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
284 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
285 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
286 [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
287 [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
288 [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
289 [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
290};
291
292static struct clk_lookup lookups[] = {
293
294 /* main clocks */
295 CLKDEV_CON_ID("extal", &extal_clk),
296 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
297 CLKDEV_CON_ID("main", &main_clk),
298 CLKDEV_CON_ID("pll1", &pll1_clk),
299 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
300 CLKDEV_CON_ID("pll3", &pll3_clk),
301 CLKDEV_CON_ID("zg", &zg_clk),
302 CLKDEV_CON_ID("zx", &zx_clk),
303 CLKDEV_CON_ID("zs", &zs_clk),
304 CLKDEV_CON_ID("hp", &hp_clk),
305 CLKDEV_CON_ID("i", &i_clk),
306 CLKDEV_CON_ID("b", &b_clk),
307 CLKDEV_CON_ID("lb", &lb_clk),
308 CLKDEV_CON_ID("p", &p_clk),
309 CLKDEV_CON_ID("cl", &cl_clk),
310 CLKDEV_CON_ID("m2", &m2_clk),
311 CLKDEV_CON_ID("imp", &imp_clk),
312 CLKDEV_CON_ID("rclk", &rclk_clk),
313 CLKDEV_CON_ID("oscclk", &oscclk_clk),
314 CLKDEV_CON_ID("zb3", &zb3_clk),
315 CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
316 CLKDEV_CON_ID("ddr", &ddr_clk),
317 CLKDEV_CON_ID("mp", &mp_clk),
318 CLKDEV_CON_ID("qspi", &qspi_clk),
319 CLKDEV_CON_ID("cp", &cp_clk),
320
321 /* DIV4 */
322 CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
323
324 /* DIV6 */
325 CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
326 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
327
328 /* MSTP */
329 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
330 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
331 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
332 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
333 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
334 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
335 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
336 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
337 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
338 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
339 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
340 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
341 CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
342 CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
343 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
344 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
345 CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
346 CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
347 CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
348 CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
349 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
350 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
351 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
352 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
353 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
354 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
355 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
356 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
357 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
358 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
359 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
360 CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
361 CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
362 CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
363 CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
364 CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
365
366 /* ICK */
367 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
368 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
369 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
370 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
371 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
372 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
373 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
374 CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
375 CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
376 CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
377 CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
378 CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
379 CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
380 CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
381 CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
382 CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
383 CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
384 CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
385 CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
386 CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
387 CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
388 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
389 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
390 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
391 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
392 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
393 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
394 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
395 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
396 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
397 CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
398
399};
400
401#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
402 extal_clk.rate = e * 1000 * 1000; \
403 main_clk.parent = m; \
404 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
405 if (mode & MD(19)) \
406 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
407 else \
408 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
409
410
411void __init r8a7790_clock_init(void)
412{
413 u32 mode = rcar_gen2_read_mode_pins();
414 int k, ret = 0;
415
416 switch (mode & (MD(14) | MD(13))) {
417 case 0:
418 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
419 break;
420 case MD(13):
421 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
422 break;
423 case MD(14):
424 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
425 break;
426 case MD(13) | MD(14):
427 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
428 break;
429 }
430
431 if (mode & (MD(18)))
432 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
433 else
434 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
435
436 if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
437 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
438 else
439 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
440
441 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
442 ret = clk_register(main_clks[k]);
443
444 if (!ret)
445 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
446
447 if (!ret)
448 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
449
450 if (!ret)
451 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
452
453 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
454
455 if (!ret)
456 shmobile_clk_init();
457 else
458 panic("failed to setup r8a7790 clocks\n");
459}
diff --git a/arch/arm/mach-shmobile/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index 388f0514d931..bf73a850aaed 100644
--- a/arch/arm/mach-shmobile/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -1,34 +1,6 @@
1#ifndef __ASM_R8A7790_H__ 1#ifndef __ASM_R8A7790_H__
2#define __ASM_R8A7790_H__ 2#define __ASM_R8A7790_H__
3 3
4/* DMA slave IDs */
5enum {
6 RCAR_DMA_SLAVE_INVALID,
7 AUDIO_DMAC_SLAVE_SSI0_TX,
8 AUDIO_DMAC_SLAVE_SSI0_RX,
9 AUDIO_DMAC_SLAVE_SSI1_TX,
10 AUDIO_DMAC_SLAVE_SSI1_RX,
11 AUDIO_DMAC_SLAVE_SSI2_TX,
12 AUDIO_DMAC_SLAVE_SSI2_RX,
13 AUDIO_DMAC_SLAVE_SSI3_TX,
14 AUDIO_DMAC_SLAVE_SSI3_RX,
15 AUDIO_DMAC_SLAVE_SSI4_TX,
16 AUDIO_DMAC_SLAVE_SSI4_RX,
17 AUDIO_DMAC_SLAVE_SSI5_TX,
18 AUDIO_DMAC_SLAVE_SSI5_RX,
19 AUDIO_DMAC_SLAVE_SSI6_TX,
20 AUDIO_DMAC_SLAVE_SSI6_RX,
21 AUDIO_DMAC_SLAVE_SSI7_TX,
22 AUDIO_DMAC_SLAVE_SSI7_RX,
23 AUDIO_DMAC_SLAVE_SSI8_TX,
24 AUDIO_DMAC_SLAVE_SSI8_RX,
25 AUDIO_DMAC_SLAVE_SSI9_TX,
26 AUDIO_DMAC_SLAVE_SSI9_RX,
27};
28
29void r8a7790_add_standard_devices(void);
30void r8a7790_clock_init(void);
31void r8a7790_pinmux_init(void);
32void r8a7790_pm_init(void); 4void r8a7790_pm_init(void);
33extern struct smp_operations r8a7790_smp_ops; 5extern struct smp_operations r8a7790_smp_ops;
34 6
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index ec7d97dca4de..3a18af4922b4 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -14,295 +14,14 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <linux/irq.h> 17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/gpio-rcar.h>
21#include <linux/platform_data/irq-renesas-irqc.h>
22#include <linux/serial_sci.h>
23#include <linux/sh_dma.h>
24#include <linux/sh_timer.h>
25 18
26#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
27 20
28#include "common.h" 21#include "common.h"
29#include "dma-register.h"
30#include "irqs.h"
31#include "r8a7790.h" 22#include "r8a7790.h"
32#include "rcar-gen2.h" 23#include "rcar-gen2.h"
33 24
34/* Audio-DMAC */
35#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
36{ \
37 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
38 .addr = _addr + 0x8, \
39 .chcr = CHCR_TX(XMIT_SZ_32BIT), \
40 .mid_rid = t, \
41}, { \
42 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
43 .addr = _addr + 0xc, \
44 .chcr = CHCR_RX(XMIT_SZ_32BIT), \
45 .mid_rid = r, \
46}
47
48static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
49 AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
50 AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
51 AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
52 AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
53 AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
54 AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
55 AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
56 AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
57 AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
58 AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
59};
60
61#define DMAE_CHANNEL(a, b) \
62{ \
63 .offset = (a) - 0x20, \
64 .dmars = (a) - 0x20 + 0x40, \
65 .chclr_bit = (b), \
66 .chclr_offset = 0x80 - 0x20, \
67}
68
69static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
70 DMAE_CHANNEL(0x8000, 0),
71 DMAE_CHANNEL(0x8080, 1),
72 DMAE_CHANNEL(0x8100, 2),
73 DMAE_CHANNEL(0x8180, 3),
74 DMAE_CHANNEL(0x8200, 4),
75 DMAE_CHANNEL(0x8280, 5),
76 DMAE_CHANNEL(0x8300, 6),
77 DMAE_CHANNEL(0x8380, 7),
78 DMAE_CHANNEL(0x8400, 8),
79 DMAE_CHANNEL(0x8480, 9),
80 DMAE_CHANNEL(0x8500, 10),
81 DMAE_CHANNEL(0x8580, 11),
82 DMAE_CHANNEL(0x8600, 12),
83};
84
85static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
86 .slave = r8a7790_audio_dmac_slaves,
87 .slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
88 .channel = r8a7790_audio_dmac_channels,
89 .channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
90 .ts_low_shift = TS_LOW_SHIFT,
91 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
92 .ts_high_shift = TS_HI_SHIFT,
93 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
94 .ts_shift = dma_ts_shift,
95 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
96 .dmaor_init = DMAOR_DME,
97 .chclr_present = 1,
98 .chclr_bitwise = 1,
99};
100
101static struct resource r8a7790_audio_dmac_resources[] = {
102 /* Channel registers and DMAOR for low */
103 DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
104 DEFINE_RES_IRQ(gic_spi(346)),
105 DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
106
107 /* Channel registers and DMAOR for hi */
108 DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
109 DEFINE_RES_IRQ(gic_spi(347)),
110 DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
111};
112
113#define r8a7790_register_audio_dmac(id) \
114 platform_device_register_resndata( \
115 NULL, "sh-dma-engine", id, \
116 &r8a7790_audio_dmac_resources[id * 3], 3, \
117 &r8a7790_audio_dmac_platform_data, \
118 sizeof(r8a7790_audio_dmac_platform_data))
119
120static const struct resource pfc_resources[] __initconst = {
121 DEFINE_RES_MEM(0xe6060000, 0x250),
122};
123
124#define r8a7790_register_pfc() \
125 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
126 ARRAY_SIZE(pfc_resources))
127
128#define R8A7790_GPIO(idx) \
129static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
130 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
131 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
132}; \
133 \
134static const struct gpio_rcar_config \
135r8a7790_gpio##idx##_platform_data __initconst = { \
136 .gpio_base = 32 * (idx), \
137 .irq_base = 0, \
138 .number_of_pins = 32, \
139 .pctl_name = "pfc-r8a7790", \
140 .has_both_edge_trigger = 1, \
141}; \
142
143R8A7790_GPIO(0);
144R8A7790_GPIO(1);
145R8A7790_GPIO(2);
146R8A7790_GPIO(3);
147R8A7790_GPIO(4);
148R8A7790_GPIO(5);
149
150#define r8a7790_register_gpio(idx) \
151 platform_device_register_resndata(NULL, "gpio_rcar", idx, \
152 r8a7790_gpio##idx##_resources, \
153 ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
154 &r8a7790_gpio##idx##_platform_data, \
155 sizeof(r8a7790_gpio##idx##_platform_data))
156
157static struct resource i2c_resources[] __initdata = {
158 /* I2C0 */
159 DEFINE_RES_MEM(0xE6508000, 0x40),
160 DEFINE_RES_IRQ(gic_spi(287)),
161 /* I2C1 */
162 DEFINE_RES_MEM(0xE6518000, 0x40),
163 DEFINE_RES_IRQ(gic_spi(288)),
164 /* I2C2 */
165 DEFINE_RES_MEM(0xE6530000, 0x40),
166 DEFINE_RES_IRQ(gic_spi(286)),
167 /* I2C3 */
168 DEFINE_RES_MEM(0xE6540000, 0x40),
169 DEFINE_RES_IRQ(gic_spi(290)),
170
171};
172
173#define r8a7790_register_i2c(idx) \
174 platform_device_register_simple( \
175 "i2c-rcar_gen2", idx, \
176 i2c_resources + (2 * idx), 2); \
177
178void __init r8a7790_pinmux_init(void)
179{
180 r8a7790_register_pfc();
181 r8a7790_register_gpio(0);
182 r8a7790_register_gpio(1);
183 r8a7790_register_gpio(2);
184 r8a7790_register_gpio(3);
185 r8a7790_register_gpio(4);
186 r8a7790_register_gpio(5);
187}
188
189#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
190static struct plat_sci_port scif##index##_platform_data = { \
191 .type = scif_type, \
192 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
193 .scscr = _scscr, \
194}; \
195 \
196static struct resource scif##index##_resources[] = { \
197 DEFINE_RES_MEM(baseaddr, 0x100), \
198 DEFINE_RES_IRQ(irq), \
199}
200
201#define R8A7790_SCIF(index, baseaddr, irq) \
202 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
203 index, baseaddr, irq)
204
205#define R8A7790_SCIFA(index, baseaddr, irq) \
206 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
207 index, baseaddr, irq)
208
209#define R8A7790_SCIFB(index, baseaddr, irq) \
210 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
211 index, baseaddr, irq)
212
213#define R8A7790_HSCIF(index, baseaddr, irq) \
214 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
215 index, baseaddr, irq)
216
217R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
218R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
219R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
220R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
221R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
222R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
223R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
224R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
225R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
226R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
227
228#define r8a7790_register_scif(index) \
229 platform_device_register_resndata(NULL, "sh-sci", index, \
230 scif##index##_resources, \
231 ARRAY_SIZE(scif##index##_resources), \
232 &scif##index##_platform_data, \
233 sizeof(scif##index##_platform_data))
234
235static const struct renesas_irqc_config irqc0_data __initconst = {
236 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
237};
238
239static const struct resource irqc0_resources[] __initconst = {
240 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
241 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
242 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
243 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
244 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
245};
246
247#define r8a7790_register_irqc(idx) \
248 platform_device_register_resndata(NULL, "renesas_irqc", \
249 idx, irqc##idx##_resources, \
250 ARRAY_SIZE(irqc##idx##_resources), \
251 &irqc##idx##_data, \
252 sizeof(struct renesas_irqc_config))
253
254static const struct resource thermal_resources[] __initconst = {
255 DEFINE_RES_MEM(0xe61f0000, 0x14),
256 DEFINE_RES_MEM(0xe61f0100, 0x38),
257 DEFINE_RES_IRQ(gic_spi(69)),
258};
259
260#define r8a7790_register_thermal() \
261 platform_device_register_simple("rcar_thermal", -1, \
262 thermal_resources, \
263 ARRAY_SIZE(thermal_resources))
264
265static struct sh_timer_config cmt0_platform_data = {
266 .channels_mask = 0x60,
267};
268
269static struct resource cmt0_resources[] = {
270 DEFINE_RES_MEM(0xffca0000, 0x1004),
271 DEFINE_RES_IRQ(gic_spi(142)),
272};
273
274#define r8a7790_register_cmt(idx) \
275 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
276 idx, cmt##idx##_resources, \
277 ARRAY_SIZE(cmt##idx##_resources), \
278 &cmt##idx##_platform_data, \
279 sizeof(struct sh_timer_config))
280
281void __init r8a7790_add_standard_devices(void)
282{
283 r8a7790_register_scif(0);
284 r8a7790_register_scif(1);
285 r8a7790_register_scif(2);
286 r8a7790_register_scif(3);
287 r8a7790_register_scif(4);
288 r8a7790_register_scif(5);
289 r8a7790_register_scif(6);
290 r8a7790_register_scif(7);
291 r8a7790_register_scif(8);
292 r8a7790_register_scif(9);
293 r8a7790_register_cmt(0);
294 r8a7790_register_irqc(0);
295 r8a7790_register_thermal();
296 r8a7790_register_i2c(0);
297 r8a7790_register_i2c(1);
298 r8a7790_register_i2c(2);
299 r8a7790_register_i2c(3);
300 r8a7790_register_audio_dmac(0);
301 r8a7790_register_audio_dmac(1);
302}
303
304#ifdef CONFIG_USE_OF
305
306static const char * const r8a7790_boards_compat_dt[] __initconst = { 25static const char * const r8a7790_boards_compat_dt[] __initconst = {
307 "renesas,r8a7790", 26 "renesas,r8a7790",
308 NULL, 27 NULL,
@@ -316,4 +35,3 @@ DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
316 .reserve = rcar_gen2_reserve, 35 .reserve = rcar_gen2_reserve,
317 .dt_compat = r8a7790_boards_compat_dt, 36 .dt_compat = r8a7790_boards_compat_dt,
318MACHINE_END 37MACHINE_END
319#endif /* CONFIG_USE_OF */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-17 04:08:35 -0400