diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-09-07 16:59:49 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-09-07 16:59:49 -0400 |
| commit | 6300d6d755842f2ed18053ed6f868944d51b5aef (patch) | |
| tree | 07cc64945858e12855c1c23c6ba213230d4f4988 | |
| parent | e6ba59bcae6968ee18ef5a237a8020a0ea331ae1 (diff) | |
| parent | c7ef35a960369bcad733b92868e4befe03ba9234 (diff) | |
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm: Do not force 1024x768 modes on unknown connectors
drm/kms: Add a module parameter to disable polling
drm/radeon/kms: fix tv-out on avivo asics
drm/radeon/kms/evergreen: fix gpu hangs in userspace accel code
drm/nv50: initialize ramht_refs list for faked 0 channel
drm/nouveau: Don't take struct_mutex around the pushbuf IOCTL.
drm/nouveau: Take fence spinlock before reading the last sequence.
drm/radeon/kms/evergreen: work around bad data in some i2c tables
drm/radeon/kms: properly set crtc high base on r7xx
drm/radeon/kms: fix tv module parameter
drm/radeon/kms: force legacy pll algo for RV515 LVDS
drm/radeon/kms: remove useless clock code
drm/radeon/kms: fix a regression on r7xx AGP due to the HDP flush fix
drm/radeon/kms: use tracked values for sclk and mclk
| -rw-r--r-- | drivers/gpu/drm/drm_crtc_helper.c | 24 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_fence.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_gem.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv50_instmem.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 48 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 48 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 18 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_atombios.c | 27 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_clocks.c | 58 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_connectors.c | 78 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 28 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_i2c.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 61 |
16 files changed, 253 insertions, 179 deletions
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 7e31d4348340..d2ab01e90a96 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c | |||
| @@ -34,6 +34,9 @@ | |||
| 34 | #include "drm_crtc_helper.h" | 34 | #include "drm_crtc_helper.h" |
| 35 | #include "drm_fb_helper.h" | 35 | #include "drm_fb_helper.h" |
| 36 | 36 | ||
| 37 | static bool drm_kms_helper_poll = true; | ||
| 38 | module_param_named(poll, drm_kms_helper_poll, bool, 0600); | ||
| 39 | |||
| 37 | static void drm_mode_validate_flag(struct drm_connector *connector, | 40 | static void drm_mode_validate_flag(struct drm_connector *connector, |
| 38 | int flags) | 41 | int flags) |
| 39 | { | 42 | { |
| @@ -99,8 +102,10 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, | |||
| 99 | connector->status = connector_status_disconnected; | 102 | connector->status = connector_status_disconnected; |
| 100 | if (connector->funcs->force) | 103 | if (connector->funcs->force) |
| 101 | connector->funcs->force(connector); | 104 | connector->funcs->force(connector); |
| 102 | } else | 105 | } else { |
| 103 | connector->status = connector->funcs->detect(connector); | 106 | connector->status = connector->funcs->detect(connector); |
| 107 | drm_helper_hpd_irq_event(dev); | ||
| 108 | } | ||
| 104 | 109 | ||
| 105 | if (connector->status == connector_status_disconnected) { | 110 | if (connector->status == connector_status_disconnected) { |
| 106 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] disconnected\n", | 111 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] disconnected\n", |
| @@ -110,11 +115,10 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, | |||
| 110 | } | 115 | } |
| 111 | 116 | ||
| 112 | count = (*connector_funcs->get_modes)(connector); | 117 | count = (*connector_funcs->get_modes)(connector); |
| 113 | if (!count) { | 118 | if (count == 0 && connector->status == connector_status_connected) |
| 114 | count = drm_add_modes_noedid(connector, 1024, 768); | 119 | count = drm_add_modes_noedid(connector, 1024, 768); |
| 115 | if (!count) | 120 | if (count == 0) |
| 116 | return 0; | 121 | goto prune; |
| 117 | } | ||
| 118 | 122 | ||
| 119 | drm_mode_connector_list_update(connector); | 123 | drm_mode_connector_list_update(connector); |
| 120 | 124 | ||
| @@ -840,6 +844,9 @@ static void output_poll_execute(struct work_struct *work) | |||
| 840 | enum drm_connector_status old_status, status; | 844 | enum drm_connector_status old_status, status; |
| 841 | bool repoll = false, changed = false; | 845 | bool repoll = false, changed = false; |
| 842 | 846 | ||
| 847 | if (!drm_kms_helper_poll) | ||
| 848 | return; | ||
| 849 | |||
| 843 | mutex_lock(&dev->mode_config.mutex); | 850 | mutex_lock(&dev->mode_config.mutex); |
| 844 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | 851 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 845 | 852 | ||
| @@ -890,6 +897,9 @@ void drm_kms_helper_poll_enable(struct drm_device *dev) | |||
| 890 | bool poll = false; | 897 | bool poll = false; |
| 891 | struct drm_connector *connector; | 898 | struct drm_connector *connector; |
| 892 | 899 | ||
| 900 | if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll) | ||
| 901 | return; | ||
| 902 | |||
| 893 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | 903 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 894 | if (connector->polled) | 904 | if (connector->polled) |
| 895 | poll = true; | 905 | poll = true; |
| @@ -919,8 +929,10 @@ void drm_helper_hpd_irq_event(struct drm_device *dev) | |||
| 919 | { | 929 | { |
| 920 | if (!dev->mode_config.poll_enabled) | 930 | if (!dev->mode_config.poll_enabled) |
| 921 | return; | 931 | return; |
| 932 | |||
| 922 | /* kill timer and schedule immediate execution, this doesn't block */ | 933 | /* kill timer and schedule immediate execution, this doesn't block */ |
| 923 | cancel_delayed_work(&dev->mode_config.output_poll_work); | 934 | cancel_delayed_work(&dev->mode_config.output_poll_work); |
| 924 | queue_delayed_work(system_nrt_wq, &dev->mode_config.output_poll_work, 0); | 935 | if (drm_kms_helper_poll) |
| 936 | queue_delayed_work(system_nrt_wq, &dev->mode_config.output_poll_work, 0); | ||
| 925 | } | 937 | } |
| 926 | EXPORT_SYMBOL(drm_helper_hpd_irq_event); | 938 | EXPORT_SYMBOL(drm_helper_hpd_irq_event); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 6b208ffafa8d..87ac21ec23d2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c | |||
| @@ -64,16 +64,17 @@ nouveau_fence_update(struct nouveau_channel *chan) | |||
| 64 | struct nouveau_fence *fence; | 64 | struct nouveau_fence *fence; |
| 65 | uint32_t sequence; | 65 | uint32_t sequence; |
| 66 | 66 | ||
| 67 | spin_lock(&chan->fence.lock); | ||
| 68 | |||
| 67 | if (USE_REFCNT) | 69 | if (USE_REFCNT) |
| 68 | sequence = nvchan_rd32(chan, 0x48); | 70 | sequence = nvchan_rd32(chan, 0x48); |
| 69 | else | 71 | else |
| 70 | sequence = atomic_read(&chan->fence.last_sequence_irq); | 72 | sequence = atomic_read(&chan->fence.last_sequence_irq); |
| 71 | 73 | ||
| 72 | if (chan->fence.sequence_ack == sequence) | 74 | if (chan->fence.sequence_ack == sequence) |
| 73 | return; | 75 | goto out; |
| 74 | chan->fence.sequence_ack = sequence; | 76 | chan->fence.sequence_ack = sequence; |
| 75 | 77 | ||
| 76 | spin_lock(&chan->fence.lock); | ||
| 77 | list_for_each_safe(entry, tmp, &chan->fence.pending) { | 78 | list_for_each_safe(entry, tmp, &chan->fence.pending) { |
| 78 | fence = list_entry(entry, struct nouveau_fence, entry); | 79 | fence = list_entry(entry, struct nouveau_fence, entry); |
| 79 | 80 | ||
| @@ -85,6 +86,7 @@ nouveau_fence_update(struct nouveau_channel *chan) | |||
| 85 | if (sequence == chan->fence.sequence_ack) | 86 | if (sequence == chan->fence.sequence_ack) |
| 86 | break; | 87 | break; |
| 87 | } | 88 | } |
| 89 | out: | ||
| 88 | spin_unlock(&chan->fence.lock); | 90 | spin_unlock(&chan->fence.lock); |
| 89 | } | 91 | } |
| 90 | 92 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 581c67cd7b24..ead7b8fc53fc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c | |||
| @@ -245,7 +245,7 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence) | |||
| 245 | list_del(&nvbo->entry); | 245 | list_del(&nvbo->entry); |
| 246 | nvbo->reserved_by = NULL; | 246 | nvbo->reserved_by = NULL; |
| 247 | ttm_bo_unreserve(&nvbo->bo); | 247 | ttm_bo_unreserve(&nvbo->bo); |
| 248 | drm_gem_object_unreference(nvbo->gem); | 248 | drm_gem_object_unreference_unlocked(nvbo->gem); |
| 249 | } | 249 | } |
| 250 | } | 250 | } |
| 251 | 251 | ||
| @@ -300,7 +300,7 @@ retry: | |||
| 300 | validate_fini(op, NULL); | 300 | validate_fini(op, NULL); |
| 301 | if (ret == -EAGAIN) | 301 | if (ret == -EAGAIN) |
| 302 | ret = ttm_bo_wait_unreserved(&nvbo->bo, false); | 302 | ret = ttm_bo_wait_unreserved(&nvbo->bo, false); |
| 303 | drm_gem_object_unreference(gem); | 303 | drm_gem_object_unreference_unlocked(gem); |
| 304 | if (ret) { | 304 | if (ret) { |
| 305 | NV_ERROR(dev, "fail reserve\n"); | 305 | NV_ERROR(dev, "fail reserve\n"); |
| 306 | return ret; | 306 | return ret; |
| @@ -616,8 +616,6 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, | |||
| 616 | return PTR_ERR(bo); | 616 | return PTR_ERR(bo); |
| 617 | } | 617 | } |
| 618 | 618 | ||
| 619 | mutex_lock(&dev->struct_mutex); | ||
| 620 | |||
| 621 | /* Mark push buffers as being used on PFIFO, the validation code | 619 | /* Mark push buffers as being used on PFIFO, the validation code |
| 622 | * will then make sure that if the pushbuf bo moves, that they | 620 | * will then make sure that if the pushbuf bo moves, that they |
| 623 | * happen on the kernel channel, which will in turn cause a sync | 621 | * happen on the kernel channel, which will in turn cause a sync |
| @@ -731,7 +729,6 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, | |||
| 731 | out: | 729 | out: |
| 732 | validate_fini(&op, fence); | 730 | validate_fini(&op, fence); |
| 733 | nouveau_fence_unref((void**)&fence); | 731 | nouveau_fence_unref((void**)&fence); |
| 734 | mutex_unlock(&dev->struct_mutex); | ||
| 735 | kfree(bo); | 732 | kfree(bo); |
| 736 | kfree(push); | 733 | kfree(push); |
| 737 | 734 | ||
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c index c95bf9b681dd..91ef93cf1f35 100644 --- a/drivers/gpu/drm/nouveau/nv50_instmem.c +++ b/drivers/gpu/drm/nouveau/nv50_instmem.c | |||
| @@ -139,6 +139,8 @@ nv50_instmem_init(struct drm_device *dev) | |||
| 139 | chan->file_priv = (struct drm_file *)-2; | 139 | chan->file_priv = (struct drm_file *)-2; |
| 140 | dev_priv->fifos[0] = dev_priv->fifos[127] = chan; | 140 | dev_priv->fifos[0] = dev_priv->fifos[127] = chan; |
| 141 | 141 | ||
| 142 | INIT_LIST_HEAD(&chan->ramht_refs); | ||
| 143 | |||
| 142 | /* Channel's PRAMIN object + heap */ | 144 | /* Channel's PRAMIN object + heap */ |
| 143 | ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0, | 145 | ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0, |
| 144 | NULL, &chan->ramin); | 146 | NULL, &chan->ramin); |
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 577239a24fd5..464a81a1990f 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
| @@ -332,6 +332,11 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc, | |||
| 332 | args.usV_SyncWidth = | 332 | args.usV_SyncWidth = |
| 333 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); | 333 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
| 334 | 334 | ||
| 335 | args.ucOverscanRight = radeon_crtc->h_border; | ||
| 336 | args.ucOverscanLeft = radeon_crtc->h_border; | ||
| 337 | args.ucOverscanBottom = radeon_crtc->v_border; | ||
| 338 | args.ucOverscanTop = radeon_crtc->v_border; | ||
| 339 | |||
| 335 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | 340 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 336 | misc |= ATOM_VSYNC_POLARITY; | 341 | misc |= ATOM_VSYNC_POLARITY; |
| 337 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | 342 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| @@ -534,6 +539,20 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
| 534 | pll->algo = PLL_ALGO_LEGACY; | 539 | pll->algo = PLL_ALGO_LEGACY; |
| 535 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; | 540 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
| 536 | } | 541 | } |
| 542 | /* There is some evidence (often anecdotal) that RV515 LVDS | ||
| 543 | * (on some boards at least) prefers the legacy algo. I'm not | ||
| 544 | * sure whether this should handled generically or on a | ||
| 545 | * case-by-case quirk basis. Both algos should work fine in the | ||
| 546 | * majority of cases. | ||
| 547 | */ | ||
| 548 | if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) && | ||
| 549 | (rdev->family == CHIP_RV515)) { | ||
| 550 | /* allow the user to overrride just in case */ | ||
| 551 | if (radeon_new_pll == 1) | ||
| 552 | pll->algo = PLL_ALGO_NEW; | ||
| 553 | else | ||
| 554 | pll->algo = PLL_ALGO_LEGACY; | ||
| 555 | } | ||
| 537 | } else { | 556 | } else { |
| 538 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) | 557 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
| 539 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; | 558 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
| @@ -1056,11 +1075,11 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
| 1056 | 1075 | ||
| 1057 | if (rdev->family >= CHIP_RV770) { | 1076 | if (rdev->family >= CHIP_RV770) { |
| 1058 | if (radeon_crtc->crtc_id) { | 1077 | if (radeon_crtc->crtc_id) { |
| 1059 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); | 1078 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1060 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); | 1079 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1061 | } else { | 1080 | } else { |
| 1062 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); | 1081 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1063 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); | 1082 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1064 | } | 1083 | } |
| 1065 | } | 1084 | } |
| 1066 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | 1085 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| @@ -1197,8 +1216,18 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, | |||
| 1197 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 1216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1198 | struct drm_device *dev = crtc->dev; | 1217 | struct drm_device *dev = crtc->dev; |
| 1199 | struct radeon_device *rdev = dev->dev_private; | 1218 | struct radeon_device *rdev = dev->dev_private; |
| 1219 | struct drm_encoder *encoder; | ||
| 1220 | bool is_tvcv = false; | ||
| 1200 | 1221 | ||
| 1201 | /* TODO color tiling */ | 1222 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1223 | /* find tv std */ | ||
| 1224 | if (encoder->crtc == crtc) { | ||
| 1225 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
| 1226 | if (radeon_encoder->active_device & | ||
| 1227 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | ||
| 1228 | is_tvcv = true; | ||
| 1229 | } | ||
| 1230 | } | ||
| 1202 | 1231 | ||
| 1203 | atombios_disable_ss(crtc); | 1232 | atombios_disable_ss(crtc); |
| 1204 | /* always set DCPLL */ | 1233 | /* always set DCPLL */ |
| @@ -1207,9 +1236,14 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, | |||
| 1207 | atombios_crtc_set_pll(crtc, adjusted_mode); | 1236 | atombios_crtc_set_pll(crtc, adjusted_mode); |
| 1208 | atombios_enable_ss(crtc); | 1237 | atombios_enable_ss(crtc); |
| 1209 | 1238 | ||
| 1210 | if (ASIC_IS_AVIVO(rdev)) | 1239 | if (ASIC_IS_DCE4(rdev)) |
| 1211 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | 1240 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
| 1212 | else { | 1241 | else if (ASIC_IS_AVIVO(rdev)) { |
| 1242 | if (is_tvcv) | ||
| 1243 | atombios_crtc_set_timing(crtc, adjusted_mode); | ||
| 1244 | else | ||
| 1245 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | ||
| 1246 | } else { | ||
| 1213 | atombios_crtc_set_timing(crtc, adjusted_mode); | 1247 | atombios_crtc_set_timing(crtc, adjusted_mode); |
| 1214 | if (radeon_crtc->crtc_id == 0) | 1248 | if (radeon_crtc->crtc_id == 0) |
| 1215 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | 1249 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 957d5067ad9c..b8b7f010b25f 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
| @@ -675,6 +675,43 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev) | |||
| 675 | return 0; | 675 | return 0; |
| 676 | } | 676 | } |
| 677 | 677 | ||
| 678 | static int evergreen_cp_start(struct radeon_device *rdev) | ||
| 679 | { | ||
| 680 | int r; | ||
| 681 | uint32_t cp_me; | ||
| 682 | |||
| 683 | r = radeon_ring_lock(rdev, 7); | ||
| 684 | if (r) { | ||
| 685 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | ||
| 686 | return r; | ||
| 687 | } | ||
| 688 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | ||
| 689 | radeon_ring_write(rdev, 0x1); | ||
| 690 | radeon_ring_write(rdev, 0x0); | ||
| 691 | radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); | ||
| 692 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | ||
| 693 | radeon_ring_write(rdev, 0); | ||
| 694 | radeon_ring_write(rdev, 0); | ||
| 695 | radeon_ring_unlock_commit(rdev); | ||
| 696 | |||
| 697 | cp_me = 0xff; | ||
| 698 | WREG32(CP_ME_CNTL, cp_me); | ||
| 699 | |||
| 700 | r = radeon_ring_lock(rdev, 4); | ||
| 701 | if (r) { | ||
| 702 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | ||
| 703 | return r; | ||
| 704 | } | ||
| 705 | /* init some VGT regs */ | ||
| 706 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | ||
| 707 | radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2); | ||
| 708 | radeon_ring_write(rdev, 0xe); | ||
| 709 | radeon_ring_write(rdev, 0x10); | ||
| 710 | radeon_ring_unlock_commit(rdev); | ||
| 711 | |||
| 712 | return 0; | ||
| 713 | } | ||
| 714 | |||
| 678 | int evergreen_cp_resume(struct radeon_device *rdev) | 715 | int evergreen_cp_resume(struct radeon_device *rdev) |
| 679 | { | 716 | { |
| 680 | u32 tmp; | 717 | u32 tmp; |
| @@ -719,7 +756,7 @@ int evergreen_cp_resume(struct radeon_device *rdev) | |||
| 719 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | 756 | rdev->cp.rptr = RREG32(CP_RB_RPTR); |
| 720 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | 757 | rdev->cp.wptr = RREG32(CP_RB_WPTR); |
| 721 | 758 | ||
| 722 | r600_cp_start(rdev); | 759 | evergreen_cp_start(rdev); |
| 723 | rdev->cp.ready = true; | 760 | rdev->cp.ready = true; |
| 724 | r = radeon_ring_test(rdev); | 761 | r = radeon_ring_test(rdev); |
| 725 | if (r) { | 762 | if (r) { |
| @@ -2054,11 +2091,6 @@ int evergreen_resume(struct radeon_device *rdev) | |||
| 2054 | */ | 2091 | */ |
| 2055 | /* post card */ | 2092 | /* post card */ |
| 2056 | atom_asic_init(rdev->mode_info.atom_context); | 2093 | atom_asic_init(rdev->mode_info.atom_context); |
| 2057 | /* Initialize clocks */ | ||
| 2058 | r = radeon_clocks_init(rdev); | ||
| 2059 | if (r) { | ||
| 2060 | return r; | ||
| 2061 | } | ||
| 2062 | 2094 | ||
| 2063 | r = evergreen_startup(rdev); | 2095 | r = evergreen_startup(rdev); |
| 2064 | if (r) { | 2096 | if (r) { |
| @@ -2164,9 +2196,6 @@ int evergreen_init(struct radeon_device *rdev) | |||
| 2164 | radeon_surface_init(rdev); | 2196 | radeon_surface_init(rdev); |
| 2165 | /* Initialize clocks */ | 2197 | /* Initialize clocks */ |
| 2166 | radeon_get_clock_info(rdev->ddev); | 2198 | radeon_get_clock_info(rdev->ddev); |
| 2167 | r = radeon_clocks_init(rdev); | ||
| 2168 | if (r) | ||
| 2169 | return r; | ||
| 2170 | /* Fence driver */ | 2199 | /* Fence driver */ |
| 2171 | r = radeon_fence_driver_init(rdev); | 2200 | r = radeon_fence_driver_init(rdev); |
| 2172 | if (r) | 2201 | if (r) |
| @@ -2236,7 +2265,6 @@ void evergreen_fini(struct radeon_device *rdev) | |||
| 2236 | evergreen_pcie_gart_fini(rdev); | 2265 | evergreen_pcie_gart_fini(rdev); |
| 2237 | radeon_gem_fini(rdev); | 2266 | radeon_gem_fini(rdev); |
| 2238 | radeon_fence_driver_fini(rdev); | 2267 | radeon_fence_driver_fini(rdev); |
| 2239 | radeon_clocks_fini(rdev); | ||
| 2240 | radeon_agp_fini(rdev); | 2268 | radeon_agp_fini(rdev); |
| 2241 | radeon_bo_fini(rdev); | 2269 | radeon_bo_fini(rdev); |
| 2242 | radeon_atombios_fini(rdev); | 2270 | radeon_atombios_fini(rdev); |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index d0ebae9dde25..afc18d87fdca 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
| @@ -2119,10 +2119,7 @@ int r600_cp_start(struct radeon_device *rdev) | |||
| 2119 | } | 2119 | } |
| 2120 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | 2120 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
| 2121 | radeon_ring_write(rdev, 0x1); | 2121 | radeon_ring_write(rdev, 0x1); |
| 2122 | if (rdev->family >= CHIP_CEDAR) { | 2122 | if (rdev->family >= CHIP_RV770) { |
| 2123 | radeon_ring_write(rdev, 0x0); | ||
| 2124 | radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); | ||
| 2125 | } else if (rdev->family >= CHIP_RV770) { | ||
| 2126 | radeon_ring_write(rdev, 0x0); | 2123 | radeon_ring_write(rdev, 0x0); |
| 2127 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); | 2124 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); |
| 2128 | } else { | 2125 | } else { |
| @@ -2489,11 +2486,6 @@ int r600_resume(struct radeon_device *rdev) | |||
| 2489 | */ | 2486 | */ |
| 2490 | /* post card */ | 2487 | /* post card */ |
| 2491 | atom_asic_init(rdev->mode_info.atom_context); | 2488 | atom_asic_init(rdev->mode_info.atom_context); |
| 2492 | /* Initialize clocks */ | ||
| 2493 | r = radeon_clocks_init(rdev); | ||
| 2494 | if (r) { | ||
| 2495 | return r; | ||
| 2496 | } | ||
| 2497 | 2489 | ||
| 2498 | r = r600_startup(rdev); | 2490 | r = r600_startup(rdev); |
| 2499 | if (r) { | 2491 | if (r) { |
| @@ -2586,9 +2578,6 @@ int r600_init(struct radeon_device *rdev) | |||
| 2586 | radeon_surface_init(rdev); | 2578 | radeon_surface_init(rdev); |
| 2587 | /* Initialize clocks */ | 2579 | /* Initialize clocks */ |
| 2588 | radeon_get_clock_info(rdev->ddev); | 2580 | radeon_get_clock_info(rdev->ddev); |
| 2589 | r = radeon_clocks_init(rdev); | ||
| 2590 | if (r) | ||
| 2591 | return r; | ||
| 2592 | /* Fence driver */ | 2581 | /* Fence driver */ |
| 2593 | r = radeon_fence_driver_init(rdev); | 2582 | r = radeon_fence_driver_init(rdev); |
| 2594 | if (r) | 2583 | if (r) |
| @@ -2663,7 +2652,6 @@ void r600_fini(struct radeon_device *rdev) | |||
| 2663 | radeon_agp_fini(rdev); | 2652 | radeon_agp_fini(rdev); |
| 2664 | radeon_gem_fini(rdev); | 2653 | radeon_gem_fini(rdev); |
| 2665 | radeon_fence_driver_fini(rdev); | 2654 | radeon_fence_driver_fini(rdev); |
| 2666 | radeon_clocks_fini(rdev); | ||
| 2667 | radeon_bo_fini(rdev); | 2655 | radeon_bo_fini(rdev); |
| 2668 | radeon_atombios_fini(rdev); | 2656 | radeon_atombios_fini(rdev); |
| 2669 | kfree(rdev->bios); | 2657 | kfree(rdev->bios); |
| @@ -3541,7 +3529,7 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) | |||
| 3541 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL | 3529 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL |
| 3542 | */ | 3530 | */ |
| 3543 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) { | 3531 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) { |
| 3544 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | 3532 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
| 3545 | u32 tmp; | 3533 | u32 tmp; |
| 3546 | 3534 | ||
| 3547 | WREG32(HDP_DEBUG1, 0); | 3535 | WREG32(HDP_DEBUG1, 0); |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 3dfcfa3ca425..a168d644bf9e 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
| @@ -1013,6 +1013,11 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, | |||
| 1013 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | 1013 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 1014 | struct drm_file *filp); | 1014 | struct drm_file *filp); |
| 1015 | 1015 | ||
| 1016 | /* VRAM scratch page for HDP bug */ | ||
| 1017 | struct r700_vram_scratch { | ||
| 1018 | struct radeon_bo *robj; | ||
| 1019 | volatile uint32_t *ptr; | ||
| 1020 | }; | ||
| 1016 | 1021 | ||
| 1017 | /* | 1022 | /* |
| 1018 | * Core structure, functions and helpers. | 1023 | * Core structure, functions and helpers. |
| @@ -1079,6 +1084,7 @@ struct radeon_device { | |||
| 1079 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | 1084 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
| 1080 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ | 1085 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
| 1081 | struct r600_blit r600_blit; | 1086 | struct r600_blit r600_blit; |
| 1087 | struct r700_vram_scratch vram_scratch; | ||
| 1082 | int msi_enabled; /* msi enabled */ | 1088 | int msi_enabled; /* msi enabled */ |
| 1083 | struct r600_ih ih; /* r6/700 interrupt ring */ | 1089 | struct r600_ih ih; /* r6/700 interrupt ring */ |
| 1084 | struct workqueue_struct *wq; | 1090 | struct workqueue_struct *wq; |
| @@ -1333,8 +1339,6 @@ extern bool radeon_card_posted(struct radeon_device *rdev); | |||
| 1333 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); | 1339 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
| 1334 | extern void radeon_update_display_priority(struct radeon_device *rdev); | 1340 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
| 1335 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); | 1341 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
| 1336 | extern int radeon_clocks_init(struct radeon_device *rdev); | ||
| 1337 | extern void radeon_clocks_fini(struct radeon_device *rdev); | ||
| 1338 | extern void radeon_scratch_init(struct radeon_device *rdev); | 1342 | extern void radeon_scratch_init(struct radeon_device *rdev); |
| 1339 | extern void radeon_surface_init(struct radeon_device *rdev); | 1343 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1340 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | 1344 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index a21bf88e8c2d..25e1dd197791 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
| @@ -858,21 +858,3 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
| 858 | return 0; | 858 | return 0; |
| 859 | } | 859 | } |
| 860 | 860 | ||
| 861 | /* | ||
| 862 | * Wrapper around modesetting bits. Move to radeon_clocks.c? | ||
| 863 | */ | ||
| 864 | int radeon_clocks_init(struct radeon_device *rdev) | ||
| 865 | { | ||
| 866 | int r; | ||
| 867 | |||
| 868 | r = radeon_static_clocks_init(rdev->ddev); | ||
| 869 | if (r) { | ||
| 870 | return r; | ||
| 871 | } | ||
| 872 | DRM_INFO("Clocks initialized !\n"); | ||
| 873 | return 0; | ||
| 874 | } | ||
| 875 | |||
| 876 | void radeon_clocks_fini(struct radeon_device *rdev) | ||
| 877 | { | ||
| 878 | } | ||
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 61141981880d..ebae14c4b768 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
| @@ -85,6 +85,19 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev | |||
| 85 | for (i = 0; i < num_indices; i++) { | 85 | for (i = 0; i < num_indices; i++) { |
| 86 | gpio = &i2c_info->asGPIO_Info[i]; | 86 | gpio = &i2c_info->asGPIO_Info[i]; |
| 87 | 87 | ||
| 88 | /* some evergreen boards have bad data for this entry */ | ||
| 89 | if (ASIC_IS_DCE4(rdev)) { | ||
| 90 | if ((i == 7) && | ||
| 91 | (gpio->usClkMaskRegisterIndex == 0x1936) && | ||
| 92 | (gpio->sucI2cId.ucAccess == 0)) { | ||
| 93 | gpio->sucI2cId.ucAccess = 0x97; | ||
| 94 | gpio->ucDataMaskShift = 8; | ||
| 95 | gpio->ucDataEnShift = 8; | ||
| 96 | gpio->ucDataY_Shift = 8; | ||
| 97 | gpio->ucDataA_Shift = 8; | ||
| 98 | } | ||
| 99 | } | ||
| 100 | |||
| 88 | if (gpio->sucI2cId.ucAccess == id) { | 101 | if (gpio->sucI2cId.ucAccess == id) { |
| 89 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; | 102 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; |
| 90 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; | 103 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; |
| @@ -147,6 +160,20 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev) | |||
| 147 | for (i = 0; i < num_indices; i++) { | 160 | for (i = 0; i < num_indices; i++) { |
| 148 | gpio = &i2c_info->asGPIO_Info[i]; | 161 | gpio = &i2c_info->asGPIO_Info[i]; |
| 149 | i2c.valid = false; | 162 | i2c.valid = false; |
| 163 | |||
| 164 | /* some evergreen boards have bad data for this entry */ | ||
| 165 | if (ASIC_IS_DCE4(rdev)) { | ||
| 166 | if ((i == 7) && | ||
| 167 | (gpio->usClkMaskRegisterIndex == 0x1936) && | ||
| 168 | (gpio->sucI2cId.ucAccess == 0)) { | ||
| 169 | gpio->sucI2cId.ucAccess = 0x97; | ||
| 170 | gpio->ucDataMaskShift = 8; | ||
| 171 | gpio->ucDataEnShift = 8; | ||
| 172 | gpio->ucDataY_Shift = 8; | ||
| 173 | gpio->ucDataA_Shift = 8; | ||
| 174 | } | ||
| 175 | } | ||
| 176 | |||
| 150 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; | 177 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; |
| 151 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; | 178 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; |
| 152 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; | 179 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; |
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c index 14448a740ba6..5249af8931e6 100644 --- a/drivers/gpu/drm/radeon/radeon_clocks.c +++ b/drivers/gpu/drm/radeon/radeon_clocks.c | |||
| @@ -327,6 +327,14 @@ void radeon_get_clock_info(struct drm_device *dev) | |||
| 327 | mpll->max_feedback_div = 0xff; | 327 | mpll->max_feedback_div = 0xff; |
| 328 | mpll->best_vco = 0; | 328 | mpll->best_vco = 0; |
| 329 | 329 | ||
| 330 | if (!rdev->clock.default_sclk) | ||
| 331 | rdev->clock.default_sclk = radeon_get_engine_clock(rdev); | ||
| 332 | if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock) | ||
| 333 | rdev->clock.default_mclk = radeon_get_memory_clock(rdev); | ||
| 334 | |||
| 335 | rdev->pm.current_sclk = rdev->clock.default_sclk; | ||
| 336 | rdev->pm.current_mclk = rdev->clock.default_mclk; | ||
| 337 | |||
| 330 | } | 338 | } |
| 331 | 339 | ||
| 332 | /* 10 khz */ | 340 | /* 10 khz */ |
| @@ -897,53 +905,3 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) | |||
| 897 | } | 905 | } |
| 898 | } | 906 | } |
| 899 | 907 | ||
| 900 | static void radeon_apply_clock_quirks(struct radeon_device *rdev) | ||
| 901 | { | ||
| 902 | uint32_t tmp; | ||
| 903 | |||
| 904 | /* XXX make sure engine is idle */ | ||
| 905 | |||
| 906 | if (rdev->family < CHIP_RS600) { | ||
| 907 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); | ||
| 908 | if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev)) | ||
| 909 | tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; | ||
| 910 | if ((rdev->family == CHIP_RV250) | ||
| 911 | || (rdev->family == CHIP_RV280)) | ||
| 912 | tmp |= | ||
| 913 | RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2; | ||
| 914 | if ((rdev->family == CHIP_RV350) | ||
| 915 | || (rdev->family == CHIP_RV380)) | ||
| 916 | tmp |= R300_SCLK_FORCE_VAP; | ||
| 917 | if (rdev->family == CHIP_R420) | ||
| 918 | tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX; | ||
| 919 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); | ||
| 920 | } else if (rdev->family < CHIP_R600) { | ||
| 921 | tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL); | ||
| 922 | tmp |= AVIVO_CP_FORCEON; | ||
| 923 | WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp); | ||
| 924 | |||
| 925 | tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL); | ||
| 926 | tmp |= AVIVO_E2_FORCEON; | ||
| 927 | WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp); | ||
| 928 | |||
| 929 | tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL); | ||
| 930 | tmp |= AVIVO_IDCT_FORCEON; | ||
| 931 | WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp); | ||
| 932 | } | ||
| 933 | } | ||
| 934 | |||
| 935 | int radeon_static_clocks_init(struct drm_device *dev) | ||
| 936 | { | ||
| 937 | struct radeon_device *rdev = dev->dev_private; | ||
| 938 | |||
| 939 | /* XXX make sure engine is idle */ | ||
| 940 | |||
| 941 | if (radeon_dynclks != -1) { | ||
| 942 | if (radeon_dynclks) { | ||
| 943 | if (rdev->asic->set_clock_gating) | ||
| 944 | radeon_set_clock_gating(rdev, 1); | ||
| 945 | } | ||
| 946 | } | ||
| 947 | radeon_apply_clock_quirks(rdev); | ||
| 948 | return 0; | ||
| 949 | } | ||
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 1a5ee392e9c7..a9dd7847d96e 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c | |||
| @@ -1051,10 +1051,16 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
| 1051 | uint32_t subpixel_order = SubPixelNone; | 1051 | uint32_t subpixel_order = SubPixelNone; |
| 1052 | bool shared_ddc = false; | 1052 | bool shared_ddc = false; |
| 1053 | 1053 | ||
| 1054 | /* fixme - tv/cv/din */ | ||
| 1055 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | 1054 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
| 1056 | return; | 1055 | return; |
| 1057 | 1056 | ||
| 1057 | /* if the user selected tv=0 don't try and add the connector */ | ||
| 1058 | if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) || | ||
| 1059 | (connector_type == DRM_MODE_CONNECTOR_Composite) || | ||
| 1060 | (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) && | ||
| 1061 | (radeon_tv == 0)) | ||
| 1062 | return; | ||
| 1063 | |||
| 1058 | /* see if we already added it */ | 1064 | /* see if we already added it */ |
| 1059 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | 1065 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 1060 | radeon_connector = to_radeon_connector(connector); | 1066 | radeon_connector = to_radeon_connector(connector); |
| @@ -1209,19 +1215,17 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
| 1209 | case DRM_MODE_CONNECTOR_SVIDEO: | 1215 | case DRM_MODE_CONNECTOR_SVIDEO: |
| 1210 | case DRM_MODE_CONNECTOR_Composite: | 1216 | case DRM_MODE_CONNECTOR_Composite: |
| 1211 | case DRM_MODE_CONNECTOR_9PinDIN: | 1217 | case DRM_MODE_CONNECTOR_9PinDIN: |
| 1212 | if (radeon_tv == 1) { | 1218 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
| 1213 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); | 1219 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
| 1214 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | 1220 | radeon_connector->dac_load_detect = true; |
| 1215 | radeon_connector->dac_load_detect = true; | 1221 | drm_connector_attach_property(&radeon_connector->base, |
| 1216 | drm_connector_attach_property(&radeon_connector->base, | 1222 | rdev->mode_info.load_detect_property, |
| 1217 | rdev->mode_info.load_detect_property, | 1223 | 1); |
| 1218 | 1); | 1224 | drm_connector_attach_property(&radeon_connector->base, |
| 1219 | drm_connector_attach_property(&radeon_connector->base, | 1225 | rdev->mode_info.tv_std_property, |
| 1220 | rdev->mode_info.tv_std_property, | 1226 | radeon_atombios_get_tv_info(rdev)); |
| 1221 | radeon_atombios_get_tv_info(rdev)); | 1227 | /* no HPD on analog connectors */ |
| 1222 | /* no HPD on analog connectors */ | 1228 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; |
| 1223 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
| 1224 | } | ||
| 1225 | break; | 1229 | break; |
| 1226 | case DRM_MODE_CONNECTOR_LVDS: | 1230 | case DRM_MODE_CONNECTOR_LVDS: |
| 1227 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | 1231 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); |
| @@ -1272,10 +1276,16 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
| 1272 | struct radeon_connector *radeon_connector; | 1276 | struct radeon_connector *radeon_connector; |
| 1273 | uint32_t subpixel_order = SubPixelNone; | 1277 | uint32_t subpixel_order = SubPixelNone; |
| 1274 | 1278 | ||
| 1275 | /* fixme - tv/cv/din */ | ||
| 1276 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | 1279 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
| 1277 | return; | 1280 | return; |
| 1278 | 1281 | ||
| 1282 | /* if the user selected tv=0 don't try and add the connector */ | ||
| 1283 | if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) || | ||
| 1284 | (connector_type == DRM_MODE_CONNECTOR_Composite) || | ||
| 1285 | (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) && | ||
| 1286 | (radeon_tv == 0)) | ||
| 1287 | return; | ||
| 1288 | |||
| 1279 | /* see if we already added it */ | 1289 | /* see if we already added it */ |
| 1280 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | 1290 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 1281 | radeon_connector = to_radeon_connector(connector); | 1291 | radeon_connector = to_radeon_connector(connector); |
| @@ -1347,26 +1357,24 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
| 1347 | case DRM_MODE_CONNECTOR_SVIDEO: | 1357 | case DRM_MODE_CONNECTOR_SVIDEO: |
| 1348 | case DRM_MODE_CONNECTOR_Composite: | 1358 | case DRM_MODE_CONNECTOR_Composite: |
| 1349 | case DRM_MODE_CONNECTOR_9PinDIN: | 1359 | case DRM_MODE_CONNECTOR_9PinDIN: |
| 1350 | if (radeon_tv == 1) { | 1360 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
| 1351 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); | 1361 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
| 1352 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | 1362 | radeon_connector->dac_load_detect = true; |
| 1353 | radeon_connector->dac_load_detect = true; | 1363 | /* RS400,RC410,RS480 chipset seems to report a lot |
| 1354 | /* RS400,RC410,RS480 chipset seems to report a lot | 1364 | * of false positive on load detect, we haven't yet |
| 1355 | * of false positive on load detect, we haven't yet | 1365 | * found a way to make load detect reliable on those |
| 1356 | * found a way to make load detect reliable on those | 1366 | * chipset, thus just disable it for TV. |
| 1357 | * chipset, thus just disable it for TV. | 1367 | */ |
| 1358 | */ | 1368 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) |
| 1359 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) | 1369 | radeon_connector->dac_load_detect = false; |
| 1360 | radeon_connector->dac_load_detect = false; | 1370 | drm_connector_attach_property(&radeon_connector->base, |
| 1361 | drm_connector_attach_property(&radeon_connector->base, | 1371 | rdev->mode_info.load_detect_property, |
| 1362 | rdev->mode_info.load_detect_property, | 1372 | radeon_connector->dac_load_detect); |
| 1363 | radeon_connector->dac_load_detect); | 1373 | drm_connector_attach_property(&radeon_connector->base, |
| 1364 | drm_connector_attach_property(&radeon_connector->base, | 1374 | rdev->mode_info.tv_std_property, |
| 1365 | rdev->mode_info.tv_std_property, | 1375 | radeon_combios_get_tv_info(rdev)); |
| 1366 | radeon_combios_get_tv_info(rdev)); | 1376 | /* no HPD on analog connectors */ |
| 1367 | /* no HPD on analog connectors */ | 1377 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; |
| 1368 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
| 1369 | } | ||
| 1370 | break; | 1378 | break; |
| 1371 | case DRM_MODE_CONNECTOR_LVDS: | 1379 | case DRM_MODE_CONNECTOR_LVDS: |
| 1372 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); | 1380 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 69b3c2291e92..256d204a6d24 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
| @@ -293,30 +293,20 @@ bool radeon_card_posted(struct radeon_device *rdev) | |||
| 293 | void radeon_update_bandwidth_info(struct radeon_device *rdev) | 293 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
| 294 | { | 294 | { |
| 295 | fixed20_12 a; | 295 | fixed20_12 a; |
| 296 | u32 sclk, mclk; | 296 | u32 sclk = rdev->pm.current_sclk; |
| 297 | u32 mclk = rdev->pm.current_mclk; | ||
| 297 | 298 | ||
| 298 | if (rdev->flags & RADEON_IS_IGP) { | 299 | /* sclk/mclk in Mhz */ |
| 299 | sclk = radeon_get_engine_clock(rdev); | 300 | a.full = dfixed_const(100); |
| 300 | mclk = rdev->clock.default_mclk; | 301 | rdev->pm.sclk.full = dfixed_const(sclk); |
| 301 | 302 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | |
| 302 | a.full = dfixed_const(100); | 303 | rdev->pm.mclk.full = dfixed_const(mclk); |
| 303 | rdev->pm.sclk.full = dfixed_const(sclk); | 304 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
| 304 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | ||
| 305 | rdev->pm.mclk.full = dfixed_const(mclk); | ||
| 306 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); | ||
| 307 | 305 | ||
| 306 | if (rdev->flags & RADEON_IS_IGP) { | ||
| 308 | a.full = dfixed_const(16); | 307 | a.full = dfixed_const(16); |
| 309 | /* core_bandwidth = sclk(Mhz) * 16 */ | 308 | /* core_bandwidth = sclk(Mhz) * 16 */ |
| 310 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); | 309 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
| 311 | } else { | ||
| 312 | sclk = radeon_get_engine_clock(rdev); | ||
| 313 | mclk = radeon_get_memory_clock(rdev); | ||
| 314 | |||
| 315 | a.full = dfixed_const(100); | ||
| 316 | rdev->pm.sclk.full = dfixed_const(sclk); | ||
| 317 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | ||
| 318 | rdev->pm.mclk.full = dfixed_const(mclk); | ||
| 319 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); | ||
| 320 | } | 310 | } |
| 321 | } | 311 | } |
| 322 | 312 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c index 0416804d8f30..6a13ee38a5b9 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c | |||
| @@ -213,7 +213,7 @@ static void post_xfer(struct i2c_adapter *i2c_adap) | |||
| 213 | 213 | ||
| 214 | static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) | 214 | static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) |
| 215 | { | 215 | { |
| 216 | u32 sclk = radeon_get_engine_clock(rdev); | 216 | u32 sclk = rdev->pm.current_sclk; |
| 217 | u32 prescale = 0; | 217 | u32 prescale = 0; |
| 218 | u32 nm; | 218 | u32 nm; |
| 219 | u8 n, m, loop; | 219 | u8 n, m, loop; |
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 8f93e2b4b0c8..efbe975312dc 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
| @@ -600,7 +600,6 @@ extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct d | |||
| 600 | void radeon_enc_destroy(struct drm_encoder *encoder); | 600 | void radeon_enc_destroy(struct drm_encoder *encoder); |
| 601 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); | 601 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
| 602 | void radeon_combios_asic_init(struct drm_device *dev); | 602 | void radeon_combios_asic_init(struct drm_device *dev); |
| 603 | extern int radeon_static_clocks_init(struct drm_device *dev); | ||
| 604 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, | 603 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
| 605 | struct drm_display_mode *mode, | 604 | struct drm_display_mode *mode, |
| 606 | struct drm_display_mode *adjusted_mode); | 605 | struct drm_display_mode *adjusted_mode); |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index f1c796810117..bfa59db374d2 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
| @@ -905,6 +905,54 @@ static void rv770_gpu_init(struct radeon_device *rdev) | |||
| 905 | 905 | ||
| 906 | } | 906 | } |
| 907 | 907 | ||
| 908 | static int rv770_vram_scratch_init(struct radeon_device *rdev) | ||
| 909 | { | ||
| 910 | int r; | ||
| 911 | u64 gpu_addr; | ||
| 912 | |||
| 913 | if (rdev->vram_scratch.robj == NULL) { | ||
| 914 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, | ||
| 915 | true, RADEON_GEM_DOMAIN_VRAM, | ||
| 916 | &rdev->vram_scratch.robj); | ||
| 917 | if (r) { | ||
| 918 | return r; | ||
| 919 | } | ||
| 920 | } | ||
| 921 | |||
| 922 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | ||
| 923 | if (unlikely(r != 0)) | ||
| 924 | return r; | ||
| 925 | r = radeon_bo_pin(rdev->vram_scratch.robj, | ||
| 926 | RADEON_GEM_DOMAIN_VRAM, &gpu_addr); | ||
| 927 | if (r) { | ||
| 928 | radeon_bo_unreserve(rdev->vram_scratch.robj); | ||
| 929 | return r; | ||
| 930 | } | ||
| 931 | r = radeon_bo_kmap(rdev->vram_scratch.robj, | ||
| 932 | (void **)&rdev->vram_scratch.ptr); | ||
| 933 | if (r) | ||
| 934 | radeon_bo_unpin(rdev->vram_scratch.robj); | ||
| 935 | radeon_bo_unreserve(rdev->vram_scratch.robj); | ||
| 936 | |||
| 937 | return r; | ||
| 938 | } | ||
| 939 | |||
| 940 | static void rv770_vram_scratch_fini(struct radeon_device *rdev) | ||
| 941 | { | ||
| 942 | int r; | ||
| 943 | |||
| 944 | if (rdev->vram_scratch.robj == NULL) { | ||
| 945 | return; | ||
| 946 | } | ||
| 947 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | ||
| 948 | if (likely(r == 0)) { | ||
| 949 | radeon_bo_kunmap(rdev->vram_scratch.robj); | ||
| 950 | radeon_bo_unpin(rdev->vram_scratch.robj); | ||
| 951 | radeon_bo_unreserve(rdev->vram_scratch.robj); | ||
| 952 | } | ||
| 953 | radeon_bo_unref(&rdev->vram_scratch.robj); | ||
| 954 | } | ||
| 955 | |||
| 908 | int rv770_mc_init(struct radeon_device *rdev) | 956 | int rv770_mc_init(struct radeon_device *rdev) |
| 909 | { | 957 | { |
| 910 | u32 tmp; | 958 | u32 tmp; |
| @@ -970,6 +1018,9 @@ static int rv770_startup(struct radeon_device *rdev) | |||
| 970 | if (r) | 1018 | if (r) |
| 971 | return r; | 1019 | return r; |
| 972 | } | 1020 | } |
| 1021 | r = rv770_vram_scratch_init(rdev); | ||
| 1022 | if (r) | ||
| 1023 | return r; | ||
| 973 | rv770_gpu_init(rdev); | 1024 | rv770_gpu_init(rdev); |
| 974 | r = r600_blit_init(rdev); | 1025 | r = r600_blit_init(rdev); |
| 975 | if (r) { | 1026 | if (r) { |
| @@ -1023,11 +1074,6 @@ int rv770_resume(struct radeon_device *rdev) | |||
| 1023 | */ | 1074 | */ |
| 1024 | /* post card */ | 1075 | /* post card */ |
| 1025 | atom_asic_init(rdev->mode_info.atom_context); | 1076 | atom_asic_init(rdev->mode_info.atom_context); |
| 1026 | /* Initialize clocks */ | ||
| 1027 | r = radeon_clocks_init(rdev); | ||
| 1028 | if (r) { | ||
| 1029 | return r; | ||
| 1030 | } | ||
| 1031 | 1077 | ||
| 1032 | r = rv770_startup(rdev); | 1078 | r = rv770_startup(rdev); |
| 1033 | if (r) { | 1079 | if (r) { |
| @@ -1118,9 +1164,6 @@ int rv770_init(struct radeon_device *rdev) | |||
| 1118 | radeon_surface_init(rdev); | 1164 | radeon_surface_init(rdev); |
| 1119 | /* Initialize clocks */ | 1165 | /* Initialize clocks */ |
| 1120 | radeon_get_clock_info(rdev->ddev); | 1166 | radeon_get_clock_info(rdev->ddev); |
| 1121 | r = radeon_clocks_init(rdev); | ||
| 1122 | if (r) | ||
| 1123 | return r; | ||
| 1124 | /* Fence driver */ | 1167 | /* Fence driver */ |
| 1125 | r = radeon_fence_driver_init(rdev); | 1168 | r = radeon_fence_driver_init(rdev); |
| 1126 | if (r) | 1169 | if (r) |
| @@ -1195,9 +1238,9 @@ void rv770_fini(struct radeon_device *rdev) | |||
| 1195 | r600_irq_fini(rdev); | 1238 | r600_irq_fini(rdev); |
| 1196 | radeon_irq_kms_fini(rdev); | 1239 | radeon_irq_kms_fini(rdev); |
| 1197 | rv770_pcie_gart_fini(rdev); | 1240 | rv770_pcie_gart_fini(rdev); |
| 1241 | rv770_vram_scratch_fini(rdev); | ||
| 1198 | radeon_gem_fini(rdev); | 1242 | radeon_gem_fini(rdev); |
| 1199 | radeon_fence_driver_fini(rdev); | 1243 | radeon_fence_driver_fini(rdev); |
| 1200 | radeon_clocks_fini(rdev); | ||
| 1201 | radeon_agp_fini(rdev); | 1244 | radeon_agp_fini(rdev); |
| 1202 | radeon_bo_fini(rdev); | 1245 | radeon_bo_fini(rdev); |
| 1203 | radeon_atombios_fini(rdev); | 1246 | radeon_atombios_fini(rdev); |
