diff options
author | Grazvydas Ignotas <notasas@gmail.com> | 2010-04-14 06:05:48 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2010-04-16 15:32:00 -0400 |
commit | 61c2a80b960361a930a4e3c4c0df694713b9dafd (patch) | |
tree | d1a2fe22a5486c08abc641479015a625d82ef84d | |
parent | a5e944f1d955f3819503348426763e21e0413ba6 (diff) |
wl1251: read default MAC address from EEPROM when available
Some wl1251 hardware configurations (like in WG7210 module) have
EEPROM attached where NVS data is kept, which includes MAC address.
In such configurations, let's read default MAC address from EEPROM,
instead of using random one.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Acked-by: Kalle Valo <kvalo@adurom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1251_main.c | 63 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1251_reg.h | 7 |
2 files changed, 70 insertions, 0 deletions
diff --git a/drivers/net/wireless/wl12xx/wl1251_main.c b/drivers/net/wireless/wl12xx/wl1251_main.c index 7b8b21212bf7..390cee7e61a1 100644 --- a/drivers/net/wireless/wl12xx/wl1251_main.c +++ b/drivers/net/wireless/wl12xx/wl1251_main.c | |||
@@ -1195,6 +1195,66 @@ static const struct ieee80211_ops wl1251_ops = { | |||
1195 | .conf_tx = wl1251_op_conf_tx, | 1195 | .conf_tx = wl1251_op_conf_tx, |
1196 | }; | 1196 | }; |
1197 | 1197 | ||
1198 | static int wl1251_read_eeprom_byte(struct wl1251 *wl, off_t offset, u8 *data) | ||
1199 | { | ||
1200 | unsigned long timeout; | ||
1201 | |||
1202 | wl1251_reg_write32(wl, EE_ADDR, offset); | ||
1203 | wl1251_reg_write32(wl, EE_CTL, EE_CTL_READ); | ||
1204 | |||
1205 | /* EE_CTL_READ clears when data is ready */ | ||
1206 | timeout = jiffies + msecs_to_jiffies(100); | ||
1207 | while (1) { | ||
1208 | if (!(wl1251_reg_read32(wl, EE_CTL) & EE_CTL_READ)) | ||
1209 | break; | ||
1210 | |||
1211 | if (time_after(jiffies, timeout)) | ||
1212 | return -ETIMEDOUT; | ||
1213 | |||
1214 | msleep(1); | ||
1215 | } | ||
1216 | |||
1217 | *data = wl1251_reg_read32(wl, EE_DATA); | ||
1218 | return 0; | ||
1219 | } | ||
1220 | |||
1221 | static int wl1251_read_eeprom(struct wl1251 *wl, off_t offset, | ||
1222 | u8 *data, size_t len) | ||
1223 | { | ||
1224 | size_t i; | ||
1225 | int ret; | ||
1226 | |||
1227 | wl1251_reg_write32(wl, EE_START, 0); | ||
1228 | |||
1229 | for (i = 0; i < len; i++) { | ||
1230 | ret = wl1251_read_eeprom_byte(wl, offset + i, &data[i]); | ||
1231 | if (ret < 0) | ||
1232 | return ret; | ||
1233 | } | ||
1234 | |||
1235 | return 0; | ||
1236 | } | ||
1237 | |||
1238 | static int wl1251_read_eeprom_mac(struct wl1251 *wl) | ||
1239 | { | ||
1240 | u8 mac[ETH_ALEN]; | ||
1241 | int i, ret; | ||
1242 | |||
1243 | wl1251_set_partition(wl, 0, 0, REGISTERS_BASE, REGISTERS_DOWN_SIZE); | ||
1244 | |||
1245 | ret = wl1251_read_eeprom(wl, 0x1c, mac, sizeof(mac)); | ||
1246 | if (ret < 0) { | ||
1247 | wl1251_warning("failed to read MAC address from EEPROM"); | ||
1248 | return ret; | ||
1249 | } | ||
1250 | |||
1251 | /* MAC is stored in reverse order */ | ||
1252 | for (i = 0; i < ETH_ALEN; i++) | ||
1253 | wl->mac_addr[i] = mac[ETH_ALEN - i - 1]; | ||
1254 | |||
1255 | return 0; | ||
1256 | } | ||
1257 | |||
1198 | static int wl1251_register_hw(struct wl1251 *wl) | 1258 | static int wl1251_register_hw(struct wl1251 *wl) |
1199 | { | 1259 | { |
1200 | int ret; | 1260 | int ret; |
@@ -1241,6 +1301,9 @@ int wl1251_init_ieee80211(struct wl1251 *wl) | |||
1241 | 1301 | ||
1242 | wl->hw->queues = 4; | 1302 | wl->hw->queues = 4; |
1243 | 1303 | ||
1304 | if (wl->use_eeprom) | ||
1305 | wl1251_read_eeprom_mac(wl); | ||
1306 | |||
1244 | ret = wl1251_register_hw(wl); | 1307 | ret = wl1251_register_hw(wl); |
1245 | if (ret) | 1308 | if (ret) |
1246 | goto out; | 1309 | goto out; |
diff --git a/drivers/net/wireless/wl12xx/wl1251_reg.h b/drivers/net/wireless/wl12xx/wl1251_reg.h index 0ca3b4326056..d16edd9bf06c 100644 --- a/drivers/net/wireless/wl12xx/wl1251_reg.h +++ b/drivers/net/wireless/wl12xx/wl1251_reg.h | |||
@@ -46,7 +46,14 @@ | |||
46 | #define SOR_CFG (REGISTERS_BASE + 0x0800) | 46 | #define SOR_CFG (REGISTERS_BASE + 0x0800) |
47 | #define ECPU_CTRL (REGISTERS_BASE + 0x0804) | 47 | #define ECPU_CTRL (REGISTERS_BASE + 0x0804) |
48 | #define HI_CFG (REGISTERS_BASE + 0x0808) | 48 | #define HI_CFG (REGISTERS_BASE + 0x0808) |
49 | |||
50 | /* EEPROM registers */ | ||
49 | #define EE_START (REGISTERS_BASE + 0x080C) | 51 | #define EE_START (REGISTERS_BASE + 0x080C) |
52 | #define EE_CTL (REGISTERS_BASE + 0x2000) | ||
53 | #define EE_DATA (REGISTERS_BASE + 0x2004) | ||
54 | #define EE_ADDR (REGISTERS_BASE + 0x2008) | ||
55 | |||
56 | #define EE_CTL_READ 2 | ||
50 | 57 | ||
51 | #define CHIP_ID_B (REGISTERS_BASE + 0x5674) | 58 | #define CHIP_ID_B (REGISTERS_BASE + 0x5674) |
52 | 59 | ||