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authorKevin Hilman <khilman@linaro.org>2013-10-18 10:02:04 -0400
committerKevin Hilman <khilman@linaro.org>2013-10-18 10:02:04 -0400
commit60cd8b09f1e26dec0e866085f110d1d665d53cec (patch)
tree7b16d53ca5d759c0419254fd2eb9d7d1c8dff61a
parent163556896d2fea757e0f87b44b537ff7d5b57807 (diff)
parent6bcf60f8d557f15c85faf82ccbfc38cf986c45cc (diff)
Merge branch 'rockchip/boards' into next/boards
From Heiko Stübner: Support for the RK3188 SoC, basic RK3188 based Radxa Rock board and RK3066a based BQ Curie2 tablet. * rockchip/boards: ARM: rockchip: add support for rk3188 and Radxa Rock board ARM: rockchip: add dts for bqcurie2 tablet ARM: rockchip: enable arm-global-timer ARM: rockchip: move shared dt properties to common source file
Diffstat
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts109
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi98
-rw-r--r--arch/arm/boot/dts/rk3188-clocks.dtsi289
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts80
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi253
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi124
-rw-r--r--arch/arm/mach-rockchip/Kconfig2
7 files changed, 858 insertions, 97 deletions
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
new file mode 100644
index 000000000000..035df4053c21
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -0,0 +1,109 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/dts-v1/;
17#include "rk3066a.dtsi"
18
19/ {
20 model = "bq Curie 2";
21
22 memory {
23 reg = <0x60000000 0x40000000>;
24 };
25
26 soc {
27 uart0: serial@10124000 {
28 status = "okay";
29 };
30
31 uart1: serial@10126000 {
32 status = "okay";
33 };
34
35 uart2: serial@20064000 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&uart2_xfer>;
38 status = "okay";
39 };
40
41 uart3: serial@20068000 {
42 status = "okay";
43 };
44
45 vcc_sd0: fixed-regulator {
46 compatible = "regulator-fixed";
47 regulator-name = "sdmmc-supply";
48 regulator-min-microvolt = <3000000>;
49 regulator-max-microvolt = <3000000>;
50 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
51 startup-delay-us = <100000>;
52 };
53
54 dwmmc@10214000 { /* sdmmc */
55 num-slots = <1>;
56 status = "okay";
57
58 pinctrl-names = "default";
59 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
60 vmmc-supply = <&vcc_sd0>;
61
62 slot@0 {
63 reg = <0>;
64 bus-width = <4>;
65 disable-wp;
66 };
67 };
68
69 dwmmc@10218000 { /* wifi */
70 num-slots = <1>;
71 status = "okay";
72 non-removable;
73
74 pinctrl-names = "default";
75 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
76
77 slot@0 {
78 reg = <0>;
79 bus-width = <4>;
80 disable-wp;
81 };
82 };
83
84 gpio-keys {
85 compatible = "gpio-keys";
86 #address-cells = <1>;
87 #size-cells = <0>;
88 autorepeat;
89
90 button@0 {
91 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
92 linux,code = <116>;
93 label = "GPIO Key Power";
94 linux,input-type = <1>;
95 gpio-key,wakeup = <1>;
96 debounce-interval = <100>;
97 };
98 button@1 {
99 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
100 linux,code = <104>;
101 label = "GPIO Key Vol-";
102 linux,input-type = <1>;
103 gpio-key,wakeup = <0>;
104 debounce-interval = <100>;
105 };
106 /* VOL+ comes somehow thru the ADC */
107 };
108 };
109};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 56bfac93d3f6..2218c64410de 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -14,15 +14,12 @@
14 */ 14 */
15 15
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/pinctrl/rockchip.h> 17#include <dt-bindings/pinctrl/rockchip.h>
20#include "skeleton.dtsi" 18#include "rk3xxx.dtsi"
21#include "rk3066a-clocks.dtsi" 19#include "rk3066a-clocks.dtsi"
22 20
23/ { 21/ {
24 compatible = "rockchip,rk3066a"; 22 compatible = "rockchip,rk3066a";
25 interrupt-parent = <&gic>;
26 23
27 cpus { 24 cpus {
28 #address-cells = <1>; 25 #address-cells = <1>;
@@ -43,33 +40,6 @@
43 }; 40 };
44 41
45 soc { 42 soc {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
49 ranges;
50
51 gic: interrupt-controller@1013d000 {
52 compatible = "arm,cortex-a9-gic";
53 interrupt-controller;
54 #interrupt-cells = <3>;
55 reg = <0x1013d000 0x1000>,
56 <0x1013c100 0x0100>;
57 };
58
59 L2: l2-cache-controller@10138000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10138000 0x1000>;
62 cache-unified;
63 cache-level = <2>;
64 };
65
66 local-timer@1013c600 {
67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0x1013c600 0x20>;
69 interrupts = <GIC_PPI 13 0x304>;
70 clocks = <&dummy150m>;
71 };
72
73 timer@20038000 { 43 timer@20038000 {
74 compatible = "snps,dw-apb-timer-osc"; 44 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>; 45 reg = <0x20038000 0x100>;
@@ -320,71 +290,5 @@
320 }; 290 };
321 }; 291 };
322 }; 292 };
323
324 uart0: serial@10124000 {
325 compatible = "snps,dw-apb-uart";
326 reg = <0x10124000 0x400>;
327 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
328 reg-shift = <2>;
329 reg-io-width = <1>;
330 clocks = <&clk_gates1 8>;
331 status = "disabled";
332 };
333
334 uart1: serial@10126000 {
335 compatible = "snps,dw-apb-uart";
336 reg = <0x10126000 0x400>;
337 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
338 reg-shift = <2>;
339 reg-io-width = <1>;
340 clocks = <&clk_gates1 10>;
341 status = "disabled";
342 };
343
344 uart2: serial@20064000 {
345 compatible = "snps,dw-apb-uart";
346 reg = <0x20064000 0x400>;
347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
348 reg-shift = <2>;
349 reg-io-width = <1>;
350 clocks = <&clk_gates1 12>;
351 status = "disabled";
352 };
353
354 uart3: serial@20068000 {
355 compatible = "snps,dw-apb-uart";
356 reg = <0x20068000 0x400>;
357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
358 reg-shift = <2>;
359 reg-io-width = <1>;
360 clocks = <&clk_gates1 14>;
361 status = "disabled";
362 };
363
364 dwmmc@10214000 {
365 compatible = "rockchip,rk2928-dw-mshc";
366 reg = <0x10214000 0x1000>;
367 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370
371 clocks = <&clk_gates5 10>, <&clk_gates2 11>;
372 clock-names = "biu", "ciu";
373
374 status = "disabled";
375 };
376
377 dwmmc@10218000 {
378 compatible = "rockchip,rk2928-dw-mshc";
379 reg = <0x10218000 0x1000>;
380 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383
384 clocks = <&clk_gates5 11>, <&clk_gates2 13>;
385 clock-names = "biu", "ciu";
386
387 status = "disabled";
388 };
389 }; 293 };
390}; 294};
diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi
new file mode 100644
index 000000000000..b1b92dc245ce
--- /dev/null
+++ b/arch/arm/boot/dts/rk3188-clocks.dtsi
@@ -0,0 +1,289 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/ {
17 clocks {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 /*
23 * This is a dummy clock, to be used as placeholder on
24 * other mux clocks when a specific parent clock is not
25 * yet implemented. It should be dropped when the driver
26 * is complete.
27 */
28 dummy: dummy {
29 compatible = "fixed-clock";
30 clock-frequency = <0>;
31 #clock-cells = <0>;
32 };
33
34 xin24m: xin24m {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 dummy48m: dummy48m {
41 compatible = "fixed-clock";
42 clock-frequency = <48000000>;
43 #clock-cells = <0>;
44 };
45
46 dummy150m: dummy150m {
47 compatible = "fixed-clock";
48 clock-frequency = <150000000>;
49 #clock-cells = <0>;
50 };
51
52 clk_gates0: gate-clk@200000d0 {
53 compatible = "rockchip,rk2928-gate-clk";
54 reg = <0x200000d0 0x4>;
55 clocks = <&dummy150m>, <&dummy>,
56 <&dummy>, <&dummy>,
57 <&dummy>, <&dummy>,
58 <&dummy>, <&dummy>,
59 <&dummy>, <&dummy>,
60 <&dummy>, <&dummy>,
61 <&dummy>, <&dummy>,
62 <&dummy>, <&dummy>;
63
64 clock-output-names =
65 "gate_core_periph", "gate_cpu_gpll",
66 "gate_ddrphy", "gate_aclk_cpu",
67 "gate_hclk_cpu", "gate_pclk_cpu",
68 "gate_atclk_cpu", "gate_aclk_core",
69 "reserved", "gate_i2s0",
70 "gate_i2s0_frac", "reserved",
71 "reserved", "gate_spdif",
72 "gate_spdif_frac", "gate_testclk";
73
74 #clock-cells = <1>;
75 };
76
77 clk_gates1: gate-clk@200000d4 {
78 compatible = "rockchip,rk2928-gate-clk";
79 reg = <0x200000d4 0x4>;
80 clocks = <&xin24m>, <&xin24m>,
81 <&xin24m>, <&dummy>,
82 <&dummy>, <&xin24m>,
83 <&xin24m>, <&dummy>,
84 <&xin24m>, <&dummy>,
85 <&xin24m>, <&dummy>,
86 <&xin24m>, <&dummy>,
87 <&xin24m>, <&dummy>;
88
89 clock-output-names =
90 "gate_timer0", "gate_timer1",
91 "gate_timer3", "gate_jtag",
92 "gate_aclk_lcdc1_src", "gate_otgphy0",
93 "gate_otgphy1", "gate_ddr_gpll",
94 "gate_uart0", "gate_frac_uart0",
95 "gate_uart1", "gate_frac_uart1",
96 "gate_uart2", "gate_frac_uart2",
97 "gate_uart3", "gate_frac_uart3";
98
99 #clock-cells = <1>;
100 };
101
102 clk_gates2: gate-clk@200000d8 {
103 compatible = "rockchip,rk2928-gate-clk";
104 reg = <0x200000d8 0x4>;
105 clocks = <&clk_gates2 1>, <&dummy>,
106 <&dummy>, <&dummy>,
107 <&dummy>, <&dummy>,
108 <&clk_gates2 3>, <&dummy>,
109 <&dummy>, <&dummy>,
110 <&dummy>, <&dummy48m>,
111 <&dummy>, <&dummy48m>,
112 <&dummy>, <&dummy>;
113
114 clock-output-names =
115 "gate_periph_src", "gate_aclk_periph",
116 "gate_hclk_periph", "gate_pclk_periph",
117 "gate_smc", "gate_mac",
118 "gate_hsadc", "gate_hsadc_frac",
119 "gate_saradc", "gate_spi0",
120 "gate_spi1", "gate_mmc0",
121 "gate_mac_lbtest", "gate_mmc1",
122 "gate_emmc", "reserved";
123
124 #clock-cells = <1>;
125 };
126
127 clk_gates3: gate-clk@200000dc {
128 compatible = "rockchip,rk2928-gate-clk";
129 reg = <0x200000dc 0x4>;
130 clocks = <&dummy>, <&dummy>,
131 <&dummy>, <&dummy>,
132 <&xin24m>, <&xin24m>,
133 <&dummy>, <&dummy>,
134 <&xin24m>, <&dummy>,
135 <&dummy>, <&dummy>,
136 <&dummy>, <&dummy>,
137 <&xin24m>, <&dummy>;
138
139 clock-output-names =
140 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
141 "gate_dclk_lcdc1", "gate_pclkin_cif0",
142 "gate_timer2", "gate_timer4",
143 "gate_hsicphy", "gate_cif0_out",
144 "gate_timer5", "gate_aclk_vepu",
145 "gate_hclk_vepu", "gate_aclk_vdpu",
146 "gate_hclk_vdpu", "reserved",
147 "gate_timer6", "gate_aclk_gpu_src";
148
149 #clock-cells = <1>;
150 };
151
152 clk_gates4: gate-clk@200000e0 {
153 compatible = "rockchip,rk2928-gate-clk";
154 reg = <0x200000e0 0x4>;
155 clocks = <&clk_gates2 2>, <&clk_gates2 3>,
156 <&clk_gates2 1>, <&clk_gates2 1>,
157 <&clk_gates2 1>, <&clk_gates2 2>,
158 <&clk_gates2 2>, <&clk_gates2 2>,
159 <&clk_gates0 4>, <&clk_gates0 4>,
160 <&clk_gates0 3>, <&dummy>,
161 <&clk_gates0 3>, <&dummy>,
162 <&dummy>, <&dummy>;
163
164 clock-output-names =
165 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
166 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
167 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
168 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
169 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
170 "gate_aclk_strc_sys", "reserved",
171 "gate_aclk_intmem", "reserved",
172 "gate_hclk_imem1", "gate_hclk_imem0";
173
174 #clock-cells = <1>;
175 };
176
177 clk_gates5: gate-clk@200000e4 {
178 compatible = "rockchip,rk2928-gate-clk";
179 reg = <0x200000e4 0x4>;
180 clocks = <&clk_gates0 3>, <&clk_gates2 1>,
181 <&clk_gates0 5>, <&clk_gates0 5>,
182 <&clk_gates0 5>, <&clk_gates0 5>,
183 <&clk_gates0 4>, <&clk_gates0 5>,
184 <&clk_gates2 1>, <&clk_gates2 2>,
185 <&clk_gates2 2>, <&clk_gates2 2>,
186 <&clk_gates2 2>, <&clk_gates4 5>;
187
188 clock-output-names =
189 "gate_aclk_dmac1", "gate_aclk_dmac2",
190 "gate_pclk_efuse", "gate_pclk_tzpc",
191 "gate_pclk_grf", "gate_pclk_pmu",
192 "gate_hclk_rom", "gate_pclk_ddrupctl",
193 "gate_aclk_smc", "gate_hclk_nandc",
194 "gate_hclk_mmc0", "gate_hclk_mmc1",
195 "gate_hclk_emmc", "gate_hclk_otg0";
196
197 #clock-cells = <1>;
198 };
199
200 clk_gates6: gate-clk@200000e8 {
201 compatible = "rockchip,rk2928-gate-clk";
202 reg = <0x200000e8 0x4>;
203 clocks = <&clk_gates3 0>, <&clk_gates0 4>,
204 <&clk_gates0 4>, <&clk_gates1 4>,
205 <&clk_gates0 4>, <&clk_gates3 0>,
206 <&dummy>, <&dummy>,
207 <&clk_gates3 0>, <&clk_gates0 4>,
208 <&clk_gates0 4>, <&clk_gates1 4>,
209 <&clk_gates0 4>, <&clk_gates3 0>;
210
211 clock-output-names =
212 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
213 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
214 "gate_hclk_cif0", "gate_aclk_cif0",
215 "reserved", "reserved",
216 "gate_aclk_ipp", "gate_hclk_ipp",
217 "gate_hclk_rga", "gate_aclk_rga",
218 "gate_hclk_vio_bus", "gate_aclk_vio0";
219
220 #clock-cells = <1>;
221 };
222
223 clk_gates7: gate-clk@200000ec {
224 compatible = "rockchip,rk2928-gate-clk";
225 reg = <0x200000ec 0x4>;
226 clocks = <&clk_gates2 2>, <&clk_gates0 4>,
227 <&clk_gates0 4>, <&dummy>,
228 <&dummy>, <&clk_gates2 2>,
229 <&clk_gates2 2>, <&clk_gates0 5>,
230 <&dummy>, <&clk_gates0 5>,
231 <&clk_gates0 5>, <&clk_gates2 3>,
232 <&clk_gates2 3>, <&clk_gates2 3>,
233 <&clk_gates2 3>, <&clk_gates2 3>;
234
235 clock-output-names =
236 "gate_hclk_emac", "gate_hclk_spdif",
237 "gate_hclk_i2s0_2ch", "gate_hclk_otg1",
238 "gate_hclk_hsic", "gate_hclk_hsadc",
239 "gate_hclk_pidf", "gate_pclk_timer0",
240 "reserved", "gate_pclk_timer2",
241 "gate_pclk_pwm01", "gate_pclk_pwm23",
242 "gate_pclk_spi0", "gate_pclk_spi1",
243 "gate_pclk_saradc", "gate_pclk_wdt";
244
245 #clock-cells = <1>;
246 };
247
248 clk_gates8: gate-clk@200000f0 {
249 compatible = "rockchip,rk2928-gate-clk";
250 reg = <0x200000f0 0x4>;
251 clocks = <&clk_gates0 5>, <&clk_gates0 5>,
252 <&clk_gates2 3>, <&clk_gates2 3>,
253 <&clk_gates0 5>, <&clk_gates0 5>,
254 <&clk_gates2 3>, <&clk_gates2 3>,
255 <&clk_gates2 3>, <&clk_gates0 5>,
256 <&clk_gates0 5>, <&clk_gates0 5>,
257 <&clk_gates2 3>, <&dummy>;
258
259 clock-output-names =
260 "gate_pclk_uart0", "gate_pclk_uart1",
261 "gate_pclk_uart2", "gate_pclk_uart3",
262 "gate_pclk_i2c0", "gate_pclk_i2c1",
263 "gate_pclk_i2c2", "gate_pclk_i2c3",
264 "gate_pclk_i2c4", "gate_pclk_gpio0",
265 "gate_pclk_gpio1", "gate_pclk_gpio2",
266 "gate_pclk_gpio3", "gate_aclk_gps";
267
268 #clock-cells = <1>;
269 };
270
271 clk_gates9: gate-clk@200000f4 {
272 compatible = "rockchip,rk2928-gate-clk";
273 reg = <0x200000f4 0x4>;
274 clocks = <&dummy>, <&dummy>,
275 <&dummy>, <&dummy>,
276 <&dummy>, <&dummy>,
277 <&dummy>, <&dummy>;
278
279 clock-output-names =
280 "gate_clk_core_dbg", "gate_pclk_dbg",
281 "gate_clk_trace", "gate_atclk",
282 "gate_clk_l2c", "gate_aclk_vio1",
283 "gate_pclk_publ", "gate_aclk_gpu";
284
285 #clock-cells = <1>;
286 };
287 };
288
289};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
new file mode 100644
index 000000000000..3ba1968a70ab
--- /dev/null
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -0,0 +1,80 @@
1/*
2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "rk3188.dtsi"
17
18/ {
19 model = "Radxa Rock";
20
21 memory {
22 reg = <0x60000000 0x80000000>;
23 };
24
25 soc {
26 uart0: serial@10124000 {
27 status = "okay";
28 };
29
30 uart1: serial@10126000 {
31 status = "okay";
32 };
33
34 uart2: serial@20064000 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&uart2_xfer>;
37 status = "okay";
38 };
39
40 uart3: serial@20068000 {
41 status = "okay";
42 };
43
44 gpio-keys {
45 compatible = "gpio-keys";
46 #address-cells = <1>;
47 #size-cells = <0>;
48 autorepeat;
49
50 button@0 {
51 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
52 linux,code = <116>;
53 label = "GPIO Key Power";
54 linux,input-type = <1>;
55 gpio-key,wakeup = <1>;
56 debounce-interval = <100>;
57 };
58 };
59
60 gpio-leds {
61 compatible = "gpio-leds";
62
63 green {
64 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
65 default-state = "off";
66 };
67
68 yellow {
69 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
70 default-state = "off";
71 };
72
73 sleep {
74 gpios = <&gpio0 15 0>;
75 default-state = "off";
76 };
77 };
78
79 };
80};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
new file mode 100644
index 000000000000..1a26b03b3649
--- /dev/null
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -0,0 +1,253 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h>
18#include "rk3xxx.dtsi"
19#include "rk3188-clocks.dtsi"
20
21/ {
22 compatible = "rockchip,rk3188";
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
33 };
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
38 reg = <0x1>;
39 };
40 cpu@2 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
44 reg = <0x2>;
45 };
46 cpu@3 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
50 reg = <0x3>;
51 };
52 };
53
54 soc {
55 global-timer@1013c200 {
56 interrupts = <GIC_PPI 11 0xf04>;
57 };
58
59 local-timer@1013c600 {
60 interrupts = <GIC_PPI 13 0xf04>;
61 };
62
63 pinctrl@20008000 {
64 compatible = "rockchip,rk3188-pinctrl";
65 reg = <0x20008000 0xa0>,
66 <0x20008164 0x1a0>;
67 reg-names = "base", "pull";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71
72 gpio0: gpio0@0x2000a000 {
73 compatible = "rockchip,rk3188-gpio-bank0";
74 reg = <0x2000a000 0x100>,
75 <0x20004064 0x8>;
76 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk_gates8 9>;
78
79 gpio-controller;
80 #gpio-cells = <2>;
81
82 interrupt-controller;
83 #interrupt-cells = <2>;
84 };
85
86 gpio1: gpio1@0x2003c000 {
87 compatible = "rockchip,gpio-bank";
88 reg = <0x2003c000 0x100>;
89 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clk_gates8 10>;
91
92 gpio-controller;
93 #gpio-cells = <2>;
94
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 };
98
99 gpio2: gpio2@2003e000 {
100 compatible = "rockchip,gpio-bank";
101 reg = <0x2003e000 0x100>;
102 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clk_gates8 11>;
104
105 gpio-controller;
106 #gpio-cells = <2>;
107
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 };
111
112 gpio3: gpio3@20080000 {
113 compatible = "rockchip,gpio-bank";
114 reg = <0x20080000 0x100>;
115 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&clk_gates8 12>;
117
118 gpio-controller;
119 #gpio-cells = <2>;
120
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 };
124
125 pcfg_pull_up: pcfg_pull_up {
126 bias-pull-up;
127 };
128
129 pcfg_pull_down: pcfg_pull_down {
130 bias-pull-down;
131 };
132
133 pcfg_pull_none: pcfg_pull_none {
134 bias-disable;
135 };
136
137 uart0 {
138 uart0_xfer: uart0-xfer {
139 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
140 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
141 };
142
143 uart0_cts: uart0-cts {
144 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
145 };
146
147 uart0_rts: uart0-rts {
148 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
149 };
150 };
151
152 uart1 {
153 uart1_xfer: uart1-xfer {
154 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
155 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
156 };
157
158 uart1_cts: uart1-cts {
159 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
160 };
161
162 uart1_rts: uart1-rts {
163 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
164 };
165 };
166
167 uart2 {
168 uart2_xfer: uart2-xfer {
169 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
170 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
171 };
172 /* no rts / cts for uart2 */
173 };
174
175 uart3 {
176 uart3_xfer: uart3-xfer {
177 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
178 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
179 };
180
181 uart3_cts: uart3-cts {
182 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
183 };
184
185 uart3_rts: uart3-rts {
186 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
187 };
188 };
189
190 sd0 {
191 sd0_clk: sd0-clk {
192 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
193 };
194
195 sd0_cmd: sd0-cmd {
196 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
197 };
198
199 sd0_cd: sd0-cd {
200 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
201 };
202
203 sd0_wp: sd0-wp {
204 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
205 };
206
207 sd0_pwr: sd0-pwr {
208 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
209 };
210
211 sd0_bus1: sd0-bus-width1 {
212 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
213 };
214
215 sd0_bus4: sd0-bus-width4 {
216 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
217 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
218 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
219 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
220 };
221 };
222
223 sd1 {
224 sd1_clk: sd1-clk {
225 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
226 };
227
228 sd1_cmd: sd1-cmd {
229 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
230 };
231
232 sd1_cd: sd1-cd {
233 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
234 };
235
236 sd1_wp: sd1-wp {
237 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
238 };
239
240 sd1_bus1: sd1-bus-width1 {
241 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
242 };
243
244 sd1_bus4: sd1-bus-width4 {
245 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
246 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
247 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
248 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
249 };
250 };
251 };
252 };
253};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
new file mode 100644
index 000000000000..0fcbcfd67de2
--- /dev/null
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -0,0 +1,124 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include "skeleton.dtsi"
19
20/ {
21 interrupt-parent = <&gic>;
22
23 soc {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 ranges;
28
29 gic: interrupt-controller@1013d000 {
30 compatible = "arm,cortex-a9-gic";
31 interrupt-controller;
32 #interrupt-cells = <3>;
33 reg = <0x1013d000 0x1000>,
34 <0x1013c100 0x0100>;
35 };
36
37 L2: l2-cache-controller@10138000 {
38 compatible = "arm,pl310-cache";
39 reg = <0x10138000 0x1000>;
40 cache-unified;
41 cache-level = <2>;
42 };
43
44 global-timer@1013c200 {
45 compatible = "arm,cortex-a9-global-timer";
46 reg = <0x1013c200 0x20>;
47 interrupts = <GIC_PPI 11 0x304>;
48 clocks = <&dummy150m>;
49 };
50
51 local-timer@1013c600 {
52 compatible = "arm,cortex-a9-twd-timer";
53 reg = <0x1013c600 0x20>;
54 interrupts = <GIC_PPI 13 0x304>;
55 clocks = <&dummy150m>;
56 };
57
58 uart0: serial@10124000 {
59 compatible = "snps,dw-apb-uart";
60 reg = <0x10124000 0x400>;
61 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
62 reg-shift = <2>;
63 reg-io-width = <1>;
64 clocks = <&clk_gates1 8>;
65 status = "disabled";
66 };
67
68 uart1: serial@10126000 {
69 compatible = "snps,dw-apb-uart";
70 reg = <0x10126000 0x400>;
71 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
72 reg-shift = <2>;
73 reg-io-width = <1>;
74 clocks = <&clk_gates1 10>;
75 status = "disabled";
76 };
77
78 uart2: serial@20064000 {
79 compatible = "snps,dw-apb-uart";
80 reg = <0x20064000 0x400>;
81 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
82 reg-shift = <2>;
83 reg-io-width = <1>;
84 clocks = <&clk_gates1 12>;
85 status = "disabled";
86 };
87
88 uart3: serial@20068000 {
89 compatible = "snps,dw-apb-uart";
90 reg = <0x20068000 0x400>;
91 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
92 reg-shift = <2>;
93 reg-io-width = <1>;
94 clocks = <&clk_gates1 14>;
95 status = "disabled";
96 };
97
98 dwmmc@10214000 {
99 compatible = "rockchip,rk2928-dw-mshc";
100 reg = <0x10214000 0x1000>;
101 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 clocks = <&clk_gates5 10>, <&clk_gates2 11>;
106 clock-names = "biu", "ciu";
107
108 status = "disabled";
109 };
110
111 dwmmc@10218000 {
112 compatible = "rockchip,rk2928-dw-mshc";
113 reg = <0x10218000 0x1000>;
114 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117
118 clocks = <&clk_gates5 11>, <&clk_gates2 13>;
119 clock-names = "biu", "ciu";
120
121 status = "disabled";
122 };
123 };
124};
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 25ee12b21f01..6fef4647b6fe 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,8 @@ config ARCH_ROCKCHIP
11 select COMMON_CLK 11 select COMMON_CLK
12 select GENERIC_CLOCKEVENTS 12 select GENERIC_CLOCKEVENTS
13 select DW_APB_TIMER_OF 13 select DW_APB_TIMER_OF
14 select ARM_GLOBAL_TIMER
15 select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
14 help 16 help
15 Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs 17 Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
16 containing the RK2928, RK30xx and RK31xx series. 18 containing the RK2928, RK30xx and RK31xx series.
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 11:28:53 -0400