aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMark Brown <broonie@linaro.org>2013-06-17 12:20:25 -0400
committerMark Brown <broonie@linaro.org>2013-06-17 12:20:25 -0400
commit60790c5735c78e2576fcb1e2fa47f5f11464445a (patch)
tree22dfa9d3bd7a0f5a1f8c808e14b2da04d5794dc7
parent3843e87ebd2f3304df5f75bb34b0ee207d3b4356 (diff)
parent9be94aeabf551aa5e2481ab9d626ba82d6b14f3d (diff)
Merge remote-tracking branch 'asoc/topic/rt5640' into asoc-next
Diffstat
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt71
-rw-r--r--Documentation/devicetree/bindings/sound/rt5640.txt30
-rw-r--r--include/sound/rt5640.h22
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/rt5640.c2128
-rw-r--r--sound/soc/codecs/rt5640.h2092
-rw-r--r--sound/soc/tegra/Kconfig10
-rw-r--r--sound/soc/tegra/Makefile2
-rw-r--r--sound/soc/tegra/tegra_rt5640.c257
10 files changed, 4618 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
new file mode 100644
index 000000000000..d130818700b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
@@ -0,0 +1,71 @@
1NVIDIA Tegra audio complex, with RT5640 CODEC
2
3Required properties:
4- compatible : "nvidia,tegra-audio-rt5640"
5- clocks : Must contain an entry for each entry in clock-names.
6- clock-names : Must include the following entries:
7 "pll_a" (The Tegra clock of that name),
8 "pll_a_out0" (The Tegra clock of that name),
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10- nvidia,model : The user-visible name of this sound complex.
11- nvidia,audio-routing : A list of the connections between audio components.
12 Each entry is a pair of strings, the first being the connection's sink,
13 the second being the connection's source. Valid names for sources and
14 sinks are the RT5640's pins, and the jacks on the board:
15
16 RT5640 pins:
17
18 * DMIC1
19 * DMIC2
20 * MICBIAS1
21 * IN1P
22 * IN1R
23 * IN2P
24 * IN2R
25 * HPOL
26 * HPOR
27 * LOUTL
28 * LOUTR
29 * MONOP
30 * MONON
31 * SPOLP
32 * SPOLN
33 * SPORP
34 * SPORN
35
36 Board connectors:
37
38 * Headphones
39 * Speakers
40
41- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
42 connected to the CODEC.
43- nvidia,audio-codec : The phandle of the RT5640 audio codec. This binding
44 assumes that AIF1 on the CODEC is connected to Tegra.
45
46Optional properties:
47- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in
48
49Example:
50
51sound {
52 compatible = "nvidia,tegra-audio-rt5640-dalmore",
53 "nvidia,tegra-audio-rt5640";
54 nvidia,model = "NVIDIA Tegra Dalmore";
55
56 nvidia,audio-routing =
57 "Headphones", "HPOR",
58 "Headphones", "HPOL",
59 "Speakers", "SPORP",
60 "Speakers", "SPORN",
61 "Speakers", "SPOLP",
62 "Speakers", "SPOLN";
63
64 nvidia,i2s-controller = <&tegra_i2s1>;
65 nvidia,audio-codec = <&rt5640>;
66
67 nvidia,hp-det-gpios = <&gpio 143 0>; /* GPIO PR7 */
68
69 clocks = <&tegra_car 216>, <&tegra_car 217>, <&tegra_car 120>;
70 clock-names = "pll_a", "pll_a_out0", "mclk";
71};
diff --git a/Documentation/devicetree/bindings/sound/rt5640.txt b/Documentation/devicetree/bindings/sound/rt5640.txt
new file mode 100644
index 000000000000..005bcb24d72d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5640.txt
@@ -0,0 +1,30 @@
1RT5640 audio CODEC
2
3This device supports I2C only.
4
5Required properties:
6
7- compatible : "realtek,rt5640".
8
9- reg : The I2C address of the device.
10
11- interrupts : The CODEC's interrupt output.
12
13Optional properties:
14
15- realtek,in1-differential
16- realtek,in2-differential
17 Boolean. Indicate MIC1/2 input are differential, rather than single-ended.
18
19- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
20
21Example:
22
23rt5640 {
24 compatible = "realtek,rt5640";
25 reg = <0x1c>;
26 interrupt-parent = <&gpio>;
27 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
28 realtek,ldo1-en-gpios =
29 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
30};
diff --git a/include/sound/rt5640.h b/include/sound/rt5640.h
new file mode 100644
index 000000000000..27cc75ed67f8
--- /dev/null
+++ b/include/sound/rt5640.h
@@ -0,0 +1,22 @@
1/*
2 * linux/sound/rt5640.h -- Platform data for RT5640
3 *
4 * Copyright 2011 Realtek Microelectronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_RT5640_H
12#define __LINUX_SND_RT5640_H
13
14struct rt5640_platform_data {
15 /* IN1 & IN2 can optionally be differential */
16 bool in1_diff;
17 bool in2_diff;
18
19 int ldo1_en; /* GPIO for LDO1_EN */
20};
21
22#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c691e222670a..0615e00b4ab7 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -56,6 +56,7 @@ config SND_SOC_ALL_CODECS
56 select SND_SOC_HDMI_CODEC 56 select SND_SOC_HDMI_CODEC
57 select SND_SOC_PCM3008 57 select SND_SOC_PCM3008
58 select SND_SOC_RT5631 if I2C 58 select SND_SOC_RT5631 if I2C
59 select SND_SOC_RT5640 if I2C
59 select SND_SOC_SGTL5000 if I2C 60 select SND_SOC_SGTL5000 if I2C
60 select SND_SOC_SI476X if MFD_SI476X_CORE 61 select SND_SOC_SI476X if MFD_SI476X_CORE
61 select SND_SOC_SN95031 if INTEL_SCU_IPC 62 select SND_SOC_SN95031 if INTEL_SCU_IPC
@@ -296,6 +297,9 @@ config SND_SOC_PCM3008
296config SND_SOC_RT5631 297config SND_SOC_RT5631
297 tristate 298 tristate
298 299
300config SND_SOC_RT5640
301 tristate
302
299#Freescale sgtl5000 codec 303#Freescale sgtl5000 codec
300config SND_SOC_SGTL5000 304config SND_SOC_SGTL5000
301 tristate 305 tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 82aa34e034c5..93b3e2220487 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -44,6 +44,7 @@ snd-soc-ml26124-objs := ml26124.o
44snd-soc-hdmi-codec-objs := hdmi.o 44snd-soc-hdmi-codec-objs := hdmi.o
45snd-soc-pcm3008-objs := pcm3008.o 45snd-soc-pcm3008-objs := pcm3008.o
46snd-soc-rt5631-objs := rt5631.o 46snd-soc-rt5631-objs := rt5631.o
47snd-soc-rt5640-objs := rt5640.o
47snd-soc-sgtl5000-objs := sgtl5000.o 48snd-soc-sgtl5000-objs := sgtl5000.o
48snd-soc-alc5623-objs := alc5623.o 49snd-soc-alc5623-objs := alc5623.o
49snd-soc-alc5632-objs := alc5632.o 50snd-soc-alc5632-objs := alc5632.o
@@ -171,6 +172,7 @@ obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
171obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o 172obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o
172obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o 173obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
173obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o 174obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
175obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
174obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 176obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
175obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o 177obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
176obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o 178obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
new file mode 100644
index 000000000000..ce585e37e38a
--- /dev/null
+++ b/sound/soc/codecs/rt5640.c
@@ -0,0 +1,2128 @@
1/*
2 * rt5640.c -- RT5640 ALSA SoC audio codec driver
3 *
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/regmap.h>
21#include <linux/of_gpio.h>
22#include <linux/platform_device.h>
23#include <linux/spi/spi.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include "rt5640.h"
33
34#define RT5640_DEVICE_ID 0x6231
35
36#define RT5640_PR_RANGE_BASE (0xff + 1)
37#define RT5640_PR_SPACING 0x100
38
39#define RT5640_PR_BASE (RT5640_PR_RANGE_BASE + (0 * RT5640_PR_SPACING))
40
41static const struct regmap_range_cfg rt5640_ranges[] = {
42 { .name = "PR", .range_min = RT5640_PR_BASE,
43 .range_max = RT5640_PR_BASE + 0xb4,
44 .selector_reg = RT5640_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5640_PRIV_DATA,
48 .window_len = 0x1, },
49};
50
51static struct reg_default init_list[] = {
52 {RT5640_PR_BASE + 0x3d, 0x3600},
53 {RT5640_PR_BASE + 0x1c, 0x0D21},
54 {RT5640_PR_BASE + 0x1b, 0x0000},
55 {RT5640_PR_BASE + 0x12, 0x0aa8},
56 {RT5640_PR_BASE + 0x14, 0x0aaa},
57 {RT5640_PR_BASE + 0x20, 0x6110},
58 {RT5640_PR_BASE + 0x21, 0xe0e0},
59 {RT5640_PR_BASE + 0x23, 0x1804},
60};
61#define RT5640_INIT_REG_LEN ARRAY_SIZE(init_list)
62
63static const struct reg_default rt5640_reg[RT5640_VENDOR_ID2 + 1] = {
64 { 0x00, 0x000e },
65 { 0x01, 0xc8c8 },
66 { 0x02, 0xc8c8 },
67 { 0x03, 0xc8c8 },
68 { 0x04, 0x8000 },
69 { 0x0d, 0x0000 },
70 { 0x0e, 0x0000 },
71 { 0x0f, 0x0808 },
72 { 0x19, 0xafaf },
73 { 0x1a, 0xafaf },
74 { 0x1b, 0x0000 },
75 { 0x1c, 0x2f2f },
76 { 0x1d, 0x2f2f },
77 { 0x1e, 0x0000 },
78 { 0x27, 0x7060 },
79 { 0x28, 0x7070 },
80 { 0x29, 0x8080 },
81 { 0x2a, 0x5454 },
82 { 0x2b, 0x5454 },
83 { 0x2c, 0xaa00 },
84 { 0x2d, 0x0000 },
85 { 0x2e, 0xa000 },
86 { 0x2f, 0x0000 },
87 { 0x3b, 0x0000 },
88 { 0x3c, 0x007f },
89 { 0x3d, 0x0000 },
90 { 0x3e, 0x007f },
91 { 0x45, 0xe000 },
92 { 0x46, 0x003e },
93 { 0x47, 0x003e },
94 { 0x48, 0xf800 },
95 { 0x49, 0x3800 },
96 { 0x4a, 0x0004 },
97 { 0x4c, 0xfc00 },
98 { 0x4d, 0x0000 },
99 { 0x4f, 0x01ff },
100 { 0x50, 0x0000 },
101 { 0x51, 0x0000 },
102 { 0x52, 0x01ff },
103 { 0x53, 0xf000 },
104 { 0x61, 0x0000 },
105 { 0x62, 0x0000 },
106 { 0x63, 0x00c0 },
107 { 0x64, 0x0000 },
108 { 0x65, 0x0000 },
109 { 0x66, 0x0000 },
110 { 0x6a, 0x0000 },
111 { 0x6c, 0x0000 },
112 { 0x70, 0x8000 },
113 { 0x71, 0x8000 },
114 { 0x72, 0x8000 },
115 { 0x73, 0x1114 },
116 { 0x74, 0x0c00 },
117 { 0x75, 0x1d00 },
118 { 0x80, 0x0000 },
119 { 0x81, 0x0000 },
120 { 0x82, 0x0000 },
121 { 0x83, 0x0000 },
122 { 0x84, 0x0000 },
123 { 0x85, 0x0008 },
124 { 0x89, 0x0000 },
125 { 0x8a, 0x0000 },
126 { 0x8b, 0x0600 },
127 { 0x8c, 0x0228 },
128 { 0x8d, 0xa000 },
129 { 0x8e, 0x0004 },
130 { 0x8f, 0x1100 },
131 { 0x90, 0x0646 },
132 { 0x91, 0x0c00 },
133 { 0x92, 0x0000 },
134 { 0x93, 0x3000 },
135 { 0xb0, 0x2080 },
136 { 0xb1, 0x0000 },
137 { 0xb4, 0x2206 },
138 { 0xb5, 0x1f00 },
139 { 0xb6, 0x0000 },
140 { 0xb8, 0x034b },
141 { 0xb9, 0x0066 },
142 { 0xba, 0x000b },
143 { 0xbb, 0x0000 },
144 { 0xbc, 0x0000 },
145 { 0xbd, 0x0000 },
146 { 0xbe, 0x0000 },
147 { 0xbf, 0x0000 },
148 { 0xc0, 0x0400 },
149 { 0xc2, 0x0000 },
150 { 0xc4, 0x0000 },
151 { 0xc5, 0x0000 },
152 { 0xc6, 0x2000 },
153 { 0xc8, 0x0000 },
154 { 0xc9, 0x0000 },
155 { 0xca, 0x0000 },
156 { 0xcb, 0x0000 },
157 { 0xcc, 0x0000 },
158 { 0xcf, 0x0013 },
159 { 0xd0, 0x0680 },
160 { 0xd1, 0x1c17 },
161 { 0xd2, 0x8c00 },
162 { 0xd3, 0xaa20 },
163 { 0xd6, 0x0400 },
164 { 0xd9, 0x0809 },
165 { 0xfe, 0x10ec },
166 { 0xff, 0x6231 },
167};
168
169static int rt5640_reset(struct snd_soc_codec *codec)
170{
171 return snd_soc_write(codec, RT5640_RESET, 0);
172}
173
174static bool rt5640_volatile_register(struct device *dev, unsigned int reg)
175{
176 int i;
177
178 for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
179 if ((reg >= rt5640_ranges[i].window_start &&
180 reg <= rt5640_ranges[i].window_start +
181 rt5640_ranges[i].window_len) ||
182 (reg >= rt5640_ranges[i].range_min &&
183 reg <= rt5640_ranges[i].range_max))
184 return true;
185
186 switch (reg) {
187 case RT5640_RESET:
188 case RT5640_ASRC_5:
189 case RT5640_EQ_CTRL1:
190 case RT5640_DRC_AGC_1:
191 case RT5640_ANC_CTRL1:
192 case RT5640_IRQ_CTRL2:
193 case RT5640_INT_IRQ_ST:
194 case RT5640_DSP_CTRL2:
195 case RT5640_DSP_CTRL3:
196 case RT5640_PRIV_INDEX:
197 case RT5640_PRIV_DATA:
198 case RT5640_PGM_REG_ARR1:
199 case RT5640_PGM_REG_ARR3:
200 case RT5640_VENDOR_ID:
201 case RT5640_VENDOR_ID1:
202 case RT5640_VENDOR_ID2:
203 return true;
204 default:
205 return false;
206 }
207}
208
209static bool rt5640_readable_register(struct device *dev, unsigned int reg)
210{
211 int i;
212
213 for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
214 if ((reg >= rt5640_ranges[i].window_start &&
215 reg <= rt5640_ranges[i].window_start +
216 rt5640_ranges[i].window_len) ||
217 (reg >= rt5640_ranges[i].range_min &&
218 reg <= rt5640_ranges[i].range_max))
219 return true;
220
221 switch (reg) {
222 case RT5640_RESET:
223 case RT5640_SPK_VOL:
224 case RT5640_HP_VOL:
225 case RT5640_OUTPUT:
226 case RT5640_MONO_OUT:
227 case RT5640_IN1_IN2:
228 case RT5640_IN3_IN4:
229 case RT5640_INL_INR_VOL:
230 case RT5640_DAC1_DIG_VOL:
231 case RT5640_DAC2_DIG_VOL:
232 case RT5640_DAC2_CTRL:
233 case RT5640_ADC_DIG_VOL:
234 case RT5640_ADC_DATA:
235 case RT5640_ADC_BST_VOL:
236 case RT5640_STO_ADC_MIXER:
237 case RT5640_MONO_ADC_MIXER:
238 case RT5640_AD_DA_MIXER:
239 case RT5640_STO_DAC_MIXER:
240 case RT5640_MONO_DAC_MIXER:
241 case RT5640_DIG_MIXER:
242 case RT5640_DSP_PATH1:
243 case RT5640_DSP_PATH2:
244 case RT5640_DIG_INF_DATA:
245 case RT5640_REC_L1_MIXER:
246 case RT5640_REC_L2_MIXER:
247 case RT5640_REC_R1_MIXER:
248 case RT5640_REC_R2_MIXER:
249 case RT5640_HPO_MIXER:
250 case RT5640_SPK_L_MIXER:
251 case RT5640_SPK_R_MIXER:
252 case RT5640_SPO_L_MIXER:
253 case RT5640_SPO_R_MIXER:
254 case RT5640_SPO_CLSD_RATIO:
255 case RT5640_MONO_MIXER:
256 case RT5640_OUT_L1_MIXER:
257 case RT5640_OUT_L2_MIXER:
258 case RT5640_OUT_L3_MIXER:
259 case RT5640_OUT_R1_MIXER:
260 case RT5640_OUT_R2_MIXER:
261 case RT5640_OUT_R3_MIXER:
262 case RT5640_LOUT_MIXER:
263 case RT5640_PWR_DIG1:
264 case RT5640_PWR_DIG2:
265 case RT5640_PWR_ANLG1:
266 case RT5640_PWR_ANLG2:
267 case RT5640_PWR_MIXER:
268 case RT5640_PWR_VOL:
269 case RT5640_PRIV_INDEX:
270 case RT5640_PRIV_DATA:
271 case RT5640_I2S1_SDP:
272 case RT5640_I2S2_SDP:
273 case RT5640_ADDA_CLK1:
274 case RT5640_ADDA_CLK2:
275 case RT5640_DMIC:
276 case RT5640_GLB_CLK:
277 case RT5640_PLL_CTRL1:
278 case RT5640_PLL_CTRL2:
279 case RT5640_ASRC_1:
280 case RT5640_ASRC_2:
281 case RT5640_ASRC_3:
282 case RT5640_ASRC_4:
283 case RT5640_ASRC_5:
284 case RT5640_HP_OVCD:
285 case RT5640_CLS_D_OVCD:
286 case RT5640_CLS_D_OUT:
287 case RT5640_DEPOP_M1:
288 case RT5640_DEPOP_M2:
289 case RT5640_DEPOP_M3:
290 case RT5640_CHARGE_PUMP:
291 case RT5640_PV_DET_SPK_G:
292 case RT5640_MICBIAS:
293 case RT5640_EQ_CTRL1:
294 case RT5640_EQ_CTRL2:
295 case RT5640_WIND_FILTER:
296 case RT5640_DRC_AGC_1:
297 case RT5640_DRC_AGC_2:
298 case RT5640_DRC_AGC_3:
299 case RT5640_SVOL_ZC:
300 case RT5640_ANC_CTRL1:
301 case RT5640_ANC_CTRL2:
302 case RT5640_ANC_CTRL3:
303 case RT5640_JD_CTRL:
304 case RT5640_ANC_JD:
305 case RT5640_IRQ_CTRL1:
306 case RT5640_IRQ_CTRL2:
307 case RT5640_INT_IRQ_ST:
308 case RT5640_GPIO_CTRL1:
309 case RT5640_GPIO_CTRL2:
310 case RT5640_GPIO_CTRL3:
311 case RT5640_DSP_CTRL1:
312 case RT5640_DSP_CTRL2:
313 case RT5640_DSP_CTRL3:
314 case RT5640_DSP_CTRL4:
315 case RT5640_PGM_REG_ARR1:
316 case RT5640_PGM_REG_ARR2:
317 case RT5640_PGM_REG_ARR3:
318 case RT5640_PGM_REG_ARR4:
319 case RT5640_PGM_REG_ARR5:
320 case RT5640_SCB_FUNC:
321 case RT5640_SCB_CTRL:
322 case RT5640_BASE_BACK:
323 case RT5640_MP3_PLUS1:
324 case RT5640_MP3_PLUS2:
325 case RT5640_3D_HP:
326 case RT5640_ADJ_HPF:
327 case RT5640_HP_CALIB_AMP_DET:
328 case RT5640_HP_CALIB2:
329 case RT5640_SV_ZCD1:
330 case RT5640_SV_ZCD2:
331 case RT5640_DUMMY1:
332 case RT5640_DUMMY2:
333 case RT5640_DUMMY3:
334 case RT5640_VENDOR_ID:
335 case RT5640_VENDOR_ID1:
336 case RT5640_VENDOR_ID2:
337 return true;
338 default:
339 return false;
340 }
341}
342
343static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
344static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
345static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
346static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
347static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
348
349/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
350static unsigned int bst_tlv[] = {
351 TLV_DB_RANGE_HEAD(7),
352 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
353 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
354 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
355 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
356 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
357 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
358 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
359};
360
361/* Interface data select */
362static const char * const rt5640_data_select[] = {
363 "Normal", "left copy to right", "right copy to left", "Swap"};
364
365static const SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
366 RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
367
368static const SOC_ENUM_SINGLE_DECL(rt5640_if1_adc_enum, RT5640_DIG_INF_DATA,
369 RT5640_IF1_ADC_SEL_SFT, rt5640_data_select);
370
371static const SOC_ENUM_SINGLE_DECL(rt5640_if2_dac_enum, RT5640_DIG_INF_DATA,
372 RT5640_IF2_DAC_SEL_SFT, rt5640_data_select);
373
374static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_enum, RT5640_DIG_INF_DATA,
375 RT5640_IF2_ADC_SEL_SFT, rt5640_data_select);
376
377/* Class D speaker gain ratio */
378static const char * const rt5640_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x",
379 "2x", "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
380
381static const SOC_ENUM_SINGLE_DECL(
382 rt5640_clsd_spk_ratio_enum, RT5640_CLS_D_OUT,
383 RT5640_CLSD_RATIO_SFT, rt5640_clsd_spk_ratio);
384
385static const struct snd_kcontrol_new rt5640_snd_controls[] = {
386 /* Speaker Output Volume */
387 SOC_DOUBLE("Speaker Playback Switch", RT5640_SPK_VOL,
388 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
389 SOC_DOUBLE("Speaker Channel Switch", RT5640_SPK_VOL,
390 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
391 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5640_SPK_VOL,
392 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
393 /* Headphone Output Volume */
394 SOC_DOUBLE("HP Playback Switch", RT5640_HP_VOL,
395 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
396 SOC_DOUBLE("HP Channel Switch", RT5640_HP_VOL,
397 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
398 SOC_DOUBLE_TLV("HP Playback Volume", RT5640_HP_VOL,
399 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
400 /* OUTPUT Control */
401 SOC_DOUBLE("OUT Playback Switch", RT5640_OUTPUT,
402 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
403 SOC_DOUBLE("OUT Channel Switch", RT5640_OUTPUT,
404 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
405 SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
406 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
407 /* MONO Output Control */
408 SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT,
409 RT5640_L_MUTE_SFT, 1, 1),
410 /* DAC Digital Volume */
411 SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
412 RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
413 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
414 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
415 175, 0, dac_vol_tlv),
416 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5640_DAC2_DIG_VOL,
417 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
418 175, 0, dac_vol_tlv),
419 /* IN1/IN2 Control */
420 SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
421 RT5640_BST_SFT1, 8, 0, bst_tlv),
422 SOC_SINGLE_TLV("IN2 Boost", RT5640_IN3_IN4,
423 RT5640_BST_SFT2, 8, 0, bst_tlv),
424 /* INL/INR Volume Control */
425 SOC_DOUBLE_TLV("IN Capture Volume", RT5640_INL_INR_VOL,
426 RT5640_INL_VOL_SFT, RT5640_INR_VOL_SFT,
427 31, 1, in_vol_tlv),
428 /* ADC Digital Volume Control */
429 SOC_DOUBLE("ADC Capture Switch", RT5640_ADC_DIG_VOL,
430 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
431 SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
432 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
433 127, 0, adc_vol_tlv),
434 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
435 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
436 127, 0, adc_vol_tlv),
437 /* ADC Boost Volume Control */
438 SOC_DOUBLE_TLV("ADC Boost Gain", RT5640_ADC_BST_VOL,
439 RT5640_ADC_L_BST_SFT, RT5640_ADC_R_BST_SFT,
440 3, 0, adc_bst_tlv),
441 /* Class D speaker gain ratio */
442 SOC_ENUM("Class D SPK Ratio Control", rt5640_clsd_spk_ratio_enum),
443
444 SOC_ENUM("ADC IF1 Data Switch", rt5640_if1_adc_enum),
445 SOC_ENUM("DAC IF1 Data Switch", rt5640_if1_dac_enum),
446 SOC_ENUM("ADC IF2 Data Switch", rt5640_if2_adc_enum),
447 SOC_ENUM("DAC IF2 Data Switch", rt5640_if2_dac_enum),
448};
449
450/**
451 * set_dmic_clk - Set parameter of dmic.
452 *
453 * @w: DAPM widget.
454 * @kcontrol: The kcontrol of this widget.
455 * @event: Event id.
456 *
457 * Choose dmic clock between 1MHz and 3MHz.
458 * It is better for clock to approximate 3MHz.
459 */
460static int set_dmic_clk(struct snd_soc_dapm_widget *w,
461 struct snd_kcontrol *kcontrol, int event)
462{
463 struct snd_soc_codec *codec = w->codec;
464 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
465 int div[] = {2, 3, 4, 6, 8, 12};
466 int idx = -EINVAL, i;
467 int rate, red, bound, temp;
468
469 rate = rt5640->sysclk;
470 red = 3000000 * 12;
471 for (i = 0; i < ARRAY_SIZE(div); i++) {
472 bound = div[i] * 3000000;
473 if (rate > bound)
474 continue;
475 temp = bound - rate;
476 if (temp < red) {
477 red = temp;
478 idx = i;
479 }
480 }
481 if (idx < 0)
482 dev_err(codec->dev, "Failed to set DMIC clock\n");
483 else
484 snd_soc_update_bits(codec, RT5640_DMIC, RT5640_DMIC_CLK_MASK,
485 idx << RT5640_DMIC_CLK_SFT);
486 return idx;
487}
488
489static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
490 struct snd_soc_dapm_widget *sink)
491{
492 unsigned int val;
493
494 val = snd_soc_read(source->codec, RT5640_GLB_CLK);
495 val &= RT5640_SCLK_SRC_MASK;
496 if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T)
497 return 1;
498 else
499 return 0;
500}
501
502/* Digital Mixer */
503static const struct snd_kcontrol_new rt5640_sto_adc_l_mix[] = {
504 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
505 RT5640_M_ADC_L1_SFT, 1, 1),
506 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
507 RT5640_M_ADC_L2_SFT, 1, 1),
508};
509
510static const struct snd_kcontrol_new rt5640_sto_adc_r_mix[] = {
511 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
512 RT5640_M_ADC_R1_SFT, 1, 1),
513 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
514 RT5640_M_ADC_R2_SFT, 1, 1),
515};
516
517static const struct snd_kcontrol_new rt5640_mono_adc_l_mix[] = {
518 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
519 RT5640_M_MONO_ADC_L1_SFT, 1, 1),
520 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
521 RT5640_M_MONO_ADC_L2_SFT, 1, 1),
522};
523
524static const struct snd_kcontrol_new rt5640_mono_adc_r_mix[] = {
525 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
526 RT5640_M_MONO_ADC_R1_SFT, 1, 1),
527 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
528 RT5640_M_MONO_ADC_R2_SFT, 1, 1),
529};
530
531static const struct snd_kcontrol_new rt5640_dac_l_mix[] = {
532 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
533 RT5640_M_ADCMIX_L_SFT, 1, 1),
534 SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
535 RT5640_M_IF1_DAC_L_SFT, 1, 1),
536};
537
538static const struct snd_kcontrol_new rt5640_dac_r_mix[] = {
539 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
540 RT5640_M_ADCMIX_R_SFT, 1, 1),
541 SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
542 RT5640_M_IF1_DAC_R_SFT, 1, 1),
543};
544
545static const struct snd_kcontrol_new rt5640_sto_dac_l_mix[] = {
546 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
547 RT5640_M_DAC_L1_SFT, 1, 1),
548 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
549 RT5640_M_DAC_L2_SFT, 1, 1),
550 SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
551 RT5640_M_ANC_DAC_L_SFT, 1, 1),
552};
553
554static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
555 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
556 RT5640_M_DAC_R1_SFT, 1, 1),
557 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
558 RT5640_M_DAC_R2_SFT, 1, 1),
559 SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
560 RT5640_M_ANC_DAC_R_SFT, 1, 1),
561};
562
563static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
564 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
565 RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
566 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
567 RT5640_M_DAC_L2_MONO_L_SFT, 1, 1),
568 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
569 RT5640_M_DAC_R2_MONO_L_SFT, 1, 1),
570};
571
572static const struct snd_kcontrol_new rt5640_mono_dac_r_mix[] = {
573 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
574 RT5640_M_DAC_R1_MONO_R_SFT, 1, 1),
575 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
576 RT5640_M_DAC_R2_MONO_R_SFT, 1, 1),
577 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
578 RT5640_M_DAC_L2_MONO_R_SFT, 1, 1),
579};
580
581static const struct snd_kcontrol_new rt5640_dig_l_mix[] = {
582 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_DIG_MIXER,
583 RT5640_M_STO_L_DAC_L_SFT, 1, 1),
584 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
585 RT5640_M_DAC_L2_DAC_L_SFT, 1, 1),
586};
587
588static const struct snd_kcontrol_new rt5640_dig_r_mix[] = {
589 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
590 RT5640_M_STO_R_DAC_R_SFT, 1, 1),
591 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
592 RT5640_M_DAC_R2_DAC_R_SFT, 1, 1),
593};
594
595/* Analog Input Mixer */
596static const struct snd_kcontrol_new rt5640_rec_l_mix[] = {
597 SOC_DAPM_SINGLE("HPOL Switch", RT5640_REC_L2_MIXER,
598 RT5640_M_HP_L_RM_L_SFT, 1, 1),
599 SOC_DAPM_SINGLE("INL Switch", RT5640_REC_L2_MIXER,
600 RT5640_M_IN_L_RM_L_SFT, 1, 1),
601 SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_L2_MIXER,
602 RT5640_M_BST4_RM_L_SFT, 1, 1),
603 SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_L2_MIXER,
604 RT5640_M_BST1_RM_L_SFT, 1, 1),
605 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_REC_L2_MIXER,
606 RT5640_M_OM_L_RM_L_SFT, 1, 1),
607};
608
609static const struct snd_kcontrol_new rt5640_rec_r_mix[] = {
610 SOC_DAPM_SINGLE("HPOR Switch", RT5640_REC_R2_MIXER,
611 RT5640_M_HP_R_RM_R_SFT, 1, 1),
612 SOC_DAPM_SINGLE("INR Switch", RT5640_REC_R2_MIXER,
613 RT5640_M_IN_R_RM_R_SFT, 1, 1),
614 SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_R2_MIXER,
615 RT5640_M_BST4_RM_R_SFT, 1, 1),
616 SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_R2_MIXER,
617 RT5640_M_BST1_RM_R_SFT, 1, 1),
618 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_REC_R2_MIXER,
619 RT5640_M_OM_R_RM_R_SFT, 1, 1),
620};
621
622/* Analog Output Mixer */
623static const struct snd_kcontrol_new rt5640_spk_l_mix[] = {
624 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_SPK_L_MIXER,
625 RT5640_M_RM_L_SM_L_SFT, 1, 1),
626 SOC_DAPM_SINGLE("INL Switch", RT5640_SPK_L_MIXER,
627 RT5640_M_IN_L_SM_L_SFT, 1, 1),
628 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPK_L_MIXER,
629 RT5640_M_DAC_L1_SM_L_SFT, 1, 1),
630 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
631 RT5640_M_DAC_L2_SM_L_SFT, 1, 1),
632 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_SPK_L_MIXER,
633 RT5640_M_OM_L_SM_L_SFT, 1, 1),
634};
635
636static const struct snd_kcontrol_new rt5640_spk_r_mix[] = {
637 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_SPK_R_MIXER,
638 RT5640_M_RM_R_SM_R_SFT, 1, 1),
639 SOC_DAPM_SINGLE("INR Switch", RT5640_SPK_R_MIXER,
640 RT5640_M_IN_R_SM_R_SFT, 1, 1),
641 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
642 RT5640_M_DAC_R1_SM_R_SFT, 1, 1),
643 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
644 RT5640_M_DAC_R2_SM_R_SFT, 1, 1),
645 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_SPK_R_MIXER,
646 RT5640_M_OM_R_SM_R_SFT, 1, 1),
647};
648
649static const struct snd_kcontrol_new rt5640_out_l_mix[] = {
650 SOC_DAPM_SINGLE("SPK MIXL Switch", RT5640_OUT_L3_MIXER,
651 RT5640_M_SM_L_OM_L_SFT, 1, 1),
652 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
653 RT5640_M_BST1_OM_L_SFT, 1, 1),
654 SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
655 RT5640_M_IN_L_OM_L_SFT, 1, 1),
656 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
657 RT5640_M_RM_L_OM_L_SFT, 1, 1),
658 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
659 RT5640_M_DAC_R2_OM_L_SFT, 1, 1),
660 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
661 RT5640_M_DAC_L2_OM_L_SFT, 1, 1),
662 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
663 RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
664};
665
666static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
667 SOC_DAPM_SINGLE("SPK MIXR Switch", RT5640_OUT_R3_MIXER,
668 RT5640_M_SM_L_OM_R_SFT, 1, 1),
669 SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
670 RT5640_M_BST4_OM_R_SFT, 1, 1),
671 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
672 RT5640_M_BST1_OM_R_SFT, 1, 1),
673 SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
674 RT5640_M_IN_R_OM_R_SFT, 1, 1),
675 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
676 RT5640_M_RM_R_OM_R_SFT, 1, 1),
677 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
678 RT5640_M_DAC_L2_OM_R_SFT, 1, 1),
679 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
680 RT5640_M_DAC_R2_OM_R_SFT, 1, 1),
681 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
682 RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
683};
684
685static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
686 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
687 RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
688 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPO_L_MIXER,
689 RT5640_M_DAC_L1_SPM_L_SFT, 1, 1),
690 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_L_MIXER,
691 RT5640_M_SV_R_SPM_L_SFT, 1, 1),
692 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5640_SPO_L_MIXER,
693 RT5640_M_SV_L_SPM_L_SFT, 1, 1),
694 SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_L_MIXER,
695 RT5640_M_BST1_SPM_L_SFT, 1, 1),
696};
697
698static const struct snd_kcontrol_new rt5640_spo_r_mix[] = {
699 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
700 RT5640_M_DAC_R1_SPM_R_SFT, 1, 1),
701 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_R_MIXER,
702 RT5640_M_SV_R_SPM_R_SFT, 1, 1),
703 SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_R_MIXER,
704 RT5640_M_BST1_SPM_R_SFT, 1, 1),
705};
706
707static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
708 SOC_DAPM_SINGLE("HPO MIX DAC2 Switch", RT5640_HPO_MIXER,
709 RT5640_M_DAC2_HM_SFT, 1, 1),
710 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
711 RT5640_M_DAC1_HM_SFT, 1, 1),
712 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
713 RT5640_M_HPVOL_HM_SFT, 1, 1),
714};
715
716static const struct snd_kcontrol_new rt5640_lout_mix[] = {
717 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
718 RT5640_M_DAC_L1_LM_SFT, 1, 1),
719 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
720 RT5640_M_DAC_R1_LM_SFT, 1, 1),
721 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_LOUT_MIXER,
722 RT5640_M_OV_L_LM_SFT, 1, 1),
723 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_LOUT_MIXER,
724 RT5640_M_OV_R_LM_SFT, 1, 1),
725};
726
727static const struct snd_kcontrol_new rt5640_mono_mix[] = {
728 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
729 RT5640_M_DAC_R2_MM_SFT, 1, 1),
730 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
731 RT5640_M_DAC_L2_MM_SFT, 1, 1),
732 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_MONO_MIXER,
733 RT5640_M_OV_R_MM_SFT, 1, 1),
734 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_MONO_MIXER,
735 RT5640_M_OV_L_MM_SFT, 1, 1),
736 SOC_DAPM_SINGLE("BST1 Switch", RT5640_MONO_MIXER,
737 RT5640_M_BST1_MM_SFT, 1, 1),
738};
739
740/* INL/R source */
741static const char * const rt5640_inl_src[] = {
742 "IN2P", "MONOP"
743};
744
745static const SOC_ENUM_SINGLE_DECL(
746 rt5640_inl_enum, RT5640_INL_INR_VOL,
747 RT5640_INL_SEL_SFT, rt5640_inl_src);
748
749static const struct snd_kcontrol_new rt5640_inl_mux =
750 SOC_DAPM_ENUM("INL source", rt5640_inl_enum);
751
752static const char * const rt5640_inr_src[] = {
753 "IN2N", "MONON"
754};
755
756static const SOC_ENUM_SINGLE_DECL(
757 rt5640_inr_enum, RT5640_INL_INR_VOL,
758 RT5640_INR_SEL_SFT, rt5640_inr_src);
759
760static const struct snd_kcontrol_new rt5640_inr_mux =
761 SOC_DAPM_ENUM("INR source", rt5640_inr_enum);
762
763/* Stereo ADC source */
764static const char * const rt5640_stereo_adc1_src[] = {
765 "DIG MIX", "ADC"
766};
767
768static const SOC_ENUM_SINGLE_DECL(
769 rt5640_stereo_adc1_enum, RT5640_STO_ADC_MIXER,
770 RT5640_ADC_1_SRC_SFT, rt5640_stereo_adc1_src);
771
772static const struct snd_kcontrol_new rt5640_sto_adc_1_mux =
773 SOC_DAPM_ENUM("Stereo ADC1 Mux", rt5640_stereo_adc1_enum);
774
775static const char * const rt5640_stereo_adc2_src[] = {
776 "DMIC1", "DMIC2", "DIG MIX"
777};
778
779static const SOC_ENUM_SINGLE_DECL(
780 rt5640_stereo_adc2_enum, RT5640_STO_ADC_MIXER,
781 RT5640_ADC_2_SRC_SFT, rt5640_stereo_adc2_src);
782
783static const struct snd_kcontrol_new rt5640_sto_adc_2_mux =
784 SOC_DAPM_ENUM("Stereo ADC2 Mux", rt5640_stereo_adc2_enum);
785
786/* Mono ADC source */
787static const char * const rt5640_mono_adc_l1_src[] = {
788 "Mono DAC MIXL", "ADCL"
789};
790
791static const SOC_ENUM_SINGLE_DECL(
792 rt5640_mono_adc_l1_enum, RT5640_MONO_ADC_MIXER,
793 RT5640_MONO_ADC_L1_SRC_SFT, rt5640_mono_adc_l1_src);
794
795static const struct snd_kcontrol_new rt5640_mono_adc_l1_mux =
796 SOC_DAPM_ENUM("Mono ADC1 left source", rt5640_mono_adc_l1_enum);
797
798static const char * const rt5640_mono_adc_l2_src[] = {
799 "DMIC L1", "DMIC L2", "Mono DAC MIXL"
800};
801
802static const SOC_ENUM_SINGLE_DECL(
803 rt5640_mono_adc_l2_enum, RT5640_MONO_ADC_MIXER,
804 RT5640_MONO_ADC_L2_SRC_SFT, rt5640_mono_adc_l2_src);
805
806static const struct snd_kcontrol_new rt5640_mono_adc_l2_mux =
807 SOC_DAPM_ENUM("Mono ADC2 left source", rt5640_mono_adc_l2_enum);
808
809static const char * const rt5640_mono_adc_r1_src[] = {
810 "Mono DAC MIXR", "ADCR"
811};
812
813static const SOC_ENUM_SINGLE_DECL(
814 rt5640_mono_adc_r1_enum, RT5640_MONO_ADC_MIXER,
815 RT5640_MONO_ADC_R1_SRC_SFT, rt5640_mono_adc_r1_src);
816
817static const struct snd_kcontrol_new rt5640_mono_adc_r1_mux =
818 SOC_DAPM_ENUM("Mono ADC1 right source", rt5640_mono_adc_r1_enum);
819
820static const char * const rt5640_mono_adc_r2_src[] = {
821 "DMIC R1", "DMIC R2", "Mono DAC MIXR"
822};
823
824static const SOC_ENUM_SINGLE_DECL(
825 rt5640_mono_adc_r2_enum, RT5640_MONO_ADC_MIXER,
826 RT5640_MONO_ADC_R2_SRC_SFT, rt5640_mono_adc_r2_src);
827
828static const struct snd_kcontrol_new rt5640_mono_adc_r2_mux =
829 SOC_DAPM_ENUM("Mono ADC2 right source", rt5640_mono_adc_r2_enum);
830
831/* DAC2 channel source */
832static const char * const rt5640_dac_l2_src[] = {
833 "IF2", "Base L/R"
834};
835
836static int rt5640_dac_l2_values[] = {
837 0,
838 3,
839};
840
841static const SOC_VALUE_ENUM_SINGLE_DECL(
842 rt5640_dac_l2_enum, RT5640_DSP_PATH2, RT5640_DAC_L2_SEL_SFT,
843 0x3, rt5640_dac_l2_src, rt5640_dac_l2_values);
844
845static const struct snd_kcontrol_new rt5640_dac_l2_mux =
846 SOC_DAPM_VALUE_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
847
848static const char * const rt5640_dac_r2_src[] = {
849 "IF2",
850};
851
852static int rt5640_dac_r2_values[] = {
853 0,
854};
855
856static const SOC_VALUE_ENUM_SINGLE_DECL(
857 rt5640_dac_r2_enum, RT5640_DSP_PATH2, RT5640_DAC_R2_SEL_SFT,
858 0x3, rt5640_dac_r2_src, rt5640_dac_r2_values);
859
860static const struct snd_kcontrol_new rt5640_dac_r2_mux =
861 SOC_DAPM_ENUM("DAC2 right channel source", rt5640_dac_r2_enum);
862
863/* digital interface and iis interface map */
864static const char * const rt5640_dai_iis_map[] = {
865 "1:1|2:2", "1:2|2:1", "1:1|2:1", "1:2|2:2"
866};
867
868static int rt5640_dai_iis_map_values[] = {
869 0,
870 5,
871 6,
872 7,
873};
874
875static const SOC_VALUE_ENUM_SINGLE_DECL(
876 rt5640_dai_iis_map_enum, RT5640_I2S1_SDP, RT5640_I2S_IF_SFT,
877 0x7, rt5640_dai_iis_map, rt5640_dai_iis_map_values);
878
879static const struct snd_kcontrol_new rt5640_dai_mux =
880 SOC_DAPM_VALUE_ENUM("DAI select", rt5640_dai_iis_map_enum);
881
882/* SDI select */
883static const char * const rt5640_sdi_sel[] = {
884 "IF1", "IF2"
885};
886
887static const SOC_ENUM_SINGLE_DECL(
888 rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
889 RT5640_I2S2_SDI_SFT, rt5640_sdi_sel);
890
891static const struct snd_kcontrol_new rt5640_sdi_mux =
892 SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
893
894static int spk_event(struct snd_soc_dapm_widget *w,
895 struct snd_kcontrol *kcontrol, int event)
896{
897 struct snd_soc_codec *codec = w->codec;
898 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
899
900 switch (event) {
901 case SND_SOC_DAPM_POST_PMU:
902 regmap_update_bits(rt5640->regmap, RT5640_PWR_DIG1,
903 0x0001, 0x0001);
904 regmap_update_bits(rt5640->regmap, RT5640_PR_BASE + 0x1c,
905 0xf000, 0xf000);
906 break;
907
908 case SND_SOC_DAPM_PRE_PMD:
909 regmap_update_bits(rt5640->regmap, RT5640_PR_BASE + 0x1c,
910 0xf000, 0x0000);
911 regmap_update_bits(rt5640->regmap, RT5640_PWR_DIG1,
912 0x0001, 0x0000);
913 break;
914
915 default:
916 return 0;
917 }
918 return 0;
919}
920
921static int rt5640_set_dmic1_event(struct snd_soc_dapm_widget *w,
922 struct snd_kcontrol *kcontrol, int event)
923{
924 struct snd_soc_codec *codec = w->codec;
925
926 switch (event) {
927 case SND_SOC_DAPM_PRE_PMU:
928 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
929 RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK,
930 RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP3_PIN_DMIC1_SDA);
931 snd_soc_update_bits(codec, RT5640_DMIC,
932 RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK |
933 RT5640_DMIC_1_DP_MASK,
934 RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING |
935 RT5640_DMIC_1_DP_IN1P);
936 break;
937
938 default:
939 return 0;
940 }
941
942 return 0;
943}
944
945static int rt5640_set_dmic2_event(struct snd_soc_dapm_widget *w,
946 struct snd_kcontrol *kcontrol, int event)
947{
948 struct snd_soc_codec *codec = w->codec;
949
950 switch (event) {
951 case SND_SOC_DAPM_PRE_PMU:
952 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
953 RT5640_GP2_PIN_MASK | RT5640_GP4_PIN_MASK,
954 RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP4_PIN_DMIC2_SDA);
955 snd_soc_update_bits(codec, RT5640_DMIC,
956 RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK |
957 RT5640_DMIC_2_DP_MASK,
958 RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING |
959 RT5640_DMIC_2_DP_IN1N);
960 break;
961
962 default:
963 return 0;
964 }
965
966 return 0;
967}
968
969static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
970 SND_SOC_DAPM_SUPPLY("PLL1", RT5640_PWR_ANLG2,
971 RT5640_PWR_PLL_BIT, 0, NULL, 0),
972 /* Input Side */
973 /* micbias */
974 SND_SOC_DAPM_SUPPLY("LDO2", RT5640_PWR_ANLG1,
975 RT5640_PWR_LDO2_BIT, 0, NULL, 0),
976 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5640_PWR_ANLG2,
977 RT5640_PWR_MB1_BIT, 0, NULL, 0),
978 /* Input Lines */
979 SND_SOC_DAPM_INPUT("DMIC1"),
980 SND_SOC_DAPM_INPUT("DMIC2"),
981 SND_SOC_DAPM_INPUT("IN1P"),
982 SND_SOC_DAPM_INPUT("IN1N"),
983 SND_SOC_DAPM_INPUT("IN2P"),
984 SND_SOC_DAPM_INPUT("IN2N"),
985 SND_SOC_DAPM_PGA("DMIC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
986 SND_SOC_DAPM_PGA("DMIC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
987 SND_SOC_DAPM_PGA("DMIC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
988 SND_SOC_DAPM_PGA("DMIC R2", SND_SOC_NOPM, 0, 0, NULL, 0),
989
990 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
991 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
992 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5640_DMIC,
993 RT5640_DMIC_1_EN_SFT, 0, rt5640_set_dmic1_event,
994 SND_SOC_DAPM_PRE_PMU),
995 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5640_DMIC,
996 RT5640_DMIC_2_EN_SFT, 0, rt5640_set_dmic2_event,
997 SND_SOC_DAPM_PRE_PMU),
998 /* Boost */
999 SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
1000 RT5640_PWR_BST1_BIT, 0, NULL, 0),
1001 SND_SOC_DAPM_PGA("BST2", RT5640_PWR_ANLG2,
1002 RT5640_PWR_BST4_BIT, 0, NULL, 0),
1003 /* Input Volume */
1004 SND_SOC_DAPM_PGA("INL VOL", RT5640_PWR_VOL,
1005 RT5640_PWR_IN_L_BIT, 0, NULL, 0),
1006 SND_SOC_DAPM_PGA("INR VOL", RT5640_PWR_VOL,
1007 RT5640_PWR_IN_R_BIT, 0, NULL, 0),
1008 /* IN Mux */
1009 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt5640_inl_mux),
1010 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt5640_inr_mux),
1011 /* REC Mixer */
1012 SND_SOC_DAPM_MIXER("RECMIXL", RT5640_PWR_MIXER, RT5640_PWR_RM_L_BIT, 0,
1013 rt5640_rec_l_mix, ARRAY_SIZE(rt5640_rec_l_mix)),
1014 SND_SOC_DAPM_MIXER("RECMIXR", RT5640_PWR_MIXER, RT5640_PWR_RM_R_BIT, 0,
1015 rt5640_rec_r_mix, ARRAY_SIZE(rt5640_rec_r_mix)),
1016 /* ADCs */
1017 SND_SOC_DAPM_ADC("ADC L", NULL, RT5640_PWR_DIG1,
1018 RT5640_PWR_ADC_L_BIT, 0),
1019 SND_SOC_DAPM_ADC("ADC R", NULL, RT5640_PWR_DIG1,
1020 RT5640_PWR_ADC_R_BIT, 0),
1021 /* ADC Mux */
1022 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1023 &rt5640_sto_adc_2_mux),
1024 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1025 &rt5640_sto_adc_2_mux),
1026 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1027 &rt5640_sto_adc_1_mux),
1028 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1029 &rt5640_sto_adc_1_mux),
1030 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1031 &rt5640_mono_adc_l2_mux),
1032 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1033 &rt5640_mono_adc_l1_mux),
1034 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1035 &rt5640_mono_adc_r1_mux),
1036 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1037 &rt5640_mono_adc_r2_mux),
1038 /* ADC Mixer */
1039 SND_SOC_DAPM_SUPPLY("Stereo Filter", RT5640_PWR_DIG2,
1040 RT5640_PWR_ADC_SF_BIT, 0, NULL, 0),
1041 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
1042 rt5640_sto_adc_l_mix, ARRAY_SIZE(rt5640_sto_adc_l_mix)),
1043 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
1044 rt5640_sto_adc_r_mix, ARRAY_SIZE(rt5640_sto_adc_r_mix)),
1045 SND_SOC_DAPM_SUPPLY("Mono Left Filter", RT5640_PWR_DIG2,
1046 RT5640_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1047 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1048 rt5640_mono_adc_l_mix, ARRAY_SIZE(rt5640_mono_adc_l_mix)),
1049 SND_SOC_DAPM_SUPPLY("Mono Right Filter", RT5640_PWR_DIG2,
1050 RT5640_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1051 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1052 rt5640_mono_adc_r_mix, ARRAY_SIZE(rt5640_mono_adc_r_mix)),
1053
1054 /* Digital Interface */
1055 SND_SOC_DAPM_SUPPLY("I2S1", RT5640_PWR_DIG1,
1056 RT5640_PWR_I2S1_BIT, 0, NULL, 0),
1057 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1058 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1059 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1060 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1061 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1062 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1063 SND_SOC_DAPM_SUPPLY("I2S2", RT5640_PWR_DIG1,
1064 RT5640_PWR_I2S2_BIT, 0, NULL, 0),
1065 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1066 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1067 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1068 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1069 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1070 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1071 /* Digital Interface Select */
1072 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1073 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1074 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1075 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1076 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1077 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1078 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1079 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1080 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1081 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1082 /* Audio Interface */
1083 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1084 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1085 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1086 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1087 /* Audio DSP */
1088 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1089 /* ANC */
1090 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
1091 /* Output Side */
1092 /* DAC mixer before sound effect */
1093 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1094 rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
1095 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1096 rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
1097 /* DAC2 channel Mux */
1098 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1099 &rt5640_dac_l2_mux),
1100 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1101 &rt5640_dac_r2_mux),
1102 /* DAC Mixer */
1103 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1104 rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
1105 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1106 rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
1107 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1108 rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
1109 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1110 rt5640_mono_dac_r_mix, ARRAY_SIZE(rt5640_mono_dac_r_mix)),
1111 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
1112 rt5640_dig_l_mix, ARRAY_SIZE(rt5640_dig_l_mix)),
1113 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
1114 rt5640_dig_r_mix, ARRAY_SIZE(rt5640_dig_r_mix)),
1115 /* DACs */
1116 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5640_PWR_DIG1,
1117 RT5640_PWR_DAC_L1_BIT, 0),
1118 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5640_PWR_DIG1,
1119 RT5640_PWR_DAC_L2_BIT, 0),
1120 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5640_PWR_DIG1,
1121 RT5640_PWR_DAC_R1_BIT, 0),
1122 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5640_PWR_DIG1,
1123 RT5640_PWR_DAC_R2_BIT, 0),
1124 /* SPK/OUT Mixer */
1125 SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
1126 0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
1127 SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
1128 0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
1129 SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1130 0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
1131 SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1132 0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
1133 /* Ouput Volume */
1134 SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
1135 RT5640_PWR_SV_L_BIT, 0, NULL, 0),
1136 SND_SOC_DAPM_PGA("SPKVOL R", RT5640_PWR_VOL,
1137 RT5640_PWR_SV_R_BIT, 0, NULL, 0),
1138 SND_SOC_DAPM_PGA("OUTVOL L", RT5640_PWR_VOL,
1139 RT5640_PWR_OV_L_BIT, 0, NULL, 0),
1140 SND_SOC_DAPM_PGA("OUTVOL R", RT5640_PWR_VOL,
1141 RT5640_PWR_OV_R_BIT, 0, NULL, 0),
1142 SND_SOC_DAPM_PGA("HPOVOL L", RT5640_PWR_VOL,
1143 RT5640_PWR_HV_L_BIT, 0, NULL, 0),
1144 SND_SOC_DAPM_PGA("HPOVOL R", RT5640_PWR_VOL,
1145 RT5640_PWR_HV_R_BIT, 0, NULL, 0),
1146 /* SPO/HPO/LOUT/Mono Mixer */
1147 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
1148 0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
1149 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
1150 0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
1151 SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1152 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1153 SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1154 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1155 SND_SOC_DAPM_MIXER("LOUT MIX", RT5640_PWR_ANLG1, RT5640_PWR_LM_BIT, 0,
1156 rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
1157 SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
1158 rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
1159 SND_SOC_DAPM_SUPPLY("Improve MONO Amp Drv", RT5640_PWR_ANLG1,
1160 RT5640_PWR_MA_BIT, 0, NULL, 0),
1161 SND_SOC_DAPM_SUPPLY("Improve HP Amp Drv", RT5640_PWR_ANLG1,
1162 SND_SOC_NOPM, 0, NULL, 0),
1163 SND_SOC_DAPM_PGA("HP L Amp", RT5640_PWR_ANLG1,
1164 RT5640_PWR_HP_L_BIT, 0, NULL, 0),
1165 SND_SOC_DAPM_PGA("HP R Amp", RT5640_PWR_ANLG1,
1166 RT5640_PWR_HP_R_BIT, 0, NULL, 0),
1167 SND_SOC_DAPM_SUPPLY("Improve SPK Amp Drv", RT5640_PWR_DIG1,
1168 SND_SOC_NOPM, 0, spk_event,
1169 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1170 /* Output Lines */
1171 SND_SOC_DAPM_OUTPUT("SPOLP"),
1172 SND_SOC_DAPM_OUTPUT("SPOLN"),
1173 SND_SOC_DAPM_OUTPUT("SPORP"),
1174 SND_SOC_DAPM_OUTPUT("SPORN"),
1175 SND_SOC_DAPM_OUTPUT("HPOL"),
1176 SND_SOC_DAPM_OUTPUT("HPOR"),
1177 SND_SOC_DAPM_OUTPUT("LOUTL"),
1178 SND_SOC_DAPM_OUTPUT("LOUTR"),
1179 SND_SOC_DAPM_OUTPUT("MONOP"),
1180 SND_SOC_DAPM_OUTPUT("MONON"),
1181};
1182
1183static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1184 {"IN1P", NULL, "LDO2"},
1185 {"IN2P", NULL, "LDO2"},
1186
1187 {"DMIC L1", NULL, "DMIC1"},
1188 {"DMIC R1", NULL, "DMIC1"},
1189 {"DMIC L2", NULL, "DMIC2"},
1190 {"DMIC R2", NULL, "DMIC2"},
1191
1192 {"BST1", NULL, "IN1P"},
1193 {"BST1", NULL, "IN1N"},
1194 {"BST2", NULL, "IN2P"},
1195 {"BST2", NULL, "IN2N"},
1196
1197 {"INL VOL", NULL, "IN2P"},
1198 {"INR VOL", NULL, "IN2N"},
1199
1200 {"RECMIXL", "HPOL Switch", "HPOL"},
1201 {"RECMIXL", "INL Switch", "INL VOL"},
1202 {"RECMIXL", "BST2 Switch", "BST2"},
1203 {"RECMIXL", "BST1 Switch", "BST1"},
1204 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
1205
1206 {"RECMIXR", "HPOR Switch", "HPOR"},
1207 {"RECMIXR", "INR Switch", "INR VOL"},
1208 {"RECMIXR", "BST2 Switch", "BST2"},
1209 {"RECMIXR", "BST1 Switch", "BST1"},
1210 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
1211
1212 {"ADC L", NULL, "RECMIXL"},
1213 {"ADC R", NULL, "RECMIXR"},
1214
1215 {"DMIC L1", NULL, "DMIC CLK"},
1216 {"DMIC L1", NULL, "DMIC1 Power"},
1217 {"DMIC R1", NULL, "DMIC CLK"},
1218 {"DMIC R1", NULL, "DMIC1 Power"},
1219 {"DMIC L2", NULL, "DMIC CLK"},
1220 {"DMIC L2", NULL, "DMIC2 Power"},
1221 {"DMIC R2", NULL, "DMIC CLK"},
1222 {"DMIC R2", NULL, "DMIC2 Power"},
1223
1224 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
1225 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
1226 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
1227 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
1228 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
1229
1230 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
1231 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
1232 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
1233 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
1234 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
1235
1236 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
1237 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
1238 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1239 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1240 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
1241
1242 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1243 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
1244 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
1245 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
1246 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1247
1248 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
1249 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
1250 {"Stereo ADC MIXL", NULL, "Stereo Filter"},
1251 {"Stereo Filter", NULL, "PLL1", check_sysclk1_source},
1252
1253 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
1254 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
1255 {"Stereo ADC MIXR", NULL, "Stereo Filter"},
1256 {"Stereo Filter", NULL, "PLL1", check_sysclk1_source},
1257
1258 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
1259 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
1260 {"Mono ADC MIXL", NULL, "Mono Left Filter"},
1261 {"Mono Left Filter", NULL, "PLL1", check_sysclk1_source},
1262
1263 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
1264 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
1265 {"Mono ADC MIXR", NULL, "Mono Right Filter"},
1266 {"Mono Right Filter", NULL, "PLL1", check_sysclk1_source},
1267
1268 {"IF2 ADC L", NULL, "Mono ADC MIXL"},
1269 {"IF2 ADC R", NULL, "Mono ADC MIXR"},
1270 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
1271 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
1272
1273 {"IF1 ADC", NULL, "I2S1"},
1274 {"IF1 ADC", NULL, "IF1 ADC L"},
1275 {"IF1 ADC", NULL, "IF1 ADC R"},
1276 {"IF2 ADC", NULL, "I2S2"},
1277 {"IF2 ADC", NULL, "IF2 ADC L"},
1278 {"IF2 ADC", NULL, "IF2 ADC R"},
1279
1280 {"DAI1 TX Mux", "1:1|2:2", "IF1 ADC"},
1281 {"DAI1 TX Mux", "1:2|2:1", "IF2 ADC"},
1282 {"DAI1 IF1 Mux", "1:1|2:1", "IF1 ADC"},
1283 {"DAI1 IF2 Mux", "1:1|2:1", "IF2 ADC"},
1284 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
1285 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
1286
1287 {"DAI2 TX Mux", "1:2|2:1", "IF1 ADC"},
1288 {"DAI2 TX Mux", "1:1|2:2", "IF2 ADC"},
1289 {"DAI2 IF1 Mux", "1:2|2:2", "IF1 ADC"},
1290 {"DAI2 IF2 Mux", "1:2|2:2", "IF2 ADC"},
1291 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
1292 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
1293
1294 {"AIF1TX", NULL, "DAI1 TX Mux"},
1295 {"AIF1TX", NULL, "SDI1 TX Mux"},
1296 {"AIF2TX", NULL, "DAI2 TX Mux"},
1297 {"AIF2TX", NULL, "SDI2 TX Mux"},
1298
1299 {"DAI1 RX Mux", "1:1|2:2", "AIF1RX"},
1300 {"DAI1 RX Mux", "1:1|2:1", "AIF1RX"},
1301 {"DAI1 RX Mux", "1:2|2:1", "AIF2RX"},
1302 {"DAI1 RX Mux", "1:2|2:2", "AIF2RX"},
1303
1304 {"DAI2 RX Mux", "1:2|2:1", "AIF1RX"},
1305 {"DAI2 RX Mux", "1:1|2:1", "AIF1RX"},
1306 {"DAI2 RX Mux", "1:1|2:2", "AIF2RX"},
1307 {"DAI2 RX Mux", "1:2|2:2", "AIF2RX"},
1308
1309 {"IF1 DAC", NULL, "I2S1"},
1310 {"IF1 DAC", NULL, "DAI1 RX Mux"},
1311 {"IF2 DAC", NULL, "I2S2"},
1312 {"IF2 DAC", NULL, "DAI2 RX Mux"},
1313
1314 {"IF1 DAC L", NULL, "IF1 DAC"},
1315 {"IF1 DAC R", NULL, "IF1 DAC"},
1316 {"IF2 DAC L", NULL, "IF2 DAC"},
1317 {"IF2 DAC R", NULL, "IF2 DAC"},
1318
1319 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
1320 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
1321 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
1322 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
1323
1324 {"ANC", NULL, "Stereo ADC MIXL"},
1325 {"ANC", NULL, "Stereo ADC MIXR"},
1326
1327 {"Audio DSP", NULL, "DAC MIXL"},
1328 {"Audio DSP", NULL, "DAC MIXR"},
1329
1330 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1331 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
1332
1333 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1334
1335 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1336 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1337 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
1338 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1339 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1340 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
1341
1342 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1343 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1344 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1345 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1346 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1347 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1348
1349 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
1350 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1351 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
1352 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1353
1354 {"DAC L1", NULL, "Stereo DAC MIXL"},
1355 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
1356 {"DAC R1", NULL, "Stereo DAC MIXR"},
1357 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
1358 {"DAC L2", NULL, "Mono DAC MIXL"},
1359 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
1360 {"DAC R2", NULL, "Mono DAC MIXR"},
1361 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
1362
1363 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
1364 {"SPK MIXL", "INL Switch", "INL VOL"},
1365 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
1366 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1367 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
1368 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
1369 {"SPK MIXR", "INR Switch", "INR VOL"},
1370 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
1371 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1372 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
1373
1374 {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
1375 {"OUT MIXL", "BST1 Switch", "BST1"},
1376 {"OUT MIXL", "INL Switch", "INL VOL"},
1377 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1378 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1379 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1380 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1381
1382 {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
1383 {"OUT MIXR", "BST2 Switch", "BST2"},
1384 {"OUT MIXR", "BST1 Switch", "BST1"},
1385 {"OUT MIXR", "INR Switch", "INR VOL"},
1386 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1387 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1388 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1389 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1390
1391 {"SPKVOL L", NULL, "SPK MIXL"},
1392 {"SPKVOL R", NULL, "SPK MIXR"},
1393 {"HPOVOL L", NULL, "OUT MIXL"},
1394 {"HPOVOL R", NULL, "OUT MIXR"},
1395 {"OUTVOL L", NULL, "OUT MIXL"},
1396 {"OUTVOL R", NULL, "OUT MIXR"},
1397
1398 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
1399 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
1400 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
1401 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
1402 {"SPOL MIX", "BST1 Switch", "BST1"},
1403 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
1404 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
1405 {"SPOR MIX", "BST1 Switch", "BST1"},
1406
1407 {"HPO MIX L", "HPO MIX DAC2 Switch", "DAC L2"},
1408 {"HPO MIX L", "HPO MIX DAC1 Switch", "DAC L1"},
1409 {"HPO MIX L", "HPO MIX HPVOL Switch", "HPOVOL L"},
1410 {"HPO MIX R", "HPO MIX DAC2 Switch", "DAC R2"},
1411 {"HPO MIX R", "HPO MIX DAC1 Switch", "DAC R1"},
1412 {"HPO MIX R", "HPO MIX HPVOL Switch", "HPOVOL R"},
1413
1414 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1415 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1416 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1417 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1418
1419 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1420 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1421 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
1422 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
1423 {"Mono MIX", "BST1 Switch", "BST1"},
1424
1425 {"HP L Amp", NULL, "HPO MIX L"},
1426 {"HP R Amp", NULL, "HPO MIX R"},
1427
1428 {"SPOLP", NULL, "SPOL MIX"},
1429 {"SPOLN", NULL, "SPOL MIX"},
1430 {"SPORP", NULL, "SPOR MIX"},
1431 {"SPORN", NULL, "SPOR MIX"},
1432
1433 {"SPOLP", NULL, "Improve SPK Amp Drv"},
1434 {"SPOLN", NULL, "Improve SPK Amp Drv"},
1435 {"SPORP", NULL, "Improve SPK Amp Drv"},
1436 {"SPORN", NULL, "Improve SPK Amp Drv"},
1437
1438 {"HPOL", NULL, "Improve HP Amp Drv"},
1439 {"HPOR", NULL, "Improve HP Amp Drv"},
1440
1441 {"HPOL", NULL, "HP L Amp"},
1442 {"HPOR", NULL, "HP R Amp"},
1443 {"LOUTL", NULL, "LOUT MIX"},
1444 {"LOUTR", NULL, "LOUT MIX"},
1445 {"MONOP", NULL, "Mono MIX"},
1446 {"MONON", NULL, "Mono MIX"},
1447 {"MONOP", NULL, "Improve MONO Amp Drv"},
1448};
1449
1450static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
1451{
1452 int ret = 0, val;
1453
1454 if (codec == NULL)
1455 return -EINVAL;
1456
1457 val = snd_soc_read(codec, RT5640_I2S1_SDP);
1458 val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT;
1459 switch (dai_id) {
1460 case RT5640_AIF1:
1461 switch (val) {
1462 case RT5640_IF_123:
1463 case RT5640_IF_132:
1464 ret |= RT5640_U_IF1;
1465 break;
1466 case RT5640_IF_113:
1467 ret |= RT5640_U_IF1;
1468 case RT5640_IF_312:
1469 case RT5640_IF_213:
1470 ret |= RT5640_U_IF2;
1471 break;
1472 }
1473 break;
1474
1475 case RT5640_AIF2:
1476 switch (val) {
1477 case RT5640_IF_231:
1478 case RT5640_IF_213:
1479 ret |= RT5640_U_IF1;
1480 break;
1481 case RT5640_IF_223:
1482 ret |= RT5640_U_IF1;
1483 case RT5640_IF_123:
1484 case RT5640_IF_321:
1485 ret |= RT5640_U_IF2;
1486 break;
1487 }
1488 break;
1489
1490 default:
1491 ret = -EINVAL;
1492 break;
1493 }
1494
1495 return ret;
1496}
1497
1498static int get_clk_info(int sclk, int rate)
1499{
1500 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1501
1502 if (sclk <= 0 || rate <= 0)
1503 return -EINVAL;
1504
1505 rate = rate << 8;
1506 for (i = 0; i < ARRAY_SIZE(pd); i++)
1507 if (sclk == rate * pd[i])
1508 return i;
1509
1510 return -EINVAL;
1511}
1512
1513static int rt5640_hw_params(struct snd_pcm_substream *substream,
1514 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1515{
1516 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1517 struct snd_soc_codec *codec = rtd->codec;
1518 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1519 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
1520 int pre_div, bclk_ms, frame_size;
1521
1522 rt5640->lrck[dai->id] = params_rate(params);
1523 pre_div = get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
1524 if (pre_div < 0) {
1525 dev_err(codec->dev, "Unsupported clock setting\n");
1526 return -EINVAL;
1527 }
1528 frame_size = snd_soc_params_to_frame_size(params);
1529 if (frame_size < 0) {
1530 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1531 return frame_size;
1532 }
1533 if (frame_size > 32)
1534 bclk_ms = 1;
1535 else
1536 bclk_ms = 0;
1537 rt5640->bclk[dai->id] = rt5640->lrck[dai->id] * (32 << bclk_ms);
1538
1539 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1540 rt5640->bclk[dai->id], rt5640->lrck[dai->id]);
1541 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1542 bclk_ms, pre_div, dai->id);
1543
1544 switch (params_format(params)) {
1545 case SNDRV_PCM_FORMAT_S16_LE:
1546 break;
1547 case SNDRV_PCM_FORMAT_S20_3LE:
1548 val_len |= RT5640_I2S_DL_20;
1549 break;
1550 case SNDRV_PCM_FORMAT_S24_LE:
1551 val_len |= RT5640_I2S_DL_24;
1552 break;
1553 case SNDRV_PCM_FORMAT_S8:
1554 val_len |= RT5640_I2S_DL_8;
1555 break;
1556 default:
1557 return -EINVAL;
1558 }
1559
1560 dai_sel = get_sdp_info(codec, dai->id);
1561 if (dai_sel < 0) {
1562 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
1563 return -EINVAL;
1564 }
1565 if (dai_sel & RT5640_U_IF1) {
1566 mask_clk = RT5640_I2S_BCLK_MS1_MASK | RT5640_I2S_PD1_MASK;
1567 val_clk = bclk_ms << RT5640_I2S_BCLK_MS1_SFT |
1568 pre_div << RT5640_I2S_PD1_SFT;
1569 snd_soc_update_bits(codec, RT5640_I2S1_SDP,
1570 RT5640_I2S_DL_MASK, val_len);
1571 snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
1572 }
1573 if (dai_sel & RT5640_U_IF2) {
1574 mask_clk = RT5640_I2S_BCLK_MS2_MASK | RT5640_I2S_PD2_MASK;
1575 val_clk = bclk_ms << RT5640_I2S_BCLK_MS2_SFT |
1576 pre_div << RT5640_I2S_PD2_SFT;
1577 snd_soc_update_bits(codec, RT5640_I2S2_SDP,
1578 RT5640_I2S_DL_MASK, val_len);
1579 snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
1580 }
1581
1582 return 0;
1583}
1584
1585static int rt5640_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1586{
1587 struct snd_soc_codec *codec = dai->codec;
1588 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1589 unsigned int reg_val = 0, dai_sel;
1590
1591 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1592 case SND_SOC_DAIFMT_CBM_CFM:
1593 rt5640->master[dai->id] = 1;
1594 break;
1595 case SND_SOC_DAIFMT_CBS_CFS:
1596 reg_val |= RT5640_I2S_MS_S;
1597 rt5640->master[dai->id] = 0;
1598 break;
1599 default:
1600 return -EINVAL;
1601 }
1602
1603 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1604 case SND_SOC_DAIFMT_NB_NF:
1605 break;
1606 case SND_SOC_DAIFMT_IB_NF:
1607 reg_val |= RT5640_I2S_BP_INV;
1608 break;
1609 default:
1610 return -EINVAL;
1611 }
1612
1613 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1614 case SND_SOC_DAIFMT_I2S:
1615 break;
1616 case SND_SOC_DAIFMT_LEFT_J:
1617 reg_val |= RT5640_I2S_DF_LEFT;
1618 break;
1619 case SND_SOC_DAIFMT_DSP_A:
1620 reg_val |= RT5640_I2S_DF_PCM_A;
1621 break;
1622 case SND_SOC_DAIFMT_DSP_B:
1623 reg_val |= RT5640_I2S_DF_PCM_B;
1624 break;
1625 default:
1626 return -EINVAL;
1627 }
1628
1629 dai_sel = get_sdp_info(codec, dai->id);
1630 if (dai_sel < 0) {
1631 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
1632 return -EINVAL;
1633 }
1634 if (dai_sel & RT5640_U_IF1) {
1635 snd_soc_update_bits(codec, RT5640_I2S1_SDP,
1636 RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1637 RT5640_I2S_DF_MASK, reg_val);
1638 }
1639 if (dai_sel & RT5640_U_IF2) {
1640 snd_soc_update_bits(codec, RT5640_I2S2_SDP,
1641 RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1642 RT5640_I2S_DF_MASK, reg_val);
1643 }
1644
1645 return 0;
1646}
1647
1648static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
1649 int clk_id, unsigned int freq, int dir)
1650{
1651 struct snd_soc_codec *codec = dai->codec;
1652 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1653 unsigned int reg_val = 0;
1654
1655 if (freq == rt5640->sysclk && clk_id == rt5640->sysclk_src)
1656 return 0;
1657
1658 switch (clk_id) {
1659 case RT5640_SCLK_S_MCLK:
1660 reg_val |= RT5640_SCLK_SRC_MCLK;
1661 break;
1662 case RT5640_SCLK_S_PLL1:
1663 reg_val |= RT5640_SCLK_SRC_PLL1;
1664 break;
1665 case RT5640_SCLK_S_PLL1_TK:
1666 reg_val |= RT5640_SCLK_SRC_PLL1T;
1667 break;
1668 case RT5640_SCLK_S_RCCLK:
1669 reg_val |= RT5640_SCLK_SRC_RCCLK;
1670 break;
1671 default:
1672 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1673 return -EINVAL;
1674 }
1675 snd_soc_update_bits(codec, RT5640_GLB_CLK,
1676 RT5640_SCLK_SRC_MASK, reg_val);
1677 rt5640->sysclk = freq;
1678 rt5640->sysclk_src = clk_id;
1679
1680 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1681 return 0;
1682}
1683
1684/**
1685 * rt5640_pll_calc - Calculate PLL M/N/K code.
1686 * @freq_in: external clock provided to codec.
1687 * @freq_out: target clock which codec works on.
1688 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1689 *
1690 * Calculate M/N/K code to configure PLL for codec. And K is assigned to 2
1691 * which make calculation more efficiently.
1692 *
1693 * Returns 0 for success or negative error code.
1694 */
1695static int rt5640_pll_calc(const unsigned int freq_in,
1696 const unsigned int freq_out, struct rt5640_pll_code *pll_code)
1697{
1698 int max_n = RT5640_PLL_N_MAX, max_m = RT5640_PLL_M_MAX;
1699 int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
1700 int red_t = abs(freq_out - freq_in);
1701 bool bypass = false;
1702
1703 if (RT5640_PLL_INP_MAX < freq_in || RT5640_PLL_INP_MIN > freq_in)
1704 return -EINVAL;
1705
1706 for (n_t = 0; n_t <= max_n; n_t++) {
1707 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
1708 if (in_t < 0)
1709 continue;
1710 if (in_t == freq_out) {
1711 bypass = true;
1712 n = n_t;
1713 goto code_find;
1714 }
1715 for (m_t = 0; m_t <= max_m; m_t++) {
1716 out_t = in_t / (m_t + 2);
1717 red = abs(out_t - freq_out);
1718 if (red < red_t) {
1719 n = n_t;
1720 m = m_t;
1721 if (red == 0)
1722 goto code_find;
1723 red_t = red;
1724 }
1725 }
1726 }
1727 pr_debug("Only get approximation about PLL\n");
1728
1729code_find:
1730 pll_code->m_bp = bypass;
1731 pll_code->m_code = m;
1732 pll_code->n_code = n;
1733 pll_code->k_code = 2;
1734 return 0;
1735}
1736
1737static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1738 unsigned int freq_in, unsigned int freq_out)
1739{
1740 struct snd_soc_codec *codec = dai->codec;
1741 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1742 struct rt5640_pll_code *pll_code = &rt5640->pll_code;
1743 int ret, dai_sel;
1744
1745 if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
1746 freq_out == rt5640->pll_out)
1747 return 0;
1748
1749 if (!freq_in || !freq_out) {
1750 dev_dbg(codec->dev, "PLL disabled\n");
1751
1752 rt5640->pll_in = 0;
1753 rt5640->pll_out = 0;
1754 snd_soc_update_bits(codec, RT5640_GLB_CLK,
1755 RT5640_SCLK_SRC_MASK, RT5640_SCLK_SRC_MCLK);
1756 return 0;
1757 }
1758
1759 switch (source) {
1760 case RT5640_PLL1_S_MCLK:
1761 snd_soc_update_bits(codec, RT5640_GLB_CLK,
1762 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_MCLK);
1763 break;
1764 case RT5640_PLL1_S_BCLK1:
1765 case RT5640_PLL1_S_BCLK2:
1766 dai_sel = get_sdp_info(codec, dai->id);
1767 if (dai_sel < 0) {
1768 dev_err(codec->dev,
1769 "Failed to get sdp info: %d\n", dai_sel);
1770 return -EINVAL;
1771 }
1772 if (dai_sel & RT5640_U_IF1) {
1773 snd_soc_update_bits(codec, RT5640_GLB_CLK,
1774 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK1);
1775 }
1776 if (dai_sel & RT5640_U_IF2) {
1777 snd_soc_update_bits(codec, RT5640_GLB_CLK,
1778 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK2);
1779 }
1780 break;
1781 default:
1782 dev_err(codec->dev, "Unknown PLL source %d\n", source);
1783 return -EINVAL;
1784 }
1785
1786 ret = rt5640_pll_calc(freq_in, freq_out, pll_code);
1787 if (ret < 0) {
1788 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1789 return ret;
1790 }
1791
1792 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp,
1793 (pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code);
1794
1795 snd_soc_write(codec, RT5640_PLL_CTRL1,
1796 pll_code->n_code << RT5640_PLL_N_SFT | pll_code->k_code);
1797 snd_soc_write(codec, RT5640_PLL_CTRL2,
1798 (pll_code->m_bp ? 0 : pll_code->m_code) << RT5640_PLL_M_SFT |
1799 pll_code->m_bp << RT5640_PLL_M_BP_SFT);
1800
1801 rt5640->pll_in = freq_in;
1802 rt5640->pll_out = freq_out;
1803 rt5640->pll_src = source;
1804
1805 return 0;
1806}
1807
1808static int rt5640_set_bias_level(struct snd_soc_codec *codec,
1809 enum snd_soc_bias_level level)
1810{
1811 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1812 switch (level) {
1813 case SND_SOC_BIAS_STANDBY:
1814 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
1815 regcache_cache_only(rt5640->regmap, false);
1816 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
1817 RT5640_PWR_VREF1 | RT5640_PWR_MB |
1818 RT5640_PWR_BG | RT5640_PWR_VREF2,
1819 RT5640_PWR_VREF1 | RT5640_PWR_MB |
1820 RT5640_PWR_BG | RT5640_PWR_VREF2);
1821 mdelay(10);
1822 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
1823 RT5640_PWR_FV1 | RT5640_PWR_FV2,
1824 RT5640_PWR_FV1 | RT5640_PWR_FV2);
1825 regcache_sync(rt5640->regmap);
1826 snd_soc_update_bits(codec, RT5640_DUMMY1,
1827 0x0301, 0x0301);
1828 snd_soc_update_bits(codec, RT5640_DEPOP_M1,
1829 0x001d, 0x0019);
1830 snd_soc_update_bits(codec, RT5640_DEPOP_M2,
1831 0x2000, 0x2000);
1832 snd_soc_update_bits(codec, RT5640_MICBIAS,
1833 0x0030, 0x0030);
1834 }
1835 break;
1836
1837 case SND_SOC_BIAS_OFF:
1838 snd_soc_write(codec, RT5640_DEPOP_M1, 0x0004);
1839 snd_soc_write(codec, RT5640_DEPOP_M2, 0x1100);
1840 snd_soc_update_bits(codec, RT5640_DUMMY1, 0x1, 0);
1841 snd_soc_write(codec, RT5640_PWR_DIG1, 0x0000);
1842 snd_soc_write(codec, RT5640_PWR_DIG2, 0x0000);
1843 snd_soc_write(codec, RT5640_PWR_VOL, 0x0000);
1844 snd_soc_write(codec, RT5640_PWR_MIXER, 0x0000);
1845 snd_soc_write(codec, RT5640_PWR_ANLG1, 0x0000);
1846 snd_soc_write(codec, RT5640_PWR_ANLG2, 0x0000);
1847 break;
1848
1849 default:
1850 break;
1851 }
1852 codec->dapm.bias_level = level;
1853
1854 return 0;
1855}
1856
1857static int rt5640_probe(struct snd_soc_codec *codec)
1858{
1859 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1860 int ret;
1861
1862 rt5640->codec = codec;
1863 codec->control_data = rt5640->regmap;
1864
1865 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1866 if (ret != 0) {
1867 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1868 return ret;
1869 }
1870
1871 codec->dapm.idle_bias_off = 1;
1872 rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
1873
1874 snd_soc_update_bits(codec, RT5640_DUMMY1, 0x0301, 0x0301);
1875 snd_soc_update_bits(codec, RT5640_DEPOP_M1, 0x001d, 0x0019);
1876 snd_soc_update_bits(codec, RT5640_DEPOP_M2, 0x2000, 0x2000);
1877 snd_soc_update_bits(codec, RT5640_MICBIAS, 0x0030, 0x0030);
1878 snd_soc_update_bits(codec, RT5640_DSP_PATH2, 0xfc00, 0x0c00);
1879
1880 return 0;
1881}
1882
1883static int rt5640_remove(struct snd_soc_codec *codec)
1884{
1885 rt5640_reset(codec);
1886
1887 return 0;
1888}
1889
1890#ifdef CONFIG_PM
1891static int rt5640_suspend(struct snd_soc_codec *codec)
1892{
1893 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1894
1895 rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
1896 rt5640_reset(codec);
1897 regcache_cache_only(rt5640->regmap, true);
1898 regcache_mark_dirty(rt5640->regmap);
1899
1900 return 0;
1901}
1902
1903static int rt5640_resume(struct snd_soc_codec *codec)
1904{
1905 rt5640_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1906
1907 return 0;
1908}
1909#else
1910#define rt5640_suspend NULL
1911#define rt5640_resume NULL
1912#endif
1913
1914#define RT5640_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1915#define RT5640_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1916 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1917
1918static const struct snd_soc_dai_ops rt5640_aif_dai_ops = {
1919 .hw_params = rt5640_hw_params,
1920 .set_fmt = rt5640_set_dai_fmt,
1921 .set_sysclk = rt5640_set_dai_sysclk,
1922 .set_pll = rt5640_set_dai_pll,
1923};
1924
1925static struct snd_soc_dai_driver rt5640_dai[] = {
1926 {
1927 .name = "rt5640-aif1",
1928 .id = RT5640_AIF1,
1929 .playback = {
1930 .stream_name = "AIF1 Playback",
1931 .channels_min = 1,
1932 .channels_max = 2,
1933 .rates = RT5640_STEREO_RATES,
1934 .formats = RT5640_FORMATS,
1935 },
1936 .capture = {
1937 .stream_name = "AIF1 Capture",
1938 .channels_min = 1,
1939 .channels_max = 2,
1940 .rates = RT5640_STEREO_RATES,
1941 .formats = RT5640_FORMATS,
1942 },
1943 .ops = &rt5640_aif_dai_ops,
1944 },
1945 {
1946 .name = "rt5640-aif2",
1947 .id = RT5640_AIF2,
1948 .playback = {
1949 .stream_name = "AIF2 Playback",
1950 .channels_min = 1,
1951 .channels_max = 2,
1952 .rates = RT5640_STEREO_RATES,
1953 .formats = RT5640_FORMATS,
1954 },
1955 .capture = {
1956 .stream_name = "AIF2 Capture",
1957 .channels_min = 1,
1958 .channels_max = 2,
1959 .rates = RT5640_STEREO_RATES,
1960 .formats = RT5640_FORMATS,
1961 },
1962 .ops = &rt5640_aif_dai_ops,
1963 },
1964};
1965
1966static struct snd_soc_codec_driver soc_codec_dev_rt5640 = {
1967 .probe = rt5640_probe,
1968 .remove = rt5640_remove,
1969 .suspend = rt5640_suspend,
1970 .resume = rt5640_resume,
1971 .set_bias_level = rt5640_set_bias_level,
1972 .controls = rt5640_snd_controls,
1973 .num_controls = ARRAY_SIZE(rt5640_snd_controls),
1974 .dapm_widgets = rt5640_dapm_widgets,
1975 .num_dapm_widgets = ARRAY_SIZE(rt5640_dapm_widgets),
1976 .dapm_routes = rt5640_dapm_routes,
1977 .num_dapm_routes = ARRAY_SIZE(rt5640_dapm_routes),
1978};
1979
1980static const struct regmap_config rt5640_regmap = {
1981 .reg_bits = 8,
1982 .val_bits = 16,
1983
1984 .max_register = RT5640_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5640_ranges) *
1985 RT5640_PR_SPACING),
1986 .volatile_reg = rt5640_volatile_register,
1987 .readable_reg = rt5640_readable_register,
1988
1989 .cache_type = REGCACHE_RBTREE,
1990 .reg_defaults = rt5640_reg,
1991 .num_reg_defaults = ARRAY_SIZE(rt5640_reg),
1992 .ranges = rt5640_ranges,
1993 .num_ranges = ARRAY_SIZE(rt5640_ranges),
1994};
1995
1996static const struct i2c_device_id rt5640_i2c_id[] = {
1997 { "rt5640", 0 },
1998 { }
1999};
2000MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
2001
2002static int rt5640_parse_dt(struct rt5640_priv *rt5640, struct device_node *np)
2003{
2004 rt5640->pdata.in1_diff = of_property_read_bool(np,
2005 "realtek,in1-differential");
2006 rt5640->pdata.in2_diff = of_property_read_bool(np,
2007 "realtek,in2-differential");
2008
2009 rt5640->pdata.ldo1_en = of_get_named_gpio(np,
2010 "realtek,ldo1-en-gpios", 0);
2011 /*
2012 * LDO1_EN is optional (it may be statically tied on the board).
2013 * -ENOENT means that the property doesn't exist, i.e. there is no
2014 * GPIO, so is not an error. Any other error code means the property
2015 * exists, but could not be parsed.
2016 */
2017 if (!gpio_is_valid(rt5640->pdata.ldo1_en) &&
2018 (rt5640->pdata.ldo1_en != -ENOENT))
2019 return rt5640->pdata.ldo1_en;
2020
2021 return 0;
2022}
2023
2024static int rt5640_i2c_probe(struct i2c_client *i2c,
2025 const struct i2c_device_id *id)
2026{
2027 struct rt5640_platform_data *pdata = dev_get_platdata(&i2c->dev);
2028 struct rt5640_priv *rt5640;
2029 int ret;
2030 unsigned int val;
2031
2032 rt5640 = devm_kzalloc(&i2c->dev,
2033 sizeof(struct rt5640_priv),
2034 GFP_KERNEL);
2035 if (NULL == rt5640)
2036 return -ENOMEM;
2037 i2c_set_clientdata(i2c, rt5640);
2038
2039 if (pdata) {
2040 rt5640->pdata = *pdata;
2041 /*
2042 * Translate zero'd out (default) pdata value to an invalid
2043 * GPIO ID. This makes the pdata and DT paths consistent in
2044 * terms of the value left in this field when no GPIO is
2045 * specified, but means we can't actually use GPIO 0.
2046 */
2047 if (!rt5640->pdata.ldo1_en)
2048 rt5640->pdata.ldo1_en = -EINVAL;
2049 } else if (i2c->dev.of_node) {
2050 ret = rt5640_parse_dt(rt5640, i2c->dev.of_node);
2051 if (ret)
2052 return ret;
2053 } else
2054 rt5640->pdata.ldo1_en = -EINVAL;
2055
2056 rt5640->regmap = devm_regmap_init_i2c(i2c, &rt5640_regmap);
2057 if (IS_ERR(rt5640->regmap)) {
2058 ret = PTR_ERR(rt5640->regmap);
2059 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2060 ret);
2061 return ret;
2062 }
2063
2064 if (gpio_is_valid(rt5640->pdata.ldo1_en)) {
2065 ret = devm_gpio_request_one(&i2c->dev, rt5640->pdata.ldo1_en,
2066 GPIOF_OUT_INIT_HIGH,
2067 "RT5640 LDO1_EN");
2068 if (ret < 0) {
2069 dev_err(&i2c->dev, "Failed to request LDO1_EN %d: %d\n",
2070 rt5640->pdata.ldo1_en, ret);
2071 return ret;
2072 }
2073 msleep(400);
2074 }
2075
2076 regmap_read(rt5640->regmap, RT5640_VENDOR_ID2, &val);
2077 if ((val != RT5640_DEVICE_ID)) {
2078 dev_err(&i2c->dev,
2079 "Device with ID register %x is not rt5640/39\n", val);
2080 return -ENODEV;
2081 }
2082
2083 regmap_write(rt5640->regmap, RT5640_RESET, 0);
2084
2085 ret = regmap_register_patch(rt5640->regmap, init_list,
2086 ARRAY_SIZE(init_list));
2087 if (ret != 0)
2088 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2089
2090 if (rt5640->pdata.in1_diff)
2091 regmap_update_bits(rt5640->regmap, RT5640_IN1_IN2,
2092 RT5640_IN_DF1, RT5640_IN_DF1);
2093
2094 if (rt5640->pdata.in2_diff)
2095 regmap_update_bits(rt5640->regmap, RT5640_IN3_IN4,
2096 RT5640_IN_DF2, RT5640_IN_DF2);
2097
2098 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640,
2099 rt5640_dai, ARRAY_SIZE(rt5640_dai));
2100 if (ret < 0)
2101 goto err;
2102
2103 return 0;
2104err:
2105 return ret;
2106}
2107
2108static int rt5640_i2c_remove(struct i2c_client *i2c)
2109{
2110 snd_soc_unregister_codec(&i2c->dev);
2111
2112 return 0;
2113}
2114
2115static struct i2c_driver rt5640_i2c_driver = {
2116 .driver = {
2117 .name = "rt5640",
2118 .owner = THIS_MODULE,
2119 },
2120 .probe = rt5640_i2c_probe,
2121 .remove = rt5640_i2c_remove,
2122 .id_table = rt5640_i2c_id,
2123};
2124module_i2c_driver(rt5640_i2c_driver);
2125
2126MODULE_DESCRIPTION("ASoC RT5640 driver");
2127MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
2128MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
new file mode 100644
index 000000000000..c48286d7118f
--- /dev/null
+++ b/sound/soc/codecs/rt5640.h
@@ -0,0 +1,2092 @@
1/*
2 * rt5640.h -- RT5640 ALSA SoC audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _RT5640_H
13#define _RT5640_H
14
15#include <sound/rt5640.h>
16
17/* Info */
18#define RT5640_RESET 0x00
19#define RT5640_VENDOR_ID 0xfd
20#define RT5640_VENDOR_ID1 0xfe
21#define RT5640_VENDOR_ID2 0xff
22/* I/O - Output */
23#define RT5640_SPK_VOL 0x01
24#define RT5640_HP_VOL 0x02
25#define RT5640_OUTPUT 0x03
26#define RT5640_MONO_OUT 0x04
27/* I/O - Input */
28#define RT5640_IN1_IN2 0x0d
29#define RT5640_IN3_IN4 0x0e
30#define RT5640_INL_INR_VOL 0x0f
31/* I/O - ADC/DAC/DMIC */
32#define RT5640_DAC1_DIG_VOL 0x19
33#define RT5640_DAC2_DIG_VOL 0x1a
34#define RT5640_DAC2_CTRL 0x1b
35#define RT5640_ADC_DIG_VOL 0x1c
36#define RT5640_ADC_DATA 0x1d
37#define RT5640_ADC_BST_VOL 0x1e
38/* Mixer - D-D */
39#define RT5640_STO_ADC_MIXER 0x27
40#define RT5640_MONO_ADC_MIXER 0x28
41#define RT5640_AD_DA_MIXER 0x29
42#define RT5640_STO_DAC_MIXER 0x2a
43#define RT5640_MONO_DAC_MIXER 0x2b
44#define RT5640_DIG_MIXER 0x2c
45#define RT5640_DSP_PATH1 0x2d
46#define RT5640_DSP_PATH2 0x2e
47#define RT5640_DIG_INF_DATA 0x2f
48/* Mixer - ADC */
49#define RT5640_REC_L1_MIXER 0x3b
50#define RT5640_REC_L2_MIXER 0x3c
51#define RT5640_REC_R1_MIXER 0x3d
52#define RT5640_REC_R2_MIXER 0x3e
53/* Mixer - DAC */
54#define RT5640_HPO_MIXER 0x45
55#define RT5640_SPK_L_MIXER 0x46
56#define RT5640_SPK_R_MIXER 0x47
57#define RT5640_SPO_L_MIXER 0x48
58#define RT5640_SPO_R_MIXER 0x49
59#define RT5640_SPO_CLSD_RATIO 0x4a
60#define RT5640_MONO_MIXER 0x4c
61#define RT5640_OUT_L1_MIXER 0x4d
62#define RT5640_OUT_L2_MIXER 0x4e
63#define RT5640_OUT_L3_MIXER 0x4f
64#define RT5640_OUT_R1_MIXER 0x50
65#define RT5640_OUT_R2_MIXER 0x51
66#define RT5640_OUT_R3_MIXER 0x52
67#define RT5640_LOUT_MIXER 0x53
68/* Power */
69#define RT5640_PWR_DIG1 0x61
70#define RT5640_PWR_DIG2 0x62
71#define RT5640_PWR_ANLG1 0x63
72#define RT5640_PWR_ANLG2 0x64
73#define RT5640_PWR_MIXER 0x65
74#define RT5640_PWR_VOL 0x66
75/* Private Register Control */
76#define RT5640_PRIV_INDEX 0x6a
77#define RT5640_PRIV_DATA 0x6c
78/* Format - ADC/DAC */
79#define RT5640_I2S1_SDP 0x70
80#define RT5640_I2S2_SDP 0x71
81#define RT5640_ADDA_CLK1 0x73
82#define RT5640_ADDA_CLK2 0x74
83#define RT5640_DMIC 0x75
84/* Function - Analog */
85#define RT5640_GLB_CLK 0x80
86#define RT5640_PLL_CTRL1 0x81
87#define RT5640_PLL_CTRL2 0x82
88#define RT5640_ASRC_1 0x83
89#define RT5640_ASRC_2 0x84
90#define RT5640_ASRC_3 0x85
91#define RT5640_ASRC_4 0x89
92#define RT5640_ASRC_5 0x8a
93#define RT5640_HP_OVCD 0x8b
94#define RT5640_CLS_D_OVCD 0x8c
95#define RT5640_CLS_D_OUT 0x8d
96#define RT5640_DEPOP_M1 0x8e
97#define RT5640_DEPOP_M2 0x8f
98#define RT5640_DEPOP_M3 0x90
99#define RT5640_CHARGE_PUMP 0x91
100#define RT5640_PV_DET_SPK_G 0x92
101#define RT5640_MICBIAS 0x93
102/* Function - Digital */
103#define RT5640_EQ_CTRL1 0xb0
104#define RT5640_EQ_CTRL2 0xb1
105#define RT5640_WIND_FILTER 0xb2
106#define RT5640_DRC_AGC_1 0xb4
107#define RT5640_DRC_AGC_2 0xb5
108#define RT5640_DRC_AGC_3 0xb6
109#define RT5640_SVOL_ZC 0xb7
110#define RT5640_ANC_CTRL1 0xb8
111#define RT5640_ANC_CTRL2 0xb9
112#define RT5640_ANC_CTRL3 0xba
113#define RT5640_JD_CTRL 0xbb
114#define RT5640_ANC_JD 0xbc
115#define RT5640_IRQ_CTRL1 0xbd
116#define RT5640_IRQ_CTRL2 0xbe
117#define RT5640_INT_IRQ_ST 0xbf
118#define RT5640_GPIO_CTRL1 0xc0
119#define RT5640_GPIO_CTRL2 0xc1
120#define RT5640_GPIO_CTRL3 0xc2
121#define RT5640_DSP_CTRL1 0xc4
122#define RT5640_DSP_CTRL2 0xc5
123#define RT5640_DSP_CTRL3 0xc6
124#define RT5640_DSP_CTRL4 0xc7
125#define RT5640_PGM_REG_ARR1 0xc8
126#define RT5640_PGM_REG_ARR2 0xc9
127#define RT5640_PGM_REG_ARR3 0xca
128#define RT5640_PGM_REG_ARR4 0xcb
129#define RT5640_PGM_REG_ARR5 0xcc
130#define RT5640_SCB_FUNC 0xcd
131#define RT5640_SCB_CTRL 0xce
132#define RT5640_BASE_BACK 0xcf
133#define RT5640_MP3_PLUS1 0xd0
134#define RT5640_MP3_PLUS2 0xd1
135#define RT5640_3D_HP 0xd2
136#define RT5640_ADJ_HPF 0xd3
137#define RT5640_HP_CALIB_AMP_DET 0xd6
138#define RT5640_HP_CALIB2 0xd7
139#define RT5640_SV_ZCD1 0xd9
140#define RT5640_SV_ZCD2 0xda
141/* Dummy Register */
142#define RT5640_DUMMY1 0xfa
143#define RT5640_DUMMY2 0xfb
144#define RT5640_DUMMY3 0xfc
145
146
147/* Index of Codec Private Register definition */
148#define RT5640_3D_SPK 0x63
149#define RT5640_WND_1 0x6c
150#define RT5640_WND_2 0x6d
151#define RT5640_WND_3 0x6e
152#define RT5640_WND_4 0x6f
153#define RT5640_WND_5 0x70
154#define RT5640_WND_8 0x73
155#define RT5640_DIP_SPK_INF 0x75
156#define RT5640_EQ_BW_LOP 0xa0
157#define RT5640_EQ_GN_LOP 0xa1
158#define RT5640_EQ_FC_BP1 0xa2
159#define RT5640_EQ_BW_BP1 0xa3
160#define RT5640_EQ_GN_BP1 0xa4
161#define RT5640_EQ_FC_BP2 0xa5
162#define RT5640_EQ_BW_BP2 0xa6
163#define RT5640_EQ_GN_BP2 0xa7
164#define RT5640_EQ_FC_BP3 0xa8
165#define RT5640_EQ_BW_BP3 0xa9
166#define RT5640_EQ_GN_BP3 0xaa
167#define RT5640_EQ_FC_BP4 0xab
168#define RT5640_EQ_BW_BP4 0xac
169#define RT5640_EQ_GN_BP4 0xad
170#define RT5640_EQ_FC_HIP1 0xae
171#define RT5640_EQ_GN_HIP1 0xaf
172#define RT5640_EQ_FC_HIP2 0xb0
173#define RT5640_EQ_BW_HIP2 0xb1
174#define RT5640_EQ_GN_HIP2 0xb2
175#define RT5640_EQ_PRE_VOL 0xb3
176#define RT5640_EQ_PST_VOL 0xb4
177
178/* global definition */
179#define RT5640_L_MUTE (0x1 << 15)
180#define RT5640_L_MUTE_SFT 15
181#define RT5640_VOL_L_MUTE (0x1 << 14)
182#define RT5640_VOL_L_SFT 14
183#define RT5640_R_MUTE (0x1 << 7)
184#define RT5640_R_MUTE_SFT 7
185#define RT5640_VOL_R_MUTE (0x1 << 6)
186#define RT5640_VOL_R_SFT 6
187#define RT5640_L_VOL_MASK (0x3f << 8)
188#define RT5640_L_VOL_SFT 8
189#define RT5640_R_VOL_MASK (0x3f)
190#define RT5640_R_VOL_SFT 0
191
192/* IN1 and IN2 Control (0x0d) */
193/* IN3 and IN4 Control (0x0e) */
194#define RT5640_BST_SFT1 12
195#define RT5640_BST_SFT2 8
196#define RT5640_IN_DF1 (0x1 << 7)
197#define RT5640_IN_SFT1 7
198#define RT5640_IN_DF2 (0x1 << 6)
199#define RT5640_IN_SFT2 6
200
201/* INL and INR Volume Control (0x0f) */
202#define RT5640_INL_SEL_MASK (0x1 << 15)
203#define RT5640_INL_SEL_SFT 15
204#define RT5640_INL_SEL_IN4P (0x0 << 15)
205#define RT5640_INL_SEL_MONOP (0x1 << 15)
206#define RT5640_INL_VOL_MASK (0x1f << 8)
207#define RT5640_INL_VOL_SFT 8
208#define RT5640_INR_SEL_MASK (0x1 << 7)
209#define RT5640_INR_SEL_SFT 7
210#define RT5640_INR_SEL_IN4N (0x0 << 7)
211#define RT5640_INR_SEL_MONON (0x1 << 7)
212#define RT5640_INR_VOL_MASK (0x1f)
213#define RT5640_INR_VOL_SFT 0
214
215/* DAC1 Digital Volume (0x19) */
216#define RT5640_DAC_L1_VOL_MASK (0xff << 8)
217#define RT5640_DAC_L1_VOL_SFT 8
218#define RT5640_DAC_R1_VOL_MASK (0xff)
219#define RT5640_DAC_R1_VOL_SFT 0
220
221/* DAC2 Digital Volume (0x1a) */
222#define RT5640_DAC_L2_VOL_MASK (0xff << 8)
223#define RT5640_DAC_L2_VOL_SFT 8
224#define RT5640_DAC_R2_VOL_MASK (0xff)
225#define RT5640_DAC_R2_VOL_SFT 0
226
227/* DAC2 Control (0x1b) */
228#define RT5640_M_DAC_L2_VOL (0x1 << 13)
229#define RT5640_M_DAC_L2_VOL_SFT 13
230#define RT5640_M_DAC_R2_VOL (0x1 << 12)
231#define RT5640_M_DAC_R2_VOL_SFT 12
232
233/* ADC Digital Volume Control (0x1c) */
234#define RT5640_ADC_L_VOL_MASK (0x7f << 8)
235#define RT5640_ADC_L_VOL_SFT 8
236#define RT5640_ADC_R_VOL_MASK (0x7f)
237#define RT5640_ADC_R_VOL_SFT 0
238
239/* Mono ADC Digital Volume Control (0x1d) */
240#define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8)
241#define RT5640_MONO_ADC_L_VOL_SFT 8
242#define RT5640_MONO_ADC_R_VOL_MASK (0x7f)
243#define RT5640_MONO_ADC_R_VOL_SFT 0
244
245/* ADC Boost Volume Control (0x1e) */
246#define RT5640_ADC_L_BST_MASK (0x3 << 14)
247#define RT5640_ADC_L_BST_SFT 14
248#define RT5640_ADC_R_BST_MASK (0x3 << 12)
249#define RT5640_ADC_R_BST_SFT 12
250#define RT5640_ADC_COMP_MASK (0x3 << 10)
251#define RT5640_ADC_COMP_SFT 10
252
253/* Stereo ADC Mixer Control (0x27) */
254#define RT5640_M_ADC_L1 (0x1 << 14)
255#define RT5640_M_ADC_L1_SFT 14
256#define RT5640_M_ADC_L2 (0x1 << 13)
257#define RT5640_M_ADC_L2_SFT 13
258#define RT5640_ADC_1_SRC_MASK (0x1 << 12)
259#define RT5640_ADC_1_SRC_SFT 12
260#define RT5640_ADC_1_SRC_ADC (0x1 << 12)
261#define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
262#define RT5640_ADC_2_SRC_MASK (0x3 << 10)
263#define RT5640_ADC_2_SRC_SFT 10
264#define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
265#define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
266#define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
267#define RT5640_M_ADC_R1 (0x1 << 6)
268#define RT5640_M_ADC_R1_SFT 6
269#define RT5640_M_ADC_R2 (0x1 << 5)
270#define RT5640_M_ADC_R2_SFT 5
271
272/* Mono ADC Mixer Control (0x28) */
273#define RT5640_M_MONO_ADC_L1 (0x1 << 14)
274#define RT5640_M_MONO_ADC_L1_SFT 14
275#define RT5640_M_MONO_ADC_L2 (0x1 << 13)
276#define RT5640_M_MONO_ADC_L2_SFT 13
277#define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
278#define RT5640_MONO_ADC_L1_SRC_SFT 12
279#define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
280#define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
281#define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
282#define RT5640_MONO_ADC_L2_SRC_SFT 10
283#define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
284#define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
285#define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
286#define RT5640_M_MONO_ADC_R1 (0x1 << 6)
287#define RT5640_M_MONO_ADC_R1_SFT 6
288#define RT5640_M_MONO_ADC_R2 (0x1 << 5)
289#define RT5640_M_MONO_ADC_R2_SFT 5
290#define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4)
291#define RT5640_MONO_ADC_R1_SRC_SFT 4
292#define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
293#define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
294#define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2)
295#define RT5640_MONO_ADC_R2_SRC_SFT 2
296#define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
297#define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
298#define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
299
300/* ADC Mixer to DAC Mixer Control (0x29) */
301#define RT5640_M_ADCMIX_L (0x1 << 15)
302#define RT5640_M_ADCMIX_L_SFT 15
303#define RT5640_M_IF1_DAC_L (0x1 << 14)
304#define RT5640_M_IF1_DAC_L_SFT 14
305#define RT5640_M_ADCMIX_R (0x1 << 7)
306#define RT5640_M_ADCMIX_R_SFT 7
307#define RT5640_M_IF1_DAC_R (0x1 << 6)
308#define RT5640_M_IF1_DAC_R_SFT 6
309
310/* Stereo DAC Mixer Control (0x2a) */
311#define RT5640_M_DAC_L1 (0x1 << 14)
312#define RT5640_M_DAC_L1_SFT 14
313#define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
314#define RT5640_DAC_L1_STO_L_VOL_SFT 13
315#define RT5640_M_DAC_L2 (0x1 << 12)
316#define RT5640_M_DAC_L2_SFT 12
317#define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
318#define RT5640_DAC_L2_STO_L_VOL_SFT 11
319#define RT5640_M_ANC_DAC_L (0x1 << 10)
320#define RT5640_M_ANC_DAC_L_SFT 10
321#define RT5640_M_DAC_R1 (0x1 << 6)
322#define RT5640_M_DAC_R1_SFT 6
323#define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
324#define RT5640_DAC_R1_STO_R_VOL_SFT 5
325#define RT5640_M_DAC_R2 (0x1 << 4)
326#define RT5640_M_DAC_R2_SFT 4
327#define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
328#define RT5640_DAC_R2_STO_R_VOL_SFT 3
329#define RT5640_M_ANC_DAC_R (0x1 << 2)
330#define RT5640_M_ANC_DAC_R_SFT 2
331
332/* Mono DAC Mixer Control (0x2b) */
333#define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
334#define RT5640_M_DAC_L1_MONO_L_SFT 14
335#define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
336#define RT5640_DAC_L1_MONO_L_VOL_SFT 13
337#define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
338#define RT5640_M_DAC_L2_MONO_L_SFT 12
339#define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
340#define RT5640_DAC_L2_MONO_L_VOL_SFT 11
341#define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
342#define RT5640_M_DAC_R2_MONO_L_SFT 10
343#define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
344#define RT5640_DAC_R2_MONO_L_VOL_SFT 9
345#define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
346#define RT5640_M_DAC_R1_MONO_R_SFT 6
347#define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
348#define RT5640_DAC_R1_MONO_R_VOL_SFT 5
349#define RT5640_M_DAC_R2_MONO_R (0x1 << 4)
350#define RT5640_M_DAC_R2_MONO_R_SFT 4
351#define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
352#define RT5640_DAC_R2_MONO_R_VOL_SFT 3
353#define RT5640_M_DAC_L2_MONO_R (0x1 << 2)
354#define RT5640_M_DAC_L2_MONO_R_SFT 2
355#define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
356#define RT5640_DAC_L2_MONO_R_VOL_SFT 1
357
358/* Digital Mixer Control (0x2c) */
359#define RT5640_M_STO_L_DAC_L (0x1 << 15)
360#define RT5640_M_STO_L_DAC_L_SFT 15
361#define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14)
362#define RT5640_STO_L_DAC_L_VOL_SFT 14
363#define RT5640_M_DAC_L2_DAC_L (0x1 << 13)
364#define RT5640_M_DAC_L2_DAC_L_SFT 13
365#define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
366#define RT5640_DAC_L2_DAC_L_VOL_SFT 12
367#define RT5640_M_STO_R_DAC_R (0x1 << 11)
368#define RT5640_M_STO_R_DAC_R_SFT 11
369#define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
370#define RT5640_STO_R_DAC_R_VOL_SFT 10
371#define RT5640_M_DAC_R2_DAC_R (0x1 << 9)
372#define RT5640_M_DAC_R2_DAC_R_SFT 9
373#define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
374#define RT5640_DAC_R2_DAC_R_VOL_SFT 8
375
376/* DSP Path Control 1 (0x2d) */
377#define RT5640_RXDP_SRC_MASK (0x1 << 15)
378#define RT5640_RXDP_SRC_SFT 15
379#define RT5640_RXDP_SRC_NOR (0x0 << 15)
380#define RT5640_RXDP_SRC_DIV3 (0x1 << 15)
381#define RT5640_TXDP_SRC_MASK (0x1 << 14)
382#define RT5640_TXDP_SRC_SFT 14
383#define RT5640_TXDP_SRC_NOR (0x0 << 14)
384#define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
385
386/* DSP Path Control 2 (0x2e) */
387#define RT5640_DAC_L2_SEL_MASK (0x3 << 14)
388#define RT5640_DAC_L2_SEL_SFT 14
389#define RT5640_DAC_L2_SEL_IF2 (0x0 << 14)
390#define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
391#define RT5640_DAC_L2_SEL_TXDC (0x2 << 14)
392#define RT5640_DAC_L2_SEL_BASS (0x3 << 14)
393#define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
394#define RT5640_DAC_R2_SEL_SFT 12
395#define RT5640_DAC_R2_SEL_IF2 (0x0 << 12)
396#define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
397#define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
398#define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
399#define RT5640_IF2_ADC_L_SEL_SFT 11
400#define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11)
401#define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
402#define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
403#define RT5640_IF2_ADC_R_SEL_SFT 10
404#define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10)
405#define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
406#define RT5640_RXDC_SEL_MASK (0x3 << 8)
407#define RT5640_RXDC_SEL_SFT 8
408#define RT5640_RXDC_SEL_NOR (0x0 << 8)
409#define RT5640_RXDC_SEL_L2R (0x1 << 8)
410#define RT5640_RXDC_SEL_R2L (0x2 << 8)
411#define RT5640_RXDC_SEL_SWAP (0x3 << 8)
412#define RT5640_RXDP_SEL_MASK (0x3 << 6)
413#define RT5640_RXDP_SEL_SFT 6
414#define RT5640_RXDP_SEL_NOR (0x0 << 6)
415#define RT5640_RXDP_SEL_L2R (0x1 << 6)
416#define RT5640_RXDP_SEL_R2L (0x2 << 6)
417#define RT5640_RXDP_SEL_SWAP (0x3 << 6)
418#define RT5640_TXDC_SEL_MASK (0x3 << 4)
419#define RT5640_TXDC_SEL_SFT 4
420#define RT5640_TXDC_SEL_NOR (0x0 << 4)
421#define RT5640_TXDC_SEL_L2R (0x1 << 4)
422#define RT5640_TXDC_SEL_R2L (0x2 << 4)
423#define RT5640_TXDC_SEL_SWAP (0x3 << 4)
424#define RT5640_TXDP_SEL_MASK (0x3 << 2)
425#define RT5640_TXDP_SEL_SFT 2
426#define RT5640_TXDP_SEL_NOR (0x0 << 2)
427#define RT5640_TXDP_SEL_L2R (0x1 << 2)
428#define RT5640_TXDP_SEL_R2L (0x2 << 2)
429#define RT5640_TRXDP_SEL_SWAP (0x3 << 2)
430
431/* Digital Interface Data Control (0x2f) */
432#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
433#define RT5640_IF1_DAC_SEL_SFT 14
434#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
435#define RT5640_IF1_DAC_SEL_L2R (0x1 << 14)
436#define RT5640_IF1_DAC_SEL_R2L (0x2 << 14)
437#define RT5640_IF1_DAC_SEL_SWAP (0x3 << 14)
438#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
439#define RT5640_IF1_ADC_SEL_SFT 12
440#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
441#define RT5640_IF1_ADC_SEL_L2R (0x1 << 12)
442#define RT5640_IF1_ADC_SEL_R2L (0x2 << 12)
443#define RT5640_IF1_ADC_SEL_SWAP (0x3 << 12)
444#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
445#define RT5640_IF2_DAC_SEL_SFT 10
446#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
447#define RT5640_IF2_DAC_SEL_L2R (0x1 << 10)
448#define RT5640_IF2_DAC_SEL_R2L (0x2 << 10)
449#define RT5640_IF2_DAC_SEL_SWAP (0x3 << 10)
450#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
451#define RT5640_IF2_ADC_SEL_SFT 8
452#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
453#define RT5640_IF2_ADC_SEL_L2R (0x1 << 8)
454#define RT5640_IF2_ADC_SEL_R2L (0x2 << 8)
455#define RT5640_IF2_ADC_SEL_SWAP (0x3 << 8)
456#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
457#define RT5640_IF3_DAC_SEL_SFT 6
458#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
459#define RT5640_IF3_DAC_SEL_L2R (0x1 << 6)
460#define RT5640_IF3_DAC_SEL_R2L (0x2 << 6)
461#define RT5640_IF3_DAC_SEL_SWAP (0x3 << 6)
462#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
463#define RT5640_IF3_ADC_SEL_SFT 4
464#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
465#define RT5640_IF3_ADC_SEL_L2R (0x1 << 4)
466#define RT5640_IF3_ADC_SEL_R2L (0x2 << 4)
467#define RT5640_IF3_ADC_SEL_SWAP (0x3 << 4)
468
469/* REC Left Mixer Control 1 (0x3b) */
470#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
471#define RT5640_G_HP_L_RM_L_SFT 13
472#define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
473#define RT5640_G_IN_L_RM_L_SFT 10
474#define RT5640_G_BST4_RM_L_MASK (0x7 << 7)
475#define RT5640_G_BST4_RM_L_SFT 7
476#define RT5640_G_BST3_RM_L_MASK (0x7 << 4)
477#define RT5640_G_BST3_RM_L_SFT 4
478#define RT5640_G_BST2_RM_L_MASK (0x7 << 1)
479#define RT5640_G_BST2_RM_L_SFT 1
480
481/* REC Left Mixer Control 2 (0x3c) */
482#define RT5640_G_BST1_RM_L_MASK (0x7 << 13)
483#define RT5640_G_BST1_RM_L_SFT 13
484#define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
485#define RT5640_G_OM_L_RM_L_SFT 10
486#define RT5640_M_HP_L_RM_L (0x1 << 6)
487#define RT5640_M_HP_L_RM_L_SFT 6
488#define RT5640_M_IN_L_RM_L (0x1 << 5)
489#define RT5640_M_IN_L_RM_L_SFT 5
490#define RT5640_M_BST4_RM_L (0x1 << 4)
491#define RT5640_M_BST4_RM_L_SFT 4
492#define RT5640_M_BST3_RM_L (0x1 << 3)
493#define RT5640_M_BST3_RM_L_SFT 3
494#define RT5640_M_BST2_RM_L (0x1 << 2)
495#define RT5640_M_BST2_RM_L_SFT 2
496#define RT5640_M_BST1_RM_L (0x1 << 1)
497#define RT5640_M_BST1_RM_L_SFT 1
498#define RT5640_M_OM_L_RM_L (0x1)
499#define RT5640_M_OM_L_RM_L_SFT 0
500
501/* REC Right Mixer Control 1 (0x3d) */
502#define RT5640_G_HP_R_RM_R_MASK (0x7 << 13)
503#define RT5640_G_HP_R_RM_R_SFT 13
504#define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
505#define RT5640_G_IN_R_RM_R_SFT 10
506#define RT5640_G_BST4_RM_R_MASK (0x7 << 7)
507#define RT5640_G_BST4_RM_R_SFT 7
508#define RT5640_G_BST3_RM_R_MASK (0x7 << 4)
509#define RT5640_G_BST3_RM_R_SFT 4
510#define RT5640_G_BST2_RM_R_MASK (0x7 << 1)
511#define RT5640_G_BST2_RM_R_SFT 1
512
513/* REC Right Mixer Control 2 (0x3e) */
514#define RT5640_G_BST1_RM_R_MASK (0x7 << 13)
515#define RT5640_G_BST1_RM_R_SFT 13
516#define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
517#define RT5640_G_OM_R_RM_R_SFT 10
518#define RT5640_M_HP_R_RM_R (0x1 << 6)
519#define RT5640_M_HP_R_RM_R_SFT 6
520#define RT5640_M_IN_R_RM_R (0x1 << 5)
521#define RT5640_M_IN_R_RM_R_SFT 5
522#define RT5640_M_BST4_RM_R (0x1 << 4)
523#define RT5640_M_BST4_RM_R_SFT 4
524#define RT5640_M_BST3_RM_R (0x1 << 3)
525#define RT5640_M_BST3_RM_R_SFT 3
526#define RT5640_M_BST2_RM_R (0x1 << 2)
527#define RT5640_M_BST2_RM_R_SFT 2
528#define RT5640_M_BST1_RM_R (0x1 << 1)
529#define RT5640_M_BST1_RM_R_SFT 1
530#define RT5640_M_OM_R_RM_R (0x1)
531#define RT5640_M_OM_R_RM_R_SFT 0
532
533/* HPMIX Control (0x45) */
534#define RT5640_M_DAC2_HM (0x1 << 15)
535#define RT5640_M_DAC2_HM_SFT 15
536#define RT5640_M_DAC1_HM (0x1 << 14)
537#define RT5640_M_DAC1_HM_SFT 14
538#define RT5640_M_HPVOL_HM (0x1 << 13)
539#define RT5640_M_HPVOL_HM_SFT 13
540#define RT5640_G_HPOMIX_MASK (0x1 << 12)
541#define RT5640_G_HPOMIX_SFT 12
542
543/* SPK Left Mixer Control (0x46) */
544#define RT5640_G_RM_L_SM_L_MASK (0x3 << 14)
545#define RT5640_G_RM_L_SM_L_SFT 14
546#define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
547#define RT5640_G_IN_L_SM_L_SFT 12
548#define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10)
549#define RT5640_G_DAC_L1_SM_L_SFT 10
550#define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8)
551#define RT5640_G_DAC_L2_SM_L_SFT 8
552#define RT5640_G_OM_L_SM_L_MASK (0x3 << 6)
553#define RT5640_G_OM_L_SM_L_SFT 6
554#define RT5640_M_RM_L_SM_L (0x1 << 5)
555#define RT5640_M_RM_L_SM_L_SFT 5
556#define RT5640_M_IN_L_SM_L (0x1 << 4)
557#define RT5640_M_IN_L_SM_L_SFT 4
558#define RT5640_M_DAC_L1_SM_L (0x1 << 3)
559#define RT5640_M_DAC_L1_SM_L_SFT 3
560#define RT5640_M_DAC_L2_SM_L (0x1 << 2)
561#define RT5640_M_DAC_L2_SM_L_SFT 2
562#define RT5640_M_OM_L_SM_L (0x1 << 1)
563#define RT5640_M_OM_L_SM_L_SFT 1
564
565/* SPK Right Mixer Control (0x47) */
566#define RT5640_G_RM_R_SM_R_MASK (0x3 << 14)
567#define RT5640_G_RM_R_SM_R_SFT 14
568#define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
569#define RT5640_G_IN_R_SM_R_SFT 12
570#define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10)
571#define RT5640_G_DAC_R1_SM_R_SFT 10
572#define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8)
573#define RT5640_G_DAC_R2_SM_R_SFT 8
574#define RT5640_G_OM_R_SM_R_MASK (0x3 << 6)
575#define RT5640_G_OM_R_SM_R_SFT 6
576#define RT5640_M_RM_R_SM_R (0x1 << 5)
577#define RT5640_M_RM_R_SM_R_SFT 5
578#define RT5640_M_IN_R_SM_R (0x1 << 4)
579#define RT5640_M_IN_R_SM_R_SFT 4
580#define RT5640_M_DAC_R1_SM_R (0x1 << 3)
581#define RT5640_M_DAC_R1_SM_R_SFT 3
582#define RT5640_M_DAC_R2_SM_R (0x1 << 2)
583#define RT5640_M_DAC_R2_SM_R_SFT 2
584#define RT5640_M_OM_R_SM_R (0x1 << 1)
585#define RT5640_M_OM_R_SM_R_SFT 1
586
587/* SPOLMIX Control (0x48) */
588#define RT5640_M_DAC_R1_SPM_L (0x1 << 15)
589#define RT5640_M_DAC_R1_SPM_L_SFT 15
590#define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
591#define RT5640_M_DAC_L1_SPM_L_SFT 14
592#define RT5640_M_SV_R_SPM_L (0x1 << 13)
593#define RT5640_M_SV_R_SPM_L_SFT 13
594#define RT5640_M_SV_L_SPM_L (0x1 << 12)
595#define RT5640_M_SV_L_SPM_L_SFT 12
596#define RT5640_M_BST1_SPM_L (0x1 << 11)
597#define RT5640_M_BST1_SPM_L_SFT 11
598
599/* SPORMIX Control (0x49) */
600#define RT5640_M_DAC_R1_SPM_R (0x1 << 13)
601#define RT5640_M_DAC_R1_SPM_R_SFT 13
602#define RT5640_M_SV_R_SPM_R (0x1 << 12)
603#define RT5640_M_SV_R_SPM_R_SFT 12
604#define RT5640_M_BST1_SPM_R (0x1 << 11)
605#define RT5640_M_BST1_SPM_R_SFT 11
606
607/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
608#define RT5640_SPO_CLSD_RATIO_MASK (0x7)
609#define RT5640_SPO_CLSD_RATIO_SFT 0
610
611/* Mono Output Mixer Control (0x4c) */
612#define RT5640_M_DAC_R2_MM (0x1 << 15)
613#define RT5640_M_DAC_R2_MM_SFT 15
614#define RT5640_M_DAC_L2_MM (0x1 << 14)
615#define RT5640_M_DAC_L2_MM_SFT 14
616#define RT5640_M_OV_R_MM (0x1 << 13)
617#define RT5640_M_OV_R_MM_SFT 13
618#define RT5640_M_OV_L_MM (0x1 << 12)
619#define RT5640_M_OV_L_MM_SFT 12
620#define RT5640_M_BST1_MM (0x1 << 11)
621#define RT5640_M_BST1_MM_SFT 11
622#define RT5640_G_MONOMIX_MASK (0x1 << 10)
623#define RT5640_G_MONOMIX_SFT 10
624
625/* Output Left Mixer Control 1 (0x4d) */
626#define RT5640_G_BST3_OM_L_MASK (0x7 << 13)
627#define RT5640_G_BST3_OM_L_SFT 13
628#define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
629#define RT5640_G_BST2_OM_L_SFT 10
630#define RT5640_G_BST1_OM_L_MASK (0x7 << 7)
631#define RT5640_G_BST1_OM_L_SFT 7
632#define RT5640_G_IN_L_OM_L_MASK (0x7 << 4)
633#define RT5640_G_IN_L_OM_L_SFT 4
634#define RT5640_G_RM_L_OM_L_MASK (0x7 << 1)
635#define RT5640_G_RM_L_OM_L_SFT 1
636
637/* Output Left Mixer Control 2 (0x4e) */
638#define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13)
639#define RT5640_G_DAC_R2_OM_L_SFT 13
640#define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10)
641#define RT5640_G_DAC_L2_OM_L_SFT 10
642#define RT5640_G_DAC_L1_OM_L_MASK (0x7 << 7)
643#define RT5640_G_DAC_L1_OM_L_SFT 7
644
645/* Output Left Mixer Control 3 (0x4f) */
646#define RT5640_M_SM_L_OM_L (0x1 << 8)
647#define RT5640_M_SM_L_OM_L_SFT 8
648#define RT5640_M_BST3_OM_L (0x1 << 7)
649#define RT5640_M_BST3_OM_L_SFT 7
650#define RT5640_M_BST2_OM_L (0x1 << 6)
651#define RT5640_M_BST2_OM_L_SFT 6
652#define RT5640_M_BST1_OM_L (0x1 << 5)
653#define RT5640_M_BST1_OM_L_SFT 5
654#define RT5640_M_IN_L_OM_L (0x1 << 4)
655#define RT5640_M_IN_L_OM_L_SFT 4
656#define RT5640_M_RM_L_OM_L (0x1 << 3)
657#define RT5640_M_RM_L_OM_L_SFT 3
658#define RT5640_M_DAC_R2_OM_L (0x1 << 2)
659#define RT5640_M_DAC_R2_OM_L_SFT 2
660#define RT5640_M_DAC_L2_OM_L (0x1 << 1)
661#define RT5640_M_DAC_L2_OM_L_SFT 1
662#define RT5640_M_DAC_L1_OM_L (0x1)
663#define RT5640_M_DAC_L1_OM_L_SFT 0
664
665/* Output Right Mixer Control 1 (0x50) */
666#define RT5640_G_BST4_OM_R_MASK (0x7 << 13)
667#define RT5640_G_BST4_OM_R_SFT 13
668#define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
669#define RT5640_G_BST2_OM_R_SFT 10
670#define RT5640_G_BST1_OM_R_MASK (0x7 << 7)
671#define RT5640_G_BST1_OM_R_SFT 7
672#define RT5640_G_IN_R_OM_R_MASK (0x7 << 4)
673#define RT5640_G_IN_R_OM_R_SFT 4
674#define RT5640_G_RM_R_OM_R_MASK (0x7 << 1)
675#define RT5640_G_RM_R_OM_R_SFT 1
676
677/* Output Right Mixer Control 2 (0x51) */
678#define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13)
679#define RT5640_G_DAC_L2_OM_R_SFT 13
680#define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10)
681#define RT5640_G_DAC_R2_OM_R_SFT 10
682#define RT5640_G_DAC_R1_OM_R_MASK (0x7 << 7)
683#define RT5640_G_DAC_R1_OM_R_SFT 7
684
685/* Output Right Mixer Control 3 (0x52) */
686#define RT5640_M_SM_L_OM_R (0x1 << 8)
687#define RT5640_M_SM_L_OM_R_SFT 8
688#define RT5640_M_BST4_OM_R (0x1 << 7)
689#define RT5640_M_BST4_OM_R_SFT 7
690#define RT5640_M_BST2_OM_R (0x1 << 6)
691#define RT5640_M_BST2_OM_R_SFT 6
692#define RT5640_M_BST1_OM_R (0x1 << 5)
693#define RT5640_M_BST1_OM_R_SFT 5
694#define RT5640_M_IN_R_OM_R (0x1 << 4)
695#define RT5640_M_IN_R_OM_R_SFT 4
696#define RT5640_M_RM_R_OM_R (0x1 << 3)
697#define RT5640_M_RM_R_OM_R_SFT 3
698#define RT5640_M_DAC_L2_OM_R (0x1 << 2)
699#define RT5640_M_DAC_L2_OM_R_SFT 2
700#define RT5640_M_DAC_R2_OM_R (0x1 << 1)
701#define RT5640_M_DAC_R2_OM_R_SFT 1
702#define RT5640_M_DAC_R1_OM_R (0x1)
703#define RT5640_M_DAC_R1_OM_R_SFT 0
704
705/* LOUT Mixer Control (0x53) */
706#define RT5640_M_DAC_L1_LM (0x1 << 15)
707#define RT5640_M_DAC_L1_LM_SFT 15
708#define RT5640_M_DAC_R1_LM (0x1 << 14)
709#define RT5640_M_DAC_R1_LM_SFT 14
710#define RT5640_M_OV_L_LM (0x1 << 13)
711#define RT5640_M_OV_L_LM_SFT 13
712#define RT5640_M_OV_R_LM (0x1 << 12)
713#define RT5640_M_OV_R_LM_SFT 12
714#define RT5640_G_LOUTMIX_MASK (0x1 << 11)
715#define RT5640_G_LOUTMIX_SFT 11
716
717/* Power Management for Digital 1 (0x61) */
718#define RT5640_PWR_I2S1 (0x1 << 15)
719#define RT5640_PWR_I2S1_BIT 15
720#define RT5640_PWR_I2S2 (0x1 << 14)
721#define RT5640_PWR_I2S2_BIT 14
722#define RT5640_PWR_DAC_L1 (0x1 << 12)
723#define RT5640_PWR_DAC_L1_BIT 12
724#define RT5640_PWR_DAC_R1 (0x1 << 11)
725#define RT5640_PWR_DAC_R1_BIT 11
726#define RT5640_PWR_DAC_L2 (0x1 << 7)
727#define RT5640_PWR_DAC_L2_BIT 7
728#define RT5640_PWR_DAC_R2 (0x1 << 6)
729#define RT5640_PWR_DAC_R2_BIT 6
730#define RT5640_PWR_ADC_L (0x1 << 2)
731#define RT5640_PWR_ADC_L_BIT 2
732#define RT5640_PWR_ADC_R (0x1 << 1)
733#define RT5640_PWR_ADC_R_BIT 1
734#define RT5640_PWR_CLS_D (0x1)
735#define RT5640_PWR_CLS_D_BIT 0
736
737/* Power Management for Digital 2 (0x62) */
738#define RT5640_PWR_ADC_SF (0x1 << 15)
739#define RT5640_PWR_ADC_SF_BIT 15
740#define RT5640_PWR_ADC_MF_L (0x1 << 14)
741#define RT5640_PWR_ADC_MF_L_BIT 14
742#define RT5640_PWR_ADC_MF_R (0x1 << 13)
743#define RT5640_PWR_ADC_MF_R_BIT 13
744#define RT5640_PWR_I2S_DSP (0x1 << 12)
745#define RT5640_PWR_I2S_DSP_BIT 12
746
747/* Power Management for Analog 1 (0x63) */
748#define RT5640_PWR_VREF1 (0x1 << 15)
749#define RT5640_PWR_VREF1_BIT 15
750#define RT5640_PWR_FV1 (0x1 << 14)
751#define RT5640_PWR_FV1_BIT 14
752#define RT5640_PWR_MB (0x1 << 13)
753#define RT5640_PWR_MB_BIT 13
754#define RT5640_PWR_LM (0x1 << 12)
755#define RT5640_PWR_LM_BIT 12
756#define RT5640_PWR_BG (0x1 << 11)
757#define RT5640_PWR_BG_BIT 11
758#define RT5640_PWR_MM (0x1 << 10)
759#define RT5640_PWR_MM_BIT 10
760#define RT5640_PWR_MA (0x1 << 8)
761#define RT5640_PWR_MA_BIT 8
762#define RT5640_PWR_HP_L (0x1 << 7)
763#define RT5640_PWR_HP_L_BIT 7
764#define RT5640_PWR_HP_R (0x1 << 6)
765#define RT5640_PWR_HP_R_BIT 6
766#define RT5640_PWR_HA (0x1 << 5)
767#define RT5640_PWR_HA_BIT 5
768#define RT5640_PWR_VREF2 (0x1 << 4)
769#define RT5640_PWR_VREF2_BIT 4
770#define RT5640_PWR_FV2 (0x1 << 3)
771#define RT5640_PWR_FV2_BIT 3
772#define RT5640_PWR_LDO2 (0x1 << 2)
773#define RT5640_PWR_LDO2_BIT 2
774
775/* Power Management for Analog 2 (0x64) */
776#define RT5640_PWR_BST1 (0x1 << 15)
777#define RT5640_PWR_BST1_BIT 15
778#define RT5640_PWR_BST2 (0x1 << 14)
779#define RT5640_PWR_BST2_BIT 14
780#define RT5640_PWR_BST3 (0x1 << 13)
781#define RT5640_PWR_BST3_BIT 13
782#define RT5640_PWR_BST4 (0x1 << 12)
783#define RT5640_PWR_BST4_BIT 12
784#define RT5640_PWR_MB1 (0x1 << 11)
785#define RT5640_PWR_MB1_BIT 11
786#define RT5640_PWR_PLL (0x1 << 9)
787#define RT5640_PWR_PLL_BIT 9
788
789/* Power Management for Mixer (0x65) */
790#define RT5640_PWR_OM_L (0x1 << 15)
791#define RT5640_PWR_OM_L_BIT 15
792#define RT5640_PWR_OM_R (0x1 << 14)
793#define RT5640_PWR_OM_R_BIT 14
794#define RT5640_PWR_SM_L (0x1 << 13)
795#define RT5640_PWR_SM_L_BIT 13
796#define RT5640_PWR_SM_R (0x1 << 12)
797#define RT5640_PWR_SM_R_BIT 12
798#define RT5640_PWR_RM_L (0x1 << 11)
799#define RT5640_PWR_RM_L_BIT 11
800#define RT5640_PWR_RM_R (0x1 << 10)
801#define RT5640_PWR_RM_R_BIT 10
802
803/* Power Management for Volume (0x66) */
804#define RT5640_PWR_SV_L (0x1 << 15)
805#define RT5640_PWR_SV_L_BIT 15
806#define RT5640_PWR_SV_R (0x1 << 14)
807#define RT5640_PWR_SV_R_BIT 14
808#define RT5640_PWR_OV_L (0x1 << 13)
809#define RT5640_PWR_OV_L_BIT 13
810#define RT5640_PWR_OV_R (0x1 << 12)
811#define RT5640_PWR_OV_R_BIT 12
812#define RT5640_PWR_HV_L (0x1 << 11)
813#define RT5640_PWR_HV_L_BIT 11
814#define RT5640_PWR_HV_R (0x1 << 10)
815#define RT5640_PWR_HV_R_BIT 10
816#define RT5640_PWR_IN_L (0x1 << 9)
817#define RT5640_PWR_IN_L_BIT 9
818#define RT5640_PWR_IN_R (0x1 << 8)
819#define RT5640_PWR_IN_R_BIT 8
820
821/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
822#define RT5640_I2S_MS_MASK (0x1 << 15)
823#define RT5640_I2S_MS_SFT 15
824#define RT5640_I2S_MS_M (0x0 << 15)
825#define RT5640_I2S_MS_S (0x1 << 15)
826#define RT5640_I2S_IF_MASK (0x7 << 12)
827#define RT5640_I2S_IF_SFT 12
828#define RT5640_I2S_O_CP_MASK (0x3 << 10)
829#define RT5640_I2S_O_CP_SFT 10
830#define RT5640_I2S_O_CP_OFF (0x0 << 10)
831#define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
832#define RT5640_I2S_O_CP_A_LAW (0x2 << 10)
833#define RT5640_I2S_I_CP_MASK (0x3 << 8)
834#define RT5640_I2S_I_CP_SFT 8
835#define RT5640_I2S_I_CP_OFF (0x0 << 8)
836#define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
837#define RT5640_I2S_I_CP_A_LAW (0x2 << 8)
838#define RT5640_I2S_BP_MASK (0x1 << 7)
839#define RT5640_I2S_BP_SFT 7
840#define RT5640_I2S_BP_NOR (0x0 << 7)
841#define RT5640_I2S_BP_INV (0x1 << 7)
842#define RT5640_I2S_DL_MASK (0x3 << 2)
843#define RT5640_I2S_DL_SFT 2
844#define RT5640_I2S_DL_16 (0x0 << 2)
845#define RT5640_I2S_DL_20 (0x1 << 2)
846#define RT5640_I2S_DL_24 (0x2 << 2)
847#define RT5640_I2S_DL_8 (0x3 << 2)
848#define RT5640_I2S_DF_MASK (0x3)
849#define RT5640_I2S_DF_SFT 0
850#define RT5640_I2S_DF_I2S (0x0)
851#define RT5640_I2S_DF_LEFT (0x1)
852#define RT5640_I2S_DF_PCM_A (0x2)
853#define RT5640_I2S_DF_PCM_B (0x3)
854
855/* I2S2 Audio Serial Data Port Control (0x71) */
856#define RT5640_I2S2_SDI_MASK (0x1 << 6)
857#define RT5640_I2S2_SDI_SFT 6
858#define RT5640_I2S2_SDI_I2S1 (0x0 << 6)
859#define RT5640_I2S2_SDI_I2S2 (0x1 << 6)
860
861/* ADC/DAC Clock Control 1 (0x73) */
862#define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15)
863#define RT5640_I2S_BCLK_MS1_SFT 15
864#define RT5640_I2S_BCLK_MS1_32 (0x0 << 15)
865#define RT5640_I2S_BCLK_MS1_64 (0x1 << 15)
866#define RT5640_I2S_PD1_MASK (0x7 << 12)
867#define RT5640_I2S_PD1_SFT 12
868#define RT5640_I2S_PD1_1 (0x0 << 12)
869#define RT5640_I2S_PD1_2 (0x1 << 12)
870#define RT5640_I2S_PD1_3 (0x2 << 12)
871#define RT5640_I2S_PD1_4 (0x3 << 12)
872#define RT5640_I2S_PD1_6 (0x4 << 12)
873#define RT5640_I2S_PD1_8 (0x5 << 12)
874#define RT5640_I2S_PD1_12 (0x6 << 12)
875#define RT5640_I2S_PD1_16 (0x7 << 12)
876#define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
877#define RT5640_I2S_BCLK_MS2_SFT 11
878#define RT5640_I2S_BCLK_MS2_32 (0x0 << 11)
879#define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
880#define RT5640_I2S_PD2_MASK (0x7 << 8)
881#define RT5640_I2S_PD2_SFT 8
882#define RT5640_I2S_PD2_1 (0x0 << 8)
883#define RT5640_I2S_PD2_2 (0x1 << 8)
884#define RT5640_I2S_PD2_3 (0x2 << 8)
885#define RT5640_I2S_PD2_4 (0x3 << 8)
886#define RT5640_I2S_PD2_6 (0x4 << 8)
887#define RT5640_I2S_PD2_8 (0x5 << 8)
888#define RT5640_I2S_PD2_12 (0x6 << 8)
889#define RT5640_I2S_PD2_16 (0x7 << 8)
890#define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7)
891#define RT5640_I2S_BCLK_MS3_SFT 7
892#define RT5640_I2S_BCLK_MS3_32 (0x0 << 7)
893#define RT5640_I2S_BCLK_MS3_64 (0x1 << 7)
894#define RT5640_I2S_PD3_MASK (0x7 << 4)
895#define RT5640_I2S_PD3_SFT 4
896#define RT5640_I2S_PD3_1 (0x0 << 4)
897#define RT5640_I2S_PD3_2 (0x1 << 4)
898#define RT5640_I2S_PD3_3 (0x2 << 4)
899#define RT5640_I2S_PD3_4 (0x3 << 4)
900#define RT5640_I2S_PD3_6 (0x4 << 4)
901#define RT5640_I2S_PD3_8 (0x5 << 4)
902#define RT5640_I2S_PD3_12 (0x6 << 4)
903#define RT5640_I2S_PD3_16 (0x7 << 4)
904#define RT5640_DAC_OSR_MASK (0x3 << 2)
905#define RT5640_DAC_OSR_SFT 2
906#define RT5640_DAC_OSR_128 (0x0 << 2)
907#define RT5640_DAC_OSR_64 (0x1 << 2)
908#define RT5640_DAC_OSR_32 (0x2 << 2)
909#define RT5640_DAC_OSR_16 (0x3 << 2)
910#define RT5640_ADC_OSR_MASK (0x3)
911#define RT5640_ADC_OSR_SFT 0
912#define RT5640_ADC_OSR_128 (0x0)
913#define RT5640_ADC_OSR_64 (0x1)
914#define RT5640_ADC_OSR_32 (0x2)
915#define RT5640_ADC_OSR_16 (0x3)
916
917/* ADC/DAC Clock Control 2 (0x74) */
918#define RT5640_DAC_L_OSR_MASK (0x3 << 14)
919#define RT5640_DAC_L_OSR_SFT 14
920#define RT5640_DAC_L_OSR_128 (0x0 << 14)
921#define RT5640_DAC_L_OSR_64 (0x1 << 14)
922#define RT5640_DAC_L_OSR_32 (0x2 << 14)
923#define RT5640_DAC_L_OSR_16 (0x3 << 14)
924#define RT5640_ADC_R_OSR_MASK (0x3 << 12)
925#define RT5640_ADC_R_OSR_SFT 12
926#define RT5640_ADC_R_OSR_128 (0x0 << 12)
927#define RT5640_ADC_R_OSR_64 (0x1 << 12)
928#define RT5640_ADC_R_OSR_32 (0x2 << 12)
929#define RT5640_ADC_R_OSR_16 (0x3 << 12)
930#define RT5640_DAHPF_EN (0x1 << 11)
931#define RT5640_DAHPF_EN_SFT 11
932#define RT5640_ADHPF_EN (0x1 << 10)
933#define RT5640_ADHPF_EN_SFT 10
934
935/* Digital Microphone Control (0x75) */
936#define RT5640_DMIC_1_EN_MASK (0x1 << 15)
937#define RT5640_DMIC_1_EN_SFT 15
938#define RT5640_DMIC_1_DIS (0x0 << 15)
939#define RT5640_DMIC_1_EN (0x1 << 15)
940#define RT5640_DMIC_2_EN_MASK (0x1 << 14)
941#define RT5640_DMIC_2_EN_SFT 14
942#define RT5640_DMIC_2_DIS (0x0 << 14)
943#define RT5640_DMIC_2_EN (0x1 << 14)
944#define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
945#define RT5640_DMIC_1L_LH_SFT 13
946#define RT5640_DMIC_1L_LH_FALLING (0x0 << 13)
947#define RT5640_DMIC_1L_LH_RISING (0x1 << 13)
948#define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
949#define RT5640_DMIC_1R_LH_SFT 12
950#define RT5640_DMIC_1R_LH_FALLING (0x0 << 12)
951#define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
952#define RT5640_DMIC_1_DP_MASK (0x1 << 11)
953#define RT5640_DMIC_1_DP_SFT 11
954#define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11)
955#define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
956#define RT5640_DMIC_2_DP_MASK (0x1 << 10)
957#define RT5640_DMIC_2_DP_SFT 10
958#define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10)
959#define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
960#define RT5640_DMIC_2L_LH_MASK (0x1 << 9)
961#define RT5640_DMIC_2L_LH_SFT 9
962#define RT5640_DMIC_2L_LH_FALLING (0x0 << 9)
963#define RT5640_DMIC_2L_LH_RISING (0x1 << 9)
964#define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
965#define RT5640_DMIC_2R_LH_SFT 8
966#define RT5640_DMIC_2R_LH_FALLING (0x0 << 8)
967#define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
968#define RT5640_DMIC_CLK_MASK (0x7 << 5)
969#define RT5640_DMIC_CLK_SFT 5
970
971/* Global Clock Control (0x80) */
972#define RT5640_SCLK_SRC_MASK (0x3 << 14)
973#define RT5640_SCLK_SRC_SFT 14
974#define RT5640_SCLK_SRC_MCLK (0x0 << 14)
975#define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
976#define RT5640_SCLK_SRC_PLL1T (0x2 << 14)
977#define RT5640_SCLK_SRC_RCCLK (0x3 << 14) /* 15MHz */
978#define RT5640_PLL1_SRC_MASK (0x3 << 12)
979#define RT5640_PLL1_SRC_SFT 12
980#define RT5640_PLL1_SRC_MCLK (0x0 << 12)
981#define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
982#define RT5640_PLL1_SRC_BCLK2 (0x2 << 12)
983#define RT5640_PLL1_SRC_BCLK3 (0x3 << 12)
984#define RT5640_PLL1_PD_MASK (0x1 << 3)
985#define RT5640_PLL1_PD_SFT 3
986#define RT5640_PLL1_PD_1 (0x0 << 3)
987#define RT5640_PLL1_PD_2 (0x1 << 3)
988
989#define RT5640_PLL_INP_MAX 40000000
990#define RT5640_PLL_INP_MIN 256000
991/* PLL M/N/K Code Control 1 (0x81) */
992#define RT5640_PLL_N_MAX 0x1ff
993#define RT5640_PLL_N_MASK (RT5640_PLL_N_MAX << 7)
994#define RT5640_PLL_N_SFT 7
995#define RT5640_PLL_K_MAX 0x1f
996#define RT5640_PLL_K_MASK (RT5640_PLL_K_MAX)
997#define RT5640_PLL_K_SFT 0
998
999/* PLL M/N/K Code Control 2 (0x82) */
1000#define RT5640_PLL_M_MAX 0xf
1001#define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12)
1002#define RT5640_PLL_M_SFT 12
1003#define RT5640_PLL_M_BP (0x1 << 11)
1004#define RT5640_PLL_M_BP_SFT 11
1005
1006/* ASRC Control 1 (0x83) */
1007#define RT5640_STO_T_MASK (0x1 << 15)
1008#define RT5640_STO_T_SFT 15
1009#define RT5640_STO_T_SCLK (0x0 << 15)
1010#define RT5640_STO_T_LRCK1 (0x1 << 15)
1011#define RT5640_M1_T_MASK (0x1 << 14)
1012#define RT5640_M1_T_SFT 14
1013#define RT5640_M1_T_I2S2 (0x0 << 14)
1014#define RT5640_M1_T_I2S2_D3 (0x1 << 14)
1015#define RT5640_I2S2_F_MASK (0x1 << 12)
1016#define RT5640_I2S2_F_SFT 12
1017#define RT5640_I2S2_F_I2S2_D2 (0x0 << 12)
1018#define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1019#define RT5640_DMIC_1_M_MASK (0x1 << 9)
1020#define RT5640_DMIC_1_M_SFT 9
1021#define RT5640_DMIC_1_M_NOR (0x0 << 9)
1022#define RT5640_DMIC_1_M_ASYN (0x1 << 9)
1023#define RT5640_DMIC_2_M_MASK (0x1 << 8)
1024#define RT5640_DMIC_2_M_SFT 8
1025#define RT5640_DMIC_2_M_NOR (0x0 << 8)
1026#define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1027
1028/* ASRC Control 2 (0x84) */
1029#define RT5640_MDA_L_M_MASK (0x1 << 15)
1030#define RT5640_MDA_L_M_SFT 15
1031#define RT5640_MDA_L_M_NOR (0x0 << 15)
1032#define RT5640_MDA_L_M_ASYN (0x1 << 15)
1033#define RT5640_MDA_R_M_MASK (0x1 << 14)
1034#define RT5640_MDA_R_M_SFT 14
1035#define RT5640_MDA_R_M_NOR (0x0 << 14)
1036#define RT5640_MDA_R_M_ASYN (0x1 << 14)
1037#define RT5640_MAD_L_M_MASK (0x1 << 13)
1038#define RT5640_MAD_L_M_SFT 13
1039#define RT5640_MAD_L_M_NOR (0x0 << 13)
1040#define RT5640_MAD_L_M_ASYN (0x1 << 13)
1041#define RT5640_MAD_R_M_MASK (0x1 << 12)
1042#define RT5640_MAD_R_M_SFT 12
1043#define RT5640_MAD_R_M_NOR (0x0 << 12)
1044#define RT5640_MAD_R_M_ASYN (0x1 << 12)
1045#define RT5640_ADC_M_MASK (0x1 << 11)
1046#define RT5640_ADC_M_SFT 11
1047#define RT5640_ADC_M_NOR (0x0 << 11)
1048#define RT5640_ADC_M_ASYN (0x1 << 11)
1049#define RT5640_STO_DAC_M_MASK (0x1 << 5)
1050#define RT5640_STO_DAC_M_SFT 5
1051#define RT5640_STO_DAC_M_NOR (0x0 << 5)
1052#define RT5640_STO_DAC_M_ASYN (0x1 << 5)
1053#define RT5640_I2S1_R_D_MASK (0x1 << 4)
1054#define RT5640_I2S1_R_D_SFT 4
1055#define RT5640_I2S1_R_D_DIS (0x0 << 4)
1056#define RT5640_I2S1_R_D_EN (0x1 << 4)
1057#define RT5640_I2S2_R_D_MASK (0x1 << 3)
1058#define RT5640_I2S2_R_D_SFT 3
1059#define RT5640_I2S2_R_D_DIS (0x0 << 3)
1060#define RT5640_I2S2_R_D_EN (0x1 << 3)
1061#define RT5640_PRE_SCLK_MASK (0x3)
1062#define RT5640_PRE_SCLK_SFT 0
1063#define RT5640_PRE_SCLK_512 (0x0)
1064#define RT5640_PRE_SCLK_1024 (0x1)
1065#define RT5640_PRE_SCLK_2048 (0x2)
1066
1067/* ASRC Control 3 (0x85) */
1068#define RT5640_I2S1_RATE_MASK (0xf << 12)
1069#define RT5640_I2S1_RATE_SFT 12
1070#define RT5640_I2S2_RATE_MASK (0xf << 8)
1071#define RT5640_I2S2_RATE_SFT 8
1072
1073/* ASRC Control 4 (0x89) */
1074#define RT5640_I2S1_PD_MASK (0x7 << 12)
1075#define RT5640_I2S1_PD_SFT 12
1076#define RT5640_I2S2_PD_MASK (0x7 << 8)
1077#define RT5640_I2S2_PD_SFT 8
1078
1079/* HPOUT Over Current Detection (0x8b) */
1080#define RT5640_HP_OVCD_MASK (0x1 << 10)
1081#define RT5640_HP_OVCD_SFT 10
1082#define RT5640_HP_OVCD_DIS (0x0 << 10)
1083#define RT5640_HP_OVCD_EN (0x1 << 10)
1084#define RT5640_HP_OC_TH_MASK (0x3 << 8)
1085#define RT5640_HP_OC_TH_SFT 8
1086#define RT5640_HP_OC_TH_90 (0x0 << 8)
1087#define RT5640_HP_OC_TH_105 (0x1 << 8)
1088#define RT5640_HP_OC_TH_120 (0x2 << 8)
1089#define RT5640_HP_OC_TH_135 (0x3 << 8)
1090
1091/* Class D Over Current Control (0x8c) */
1092#define RT5640_CLSD_OC_MASK (0x1 << 9)
1093#define RT5640_CLSD_OC_SFT 9
1094#define RT5640_CLSD_OC_PU (0x0 << 9)
1095#define RT5640_CLSD_OC_PD (0x1 << 9)
1096#define RT5640_AUTO_PD_MASK (0x1 << 8)
1097#define RT5640_AUTO_PD_SFT 8
1098#define RT5640_AUTO_PD_DIS (0x0 << 8)
1099#define RT5640_AUTO_PD_EN (0x1 << 8)
1100#define RT5640_CLSD_OC_TH_MASK (0x3f)
1101#define RT5640_CLSD_OC_TH_SFT 0
1102
1103/* Class D Output Control (0x8d) */
1104#define RT5640_CLSD_RATIO_MASK (0xf << 12)
1105#define RT5640_CLSD_RATIO_SFT 12
1106#define RT5640_CLSD_OM_MASK (0x1 << 11)
1107#define RT5640_CLSD_OM_SFT 11
1108#define RT5640_CLSD_OM_MONO (0x0 << 11)
1109#define RT5640_CLSD_OM_STO (0x1 << 11)
1110#define RT5640_CLSD_SCH_MASK (0x1 << 10)
1111#define RT5640_CLSD_SCH_SFT 10
1112#define RT5640_CLSD_SCH_L (0x0 << 10)
1113#define RT5640_CLSD_SCH_S (0x1 << 10)
1114
1115/* Depop Mode Control 1 (0x8e) */
1116#define RT5640_SMT_TRIG_MASK (0x1 << 15)
1117#define RT5640_SMT_TRIG_SFT 15
1118#define RT5640_SMT_TRIG_DIS (0x0 << 15)
1119#define RT5640_SMT_TRIG_EN (0x1 << 15)
1120#define RT5640_HP_L_SMT_MASK (0x1 << 9)
1121#define RT5640_HP_L_SMT_SFT 9
1122#define RT5640_HP_L_SMT_DIS (0x0 << 9)
1123#define RT5640_HP_L_SMT_EN (0x1 << 9)
1124#define RT5640_HP_R_SMT_MASK (0x1 << 8)
1125#define RT5640_HP_R_SMT_SFT 8
1126#define RT5640_HP_R_SMT_DIS (0x0 << 8)
1127#define RT5640_HP_R_SMT_EN (0x1 << 8)
1128#define RT5640_HP_CD_PD_MASK (0x1 << 7)
1129#define RT5640_HP_CD_PD_SFT 7
1130#define RT5640_HP_CD_PD_DIS (0x0 << 7)
1131#define RT5640_HP_CD_PD_EN (0x1 << 7)
1132#define RT5640_RSTN_MASK (0x1 << 6)
1133#define RT5640_RSTN_SFT 6
1134#define RT5640_RSTN_DIS (0x0 << 6)
1135#define RT5640_RSTN_EN (0x1 << 6)
1136#define RT5640_RSTP_MASK (0x1 << 5)
1137#define RT5640_RSTP_SFT 5
1138#define RT5640_RSTP_DIS (0x0 << 5)
1139#define RT5640_RSTP_EN (0x1 << 5)
1140#define RT5640_HP_CO_MASK (0x1 << 4)
1141#define RT5640_HP_CO_SFT 4
1142#define RT5640_HP_CO_DIS (0x0 << 4)
1143#define RT5640_HP_CO_EN (0x1 << 4)
1144#define RT5640_HP_CP_MASK (0x1 << 3)
1145#define RT5640_HP_CP_SFT 3
1146#define RT5640_HP_CP_PD (0x0 << 3)
1147#define RT5640_HP_CP_PU (0x1 << 3)
1148#define RT5640_HP_SG_MASK (0x1 << 2)
1149#define RT5640_HP_SG_SFT 2
1150#define RT5640_HP_SG_DIS (0x0 << 2)
1151#define RT5640_HP_SG_EN (0x1 << 2)
1152#define RT5640_HP_DP_MASK (0x1 << 1)
1153#define RT5640_HP_DP_SFT 1
1154#define RT5640_HP_DP_PD (0x0 << 1)
1155#define RT5640_HP_DP_PU (0x1 << 1)
1156#define RT5640_HP_CB_MASK (0x1)
1157#define RT5640_HP_CB_SFT 0
1158#define RT5640_HP_CB_PD (0x0)
1159#define RT5640_HP_CB_PU (0x1)
1160
1161/* Depop Mode Control 2 (0x8f) */
1162#define RT5640_DEPOP_MASK (0x1 << 13)
1163#define RT5640_DEPOP_SFT 13
1164#define RT5640_DEPOP_AUTO (0x0 << 13)
1165#define RT5640_DEPOP_MAN (0x1 << 13)
1166#define RT5640_RAMP_MASK (0x1 << 12)
1167#define RT5640_RAMP_SFT 12
1168#define RT5640_RAMP_DIS (0x0 << 12)
1169#define RT5640_RAMP_EN (0x1 << 12)
1170#define RT5640_BPS_MASK (0x1 << 11)
1171#define RT5640_BPS_SFT 11
1172#define RT5640_BPS_DIS (0x0 << 11)
1173#define RT5640_BPS_EN (0x1 << 11)
1174#define RT5640_FAST_UPDN_MASK (0x1 << 10)
1175#define RT5640_FAST_UPDN_SFT 10
1176#define RT5640_FAST_UPDN_DIS (0x0 << 10)
1177#define RT5640_FAST_UPDN_EN (0x1 << 10)
1178#define RT5640_MRES_MASK (0x3 << 8)
1179#define RT5640_MRES_SFT 8
1180#define RT5640_MRES_15MO (0x0 << 8)
1181#define RT5640_MRES_25MO (0x1 << 8)
1182#define RT5640_MRES_35MO (0x2 << 8)
1183#define RT5640_MRES_45MO (0x3 << 8)
1184#define RT5640_VLO_MASK (0x1 << 7)
1185#define RT5640_VLO_SFT 7
1186#define RT5640_VLO_3V (0x0 << 7)
1187#define RT5640_VLO_32V (0x1 << 7)
1188#define RT5640_DIG_DP_MASK (0x1 << 6)
1189#define RT5640_DIG_DP_SFT 6
1190#define RT5640_DIG_DP_DIS (0x0 << 6)
1191#define RT5640_DIG_DP_EN (0x1 << 6)
1192#define RT5640_DP_TH_MASK (0x3 << 4)
1193#define RT5640_DP_TH_SFT 4
1194
1195/* Depop Mode Control 3 (0x90) */
1196#define RT5640_CP_SYS_MASK (0x7 << 12)
1197#define RT5640_CP_SYS_SFT 12
1198#define RT5640_CP_FQ1_MASK (0x7 << 8)
1199#define RT5640_CP_FQ1_SFT 8
1200#define RT5640_CP_FQ2_MASK (0x7 << 4)
1201#define RT5640_CP_FQ2_SFT 4
1202#define RT5640_CP_FQ3_MASK (0x7)
1203#define RT5640_CP_FQ3_SFT 0
1204
1205/* HPOUT charge pump (0x91) */
1206#define RT5640_OSW_L_MASK (0x1 << 11)
1207#define RT5640_OSW_L_SFT 11
1208#define RT5640_OSW_L_DIS (0x0 << 11)
1209#define RT5640_OSW_L_EN (0x1 << 11)
1210#define RT5640_OSW_R_MASK (0x1 << 10)
1211#define RT5640_OSW_R_SFT 10
1212#define RT5640_OSW_R_DIS (0x0 << 10)
1213#define RT5640_OSW_R_EN (0x1 << 10)
1214#define RT5640_PM_HP_MASK (0x3 << 8)
1215#define RT5640_PM_HP_SFT 8
1216#define RT5640_PM_HP_LV (0x0 << 8)
1217#define RT5640_PM_HP_MV (0x1 << 8)
1218#define RT5640_PM_HP_HV (0x2 << 8)
1219#define RT5640_IB_HP_MASK (0x3 << 6)
1220#define RT5640_IB_HP_SFT 6
1221#define RT5640_IB_HP_125IL (0x0 << 6)
1222#define RT5640_IB_HP_25IL (0x1 << 6)
1223#define RT5640_IB_HP_5IL (0x2 << 6)
1224#define RT5640_IB_HP_1IL (0x3 << 6)
1225
1226/* PV detection and SPK gain control (0x92) */
1227#define RT5640_PVDD_DET_MASK (0x1 << 15)
1228#define RT5640_PVDD_DET_SFT 15
1229#define RT5640_PVDD_DET_DIS (0x0 << 15)
1230#define RT5640_PVDD_DET_EN (0x1 << 15)
1231#define RT5640_SPK_AG_MASK (0x1 << 14)
1232#define RT5640_SPK_AG_SFT 14
1233#define RT5640_SPK_AG_DIS (0x0 << 14)
1234#define RT5640_SPK_AG_EN (0x1 << 14)
1235
1236/* Micbias Control (0x93) */
1237#define RT5640_MIC1_BS_MASK (0x1 << 15)
1238#define RT5640_MIC1_BS_SFT 15
1239#define RT5640_MIC1_BS_9AV (0x0 << 15)
1240#define RT5640_MIC1_BS_75AV (0x1 << 15)
1241#define RT5640_MIC2_BS_MASK (0x1 << 14)
1242#define RT5640_MIC2_BS_SFT 14
1243#define RT5640_MIC2_BS_9AV (0x0 << 14)
1244#define RT5640_MIC2_BS_75AV (0x1 << 14)
1245#define RT5640_MIC1_CLK_MASK (0x1 << 13)
1246#define RT5640_MIC1_CLK_SFT 13
1247#define RT5640_MIC1_CLK_DIS (0x0 << 13)
1248#define RT5640_MIC1_CLK_EN (0x1 << 13)
1249#define RT5640_MIC2_CLK_MASK (0x1 << 12)
1250#define RT5640_MIC2_CLK_SFT 12
1251#define RT5640_MIC2_CLK_DIS (0x0 << 12)
1252#define RT5640_MIC2_CLK_EN (0x1 << 12)
1253#define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1254#define RT5640_MIC1_OVCD_SFT 11
1255#define RT5640_MIC1_OVCD_DIS (0x0 << 11)
1256#define RT5640_MIC1_OVCD_EN (0x1 << 11)
1257#define RT5640_MIC1_OVTH_MASK (0x3 << 9)
1258#define RT5640_MIC1_OVTH_SFT 9
1259#define RT5640_MIC1_OVTH_600UA (0x0 << 9)
1260#define RT5640_MIC1_OVTH_1500UA (0x1 << 9)
1261#define RT5640_MIC1_OVTH_2000UA (0x2 << 9)
1262#define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1263#define RT5640_MIC2_OVCD_SFT 8
1264#define RT5640_MIC2_OVCD_DIS (0x0 << 8)
1265#define RT5640_MIC2_OVCD_EN (0x1 << 8)
1266#define RT5640_MIC2_OVTH_MASK (0x3 << 6)
1267#define RT5640_MIC2_OVTH_SFT 6
1268#define RT5640_MIC2_OVTH_600UA (0x0 << 6)
1269#define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
1270#define RT5640_MIC2_OVTH_2000UA (0x2 << 6)
1271#define RT5640_PWR_MB_MASK (0x1 << 5)
1272#define RT5640_PWR_MB_SFT 5
1273#define RT5640_PWR_MB_PD (0x0 << 5)
1274#define RT5640_PWR_MB_PU (0x1 << 5)
1275#define RT5640_PWR_CLK25M_MASK (0x1 << 4)
1276#define RT5640_PWR_CLK25M_SFT 4
1277#define RT5640_PWR_CLK25M_PD (0x0 << 4)
1278#define RT5640_PWR_CLK25M_PU (0x1 << 4)
1279
1280/* EQ Control 1 (0xb0) */
1281#define RT5640_EQ_SRC_MASK (0x1 << 15)
1282#define RT5640_EQ_SRC_SFT 15
1283#define RT5640_EQ_SRC_DAC (0x0 << 15)
1284#define RT5640_EQ_SRC_ADC (0x1 << 15)
1285#define RT5640_EQ_UPD (0x1 << 14)
1286#define RT5640_EQ_UPD_BIT 14
1287#define RT5640_EQ_CD_MASK (0x1 << 13)
1288#define RT5640_EQ_CD_SFT 13
1289#define RT5640_EQ_CD_DIS (0x0 << 13)
1290#define RT5640_EQ_CD_EN (0x1 << 13)
1291#define RT5640_EQ_DITH_MASK (0x3 << 8)
1292#define RT5640_EQ_DITH_SFT 8
1293#define RT5640_EQ_DITH_NOR (0x0 << 8)
1294#define RT5640_EQ_DITH_LSB (0x1 << 8)
1295#define RT5640_EQ_DITH_LSB_1 (0x2 << 8)
1296#define RT5640_EQ_DITH_LSB_2 (0x3 << 8)
1297
1298/* EQ Control 2 (0xb1) */
1299#define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1300#define RT5640_EQ_HPF1_M_SFT 8
1301#define RT5640_EQ_HPF1_M_HI (0x0 << 8)
1302#define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1303#define RT5640_EQ_LPF1_M_MASK (0x1 << 7)
1304#define RT5640_EQ_LPF1_M_SFT 7
1305#define RT5640_EQ_LPF1_M_LO (0x0 << 7)
1306#define RT5640_EQ_LPF1_M_1ST (0x1 << 7)
1307#define RT5640_EQ_HPF2_MASK (0x1 << 6)
1308#define RT5640_EQ_HPF2_SFT 6
1309#define RT5640_EQ_HPF2_DIS (0x0 << 6)
1310#define RT5640_EQ_HPF2_EN (0x1 << 6)
1311#define RT5640_EQ_HPF1_MASK (0x1 << 5)
1312#define RT5640_EQ_HPF1_SFT 5
1313#define RT5640_EQ_HPF1_DIS (0x0 << 5)
1314#define RT5640_EQ_HPF1_EN (0x1 << 5)
1315#define RT5640_EQ_BPF4_MASK (0x1 << 4)
1316#define RT5640_EQ_BPF4_SFT 4
1317#define RT5640_EQ_BPF4_DIS (0x0 << 4)
1318#define RT5640_EQ_BPF4_EN (0x1 << 4)
1319#define RT5640_EQ_BPF3_MASK (0x1 << 3)
1320#define RT5640_EQ_BPF3_SFT 3
1321#define RT5640_EQ_BPF3_DIS (0x0 << 3)
1322#define RT5640_EQ_BPF3_EN (0x1 << 3)
1323#define RT5640_EQ_BPF2_MASK (0x1 << 2)
1324#define RT5640_EQ_BPF2_SFT 2
1325#define RT5640_EQ_BPF2_DIS (0x0 << 2)
1326#define RT5640_EQ_BPF2_EN (0x1 << 2)
1327#define RT5640_EQ_BPF1_MASK (0x1 << 1)
1328#define RT5640_EQ_BPF1_SFT 1
1329#define RT5640_EQ_BPF1_DIS (0x0 << 1)
1330#define RT5640_EQ_BPF1_EN (0x1 << 1)
1331#define RT5640_EQ_LPF_MASK (0x1)
1332#define RT5640_EQ_LPF_SFT 0
1333#define RT5640_EQ_LPF_DIS (0x0)
1334#define RT5640_EQ_LPF_EN (0x1)
1335
1336/* Memory Test (0xb2) */
1337#define RT5640_MT_MASK (0x1 << 15)
1338#define RT5640_MT_SFT 15
1339#define RT5640_MT_DIS (0x0 << 15)
1340#define RT5640_MT_EN (0x1 << 15)
1341
1342/* DRC/AGC Control 1 (0xb4) */
1343#define RT5640_DRC_AGC_P_MASK (0x1 << 15)
1344#define RT5640_DRC_AGC_P_SFT 15
1345#define RT5640_DRC_AGC_P_DAC (0x0 << 15)
1346#define RT5640_DRC_AGC_P_ADC (0x1 << 15)
1347#define RT5640_DRC_AGC_MASK (0x1 << 14)
1348#define RT5640_DRC_AGC_SFT 14
1349#define RT5640_DRC_AGC_DIS (0x0 << 14)
1350#define RT5640_DRC_AGC_EN (0x1 << 14)
1351#define RT5640_DRC_AGC_UPD (0x1 << 13)
1352#define RT5640_DRC_AGC_UPD_BIT 13
1353#define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
1354#define RT5640_DRC_AGC_AR_SFT 8
1355#define RT5640_DRC_AGC_R_MASK (0x7 << 5)
1356#define RT5640_DRC_AGC_R_SFT 5
1357#define RT5640_DRC_AGC_R_48K (0x1 << 5)
1358#define RT5640_DRC_AGC_R_96K (0x2 << 5)
1359#define RT5640_DRC_AGC_R_192K (0x3 << 5)
1360#define RT5640_DRC_AGC_R_441K (0x5 << 5)
1361#define RT5640_DRC_AGC_R_882K (0x6 << 5)
1362#define RT5640_DRC_AGC_R_1764K (0x7 << 5)
1363#define RT5640_DRC_AGC_RC_MASK (0x1f)
1364#define RT5640_DRC_AGC_RC_SFT 0
1365
1366/* DRC/AGC Control 2 (0xb5) */
1367#define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
1368#define RT5640_DRC_AGC_POB_SFT 8
1369#define RT5640_DRC_AGC_CP_MASK (0x1 << 7)
1370#define RT5640_DRC_AGC_CP_SFT 7
1371#define RT5640_DRC_AGC_CP_DIS (0x0 << 7)
1372#define RT5640_DRC_AGC_CP_EN (0x1 << 7)
1373#define RT5640_DRC_AGC_CPR_MASK (0x3 << 5)
1374#define RT5640_DRC_AGC_CPR_SFT 5
1375#define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5)
1376#define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5)
1377#define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5)
1378#define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5)
1379#define RT5640_DRC_AGC_PRB_MASK (0x1f)
1380#define RT5640_DRC_AGC_PRB_SFT 0
1381
1382/* DRC/AGC Control 3 (0xb6) */
1383#define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
1384#define RT5640_DRC_AGC_NGB_SFT 12
1385#define RT5640_DRC_AGC_TAR_MASK (0x1f << 7)
1386#define RT5640_DRC_AGC_TAR_SFT 7
1387#define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
1388#define RT5640_DRC_AGC_NG_SFT 6
1389#define RT5640_DRC_AGC_NG_DIS (0x0 << 6)
1390#define RT5640_DRC_AGC_NG_EN (0x1 << 6)
1391#define RT5640_DRC_AGC_NGH_MASK (0x1 << 5)
1392#define RT5640_DRC_AGC_NGH_SFT 5
1393#define RT5640_DRC_AGC_NGH_DIS (0x0 << 5)
1394#define RT5640_DRC_AGC_NGH_EN (0x1 << 5)
1395#define RT5640_DRC_AGC_NGT_MASK (0x1f)
1396#define RT5640_DRC_AGC_NGT_SFT 0
1397
1398/* ANC Control 1 (0xb8) */
1399#define RT5640_ANC_M_MASK (0x1 << 15)
1400#define RT5640_ANC_M_SFT 15
1401#define RT5640_ANC_M_NOR (0x0 << 15)
1402#define RT5640_ANC_M_REV (0x1 << 15)
1403#define RT5640_ANC_MASK (0x1 << 14)
1404#define RT5640_ANC_SFT 14
1405#define RT5640_ANC_DIS (0x0 << 14)
1406#define RT5640_ANC_EN (0x1 << 14)
1407#define RT5640_ANC_MD_MASK (0x3 << 12)
1408#define RT5640_ANC_MD_SFT 12
1409#define RT5640_ANC_MD_DIS (0x0 << 12)
1410#define RT5640_ANC_MD_67MS (0x1 << 12)
1411#define RT5640_ANC_MD_267MS (0x2 << 12)
1412#define RT5640_ANC_MD_1067MS (0x3 << 12)
1413#define RT5640_ANC_SN_MASK (0x1 << 11)
1414#define RT5640_ANC_SN_SFT 11
1415#define RT5640_ANC_SN_DIS (0x0 << 11)
1416#define RT5640_ANC_SN_EN (0x1 << 11)
1417#define RT5640_ANC_CLK_MASK (0x1 << 10)
1418#define RT5640_ANC_CLK_SFT 10
1419#define RT5640_ANC_CLK_ANC (0x0 << 10)
1420#define RT5640_ANC_CLK_REG (0x1 << 10)
1421#define RT5640_ANC_ZCD_MASK (0x3 << 8)
1422#define RT5640_ANC_ZCD_SFT 8
1423#define RT5640_ANC_ZCD_DIS (0x0 << 8)
1424#define RT5640_ANC_ZCD_T1 (0x1 << 8)
1425#define RT5640_ANC_ZCD_T2 (0x2 << 8)
1426#define RT5640_ANC_ZCD_WT (0x3 << 8)
1427#define RT5640_ANC_CS_MASK (0x1 << 7)
1428#define RT5640_ANC_CS_SFT 7
1429#define RT5640_ANC_CS_DIS (0x0 << 7)
1430#define RT5640_ANC_CS_EN (0x1 << 7)
1431#define RT5640_ANC_SW_MASK (0x1 << 6)
1432#define RT5640_ANC_SW_SFT 6
1433#define RT5640_ANC_SW_NOR (0x0 << 6)
1434#define RT5640_ANC_SW_AUTO (0x1 << 6)
1435#define RT5640_ANC_CO_L_MASK (0x3f)
1436#define RT5640_ANC_CO_L_SFT 0
1437
1438/* ANC Control 2 (0xb6) */
1439#define RT5640_ANC_FG_R_MASK (0xf << 12)
1440#define RT5640_ANC_FG_R_SFT 12
1441#define RT5640_ANC_FG_L_MASK (0xf << 8)
1442#define RT5640_ANC_FG_L_SFT 8
1443#define RT5640_ANC_CG_R_MASK (0xf << 4)
1444#define RT5640_ANC_CG_R_SFT 4
1445#define RT5640_ANC_CG_L_MASK (0xf)
1446#define RT5640_ANC_CG_L_SFT 0
1447
1448/* ANC Control 3 (0xb6) */
1449#define RT5640_ANC_CD_MASK (0x1 << 6)
1450#define RT5640_ANC_CD_SFT 6
1451#define RT5640_ANC_CD_BOTH (0x0 << 6)
1452#define RT5640_ANC_CD_IND (0x1 << 6)
1453#define RT5640_ANC_CO_R_MASK (0x3f)
1454#define RT5640_ANC_CO_R_SFT 0
1455
1456/* Jack Detect Control (0xbb) */
1457#define RT5640_JD_MASK (0x7 << 13)
1458#define RT5640_JD_SFT 13
1459#define RT5640_JD_DIS (0x0 << 13)
1460#define RT5640_JD_GPIO1 (0x1 << 13)
1461#define RT5640_JD_JD1_IN4P (0x2 << 13)
1462#define RT5640_JD_JD2_IN4N (0x3 << 13)
1463#define RT5640_JD_GPIO2 (0x4 << 13)
1464#define RT5640_JD_GPIO3 (0x5 << 13)
1465#define RT5640_JD_GPIO4 (0x6 << 13)
1466#define RT5640_JD_HP_MASK (0x1 << 11)
1467#define RT5640_JD_HP_SFT 11
1468#define RT5640_JD_HP_DIS (0x0 << 11)
1469#define RT5640_JD_HP_EN (0x1 << 11)
1470#define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1471#define RT5640_JD_HP_TRG_SFT 10
1472#define RT5640_JD_HP_TRG_LO (0x0 << 10)
1473#define RT5640_JD_HP_TRG_HI (0x1 << 10)
1474#define RT5640_JD_SPL_MASK (0x1 << 9)
1475#define RT5640_JD_SPL_SFT 9
1476#define RT5640_JD_SPL_DIS (0x0 << 9)
1477#define RT5640_JD_SPL_EN (0x1 << 9)
1478#define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1479#define RT5640_JD_SPL_TRG_SFT 8
1480#define RT5640_JD_SPL_TRG_LO (0x0 << 8)
1481#define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1482#define RT5640_JD_SPR_MASK (0x1 << 7)
1483#define RT5640_JD_SPR_SFT 7
1484#define RT5640_JD_SPR_DIS (0x0 << 7)
1485#define RT5640_JD_SPR_EN (0x1 << 7)
1486#define RT5640_JD_SPR_TRG_MASK (0x1 << 6)
1487#define RT5640_JD_SPR_TRG_SFT 6
1488#define RT5640_JD_SPR_TRG_LO (0x0 << 6)
1489#define RT5640_JD_SPR_TRG_HI (0x1 << 6)
1490#define RT5640_JD_MO_MASK (0x1 << 5)
1491#define RT5640_JD_MO_SFT 5
1492#define RT5640_JD_MO_DIS (0x0 << 5)
1493#define RT5640_JD_MO_EN (0x1 << 5)
1494#define RT5640_JD_MO_TRG_MASK (0x1 << 4)
1495#define RT5640_JD_MO_TRG_SFT 4
1496#define RT5640_JD_MO_TRG_LO (0x0 << 4)
1497#define RT5640_JD_MO_TRG_HI (0x1 << 4)
1498#define RT5640_JD_LO_MASK (0x1 << 3)
1499#define RT5640_JD_LO_SFT 3
1500#define RT5640_JD_LO_DIS (0x0 << 3)
1501#define RT5640_JD_LO_EN (0x1 << 3)
1502#define RT5640_JD_LO_TRG_MASK (0x1 << 2)
1503#define RT5640_JD_LO_TRG_SFT 2
1504#define RT5640_JD_LO_TRG_LO (0x0 << 2)
1505#define RT5640_JD_LO_TRG_HI (0x1 << 2)
1506#define RT5640_JD1_IN4P_MASK (0x1 << 1)
1507#define RT5640_JD1_IN4P_SFT 1
1508#define RT5640_JD1_IN4P_DIS (0x0 << 1)
1509#define RT5640_JD1_IN4P_EN (0x1 << 1)
1510#define RT5640_JD2_IN4N_MASK (0x1)
1511#define RT5640_JD2_IN4N_SFT 0
1512#define RT5640_JD2_IN4N_DIS (0x0)
1513#define RT5640_JD2_IN4N_EN (0x1)
1514
1515/* Jack detect for ANC (0xbc) */
1516#define RT5640_ANC_DET_MASK (0x3 << 4)
1517#define RT5640_ANC_DET_SFT 4
1518#define RT5640_ANC_DET_DIS (0x0 << 4)
1519#define RT5640_ANC_DET_MB1 (0x1 << 4)
1520#define RT5640_ANC_DET_MB2 (0x2 << 4)
1521#define RT5640_ANC_DET_JD (0x3 << 4)
1522#define RT5640_AD_TRG_MASK (0x1 << 3)
1523#define RT5640_AD_TRG_SFT 3
1524#define RT5640_AD_TRG_LO (0x0 << 3)
1525#define RT5640_AD_TRG_HI (0x1 << 3)
1526#define RT5640_ANCM_DET_MASK (0x3 << 4)
1527#define RT5640_ANCM_DET_SFT 4
1528#define RT5640_ANCM_DET_DIS (0x0 << 4)
1529#define RT5640_ANCM_DET_MB1 (0x1 << 4)
1530#define RT5640_ANCM_DET_MB2 (0x2 << 4)
1531#define RT5640_ANCM_DET_JD (0x3 << 4)
1532#define RT5640_AMD_TRG_MASK (0x1 << 3)
1533#define RT5640_AMD_TRG_SFT 3
1534#define RT5640_AMD_TRG_LO (0x0 << 3)
1535#define RT5640_AMD_TRG_HI (0x1 << 3)
1536
1537/* IRQ Control 1 (0xbd) */
1538#define RT5640_IRQ_JD_MASK (0x1 << 15)
1539#define RT5640_IRQ_JD_SFT 15
1540#define RT5640_IRQ_JD_BP (0x0 << 15)
1541#define RT5640_IRQ_JD_NOR (0x1 << 15)
1542#define RT5640_IRQ_OT_MASK (0x1 << 14)
1543#define RT5640_IRQ_OT_SFT 14
1544#define RT5640_IRQ_OT_BP (0x0 << 14)
1545#define RT5640_IRQ_OT_NOR (0x1 << 14)
1546#define RT5640_JD_STKY_MASK (0x1 << 13)
1547#define RT5640_JD_STKY_SFT 13
1548#define RT5640_JD_STKY_DIS (0x0 << 13)
1549#define RT5640_JD_STKY_EN (0x1 << 13)
1550#define RT5640_OT_STKY_MASK (0x1 << 12)
1551#define RT5640_OT_STKY_SFT 12
1552#define RT5640_OT_STKY_DIS (0x0 << 12)
1553#define RT5640_OT_STKY_EN (0x1 << 12)
1554#define RT5640_JD_P_MASK (0x1 << 11)
1555#define RT5640_JD_P_SFT 11
1556#define RT5640_JD_P_NOR (0x0 << 11)
1557#define RT5640_JD_P_INV (0x1 << 11)
1558#define RT5640_OT_P_MASK (0x1 << 10)
1559#define RT5640_OT_P_SFT 10
1560#define RT5640_OT_P_NOR (0x0 << 10)
1561#define RT5640_OT_P_INV (0x1 << 10)
1562
1563/* IRQ Control 2 (0xbe) */
1564#define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
1565#define RT5640_IRQ_MB1_OC_SFT 15
1566#define RT5640_IRQ_MB1_OC_BP (0x0 << 15)
1567#define RT5640_IRQ_MB1_OC_NOR (0x1 << 15)
1568#define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
1569#define RT5640_IRQ_MB2_OC_SFT 14
1570#define RT5640_IRQ_MB2_OC_BP (0x0 << 14)
1571#define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
1572#define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1573#define RT5640_MB1_OC_STKY_SFT 11
1574#define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
1575#define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1576#define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1577#define RT5640_MB2_OC_STKY_SFT 10
1578#define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
1579#define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1580#define RT5640_MB1_OC_P_MASK (0x1 << 7)
1581#define RT5640_MB1_OC_P_SFT 7
1582#define RT5640_MB1_OC_P_NOR (0x0 << 7)
1583#define RT5640_MB1_OC_P_INV (0x1 << 7)
1584#define RT5640_MB2_OC_P_MASK (0x1 << 6)
1585#define RT5640_MB2_OC_P_SFT 6
1586#define RT5640_MB2_OC_P_NOR (0x0 << 6)
1587#define RT5640_MB2_OC_P_INV (0x1 << 6)
1588#define RT5640_MB1_OC_CLR (0x1 << 3)
1589#define RT5640_MB1_OC_CLR_SFT 3
1590#define RT5640_MB2_OC_CLR (0x1 << 2)
1591#define RT5640_MB2_OC_CLR_SFT 2
1592
1593/* GPIO Control 1 (0xc0) */
1594#define RT5640_GP1_PIN_MASK (0x1 << 15)
1595#define RT5640_GP1_PIN_SFT 15
1596#define RT5640_GP1_PIN_GPIO1 (0x0 << 15)
1597#define RT5640_GP1_PIN_IRQ (0x1 << 15)
1598#define RT5640_GP2_PIN_MASK (0x1 << 14)
1599#define RT5640_GP2_PIN_SFT 14
1600#define RT5640_GP2_PIN_GPIO2 (0x0 << 14)
1601#define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14)
1602#define RT5640_GP3_PIN_MASK (0x3 << 12)
1603#define RT5640_GP3_PIN_SFT 12
1604#define RT5640_GP3_PIN_GPIO3 (0x0 << 12)
1605#define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1606#define RT5640_GP3_PIN_IRQ (0x2 << 12)
1607#define RT5640_GP4_PIN_MASK (0x1 << 11)
1608#define RT5640_GP4_PIN_SFT 11
1609#define RT5640_GP4_PIN_GPIO4 (0x0 << 11)
1610#define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1611#define RT5640_DP_SIG_MASK (0x1 << 10)
1612#define RT5640_DP_SIG_SFT 10
1613#define RT5640_DP_SIG_TEST (0x0 << 10)
1614#define RT5640_DP_SIG_AP (0x1 << 10)
1615#define RT5640_GPIO_M_MASK (0x1 << 9)
1616#define RT5640_GPIO_M_SFT 9
1617#define RT5640_GPIO_M_FLT (0x0 << 9)
1618#define RT5640_GPIO_M_PH (0x1 << 9)
1619
1620/* GPIO Control 3 (0xc2) */
1621#define RT5640_GP4_PF_MASK (0x1 << 11)
1622#define RT5640_GP4_PF_SFT 11
1623#define RT5640_GP4_PF_IN (0x0 << 11)
1624#define RT5640_GP4_PF_OUT (0x1 << 11)
1625#define RT5640_GP4_OUT_MASK (0x1 << 10)
1626#define RT5640_GP4_OUT_SFT 10
1627#define RT5640_GP4_OUT_LO (0x0 << 10)
1628#define RT5640_GP4_OUT_HI (0x1 << 10)
1629#define RT5640_GP4_P_MASK (0x1 << 9)
1630#define RT5640_GP4_P_SFT 9
1631#define RT5640_GP4_P_NOR (0x0 << 9)
1632#define RT5640_GP4_P_INV (0x1 << 9)
1633#define RT5640_GP3_PF_MASK (0x1 << 8)
1634#define RT5640_GP3_PF_SFT 8
1635#define RT5640_GP3_PF_IN (0x0 << 8)
1636#define RT5640_GP3_PF_OUT (0x1 << 8)
1637#define RT5640_GP3_OUT_MASK (0x1 << 7)
1638#define RT5640_GP3_OUT_SFT 7
1639#define RT5640_GP3_OUT_LO (0x0 << 7)
1640#define RT5640_GP3_OUT_HI (0x1 << 7)
1641#define RT5640_GP3_P_MASK (0x1 << 6)
1642#define RT5640_GP3_P_SFT 6
1643#define RT5640_GP3_P_NOR (0x0 << 6)
1644#define RT5640_GP3_P_INV (0x1 << 6)
1645#define RT5640_GP2_PF_MASK (0x1 << 5)
1646#define RT5640_GP2_PF_SFT 5
1647#define RT5640_GP2_PF_IN (0x0 << 5)
1648#define RT5640_GP2_PF_OUT (0x1 << 5)
1649#define RT5640_GP2_OUT_MASK (0x1 << 4)
1650#define RT5640_GP2_OUT_SFT 4
1651#define RT5640_GP2_OUT_LO (0x0 << 4)
1652#define RT5640_GP2_OUT_HI (0x1 << 4)
1653#define RT5640_GP2_P_MASK (0x1 << 3)
1654#define RT5640_GP2_P_SFT 3
1655#define RT5640_GP2_P_NOR (0x0 << 3)
1656#define RT5640_GP2_P_INV (0x1 << 3)
1657#define RT5640_GP1_PF_MASK (0x1 << 2)
1658#define RT5640_GP1_PF_SFT 2
1659#define RT5640_GP1_PF_IN (0x0 << 2)
1660#define RT5640_GP1_PF_OUT (0x1 << 2)
1661#define RT5640_GP1_OUT_MASK (0x1 << 1)
1662#define RT5640_GP1_OUT_SFT 1
1663#define RT5640_GP1_OUT_LO (0x0 << 1)
1664#define RT5640_GP1_OUT_HI (0x1 << 1)
1665#define RT5640_GP1_P_MASK (0x1)
1666#define RT5640_GP1_P_SFT 0
1667#define RT5640_GP1_P_NOR (0x0)
1668#define RT5640_GP1_P_INV (0x1)
1669
1670/* FM34-500 Register Control 1 (0xc4) */
1671#define RT5640_DSP_ADD_SFT 0
1672
1673/* FM34-500 Register Control 2 (0xc5) */
1674#define RT5640_DSP_DAT_SFT 0
1675
1676/* FM34-500 Register Control 3 (0xc6) */
1677#define RT5640_DSP_BUSY_MASK (0x1 << 15)
1678#define RT5640_DSP_BUSY_BIT 15
1679#define RT5640_DSP_DS_MASK (0x1 << 14)
1680#define RT5640_DSP_DS_SFT 14
1681#define RT5640_DSP_DS_FM3010 (0x1 << 14)
1682#define RT5640_DSP_DS_TEMP (0x1 << 14)
1683#define RT5640_DSP_CLK_MASK (0x3 << 12)
1684#define RT5640_DSP_CLK_SFT 12
1685#define RT5640_DSP_CLK_384K (0x0 << 12)
1686#define RT5640_DSP_CLK_192K (0x1 << 12)
1687#define RT5640_DSP_CLK_96K (0x2 << 12)
1688#define RT5640_DSP_CLK_64K (0x3 << 12)
1689#define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1690#define RT5640_DSP_PD_PIN_SFT 11
1691#define RT5640_DSP_PD_PIN_LO (0x0 << 11)
1692#define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1693#define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1694#define RT5640_DSP_RST_PIN_SFT 10
1695#define RT5640_DSP_RST_PIN_LO (0x0 << 10)
1696#define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1697#define RT5640_DSP_R_EN (0x1 << 9)
1698#define RT5640_DSP_R_EN_BIT 9
1699#define RT5640_DSP_W_EN (0x1 << 8)
1700#define RT5640_DSP_W_EN_BIT 8
1701#define RT5640_DSP_CMD_MASK (0xff)
1702#define RT5640_DSP_CMD_SFT 0
1703#define RT5640_DSP_CMD_MW (0x3B) /* Memory Write */
1704#define RT5640_DSP_CMD_MR (0x37) /* Memory Read */
1705#define RT5640_DSP_CMD_RR (0x60) /* Register Read */
1706#define RT5640_DSP_CMD_RW (0x68) /* Register Write */
1707
1708/* Programmable Register Array Control 1 (0xc8) */
1709#define RT5640_REG_SEQ_MASK (0xf << 12)
1710#define RT5640_REG_SEQ_SFT 12
1711#define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1712#define RT5640_SEQ1_ST_SFT 11
1713#define RT5640_SEQ1_ST_RUN (0x0 << 11)
1714#define RT5640_SEQ1_ST_FIN (0x1 << 11)
1715#define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1716#define RT5640_SEQ2_ST_SFT 10
1717#define RT5640_SEQ2_ST_RUN (0x0 << 10)
1718#define RT5640_SEQ2_ST_FIN (0x1 << 10)
1719#define RT5640_REG_LV_MASK (0x1 << 9)
1720#define RT5640_REG_LV_SFT 9
1721#define RT5640_REG_LV_MX (0x0 << 9)
1722#define RT5640_REG_LV_PR (0x1 << 9)
1723#define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1724#define RT5640_SEQ_2_PT_BIT 8
1725#define RT5640_REG_IDX_MASK (0xff)
1726#define RT5640_REG_IDX_SFT 0
1727
1728/* Programmable Register Array Control 2 (0xc9) */
1729#define RT5640_REG_DAT_MASK (0xffff)
1730#define RT5640_REG_DAT_SFT 0
1731
1732/* Programmable Register Array Control 3 (0xca) */
1733#define RT5640_SEQ_DLY_MASK (0xff << 8)
1734#define RT5640_SEQ_DLY_SFT 8
1735#define RT5640_PROG_MASK (0x1 << 7)
1736#define RT5640_PROG_SFT 7
1737#define RT5640_PROG_DIS (0x0 << 7)
1738#define RT5640_PROG_EN (0x1 << 7)
1739#define RT5640_SEQ1_PT_RUN (0x1 << 6)
1740#define RT5640_SEQ1_PT_RUN_BIT 6
1741#define RT5640_SEQ2_PT_RUN (0x1 << 5)
1742#define RT5640_SEQ2_PT_RUN_BIT 5
1743
1744/* Programmable Register Array Control 4 (0xcb) */
1745#define RT5640_SEQ1_START_MASK (0xf << 8)
1746#define RT5640_SEQ1_START_SFT 8
1747#define RT5640_SEQ1_END_MASK (0xf)
1748#define RT5640_SEQ1_END_SFT 0
1749
1750/* Programmable Register Array Control 5 (0xcc) */
1751#define RT5640_SEQ2_START_MASK (0xf << 8)
1752#define RT5640_SEQ2_START_SFT 8
1753#define RT5640_SEQ2_END_MASK (0xf)
1754#define RT5640_SEQ2_END_SFT 0
1755
1756/* Scramble Function (0xcd) */
1757#define RT5640_SCB_KEY_MASK (0xff)
1758#define RT5640_SCB_KEY_SFT 0
1759
1760/* Scramble Control (0xce) */
1761#define RT5640_SCB_SWAP_MASK (0x1 << 15)
1762#define RT5640_SCB_SWAP_SFT 15
1763#define RT5640_SCB_SWAP_DIS (0x0 << 15)
1764#define RT5640_SCB_SWAP_EN (0x1 << 15)
1765#define RT5640_SCB_MASK (0x1 << 14)
1766#define RT5640_SCB_SFT 14
1767#define RT5640_SCB_DIS (0x0 << 14)
1768#define RT5640_SCB_EN (0x1 << 14)
1769
1770/* Baseback Control (0xcf) */
1771#define RT5640_BB_MASK (0x1 << 15)
1772#define RT5640_BB_SFT 15
1773#define RT5640_BB_DIS (0x0 << 15)
1774#define RT5640_BB_EN (0x1 << 15)
1775#define RT5640_BB_CT_MASK (0x7 << 12)
1776#define RT5640_BB_CT_SFT 12
1777#define RT5640_BB_CT_A (0x0 << 12)
1778#define RT5640_BB_CT_B (0x1 << 12)
1779#define RT5640_BB_CT_C (0x2 << 12)
1780#define RT5640_BB_CT_D (0x3 << 12)
1781#define RT5640_M_BB_L_MASK (0x1 << 9)
1782#define RT5640_M_BB_L_SFT 9
1783#define RT5640_M_BB_R_MASK (0x1 << 8)
1784#define RT5640_M_BB_R_SFT 8
1785#define RT5640_M_BB_HPF_L_MASK (0x1 << 7)
1786#define RT5640_M_BB_HPF_L_SFT 7
1787#define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
1788#define RT5640_M_BB_HPF_R_SFT 6
1789#define RT5640_G_BB_BST_MASK (0x3f)
1790#define RT5640_G_BB_BST_SFT 0
1791
1792/* MP3 Plus Control 1 (0xd0) */
1793#define RT5640_M_MP3_L_MASK (0x1 << 15)
1794#define RT5640_M_MP3_L_SFT 15
1795#define RT5640_M_MP3_R_MASK (0x1 << 14)
1796#define RT5640_M_MP3_R_SFT 14
1797#define RT5640_M_MP3_MASK (0x1 << 13)
1798#define RT5640_M_MP3_SFT 13
1799#define RT5640_M_MP3_DIS (0x0 << 13)
1800#define RT5640_M_MP3_EN (0x1 << 13)
1801#define RT5640_EG_MP3_MASK (0x1f << 8)
1802#define RT5640_EG_MP3_SFT 8
1803#define RT5640_MP3_HLP_MASK (0x1 << 7)
1804#define RT5640_MP3_HLP_SFT 7
1805#define RT5640_MP3_HLP_DIS (0x0 << 7)
1806#define RT5640_MP3_HLP_EN (0x1 << 7)
1807#define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
1808#define RT5640_M_MP3_ORG_L_SFT 6
1809#define RT5640_M_MP3_ORG_R_MASK (0x1 << 5)
1810#define RT5640_M_MP3_ORG_R_SFT 5
1811
1812/* MP3 Plus Control 2 (0xd1) */
1813#define RT5640_MP3_WT_MASK (0x1 << 13)
1814#define RT5640_MP3_WT_SFT 13
1815#define RT5640_MP3_WT_1_4 (0x0 << 13)
1816#define RT5640_MP3_WT_1_2 (0x1 << 13)
1817#define RT5640_OG_MP3_MASK (0x1f << 8)
1818#define RT5640_OG_MP3_SFT 8
1819#define RT5640_HG_MP3_MASK (0x3f)
1820#define RT5640_HG_MP3_SFT 0
1821
1822/* 3D HP Control 1 (0xd2) */
1823#define RT5640_3D_CF_MASK (0x1 << 15)
1824#define RT5640_3D_CF_SFT 15
1825#define RT5640_3D_CF_DIS (0x0 << 15)
1826#define RT5640_3D_CF_EN (0x1 << 15)
1827#define RT5640_3D_HP_MASK (0x1 << 14)
1828#define RT5640_3D_HP_SFT 14
1829#define RT5640_3D_HP_DIS (0x0 << 14)
1830#define RT5640_3D_HP_EN (0x1 << 14)
1831#define RT5640_3D_BT_MASK (0x1 << 13)
1832#define RT5640_3D_BT_SFT 13
1833#define RT5640_3D_BT_DIS (0x0 << 13)
1834#define RT5640_3D_BT_EN (0x1 << 13)
1835#define RT5640_3D_1F_MIX_MASK (0x3 << 11)
1836#define RT5640_3D_1F_MIX_SFT 11
1837#define RT5640_3D_HP_M_MASK (0x1 << 10)
1838#define RT5640_3D_HP_M_SFT 10
1839#define RT5640_3D_HP_M_SUR (0x0 << 10)
1840#define RT5640_3D_HP_M_FRO (0x1 << 10)
1841#define RT5640_M_3D_HRTF_MASK (0x1 << 9)
1842#define RT5640_M_3D_HRTF_SFT 9
1843#define RT5640_M_3D_D2H_MASK (0x1 << 8)
1844#define RT5640_M_3D_D2H_SFT 8
1845#define RT5640_M_3D_D2R_MASK (0x1 << 7)
1846#define RT5640_M_3D_D2R_SFT 7
1847#define RT5640_M_3D_REVB_MASK (0x1 << 6)
1848#define RT5640_M_3D_REVB_SFT 6
1849
1850/* Adjustable high pass filter control 1 (0xd3) */
1851#define RT5640_2ND_HPF_MASK (0x1 << 15)
1852#define RT5640_2ND_HPF_SFT 15
1853#define RT5640_2ND_HPF_DIS (0x0 << 15)
1854#define RT5640_2ND_HPF_EN (0x1 << 15)
1855#define RT5640_HPF_CF_L_MASK (0x7 << 12)
1856#define RT5640_HPF_CF_L_SFT 12
1857#define RT5640_1ST_HPF_MASK (0x1 << 11)
1858#define RT5640_1ST_HPF_SFT 11
1859#define RT5640_1ST_HPF_DIS (0x0 << 11)
1860#define RT5640_1ST_HPF_EN (0x1 << 11)
1861#define RT5640_HPF_CF_R_MASK (0x7 << 8)
1862#define RT5640_HPF_CF_R_SFT 8
1863#define RT5640_ZD_T_MASK (0x3 << 6)
1864#define RT5640_ZD_T_SFT 6
1865#define RT5640_ZD_F_MASK (0x3 << 4)
1866#define RT5640_ZD_F_SFT 4
1867#define RT5640_ZD_F_IM (0x0 << 4)
1868#define RT5640_ZD_F_ZC_IM (0x1 << 4)
1869#define RT5640_ZD_F_ZC_IOD (0x2 << 4)
1870#define RT5640_ZD_F_UN (0x3 << 4)
1871
1872/* HP calibration control and Amp detection (0xd6) */
1873#define RT5640_SI_DAC_MASK (0x1 << 11)
1874#define RT5640_SI_DAC_SFT 11
1875#define RT5640_SI_DAC_AUTO (0x0 << 11)
1876#define RT5640_SI_DAC_TEST (0x1 << 11)
1877#define RT5640_DC_CAL_M_MASK (0x1 << 10)
1878#define RT5640_DC_CAL_M_SFT 10
1879#define RT5640_DC_CAL_M_CAL (0x0 << 10)
1880#define RT5640_DC_CAL_M_NOR (0x1 << 10)
1881#define RT5640_DC_CAL_MASK (0x1 << 9)
1882#define RT5640_DC_CAL_SFT 9
1883#define RT5640_DC_CAL_DIS (0x0 << 9)
1884#define RT5640_DC_CAL_EN (0x1 << 9)
1885#define RT5640_HPD_RCV_MASK (0x7 << 6)
1886#define RT5640_HPD_RCV_SFT 6
1887#define RT5640_HPD_PS_MASK (0x1 << 5)
1888#define RT5640_HPD_PS_SFT 5
1889#define RT5640_HPD_PS_DIS (0x0 << 5)
1890#define RT5640_HPD_PS_EN (0x1 << 5)
1891#define RT5640_CAL_M_MASK (0x1 << 4)
1892#define RT5640_CAL_M_SFT 4
1893#define RT5640_CAL_M_DEP (0x0 << 4)
1894#define RT5640_CAL_M_CAL (0x1 << 4)
1895#define RT5640_CAL_MASK (0x1 << 3)
1896#define RT5640_CAL_SFT 3
1897#define RT5640_CAL_DIS (0x0 << 3)
1898#define RT5640_CAL_EN (0x1 << 3)
1899#define RT5640_CAL_TEST_MASK (0x1 << 2)
1900#define RT5640_CAL_TEST_SFT 2
1901#define RT5640_CAL_TEST_DIS (0x0 << 2)
1902#define RT5640_CAL_TEST_EN (0x1 << 2)
1903#define RT5640_CAL_P_MASK (0x3)
1904#define RT5640_CAL_P_SFT 0
1905#define RT5640_CAL_P_NONE (0x0)
1906#define RT5640_CAL_P_CAL (0x1)
1907#define RT5640_CAL_P_DAC_CAL (0x2)
1908
1909/* Soft volume and zero cross control 1 (0xd9) */
1910#define RT5640_SV_MASK (0x1 << 15)
1911#define RT5640_SV_SFT 15
1912#define RT5640_SV_DIS (0x0 << 15)
1913#define RT5640_SV_EN (0x1 << 15)
1914#define RT5640_SPO_SV_MASK (0x1 << 14)
1915#define RT5640_SPO_SV_SFT 14
1916#define RT5640_SPO_SV_DIS (0x0 << 14)
1917#define RT5640_SPO_SV_EN (0x1 << 14)
1918#define RT5640_OUT_SV_MASK (0x1 << 13)
1919#define RT5640_OUT_SV_SFT 13
1920#define RT5640_OUT_SV_DIS (0x0 << 13)
1921#define RT5640_OUT_SV_EN (0x1 << 13)
1922#define RT5640_HP_SV_MASK (0x1 << 12)
1923#define RT5640_HP_SV_SFT 12
1924#define RT5640_HP_SV_DIS (0x0 << 12)
1925#define RT5640_HP_SV_EN (0x1 << 12)
1926#define RT5640_ZCD_DIG_MASK (0x1 << 11)
1927#define RT5640_ZCD_DIG_SFT 11
1928#define RT5640_ZCD_DIG_DIS (0x0 << 11)
1929#define RT5640_ZCD_DIG_EN (0x1 << 11)
1930#define RT5640_ZCD_MASK (0x1 << 10)
1931#define RT5640_ZCD_SFT 10
1932#define RT5640_ZCD_PD (0x0 << 10)
1933#define RT5640_ZCD_PU (0x1 << 10)
1934#define RT5640_M_ZCD_MASK (0x3f << 4)
1935#define RT5640_M_ZCD_SFT 4
1936#define RT5640_M_ZCD_RM_L (0x1 << 9)
1937#define RT5640_M_ZCD_RM_R (0x1 << 8)
1938#define RT5640_M_ZCD_SM_L (0x1 << 7)
1939#define RT5640_M_ZCD_SM_R (0x1 << 6)
1940#define RT5640_M_ZCD_OM_L (0x1 << 5)
1941#define RT5640_M_ZCD_OM_R (0x1 << 4)
1942#define RT5640_SV_DLY_MASK (0xf)
1943#define RT5640_SV_DLY_SFT 0
1944
1945/* Soft volume and zero cross control 2 (0xda) */
1946#define RT5640_ZCD_HP_MASK (0x1 << 15)
1947#define RT5640_ZCD_HP_SFT 15
1948#define RT5640_ZCD_HP_DIS (0x0 << 15)
1949#define RT5640_ZCD_HP_EN (0x1 << 15)
1950
1951
1952/* Codec Private Register definition */
1953/* 3D Speaker Control (0x63) */
1954#define RT5640_3D_SPK_MASK (0x1 << 15)
1955#define RT5640_3D_SPK_SFT 15
1956#define RT5640_3D_SPK_DIS (0x0 << 15)
1957#define RT5640_3D_SPK_EN (0x1 << 15)
1958#define RT5640_3D_SPK_M_MASK (0x3 << 13)
1959#define RT5640_3D_SPK_M_SFT 13
1960#define RT5640_3D_SPK_CG_MASK (0x1f << 8)
1961#define RT5640_3D_SPK_CG_SFT 8
1962#define RT5640_3D_SPK_SG_MASK (0x1f)
1963#define RT5640_3D_SPK_SG_SFT 0
1964
1965/* Wind Noise Detection Control 1 (0x6c) */
1966#define RT5640_WND_MASK (0x1 << 15)
1967#define RT5640_WND_SFT 15
1968#define RT5640_WND_DIS (0x0 << 15)
1969#define RT5640_WND_EN (0x1 << 15)
1970
1971/* Wind Noise Detection Control 2 (0x6d) */
1972#define RT5640_WND_FC_NW_MASK (0x3f << 10)
1973#define RT5640_WND_FC_NW_SFT 10
1974#define RT5640_WND_FC_WK_MASK (0x3f << 4)
1975#define RT5640_WND_FC_WK_SFT 4
1976
1977/* Wind Noise Detection Control 3 (0x6e) */
1978#define RT5640_HPF_FC_MASK (0x3f << 6)
1979#define RT5640_HPF_FC_SFT 6
1980#define RT5640_WND_FC_ST_MASK (0x3f)
1981#define RT5640_WND_FC_ST_SFT 0
1982
1983/* Wind Noise Detection Control 4 (0x6f) */
1984#define RT5640_WND_TH_LO_MASK (0x3ff)
1985#define RT5640_WND_TH_LO_SFT 0
1986
1987/* Wind Noise Detection Control 5 (0x70) */
1988#define RT5640_WND_TH_HI_MASK (0x3ff)
1989#define RT5640_WND_TH_HI_SFT 0
1990
1991/* Wind Noise Detection Control 8 (0x73) */
1992#define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1993#define RT5640_WND_WIND_SFT 13
1994#define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1995#define RT5640_WND_STRONG_SFT 12
1996enum {
1997 RT5640_NO_WIND,
1998 RT5640_BREEZE,
1999 RT5640_STORM,
2000};
2001
2002/* Dipole Speaker Interface (0x75) */
2003#define RT5640_DP_ATT_MASK (0x3 << 14)
2004#define RT5640_DP_ATT_SFT 14
2005#define RT5640_DP_SPK_MASK (0x1 << 10)
2006#define RT5640_DP_SPK_SFT 10
2007#define RT5640_DP_SPK_DIS (0x0 << 10)
2008#define RT5640_DP_SPK_EN (0x1 << 10)
2009
2010/* EQ Pre Volume Control (0xb3) */
2011#define RT5640_EQ_PRE_VOL_MASK (0xffff)
2012#define RT5640_EQ_PRE_VOL_SFT 0
2013
2014/* EQ Post Volume Control (0xb4) */
2015#define RT5640_EQ_PST_VOL_MASK (0xffff)
2016#define RT5640_EQ_PST_VOL_SFT 0
2017
2018#define RT5640_NO_JACK BIT(0)
2019#define RT5640_HEADSET_DET BIT(1)
2020#define RT5640_HEADPHO_DET BIT(2)
2021
2022/* System Clock Source */
2023#define RT5640_SCLK_S_MCLK 0
2024#define RT5640_SCLK_S_PLL1 1
2025#define RT5640_SCLK_S_PLL1_TK 2
2026#define RT5640_SCLK_S_RCCLK 3
2027
2028/* PLL1 Source */
2029#define RT5640_PLL1_S_MCLK 0
2030#define RT5640_PLL1_S_BCLK1 1
2031#define RT5640_PLL1_S_BCLK2 2
2032#define RT5640_PLL1_S_BCLK3 3
2033
2034
2035enum {
2036 RT5640_AIF1,
2037 RT5640_AIF2,
2038 RT5640_AIF3,
2039 RT5640_AIFS,
2040};
2041
2042enum {
2043 RT5640_U_IF1 = 0x1,
2044 RT5640_U_IF2 = 0x2,
2045 RT5640_U_IF3 = 0x4,
2046};
2047
2048enum {
2049 RT5640_IF_123,
2050 RT5640_IF_132,
2051 RT5640_IF_312,
2052 RT5640_IF_321,
2053 RT5640_IF_231,
2054 RT5640_IF_213,
2055 RT5640_IF_113,
2056 RT5640_IF_223,
2057 RT5640_IF_ALL,
2058};
2059
2060enum {
2061 RT5640_DMIC_DIS,
2062 RT5640_DMIC1,
2063 RT5640_DMIC2,
2064};
2065
2066struct rt5640_pll_code {
2067 bool m_bp; /* Indicates bypass m code or not. */
2068 int m_code;
2069 int n_code;
2070 int k_code;
2071};
2072
2073struct rt5640_priv {
2074 struct snd_soc_codec *codec;
2075 struct rt5640_platform_data pdata;
2076 struct regmap *regmap;
2077
2078 int sysclk;
2079 int sysclk_src;
2080 int lrck[RT5640_AIFS];
2081 int bclk[RT5640_AIFS];
2082 int master[RT5640_AIFS];
2083
2084 struct rt5640_pll_code pll_code;
2085 int pll_src;
2086 int pll_in;
2087 int pll_out;
2088
2089 int dmic_en;
2090};
2091
2092#endif
diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index b1c9d573da05..995b120c2cd0 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -59,6 +59,16 @@ config SND_SOC_TEGRA30_I2S
59 Tegra30 I2S interface. You will also need to select the individual 59 Tegra30 I2S interface. You will also need to select the individual
60 machine drivers to support below. 60 machine drivers to support below.
61 61
62config SND_SOC_TEGRA_RT5640
63 tristate "SoC Audio support for Tegra boards using an RT5640 codec"
64 depends on SND_SOC_TEGRA && I2C
65 select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC
66 select SND_SOC_TEGRA30_I2S if ARCH_TEGRA_3x_SOC
67 select SND_SOC_RT5640
68 help
69 Say Y or M here if you want to add support for SoC audio on Tegra
70 boards using the RT5640 codec, such as Dalmore.
71
62config SND_SOC_TEGRA_WM8753 72config SND_SOC_TEGRA_WM8753
63 tristate "SoC Audio support for Tegra boards using a WM8753 codec" 73 tristate "SoC Audio support for Tegra boards using a WM8753 codec"
64 depends on SND_SOC_TEGRA && I2C 74 depends on SND_SOC_TEGRA && I2C
diff --git a/sound/soc/tegra/Makefile b/sound/soc/tegra/Makefile
index 416a14bde41b..21d2550a08a4 100644
--- a/sound/soc/tegra/Makefile
+++ b/sound/soc/tegra/Makefile
@@ -18,12 +18,14 @@ obj-$(CONFIG_SND_SOC_TEGRA30_AHUB) += snd-soc-tegra30-ahub.o
18obj-$(CONFIG_SND_SOC_TEGRA30_I2S) += snd-soc-tegra30-i2s.o 18obj-$(CONFIG_SND_SOC_TEGRA30_I2S) += snd-soc-tegra30-i2s.o
19 19
20# Tegra machine Support 20# Tegra machine Support
21snd-soc-tegra-rt5640-objs := tegra_rt5640.o
21snd-soc-tegra-wm8753-objs := tegra_wm8753.o 22snd-soc-tegra-wm8753-objs := tegra_wm8753.o
22snd-soc-tegra-wm8903-objs := tegra_wm8903.o 23snd-soc-tegra-wm8903-objs := tegra_wm8903.o
23snd-soc-tegra-wm9712-objs := tegra_wm9712.o 24snd-soc-tegra-wm9712-objs := tegra_wm9712.o
24snd-soc-tegra-trimslice-objs := trimslice.o 25snd-soc-tegra-trimslice-objs := trimslice.o
25snd-soc-tegra-alc5632-objs := tegra_alc5632.o 26snd-soc-tegra-alc5632-objs := tegra_alc5632.o
26 27
28obj-$(CONFIG_SND_SOC_TEGRA_RT5640) += snd-soc-tegra-rt5640.o
27obj-$(CONFIG_SND_SOC_TEGRA_WM8753) += snd-soc-tegra-wm8753.o 29obj-$(CONFIG_SND_SOC_TEGRA_WM8753) += snd-soc-tegra-wm8753.o
28obj-$(CONFIG_SND_SOC_TEGRA_WM8903) += snd-soc-tegra-wm8903.o 30obj-$(CONFIG_SND_SOC_TEGRA_WM8903) += snd-soc-tegra-wm8903.o
29obj-$(CONFIG_SND_SOC_TEGRA_WM9712) += snd-soc-tegra-wm9712.o 31obj-$(CONFIG_SND_SOC_TEGRA_WM9712) += snd-soc-tegra-wm9712.o
diff --git a/sound/soc/tegra/tegra_rt5640.c b/sound/soc/tegra/tegra_rt5640.c
new file mode 100644
index 000000000000..08794f915a94
--- /dev/null
+++ b/sound/soc/tegra/tegra_rt5640.c
@@ -0,0 +1,257 @@
1/*
2* tegra_rt5640.c - Tegra machine ASoC driver for boards using WM8903 codec.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Based on code copyright/by:
19 *
20 * Copyright (C) 2010-2012 - NVIDIA, Inc.
21 * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net>
22 * (c) 2009, 2010 Nvidia Graphics Pvt. Ltd.
23 * Copyright 2007 Wolfson Microelectronics PLC.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <linux/gpio.h>
30#include <linux/of_gpio.h>
31
32#include <sound/core.h>
33#include <sound/jack.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/soc.h>
37
38#include "../codecs/rt5640.h"
39
40#include "tegra_asoc_utils.h"
41
42#define DRV_NAME "tegra-snd-rt5640"
43
44struct tegra_rt5640 {
45 struct tegra_asoc_utils_data util_data;
46 int gpio_hp_det;
47};
48
49static int tegra_rt5640_asoc_hw_params(struct snd_pcm_substream *substream,
50 struct snd_pcm_hw_params *params)
51{
52 struct snd_soc_pcm_runtime *rtd = substream->private_data;
53 struct snd_soc_dai *codec_dai = rtd->codec_dai;
54 struct snd_soc_codec *codec = codec_dai->codec;
55 struct snd_soc_card *card = codec->card;
56 struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
57 int srate, mclk;
58 int err;
59
60 srate = params_rate(params);
61 mclk = 256 * srate;
62
63 err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
64 if (err < 0) {
65 dev_err(card->dev, "Can't configure clocks\n");
66 return err;
67 }
68
69 err = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_MCLK, mclk,
70 SND_SOC_CLOCK_IN);
71 if (err < 0) {
72 dev_err(card->dev, "codec_dai clock not set\n");
73 return err;
74 }
75
76 return 0;
77}
78
79static struct snd_soc_ops tegra_rt5640_ops = {
80 .hw_params = tegra_rt5640_asoc_hw_params,
81};
82
83static struct snd_soc_jack tegra_rt5640_hp_jack;
84
85static struct snd_soc_jack_pin tegra_rt5640_hp_jack_pins[] = {
86 {
87 .pin = "Headphones",
88 .mask = SND_JACK_HEADPHONE,
89 },
90};
91
92static struct snd_soc_jack_gpio tegra_rt5640_hp_jack_gpio = {
93 .name = "Headphone detection",
94 .report = SND_JACK_HEADPHONE,
95 .debounce_time = 150,
96 .invert = 1,
97};
98
99static const struct snd_soc_dapm_widget tegra_rt5640_dapm_widgets[] = {
100 SND_SOC_DAPM_HP("Headphones", NULL),
101 SND_SOC_DAPM_SPK("Speakers", NULL),
102};
103
104static const struct snd_kcontrol_new tegra_rt5640_controls[] = {
105 SOC_DAPM_PIN_SWITCH("Speakers"),
106};
107
108static int tegra_rt5640_asoc_init(struct snd_soc_pcm_runtime *rtd)
109{
110 struct snd_soc_dai *codec_dai = rtd->codec_dai;
111 struct snd_soc_codec *codec = codec_dai->codec;
112 struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(codec->card);
113
114 snd_soc_jack_new(codec, "Headphones", SND_JACK_HEADPHONE,
115 &tegra_rt5640_hp_jack);
116 snd_soc_jack_add_pins(&tegra_rt5640_hp_jack,
117 ARRAY_SIZE(tegra_rt5640_hp_jack_pins),
118 tegra_rt5640_hp_jack_pins);
119
120 if (gpio_is_valid(machine->gpio_hp_det)) {
121 tegra_rt5640_hp_jack_gpio.gpio = machine->gpio_hp_det;
122 snd_soc_jack_add_gpios(&tegra_rt5640_hp_jack,
123 1,
124 &tegra_rt5640_hp_jack_gpio);
125 }
126
127 return 0;
128}
129
130static struct snd_soc_dai_link tegra_rt5640_dai = {
131 .name = "RT5640",
132 .stream_name = "RT5640 PCM",
133 .codec_dai_name = "rt5640-aif1",
134 .init = tegra_rt5640_asoc_init,
135 .ops = &tegra_rt5640_ops,
136 .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
137 SND_SOC_DAIFMT_CBS_CFS,
138};
139
140static struct snd_soc_card snd_soc_tegra_rt5640 = {
141 .name = "tegra-rt5640",
142 .owner = THIS_MODULE,
143 .dai_link = &tegra_rt5640_dai,
144 .num_links = 1,
145 .controls = tegra_rt5640_controls,
146 .num_controls = ARRAY_SIZE(tegra_rt5640_controls),
147 .dapm_widgets = tegra_rt5640_dapm_widgets,
148 .num_dapm_widgets = ARRAY_SIZE(tegra_rt5640_dapm_widgets),
149 .fully_routed = true,
150};
151
152static int tegra_rt5640_probe(struct platform_device *pdev)
153{
154 struct device_node *np = pdev->dev.of_node;
155 struct snd_soc_card *card = &snd_soc_tegra_rt5640;
156 struct tegra_rt5640 *machine;
157 int ret;
158
159 machine = devm_kzalloc(&pdev->dev,
160 sizeof(struct tegra_rt5640), GFP_KERNEL);
161 if (!machine) {
162 dev_err(&pdev->dev, "Can't allocate tegra_rt5640\n");
163 return -ENOMEM;
164 }
165
166 card->dev = &pdev->dev;
167 platform_set_drvdata(pdev, card);
168 snd_soc_card_set_drvdata(card, machine);
169
170 machine->gpio_hp_det = of_get_named_gpio(np, "nvidia,hp-det-gpios", 0);
171 if (machine->gpio_hp_det == -EPROBE_DEFER)
172 return -EPROBE_DEFER;
173
174 ret = snd_soc_of_parse_card_name(card, "nvidia,model");
175 if (ret)
176 goto err;
177
178 ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
179 if (ret)
180 goto err;
181
182 tegra_rt5640_dai.codec_of_node = of_parse_phandle(np,
183 "nvidia,audio-codec", 0);
184 if (!tegra_rt5640_dai.codec_of_node) {
185 dev_err(&pdev->dev,
186 "Property 'nvidia,audio-codec' missing or invalid\n");
187 ret = -EINVAL;
188 goto err;
189 }
190
191 tegra_rt5640_dai.cpu_of_node = of_parse_phandle(np,
192 "nvidia,i2s-controller", 0);
193 if (!tegra_rt5640_dai.cpu_of_node) {
194 dev_err(&pdev->dev,
195 "Property 'nvidia,i2s-controller' missing or invalid\n");
196 ret = -EINVAL;
197 goto err;
198 }
199
200 tegra_rt5640_dai.platform_of_node = tegra_rt5640_dai.cpu_of_node;
201
202 ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
203 if (ret)
204 goto err;
205
206 ret = snd_soc_register_card(card);
207 if (ret) {
208 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
209 ret);
210 goto err_fini_utils;
211 }
212
213 return 0;
214
215err_fini_utils:
216 tegra_asoc_utils_fini(&machine->util_data);
217err:
218 return ret;
219}
220
221static int tegra_rt5640_remove(struct platform_device *pdev)
222{
223 struct snd_soc_card *card = platform_get_drvdata(pdev);
224 struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
225
226 snd_soc_jack_free_gpios(&tegra_rt5640_hp_jack, 1,
227 &tegra_rt5640_hp_jack_gpio);
228
229 snd_soc_unregister_card(card);
230
231 tegra_asoc_utils_fini(&machine->util_data);
232
233 return 0;
234}
235
236static const struct of_device_id tegra_rt5640_of_match[] = {
237 { .compatible = "nvidia,tegra-audio-rt5640", },
238 {},
239};
240
241static struct platform_driver tegra_rt5640_driver = {
242 .driver = {
243 .name = DRV_NAME,
244 .owner = THIS_MODULE,
245 .pm = &snd_soc_pm_ops,
246 .of_match_table = tegra_rt5640_of_match,
247 },
248 .probe = tegra_rt5640_probe,
249 .remove = tegra_rt5640_remove,
250};
251module_platform_driver(tegra_rt5640_driver);
252
253MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
254MODULE_DESCRIPTION("Tegra+RT5640 machine ASoC driver");
255MODULE_LICENSE("GPL v2");
256MODULE_ALIAS("platform:" DRV_NAME);
257MODULE_DEVICE_TABLE(of, tegra_rt5640_of_match);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-17 14:49:38 -0400