diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2015-02-12 01:01:25 -0500 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2015-03-02 07:51:55 -0500 |
| commit | 5f80e19081e233698c8ea77ed2dd84a66f49fc54 (patch) | |
| tree | 1cd084e17602544692ad03e8116d0eacdfd4f4f0 | |
| parent | af321d2e32b3167129b35856316d4c55126556cf (diff) | |
ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
This patch adds a macro to define the GPR3 MIPI muxing control register field
shift bits.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c877cad61a13..d16f4c82c568 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |||
| @@ -207,6 +207,7 @@ | |||
| 207 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) | 207 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) |
| 208 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) | 208 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) |
| 209 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) | 209 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) |
| 210 | #define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 | ||
| 210 | #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) | 211 | #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) |
| 211 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) | 212 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) |
| 212 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) | 213 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) |