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authorStephen Boyd <sboyd@codeaurora.org>2014-07-10 04:18:29 -0400
committerStephen Boyd <sboyd@codeaurora.org>2014-07-11 16:21:22 -0400
commit5f775498bdc44f294c37eaa7a205335e3b6667df (patch)
treec6f015755676ae4d12731a587aef7b654dbcec0f
parent7f9b72ae972fd6395debeb2f859b7cadf2c2466e (diff)
clk: qcom: Fully support apq8064 global clock control
Add in the handful of new clocks and introduce a new reset table with the few new resets. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c573
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8960.h11
-rw-r--r--include/dt-bindings/reset/qcom,gcc-msm8960.h16
3 files changed, 596 insertions, 4 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 4cb2927889ce..007534f7a2d7 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -104,6 +104,7 @@ static struct clk_regmap pll14_vote = {
104 104
105#define P_PXO 0 105#define P_PXO 0
106#define P_PLL8 1 106#define P_PLL8 1
107#define P_PLL3 2
107#define P_CXO 2 108#define P_CXO 2
108 109
109static const u8 gcc_pxo_pll8_map[] = { 110static const u8 gcc_pxo_pll8_map[] = {
@@ -128,6 +129,18 @@ static const char *gcc_pxo_pll8_cxo[] = {
128 "cxo", 129 "cxo",
129}; 130};
130 131
132static const u8 gcc_pxo_pll8_pll3_map[] = {
133 [P_PXO] = 0,
134 [P_PLL8] = 3,
135 [P_PLL3] = 6,
136};
137
138static const char *gcc_pxo_pll8_pll3[] = {
139 "pxo",
140 "pll8_vote",
141 "pll3",
142};
143
131static struct freq_tbl clk_tbl_gsbi_uart[] = { 144static struct freq_tbl clk_tbl_gsbi_uart[] = {
132 { 1843200, P_PLL8, 2, 6, 625 }, 145 { 1843200, P_PLL8, 2, 6, 625 },
133 { 3686400, P_PLL8, 2, 12, 625 }, 146 { 3686400, P_PLL8, 2, 12, 625 },
@@ -1928,6 +1941,104 @@ static struct clk_branch usb_hs1_xcvr_clk = {
1928 }, 1941 },
1929}; 1942};
1930 1943
1944static struct clk_rcg usb_hs3_xcvr_src = {
1945 .ns_reg = 0x370c,
1946 .md_reg = 0x3708,
1947 .mn = {
1948 .mnctr_en_bit = 8,
1949 .mnctr_reset_bit = 7,
1950 .mnctr_mode_shift = 5,
1951 .n_val_shift = 16,
1952 .m_val_shift = 16,
1953 .width = 8,
1954 },
1955 .p = {
1956 .pre_div_shift = 3,
1957 .pre_div_width = 2,
1958 },
1959 .s = {
1960 .src_sel_shift = 0,
1961 .parent_map = gcc_pxo_pll8_map,
1962 },
1963 .freq_tbl = clk_tbl_usb,
1964 .clkr = {
1965 .enable_reg = 0x370c,
1966 .enable_mask = BIT(11),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "usb_hs3_xcvr_src",
1969 .parent_names = gcc_pxo_pll8,
1970 .num_parents = 2,
1971 .ops = &clk_rcg_ops,
1972 .flags = CLK_SET_RATE_GATE,
1973 },
1974 }
1975};
1976
1977static struct clk_branch usb_hs3_xcvr_clk = {
1978 .halt_reg = 0x2fc8,
1979 .halt_bit = 30,
1980 .clkr = {
1981 .enable_reg = 0x370c,
1982 .enable_mask = BIT(9),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "usb_hs3_xcvr_clk",
1985 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1986 .num_parents = 1,
1987 .ops = &clk_branch_ops,
1988 .flags = CLK_SET_RATE_PARENT,
1989 },
1990 },
1991};
1992
1993static struct clk_rcg usb_hs4_xcvr_src = {
1994 .ns_reg = 0x372c,
1995 .md_reg = 0x3728,
1996 .mn = {
1997 .mnctr_en_bit = 8,
1998 .mnctr_reset_bit = 7,
1999 .mnctr_mode_shift = 5,
2000 .n_val_shift = 16,
2001 .m_val_shift = 16,
2002 .width = 8,
2003 },
2004 .p = {
2005 .pre_div_shift = 3,
2006 .pre_div_width = 2,
2007 },
2008 .s = {
2009 .src_sel_shift = 0,
2010 .parent_map = gcc_pxo_pll8_map,
2011 },
2012 .freq_tbl = clk_tbl_usb,
2013 .clkr = {
2014 .enable_reg = 0x372c,
2015 .enable_mask = BIT(11),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "usb_hs4_xcvr_src",
2018 .parent_names = gcc_pxo_pll8,
2019 .num_parents = 2,
2020 .ops = &clk_rcg_ops,
2021 .flags = CLK_SET_RATE_GATE,
2022 },
2023 }
2024};
2025
2026static struct clk_branch usb_hs4_xcvr_clk = {
2027 .halt_reg = 0x2fc8,
2028 .halt_bit = 2,
2029 .clkr = {
2030 .enable_reg = 0x372c,
2031 .enable_mask = BIT(9),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "usb_hs4_xcvr_clk",
2034 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2035 .num_parents = 1,
2036 .ops = &clk_branch_ops,
2037 .flags = CLK_SET_RATE_PARENT,
2038 },
2039 },
2040};
2041
1931static struct clk_rcg usb_hsic_xcvr_fs_src = { 2042static struct clk_rcg usb_hsic_xcvr_fs_src = {
1932 .ns_reg = 0x2928, 2043 .ns_reg = 0x2928,
1933 .md_reg = 0x2924, 2044 .md_reg = 0x2924,
@@ -2456,6 +2567,34 @@ static struct clk_branch usb_hs1_h_clk = {
2456 }, 2567 },
2457}; 2568};
2458 2569
2570static struct clk_branch usb_hs3_h_clk = {
2571 .halt_reg = 0x2fc8,
2572 .halt_bit = 31,
2573 .clkr = {
2574 .enable_reg = 0x3700,
2575 .enable_mask = BIT(4),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "usb_hs3_h_clk",
2578 .ops = &clk_branch_ops,
2579 .flags = CLK_IS_ROOT,
2580 },
2581 },
2582};
2583
2584static struct clk_branch usb_hs4_h_clk = {
2585 .halt_reg = 0x2fc8,
2586 .halt_bit = 7,
2587 .clkr = {
2588 .enable_reg = 0x3720,
2589 .enable_mask = BIT(4),
2590 .hw.init = &(struct clk_init_data){
2591 .name = "usb_hs4_h_clk",
2592 .ops = &clk_branch_ops,
2593 .flags = CLK_IS_ROOT,
2594 },
2595 },
2596};
2597
2459static struct clk_branch usb_hsic_h_clk = { 2598static struct clk_branch usb_hsic_h_clk = {
2460 .halt_reg = 0x2fcc, 2599 .halt_reg = 0x2fcc,
2461 .halt_bit = 28, 2600 .halt_bit = 28,
@@ -2582,6 +2721,244 @@ static struct clk_branch adm0_pbus_clk = {
2582 }, 2721 },
2583}; 2722};
2584 2723
2724static struct freq_tbl clk_tbl_ce3[] = {
2725 { 48000000, P_PLL8, 8 },
2726 { 100000000, P_PLL3, 12 },
2727 { 120000000, P_PLL3, 10 },
2728 { }
2729};
2730
2731static struct clk_rcg ce3_src = {
2732 .ns_reg = 0x36c0,
2733 .p = {
2734 .pre_div_shift = 3,
2735 .pre_div_width = 4,
2736 },
2737 .s = {
2738 .src_sel_shift = 0,
2739 .parent_map = gcc_pxo_pll8_pll3_map,
2740 },
2741 .freq_tbl = clk_tbl_ce3,
2742 .clkr = {
2743 .enable_reg = 0x2c08,
2744 .enable_mask = BIT(7),
2745 .hw.init = &(struct clk_init_data){
2746 .name = "ce3_src",
2747 .parent_names = gcc_pxo_pll8_pll3,
2748 .num_parents = 3,
2749 .ops = &clk_rcg_ops,
2750 .flags = CLK_SET_RATE_GATE,
2751 },
2752 },
2753};
2754
2755static struct clk_branch ce3_core_clk = {
2756 .halt_reg = 0x2fdc,
2757 .halt_bit = 5,
2758 .clkr = {
2759 .enable_reg = 0x36c4,
2760 .enable_mask = BIT(4),
2761 .hw.init = &(struct clk_init_data){
2762 .name = "ce3_core_clk",
2763 .parent_names = (const char *[]){ "ce3_src" },
2764 .num_parents = 1,
2765 .ops = &clk_branch_ops,
2766 .flags = CLK_SET_RATE_PARENT,
2767 },
2768 },
2769};
2770
2771static struct clk_branch ce3_h_clk = {
2772 .halt_reg = 0x2fc4,
2773 .halt_bit = 16,
2774 .clkr = {
2775 .enable_reg = 0x36c4,
2776 .enable_mask = BIT(4),
2777 .hw.init = &(struct clk_init_data){
2778 .name = "ce3_h_clk",
2779 .parent_names = (const char *[]){ "ce3_src" },
2780 .num_parents = 1,
2781 .ops = &clk_branch_ops,
2782 .flags = CLK_SET_RATE_PARENT,
2783 },
2784 },
2785};
2786
2787static const struct freq_tbl clk_tbl_sata_ref[] = {
2788 { 48000000, P_PLL8, 8, 0, 0 },
2789 { 100000000, P_PLL3, 12, 0, 0 },
2790 { }
2791};
2792
2793static struct clk_rcg sata_clk_src = {
2794 .ns_reg = 0x2c08,
2795 .p = {
2796 .pre_div_shift = 3,
2797 .pre_div_width = 4,
2798 },
2799 .s = {
2800 .src_sel_shift = 0,
2801 .parent_map = gcc_pxo_pll8_pll3_map,
2802 },
2803 .freq_tbl = clk_tbl_sata_ref,
2804 .clkr = {
2805 .enable_reg = 0x2c08,
2806 .enable_mask = BIT(7),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "sata_clk_src",
2809 .parent_names = gcc_pxo_pll8_pll3,
2810 .num_parents = 3,
2811 .ops = &clk_rcg_ops,
2812 .flags = CLK_SET_RATE_GATE,
2813 },
2814 },
2815};
2816
2817static struct clk_branch sata_rxoob_clk = {
2818 .halt_reg = 0x2fdc,
2819 .halt_bit = 26,
2820 .clkr = {
2821 .enable_reg = 0x2c0c,
2822 .enable_mask = BIT(4),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "sata_rxoob_clk",
2825 .parent_names = (const char *[]){ "sata_clk_src" },
2826 .num_parents = 1,
2827 .ops = &clk_branch_ops,
2828 .flags = CLK_SET_RATE_PARENT,
2829 },
2830 },
2831};
2832
2833static struct clk_branch sata_pmalive_clk = {
2834 .halt_reg = 0x2fdc,
2835 .halt_bit = 25,
2836 .clkr = {
2837 .enable_reg = 0x2c10,
2838 .enable_mask = BIT(4),
2839 .hw.init = &(struct clk_init_data){
2840 .name = "sata_pmalive_clk",
2841 .parent_names = (const char *[]){ "sata_clk_src" },
2842 .num_parents = 1,
2843 .ops = &clk_branch_ops,
2844 .flags = CLK_SET_RATE_PARENT,
2845 },
2846 },
2847};
2848
2849static struct clk_branch sata_phy_ref_clk = {
2850 .halt_reg = 0x2fdc,
2851 .halt_bit = 24,
2852 .clkr = {
2853 .enable_reg = 0x2c14,
2854 .enable_mask = BIT(4),
2855 .hw.init = &(struct clk_init_data){
2856 .name = "sata_phy_ref_clk",
2857 .parent_names = (const char *[]){ "pxo" },
2858 .num_parents = 1,
2859 .ops = &clk_branch_ops,
2860 },
2861 },
2862};
2863
2864static struct clk_branch sata_a_clk = {
2865 .halt_reg = 0x2fc0,
2866 .halt_bit = 12,
2867 .clkr = {
2868 .enable_reg = 0x2c20,
2869 .enable_mask = BIT(4),
2870 .hw.init = &(struct clk_init_data){
2871 .name = "sata_a_clk",
2872 .ops = &clk_branch_ops,
2873 .flags = CLK_IS_ROOT,
2874 },
2875 },
2876};
2877
2878static struct clk_branch sata_h_clk = {
2879 .halt_reg = 0x2fdc,
2880 .halt_bit = 27,
2881 .clkr = {
2882 .enable_reg = 0x2c00,
2883 .enable_mask = BIT(4),
2884 .hw.init = &(struct clk_init_data){
2885 .name = "sata_h_clk",
2886 .ops = &clk_branch_ops,
2887 .flags = CLK_IS_ROOT,
2888 },
2889 },
2890};
2891
2892static struct clk_branch sfab_sata_s_h_clk = {
2893 .halt_reg = 0x2fc4,
2894 .halt_bit = 14,
2895 .clkr = {
2896 .enable_reg = 0x2480,
2897 .enable_mask = BIT(4),
2898 .hw.init = &(struct clk_init_data){
2899 .name = "sfab_sata_s_h_clk",
2900 .ops = &clk_branch_ops,
2901 .flags = CLK_IS_ROOT,
2902 },
2903 },
2904};
2905
2906static struct clk_branch sata_phy_cfg_clk = {
2907 .halt_reg = 0x2fcc,
2908 .halt_bit = 12,
2909 .clkr = {
2910 .enable_reg = 0x2c40,
2911 .enable_mask = BIT(4),
2912 .hw.init = &(struct clk_init_data){
2913 .name = "sata_phy_cfg_clk",
2914 .ops = &clk_branch_ops,
2915 .flags = CLK_IS_ROOT,
2916 },
2917 },
2918};
2919
2920static struct clk_branch pcie_phy_ref_clk = {
2921 .halt_reg = 0x2fdc,
2922 .halt_bit = 29,
2923 .clkr = {
2924 .enable_reg = 0x22d0,
2925 .enable_mask = BIT(4),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "pcie_phy_ref_clk",
2928 .ops = &clk_branch_ops,
2929 .flags = CLK_IS_ROOT,
2930 },
2931 },
2932};
2933
2934static struct clk_branch pcie_h_clk = {
2935 .halt_reg = 0x2fd4,
2936 .halt_bit = 8,
2937 .clkr = {
2938 .enable_reg = 0x22cc,
2939 .enable_mask = BIT(4),
2940 .hw.init = &(struct clk_init_data){
2941 .name = "pcie_h_clk",
2942 .ops = &clk_branch_ops,
2943 .flags = CLK_IS_ROOT,
2944 },
2945 },
2946};
2947
2948static struct clk_branch pcie_a_clk = {
2949 .halt_reg = 0x2fc0,
2950 .halt_bit = 13,
2951 .clkr = {
2952 .enable_reg = 0x22c0,
2953 .enable_mask = BIT(4),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "pcie_a_clk",
2956 .ops = &clk_branch_ops,
2957 .flags = CLK_IS_ROOT,
2958 },
2959 },
2960};
2961
2585static struct clk_branch pmic_arb0_h_clk = { 2962static struct clk_branch pmic_arb0_h_clk = {
2586 .halt_reg = 0x2fd8, 2963 .halt_reg = 0x2fd8,
2587 .halt_check = BRANCH_HALT_VOTED, 2964 .halt_check = BRANCH_HALT_VOTED,
@@ -2869,13 +3246,48 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = {
2869}; 3246};
2870 3247
2871static struct clk_regmap *gcc_apq8064_clks[] = { 3248static struct clk_regmap *gcc_apq8064_clks[] = {
3249 [PLL3] = &pll3.clkr,
2872 [PLL8] = &pll8.clkr, 3250 [PLL8] = &pll8.clkr,
2873 [PLL8_VOTE] = &pll8_vote, 3251 [PLL8_VOTE] = &pll8_vote,
3252 [PLL14] = &pll14.clkr,
3253 [PLL14_VOTE] = &pll14_vote,
3254 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3255 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3256 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3257 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3258 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3259 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3260 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3261 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3262 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3263 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3264 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3265 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2874 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 3266 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2875 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 3267 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3268 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3269 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3270 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3271 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3272 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3273 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3274 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3275 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3276 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3277 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3278 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3279 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2876 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 3280 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2877 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 3281 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2878 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 3282 [GP0_SRC] = &gp0_src.clkr,
3283 [GP0_CLK] = &gp0_clk.clkr,
3284 [GP1_SRC] = &gp1_src.clkr,
3285 [GP1_CLK] = &gp1_clk.clkr,
3286 [GP2_SRC] = &gp2_src.clkr,
3287 [GP2_CLK] = &gp2_clk.clkr,
3288 [PMEM_A_CLK] = &pmem_clk.clkr,
3289 [PRNG_SRC] = &prng_src.clkr,
3290 [PRNG_CLK] = &prng_clk.clkr,
2879 [SDC1_SRC] = &sdc1_src.clkr, 3291 [SDC1_SRC] = &sdc1_src.clkr,
2880 [SDC1_CLK] = &sdc1_clk.clkr, 3292 [SDC1_CLK] = &sdc1_clk.clkr,
2881 [SDC2_SRC] = &sdc2_src.clkr, 3293 [SDC2_SRC] = &sdc2_src.clkr,
@@ -2884,10 +3296,155 @@ static struct clk_regmap *gcc_apq8064_clks[] = {
2884 [SDC3_CLK] = &sdc3_clk.clkr, 3296 [SDC3_CLK] = &sdc3_clk.clkr,
2885 [SDC4_SRC] = &sdc4_src.clkr, 3297 [SDC4_SRC] = &sdc4_src.clkr,
2886 [SDC4_CLK] = &sdc4_clk.clkr, 3298 [SDC4_CLK] = &sdc4_clk.clkr,
3299 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3300 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3301 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3302 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3303 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3304 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3305 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3306 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3307 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3308 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3309 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3310 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3311 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3312 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3313 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3314 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3315 [SATA_H_CLK] = &sata_h_clk.clkr,
3316 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3317 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3318 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3319 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3320 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3321 [SATA_A_CLK] = &sata_a_clk.clkr,
3322 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3323 [CE3_SRC] = &ce3_src.clkr,
3324 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3325 [CE3_H_CLK] = &ce3_h_clk.clkr,
3326 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3327 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3328 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3329 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3330 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3331 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3332 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3333 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3334 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3335 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3336 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3337 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3338 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3339 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
2887 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 3340 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2888 [SDC2_H_CLK] = &sdc2_h_clk.clkr, 3341 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2889 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 3342 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2890 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 3343 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3344 [ADM0_CLK] = &adm0_clk.clkr,
3345 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3346 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3347 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3348 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3349 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3350 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3351 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3352 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3353};
3354
3355static const struct qcom_reset_map gcc_apq8064_resets[] = {
3356 [QDSS_STM_RESET] = { 0x2060, 6 },
3357 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3358 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3359 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3360 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3361 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3362 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3363 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3364 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3365 [ADM0_C2_RESET] = { 0x220c, 4},
3366 [ADM0_C1_RESET] = { 0x220c, 3},
3367 [ADM0_C0_RESET] = { 0x220c, 2},
3368 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3369 [ADM0_RESET] = { 0x220c },
3370 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3371 [QDSS_POR_RESET] = { 0x2260, 4 },
3372 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3373 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3374 [QDSS_AXI_RESET] = { 0x2260, 1 },
3375 [QDSS_DBG_RESET] = { 0x2260 },
3376 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3377 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3378 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3379 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3380 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3381 [PCIE_POR_RESET] = { 0x22dc, 3 },
3382 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3383 [PCIE_ACLK_RESET] = { 0x22dc },
3384 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3385 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3386 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3387 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3388 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3389 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3390 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3391 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3392 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3393 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3394 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3395 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3396 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3397 [PPSS_PROC_RESET] = { 0x2594, 1 },
3398 [PPSS_RESET] = { 0x2594},
3399 [DMA_BAM_RESET] = { 0x25c0, 7 },
3400 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3401 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3402 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3403 [TSIF_H_RESET] = { 0x2700, 7 },
3404 [CE1_H_RESET] = { 0x2720, 7 },
3405 [CE1_CORE_RESET] = { 0x2724, 7 },
3406 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3407 [CE2_H_RESET] = { 0x2740, 7 },
3408 [CE2_CORE_RESET] = { 0x2744, 7 },
3409 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3410 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3411 [RPM_PROC_RESET] = { 0x27c0, 7 },
3412 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3413 [SDC1_RESET] = { 0x2830 },
3414 [SDC2_RESET] = { 0x2850 },
3415 [SDC3_RESET] = { 0x2870 },
3416 [SDC4_RESET] = { 0x2890 },
3417 [USB_HS1_RESET] = { 0x2910 },
3418 [USB_HSIC_RESET] = { 0x2934 },
3419 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3420 [USB_FS1_RESET] = { 0x2974 },
3421 [GSBI1_RESET] = { 0x29dc },
3422 [GSBI2_RESET] = { 0x29fc },
3423 [GSBI3_RESET] = { 0x2a1c },
3424 [GSBI4_RESET] = { 0x2a3c },
3425 [GSBI5_RESET] = { 0x2a5c },
3426 [GSBI6_RESET] = { 0x2a7c },
3427 [GSBI7_RESET] = { 0x2a9c },
3428 [SPDM_RESET] = { 0x2b6c },
3429 [TLMM_H_RESET] = { 0x2ba0, 7 },
3430 [SATA_SFAB_M_RESET] = { 0x2c18 },
3431 [SATA_RESET] = { 0x2c1c },
3432 [GSS_SLP_RESET] = { 0x2c60, 7 },
3433 [GSS_RESET] = { 0x2c64 },
3434 [TSSC_RESET] = { 0x2ca0, 7 },
3435 [PDM_RESET] = { 0x2cc0, 12 },
3436 [MPM_H_RESET] = { 0x2da0, 7 },
3437 [MPM_RESET] = { 0x2da4 },
3438 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3439 [PRNG_RESET] = { 0x2e80, 12 },
3440 [RIVA_RESET] = { 0x35e0 },
3441 [CE3_H_RESET] = { 0x36c4, 7 },
3442 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3443 [SFAB_CE3_S_RESET] = { 0x36c8 },
3444 [CE3_RESET] = { 0x36cc, 7 },
3445 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3446 [USB_HS3_RESET] = { 0x3710 },
3447 [USB_HS4_RESET] = { 0x3730 },
2891}; 3448};
2892 3449
2893static const struct regmap_config gcc_msm8960_regmap_config = { 3450static const struct regmap_config gcc_msm8960_regmap_config = {
@@ -2898,6 +3455,14 @@ static const struct regmap_config gcc_msm8960_regmap_config = {
2898 .fast_io = true, 3455 .fast_io = true,
2899}; 3456};
2900 3457
3458static const struct regmap_config gcc_apq8064_regmap_config = {
3459 .reg_bits = 32,
3460 .reg_stride = 4,
3461 .val_bits = 32,
3462 .max_register = 0x3880,
3463 .fast_io = true,
3464};
3465
2901static const struct qcom_cc_desc gcc_msm8960_desc = { 3466static const struct qcom_cc_desc gcc_msm8960_desc = {
2902 .config = &gcc_msm8960_regmap_config, 3467 .config = &gcc_msm8960_regmap_config,
2903 .clks = gcc_msm8960_clks, 3468 .clks = gcc_msm8960_clks,
@@ -2907,11 +3472,11 @@ static const struct qcom_cc_desc gcc_msm8960_desc = {
2907}; 3472};
2908 3473
2909static const struct qcom_cc_desc gcc_apq8064_desc = { 3474static const struct qcom_cc_desc gcc_apq8064_desc = {
2910 .config = &gcc_msm8960_regmap_config, 3475 .config = &gcc_apq8064_regmap_config,
2911 .clks = gcc_apq8064_clks, 3476 .clks = gcc_apq8064_clks,
2912 .num_clks = ARRAY_SIZE(gcc_apq8064_clks), 3477 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
2913 .resets = gcc_msm8960_resets, 3478 .resets = gcc_apq8064_resets,
2914 .num_resets = ARRAY_SIZE(gcc_msm8960_resets), 3479 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
2915}; 3480};
2916 3481
2917static const struct of_device_id gcc_msm8960_match_table[] = { 3482static const struct of_device_id gcc_msm8960_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
index f9f547146a15..7d20eedfee98 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -308,5 +308,16 @@
308#define PLL13 292 308#define PLL13 292
309#define PLL14 293 309#define PLL14 293
310#define PLL14_VOTE 294 310#define PLL14_VOTE 294
311#define USB_HS3_H_CLK 295
312#define USB_HS3_XCVR_SRC 296
313#define USB_HS3_XCVR_CLK 297
314#define USB_HS4_H_CLK 298
315#define USB_HS4_XCVR_SRC 299
316#define USB_HS4_XCVR_CLK 300
317#define SATA_PHY_CFG_CLK 301
318#define SATA_A_CLK 302
319#define CE3_SRC 303
320#define CE3_CORE_CLK 304
321#define CE3_H_CLK 305
311 322
312#endif 323#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
index 07edd0e65eed..47c8686955da 100644
--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -114,5 +114,21 @@
114#define SFAB_SMPSS_S_RESET 97 114#define SFAB_SMPSS_S_RESET 97
115#define PRNG_RESET 98 115#define PRNG_RESET 98
116#define RIVA_RESET 99 116#define RIVA_RESET 99
117#define USB_HS3_RESET 100
118#define USB_HS4_RESET 101
119#define CE3_RESET 102
120#define PCIE_EXT_PCI_RESET 103
121#define PCIE_PHY_RESET 104
122#define PCIE_PCI_RESET 105
123#define PCIE_POR_RESET 106
124#define PCIE_HCLK_RESET 107
125#define PCIE_ACLK_RESET 108
126#define CE3_H_RESET 109
127#define SFAB_CE3_M_RESET 110
128#define SFAB_CE3_S_RESET 111
129#define SATA_RESET 112
130#define CE3_SLEEP_RESET 113
131#define GSS_SLP_RESET 114
132#define GSS_RESET 115
117 133
118#endif 134#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 10:56:48 -0400