aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2012-11-30 12:08:56 -0500
committerOlof Johansson <olof@lixom.net>2012-11-30 12:08:56 -0500
commit5e5d8999a316d596f2012fe1cf4c59e0de693dab (patch)
tree56d0aeed586f34e97acbc78759606fddb3ba0627
parent0c0029cb1806601430692d48c130a17302a18225 (diff)
parent3ee11aef75db51c69cb8cb91dd01afb28036f1b5 (diff)
Merge tag 'mvebu_cache_l2x0_for_3.8' of git://git.infradead.org/users/jcooper/linux into late/mvebu
From Jason Cooper: mvebu cache-l2x0 for v3.8 - Add support for l2x0 cache on mvebu boards - Depends on mvebu/everything * tag 'mvebu_cache_l2x0_for_3.8' of git://git.infradead.org/users/jcooper/linux: arm: l2x0: add aurora related properties to OF binding arm: mvebu: add Aurora L2 Cache Controller to the DT arm: mvebu: add L2 cache support
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/l2cc.txt9
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi6
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi7
-rw-r--r--arch/arm/mach-mvebu/Kconfig1
-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c4
5 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 7ca52161e7ab..76b0ee6ee9a4 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -10,6 +10,12 @@ Required properties:
10 "arm,pl310-cache" 10 "arm,pl310-cache"
11 "arm,l220-cache" 11 "arm,l220-cache"
12 "arm,l210-cache" 12 "arm,l210-cache"
13 "marvell,aurora-system-cache": Marvell Controller designed to be
14 compatible with the ARM one, with system cache mode (meaning
15 maintenance operations on L1 are broadcasted to the L2 and L2
16 performs the same operation).
17 "marvell,"aurora-outer-cache: Marvell Controller designed to be
18 compatible with the ARM one with outer cache mode.
13- cache-unified : Specifies the cache is a unified cache. 19- cache-unified : Specifies the cache is a unified cache.
14- cache-level : Should be set to 2 for a level 2 cache. 20- cache-level : Should be set to 2 for a level 2 cache.
15- reg : Physical base address and size of cache controller's memory mapped 21- reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties:
29 filter. Addresses in the filter window are directed to the M1 port. Other 35 filter. Addresses in the filter window are directed to the M1 port. Other
30 addresses will go to the M0 port. 36 addresses will go to the M0 port.
31- interrupts : 1 combined interrupt. 37- interrupts : 1 combined interrupt.
38- cache-id-part: cache id part number to be used if it is not present
39 on hardware
40- wt-override: If present then L2 is forced to Write through mode
32 41
33Example: 42Example:
34 43
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 7fbac28b01f3..636cf7d4009e 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,6 +20,12 @@
20/ { 20/ {
21 model = "Marvell Armada 370 family SoC"; 21 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp"; 22 compatible = "marvell,armada370", "marvell,armada-370-xp";
23 L2: l2-cache {
24 compatible = "marvell,aurora-outer-cache";
25 reg = <0xd0008000 0x1000>;
26 cache-id-part = <0x100>;
27 wt-override;
28 };
23 29
24 aliases { 30 aliases {
25 gpio0 = &gpio0; 31 gpio0 = &gpio0;
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 45a567c2e9ba..367aa3f94912 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,13 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 L2: l2-cache {
26 compatible = "marvell,aurora-system-cache";
27 reg = <0xd0008000 0x1000>;
28 cache-id-part = <0x100>;
29 wt-override;
30 };
31
25 mpic: interrupt-controller@d0020000 { 32 mpic: interrupt-controller@d0020000 {
26 reg = <0xd0020a00 0x1d0>, 33 reg = <0xd0020a00 0x1d0>,
27 <0xd0021070 0x58>; 34 <0xd0021070 0x58>;
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index c934e1d4933d..440b13ef1fed 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -22,6 +22,7 @@ config MACH_ARMADA_370_XP
22 bool 22 bool
23 select ARMADA_370_XP_TIMER 23 select ARMADA_370_XP_TIMER
24 select HAVE_SMP 24 select HAVE_SMP
25 select CACHE_L2X0
25 select CPU_PJ4B 26 select CPU_PJ4B
26 27
27config MACH_ARMADA_370 28config MACH_ARMADA_370
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 549b6846f940..8e3fb082c3c6 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -25,6 +25,7 @@
25#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/exception.h> 26#include <asm/exception.h>
27#include <asm/smp_plat.h> 27#include <asm/smp_plat.h>
28#include <asm/hardware/cache-l2x0.h>
28 29
29/* Interrupt Controller Registers Map */ 30/* Interrupt Controller Registers Map */
30#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) 31#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
@@ -210,4 +211,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
210void __init armada_370_xp_init_irq(void) 211void __init armada_370_xp_init_irq(void)
211{ 212{
212 of_irq_init(mpic_of_match); 213 of_irq_init(mpic_of_match);
214#ifdef CONFIG_CACHE_L2X0
215 l2x0_of_init(0, ~0UL);
216#endif
213} 217}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 23:49:23 -0500