diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-24 18:48:12 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-24 18:48:12 -0400 |
| commit | 5e30ca1e44029dad8304976128e3af76e4575cd1 (patch) | |
| tree | 7b60cb2976501f7dabf7558bfa691088664503b3 | |
| parent | d856f32a86b2b015ab180ab7a55e455ed8d3ccc5 (diff) | |
| parent | a284e9d14e35b776807c3a40dd1ff1e05429d4a4 (diff) | |
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Intel and radeon fixes.
Post KS/LC git requests from i915 and radeon stacked up. They are all
fixes along with some new pci ids for radeon, and one maintainers file
entry.
- i915: display fixes and irq fixes
- radeon: pci ids, and misc gpuvm, dpm and hdp cache"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (29 commits)
MAINTAINERS: Add entry for Renesas DRM drivers
drm/radeon: add additional SI pci ids
drm/radeon: add new bonaire pci ids
drm/radeon: add new KV pci id
Revert "drm/radeon: Use write-combined CPU mappings of ring buffers with PCIe"
drm/radeon: fix active_cu mask on SI and CIK after re-init (v3)
drm/radeon: fix active cu count for SI and CIK
drm/radeon: re-enable selective GPUVM flushing
drm/radeon: Sync ME and PFP after CP semaphore waits v4
drm/radeon: fix display handling in radeon_gpu_reset
drm/radeon: fix pm handling in radeon_gpu_reset
drm/radeon: Only flush HDP cache for indirect buffers from userspace
drm/radeon: properly document reloc priority mask
drm/i915: don't try to retrain a DP link on an inactive CRTC
drm/i915: make sure VDD is turned off during system suspend
drm/i915: cancel hotplug and dig_port work during suspend and unload
drm/i915: fix HPD IRQ reenable work cancelation
drm/i915: take display port power domain in DP HPD handler
drm/i915: Don't try to enable cursor from setplane when crtc is disabled
drm/i915: Skip load detect when intel_crtc->new_enable==true
...
44 files changed, 328 insertions, 167 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index f01f54f27750..c1c08a2652f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -3121,6 +3121,17 @@ F: include/linux/host1x.h | |||
| 3121 | F: include/uapi/drm/tegra_drm.h | 3121 | F: include/uapi/drm/tegra_drm.h |
| 3122 | F: Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | 3122 | F: Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt |
| 3123 | 3123 | ||
| 3124 | DRM DRIVERS FOR RENESAS | ||
| 3125 | M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | ||
| 3126 | L: dri-devel@lists.freedesktop.org | ||
| 3127 | L: linux-sh@vger.kernel.org | ||
| 3128 | T: git git://people.freedesktop.org/~airlied/linux | ||
| 3129 | S: Supported | ||
| 3130 | F: drivers/gpu/drm/rcar-du/ | ||
| 3131 | F: drivers/gpu/drm/shmobile/ | ||
| 3132 | F: include/linux/platform_data/rcar-du.h | ||
| 3133 | F: include/linux/platform_data/shmob_drm.h | ||
| 3134 | |||
| 3124 | DSBR100 USB FM RADIO DRIVER | 3135 | DSBR100 USB FM RADIO DRIVER |
| 3125 | M: Alexey Klimov <klimov.linux@gmail.com> | 3136 | M: Alexey Klimov <klimov.linux@gmail.com> |
| 3126 | L: linux-media@vger.kernel.org | 3137 | L: linux-media@vger.kernel.org |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ec96f9a9724c..e27cdbe9d524 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
| @@ -494,6 +494,36 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) | |||
| 494 | return true; | 494 | return true; |
| 495 | } | 495 | } |
| 496 | 496 | ||
| 497 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) | ||
| 498 | { | ||
| 499 | spin_lock_irq(&dev_priv->irq_lock); | ||
| 500 | |||
| 501 | dev_priv->long_hpd_port_mask = 0; | ||
| 502 | dev_priv->short_hpd_port_mask = 0; | ||
| 503 | dev_priv->hpd_event_bits = 0; | ||
| 504 | |||
| 505 | spin_unlock_irq(&dev_priv->irq_lock); | ||
| 506 | |||
| 507 | cancel_work_sync(&dev_priv->dig_port_work); | ||
| 508 | cancel_work_sync(&dev_priv->hotplug_work); | ||
| 509 | cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work); | ||
| 510 | } | ||
| 511 | |||
| 512 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) | ||
| 513 | { | ||
| 514 | struct drm_device *dev = dev_priv->dev; | ||
| 515 | struct drm_encoder *encoder; | ||
| 516 | |||
| 517 | drm_modeset_lock_all(dev); | ||
| 518 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | ||
| 519 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | ||
| 520 | |||
| 521 | if (intel_encoder->suspend) | ||
| 522 | intel_encoder->suspend(intel_encoder); | ||
| 523 | } | ||
| 524 | drm_modeset_unlock_all(dev); | ||
| 525 | } | ||
| 526 | |||
| 497 | static int i915_drm_freeze(struct drm_device *dev) | 527 | static int i915_drm_freeze(struct drm_device *dev) |
| 498 | { | 528 | { |
| 499 | struct drm_i915_private *dev_priv = dev->dev_private; | 529 | struct drm_i915_private *dev_priv = dev->dev_private; |
| @@ -538,6 +568,9 @@ static int i915_drm_freeze(struct drm_device *dev) | |||
| 538 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | 568 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 539 | 569 | ||
| 540 | intel_runtime_pm_disable_interrupts(dev); | 570 | intel_runtime_pm_disable_interrupts(dev); |
| 571 | intel_hpd_cancel_work(dev_priv); | ||
| 572 | |||
| 573 | intel_suspend_encoders(dev_priv); | ||
| 541 | 574 | ||
| 542 | intel_suspend_gt_powersave(dev); | 575 | intel_suspend_gt_powersave(dev); |
| 543 | 576 | ||
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4412f6a4383b..7a830eac5ba3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
| @@ -1458,7 +1458,7 @@ struct drm_i915_private { | |||
| 1458 | } hpd_mark; | 1458 | } hpd_mark; |
| 1459 | } hpd_stats[HPD_NUM_PINS]; | 1459 | } hpd_stats[HPD_NUM_PINS]; |
| 1460 | u32 hpd_event_bits; | 1460 | u32 hpd_event_bits; |
| 1461 | struct timer_list hotplug_reenable_timer; | 1461 | struct delayed_work hotplug_reenable_work; |
| 1462 | 1462 | ||
| 1463 | struct i915_fbc fbc; | 1463 | struct i915_fbc fbc; |
| 1464 | struct i915_drrs drrs; | 1464 | struct i915_drrs drrs; |
| @@ -2178,6 +2178,7 @@ extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |||
| 2178 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | 2178 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 2179 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | 2179 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 2180 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); | 2180 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
| 2181 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | ||
| 2181 | 2182 | ||
| 2182 | extern void intel_console_resume(struct work_struct *work); | 2183 | extern void intel_console_resume(struct work_struct *work); |
| 2183 | 2184 | ||
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 390ccc2a3096..0050ee9470f1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
| @@ -1189,8 +1189,8 @@ static void i915_hotplug_work_func(struct work_struct *work) | |||
| 1189 | * some connectors */ | 1189 | * some connectors */ |
| 1190 | if (hpd_disabled) { | 1190 | if (hpd_disabled) { |
| 1191 | drm_kms_helper_poll_enable(dev); | 1191 | drm_kms_helper_poll_enable(dev); |
| 1192 | mod_timer(&dev_priv->hotplug_reenable_timer, | 1192 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
| 1193 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | 1193 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); |
| 1194 | } | 1194 | } |
| 1195 | 1195 | ||
| 1196 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 1196 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| @@ -1213,11 +1213,6 @@ static void i915_hotplug_work_func(struct work_struct *work) | |||
| 1213 | drm_kms_helper_hotplug_event(dev); | 1213 | drm_kms_helper_hotplug_event(dev); |
| 1214 | } | 1214 | } |
| 1215 | 1215 | ||
| 1216 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) | ||
| 1217 | { | ||
| 1218 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | ||
| 1219 | } | ||
| 1220 | |||
| 1221 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) | 1216 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
| 1222 | { | 1217 | { |
| 1223 | struct drm_i915_private *dev_priv = dev->dev_private; | 1218 | struct drm_i915_private *dev_priv = dev->dev_private; |
| @@ -3892,8 +3887,6 @@ static void gen8_irq_uninstall(struct drm_device *dev) | |||
| 3892 | if (!dev_priv) | 3887 | if (!dev_priv) |
| 3893 | return; | 3888 | return; |
| 3894 | 3889 | ||
| 3895 | intel_hpd_irq_uninstall(dev_priv); | ||
| 3896 | |||
| 3897 | gen8_irq_reset(dev); | 3890 | gen8_irq_reset(dev); |
| 3898 | } | 3891 | } |
| 3899 | 3892 | ||
| @@ -3908,8 +3901,6 @@ static void valleyview_irq_uninstall(struct drm_device *dev) | |||
| 3908 | 3901 | ||
| 3909 | I915_WRITE(VLV_MASTER_IER, 0); | 3902 | I915_WRITE(VLV_MASTER_IER, 0); |
| 3910 | 3903 | ||
| 3911 | intel_hpd_irq_uninstall(dev_priv); | ||
| 3912 | |||
| 3913 | for_each_pipe(pipe) | 3904 | for_each_pipe(pipe) |
| 3914 | I915_WRITE(PIPESTAT(pipe), 0xffff); | 3905 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3915 | 3906 | ||
| @@ -3988,8 +3979,6 @@ static void ironlake_irq_uninstall(struct drm_device *dev) | |||
| 3988 | if (!dev_priv) | 3979 | if (!dev_priv) |
| 3989 | return; | 3980 | return; |
| 3990 | 3981 | ||
| 3991 | intel_hpd_irq_uninstall(dev_priv); | ||
| 3992 | |||
| 3993 | ironlake_irq_reset(dev); | 3982 | ironlake_irq_reset(dev); |
| 3994 | } | 3983 | } |
| 3995 | 3984 | ||
| @@ -4360,8 +4349,6 @@ static void i915_irq_uninstall(struct drm_device * dev) | |||
| 4360 | struct drm_i915_private *dev_priv = dev->dev_private; | 4349 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4361 | int pipe; | 4350 | int pipe; |
| 4362 | 4351 | ||
| 4363 | intel_hpd_irq_uninstall(dev_priv); | ||
| 4364 | |||
| 4365 | if (I915_HAS_HOTPLUG(dev)) { | 4352 | if (I915_HAS_HOTPLUG(dev)) { |
| 4366 | I915_WRITE(PORT_HOTPLUG_EN, 0); | 4353 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4367 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | 4354 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| @@ -4598,8 +4585,6 @@ static void i965_irq_uninstall(struct drm_device * dev) | |||
| 4598 | if (!dev_priv) | 4585 | if (!dev_priv) |
| 4599 | return; | 4586 | return; |
| 4600 | 4587 | ||
| 4601 | intel_hpd_irq_uninstall(dev_priv); | ||
| 4602 | |||
| 4603 | I915_WRITE(PORT_HOTPLUG_EN, 0); | 4588 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4604 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | 4589 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 4605 | 4590 | ||
| @@ -4615,14 +4600,18 @@ static void i965_irq_uninstall(struct drm_device * dev) | |||
| 4615 | I915_WRITE(IIR, I915_READ(IIR)); | 4600 | I915_WRITE(IIR, I915_READ(IIR)); |
| 4616 | } | 4601 | } |
| 4617 | 4602 | ||
| 4618 | static void intel_hpd_irq_reenable(unsigned long data) | 4603 | static void intel_hpd_irq_reenable(struct work_struct *work) |
| 4619 | { | 4604 | { |
| 4620 | struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; | 4605 | struct drm_i915_private *dev_priv = |
| 4606 | container_of(work, typeof(*dev_priv), | ||
| 4607 | hotplug_reenable_work.work); | ||
| 4621 | struct drm_device *dev = dev_priv->dev; | 4608 | struct drm_device *dev = dev_priv->dev; |
| 4622 | struct drm_mode_config *mode_config = &dev->mode_config; | 4609 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 4623 | unsigned long irqflags; | 4610 | unsigned long irqflags; |
| 4624 | int i; | 4611 | int i; |
| 4625 | 4612 | ||
| 4613 | intel_runtime_pm_get(dev_priv); | ||
| 4614 | |||
| 4626 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | 4615 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 4627 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | 4616 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
| 4628 | struct drm_connector *connector; | 4617 | struct drm_connector *connector; |
| @@ -4648,6 +4637,8 @@ static void intel_hpd_irq_reenable(unsigned long data) | |||
| 4648 | if (dev_priv->display.hpd_irq_setup) | 4637 | if (dev_priv->display.hpd_irq_setup) |
| 4649 | dev_priv->display.hpd_irq_setup(dev); | 4638 | dev_priv->display.hpd_irq_setup(dev); |
| 4650 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 4639 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 4640 | |||
| 4641 | intel_runtime_pm_put(dev_priv); | ||
| 4651 | } | 4642 | } |
| 4652 | 4643 | ||
| 4653 | void intel_irq_init(struct drm_device *dev) | 4644 | void intel_irq_init(struct drm_device *dev) |
| @@ -4670,8 +4661,8 @@ void intel_irq_init(struct drm_device *dev) | |||
| 4670 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, | 4661 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 4671 | i915_hangcheck_elapsed, | 4662 | i915_hangcheck_elapsed, |
| 4672 | (unsigned long) dev); | 4663 | (unsigned long) dev); |
| 4673 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, | 4664 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
| 4674 | (unsigned long) dev_priv); | 4665 | intel_hpd_irq_reenable); |
| 4675 | 4666 | ||
| 4676 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); | 4667 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
| 4677 | 4668 | ||
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 2efaf8e8d9c4..e8abfce40976 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
| @@ -699,16 +699,21 @@ intel_crt_detect(struct drm_connector *connector, bool force) | |||
| 699 | goto out; | 699 | goto out; |
| 700 | } | 700 | } |
| 701 | 701 | ||
| 702 | drm_modeset_acquire_init(&ctx, 0); | ||
| 703 | |||
| 702 | /* for pre-945g platforms use load detect */ | 704 | /* for pre-945g platforms use load detect */ |
| 703 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { | 705 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
| 704 | if (intel_crt_detect_ddc(connector)) | 706 | if (intel_crt_detect_ddc(connector)) |
| 705 | status = connector_status_connected; | 707 | status = connector_status_connected; |
| 706 | else | 708 | else |
| 707 | status = intel_crt_load_detect(crt); | 709 | status = intel_crt_load_detect(crt); |
| 708 | intel_release_load_detect_pipe(connector, &tmp, &ctx); | 710 | intel_release_load_detect_pipe(connector, &tmp); |
| 709 | } else | 711 | } else |
| 710 | status = connector_status_unknown; | 712 | status = connector_status_unknown; |
| 711 | 713 | ||
| 714 | drm_modeset_drop_locks(&ctx); | ||
| 715 | drm_modeset_acquire_fini(&ctx); | ||
| 716 | |||
| 712 | out: | 717 | out: |
| 713 | intel_display_power_put(dev_priv, power_domain); | 718 | intel_display_power_put(dev_priv, power_domain); |
| 714 | return status; | 719 | return status; |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 018fb7222f60..d074d704f458 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
| @@ -8462,8 +8462,6 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector, | |||
| 8462 | connector->base.id, connector->name, | 8462 | connector->base.id, connector->name, |
| 8463 | encoder->base.id, encoder->name); | 8463 | encoder->base.id, encoder->name); |
| 8464 | 8464 | ||
| 8465 | drm_modeset_acquire_init(ctx, 0); | ||
| 8466 | |||
| 8467 | retry: | 8465 | retry: |
| 8468 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | 8466 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
| 8469 | if (ret) | 8467 | if (ret) |
| @@ -8502,10 +8500,14 @@ retry: | |||
| 8502 | i++; | 8500 | i++; |
| 8503 | if (!(encoder->possible_crtcs & (1 << i))) | 8501 | if (!(encoder->possible_crtcs & (1 << i))) |
| 8504 | continue; | 8502 | continue; |
| 8505 | if (!possible_crtc->enabled) { | 8503 | if (possible_crtc->enabled) |
| 8506 | crtc = possible_crtc; | 8504 | continue; |
| 8507 | break; | 8505 | /* This can occur when applying the pipe A quirk on resume. */ |
| 8508 | } | 8506 | if (to_intel_crtc(possible_crtc)->new_enabled) |
| 8507 | continue; | ||
| 8508 | |||
| 8509 | crtc = possible_crtc; | ||
| 8510 | break; | ||
| 8509 | } | 8511 | } |
| 8510 | 8512 | ||
| 8511 | /* | 8513 | /* |
| @@ -8574,15 +8576,11 @@ fail_unlock: | |||
| 8574 | goto retry; | 8576 | goto retry; |
| 8575 | } | 8577 | } |
| 8576 | 8578 | ||
| 8577 | drm_modeset_drop_locks(ctx); | ||
| 8578 | drm_modeset_acquire_fini(ctx); | ||
| 8579 | |||
| 8580 | return false; | 8579 | return false; |
| 8581 | } | 8580 | } |
| 8582 | 8581 | ||
| 8583 | void intel_release_load_detect_pipe(struct drm_connector *connector, | 8582 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
| 8584 | struct intel_load_detect_pipe *old, | 8583 | struct intel_load_detect_pipe *old) |
| 8585 | struct drm_modeset_acquire_ctx *ctx) | ||
| 8586 | { | 8584 | { |
| 8587 | struct intel_encoder *intel_encoder = | 8585 | struct intel_encoder *intel_encoder = |
| 8588 | intel_attached_encoder(connector); | 8586 | intel_attached_encoder(connector); |
| @@ -8606,17 +8604,12 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, | |||
| 8606 | drm_framebuffer_unreference(old->release_fb); | 8604 | drm_framebuffer_unreference(old->release_fb); |
| 8607 | } | 8605 | } |
| 8608 | 8606 | ||
| 8609 | goto unlock; | ||
| 8610 | return; | 8607 | return; |
| 8611 | } | 8608 | } |
| 8612 | 8609 | ||
| 8613 | /* Switch crtc and encoder back off if necessary */ | 8610 | /* Switch crtc and encoder back off if necessary */ |
| 8614 | if (old->dpms_mode != DRM_MODE_DPMS_ON) | 8611 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
| 8615 | connector->funcs->dpms(connector, old->dpms_mode); | 8612 | connector->funcs->dpms(connector, old->dpms_mode); |
| 8616 | |||
| 8617 | unlock: | ||
| 8618 | drm_modeset_drop_locks(ctx); | ||
| 8619 | drm_modeset_acquire_fini(ctx); | ||
| 8620 | } | 8613 | } |
| 8621 | 8614 | ||
| 8622 | static int i9xx_pll_refclk(struct drm_device *dev, | 8615 | static int i9xx_pll_refclk(struct drm_device *dev, |
| @@ -11700,8 +11693,8 @@ intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |||
| 11700 | }; | 11693 | }; |
| 11701 | const struct drm_rect clip = { | 11694 | const struct drm_rect clip = { |
| 11702 | /* integer pixels */ | 11695 | /* integer pixels */ |
| 11703 | .x2 = intel_crtc->config.pipe_src_w, | 11696 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
| 11704 | .y2 = intel_crtc->config.pipe_src_h, | 11697 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
| 11705 | }; | 11698 | }; |
| 11706 | bool visible; | 11699 | bool visible; |
| 11707 | int ret; | 11700 | int ret; |
| @@ -12659,7 +12652,7 @@ static void intel_enable_pipe_a(struct drm_device *dev) | |||
| 12659 | struct intel_connector *connector; | 12652 | struct intel_connector *connector; |
| 12660 | struct drm_connector *crt = NULL; | 12653 | struct drm_connector *crt = NULL; |
| 12661 | struct intel_load_detect_pipe load_detect_temp; | 12654 | struct intel_load_detect_pipe load_detect_temp; |
| 12662 | struct drm_modeset_acquire_ctx ctx; | 12655 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
| 12663 | 12656 | ||
| 12664 | /* We can't just switch on the pipe A, we need to set things up with a | 12657 | /* We can't just switch on the pipe A, we need to set things up with a |
| 12665 | * proper mode and output configuration. As a gross hack, enable pipe A | 12658 | * proper mode and output configuration. As a gross hack, enable pipe A |
| @@ -12676,10 +12669,8 @@ static void intel_enable_pipe_a(struct drm_device *dev) | |||
| 12676 | if (!crt) | 12669 | if (!crt) |
| 12677 | return; | 12670 | return; |
| 12678 | 12671 | ||
| 12679 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx)) | 12672 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
| 12680 | intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx); | 12673 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
| 12681 | |||
| 12682 | |||
| 12683 | } | 12674 | } |
| 12684 | 12675 | ||
| 12685 | static bool | 12676 | static bool |
| @@ -13112,7 +13103,7 @@ void intel_modeset_cleanup(struct drm_device *dev) | |||
| 13112 | * experience fancy races otherwise. | 13103 | * experience fancy races otherwise. |
| 13113 | */ | 13104 | */ |
| 13114 | drm_irq_uninstall(dev); | 13105 | drm_irq_uninstall(dev); |
| 13115 | cancel_work_sync(&dev_priv->hotplug_work); | 13106 | intel_hpd_cancel_work(dev_priv); |
| 13116 | dev_priv->pm._irqs_disabled = true; | 13107 | dev_priv->pm._irqs_disabled = true; |
| 13117 | 13108 | ||
| 13118 | /* | 13109 | /* |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ee3942f0b068..67cfed6d911a 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
| @@ -3553,6 +3553,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) | |||
| 3553 | if (WARN_ON(!intel_encoder->base.crtc)) | 3553 | if (WARN_ON(!intel_encoder->base.crtc)) |
| 3554 | return; | 3554 | return; |
| 3555 | 3555 | ||
| 3556 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | ||
| 3557 | return; | ||
| 3558 | |||
| 3556 | /* Try to read receiver status if the link appears to be up */ | 3559 | /* Try to read receiver status if the link appears to be up */ |
| 3557 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | 3560 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 3558 | return; | 3561 | return; |
| @@ -4003,6 +4006,16 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) | |||
| 4003 | kfree(intel_dig_port); | 4006 | kfree(intel_dig_port); |
| 4004 | } | 4007 | } |
| 4005 | 4008 | ||
| 4009 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) | ||
| 4010 | { | ||
| 4011 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | ||
| 4012 | |||
| 4013 | if (!is_edp(intel_dp)) | ||
| 4014 | return; | ||
| 4015 | |||
| 4016 | edp_panel_vdd_off_sync(intel_dp); | ||
| 4017 | } | ||
| 4018 | |||
| 4006 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) | 4019 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
| 4007 | { | 4020 | { |
| 4008 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); | 4021 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); |
| @@ -4037,15 +4050,21 @@ bool | |||
| 4037 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) | 4050 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
| 4038 | { | 4051 | { |
| 4039 | struct intel_dp *intel_dp = &intel_dig_port->dp; | 4052 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 4053 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | ||
| 4040 | struct drm_device *dev = intel_dig_port->base.base.dev; | 4054 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4041 | struct drm_i915_private *dev_priv = dev->dev_private; | 4055 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4042 | int ret; | 4056 | enum intel_display_power_domain power_domain; |
| 4057 | bool ret = true; | ||
| 4058 | |||
| 4043 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) | 4059 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
| 4044 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; | 4060 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
| 4045 | 4061 | ||
| 4046 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, | 4062 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, |
| 4047 | long_hpd ? "long" : "short"); | 4063 | long_hpd ? "long" : "short"); |
| 4048 | 4064 | ||
| 4065 | power_domain = intel_display_port_power_domain(intel_encoder); | ||
| 4066 | intel_display_power_get(dev_priv, power_domain); | ||
| 4067 | |||
| 4049 | if (long_hpd) { | 4068 | if (long_hpd) { |
| 4050 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) | 4069 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
| 4051 | goto mst_fail; | 4070 | goto mst_fail; |
| @@ -4061,8 +4080,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) | |||
| 4061 | 4080 | ||
| 4062 | } else { | 4081 | } else { |
| 4063 | if (intel_dp->is_mst) { | 4082 | if (intel_dp->is_mst) { |
| 4064 | ret = intel_dp_check_mst_status(intel_dp); | 4083 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
| 4065 | if (ret == -EINVAL) | ||
| 4066 | goto mst_fail; | 4084 | goto mst_fail; |
| 4067 | } | 4085 | } |
| 4068 | 4086 | ||
| @@ -4076,7 +4094,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) | |||
| 4076 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | 4094 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 4077 | } | 4095 | } |
| 4078 | } | 4096 | } |
| 4079 | return false; | 4097 | ret = false; |
| 4098 | goto put_power; | ||
| 4080 | mst_fail: | 4099 | mst_fail: |
| 4081 | /* if we were in MST mode, and device is not there get out of MST mode */ | 4100 | /* if we were in MST mode, and device is not there get out of MST mode */ |
| 4082 | if (intel_dp->is_mst) { | 4101 | if (intel_dp->is_mst) { |
| @@ -4084,7 +4103,10 @@ mst_fail: | |||
| 4084 | intel_dp->is_mst = false; | 4103 | intel_dp->is_mst = false; |
| 4085 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | 4104 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 4086 | } | 4105 | } |
| 4087 | return true; | 4106 | put_power: |
| 4107 | intel_display_power_put(dev_priv, power_domain); | ||
| 4108 | |||
| 4109 | return ret; | ||
| 4088 | } | 4110 | } |
| 4089 | 4111 | ||
| 4090 | /* Return which DP Port should be selected for Transcoder DP control */ | 4112 | /* Return which DP Port should be selected for Transcoder DP control */ |
| @@ -4722,6 +4744,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |||
| 4722 | intel_encoder->disable = intel_disable_dp; | 4744 | intel_encoder->disable = intel_disable_dp; |
| 4723 | intel_encoder->get_hw_state = intel_dp_get_hw_state; | 4745 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
| 4724 | intel_encoder->get_config = intel_dp_get_config; | 4746 | intel_encoder->get_config = intel_dp_get_config; |
| 4747 | intel_encoder->suspend = intel_dp_encoder_suspend; | ||
| 4725 | if (IS_CHERRYVIEW(dev)) { | 4748 | if (IS_CHERRYVIEW(dev)) { |
| 4726 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; | 4749 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
| 4727 | intel_encoder->pre_enable = chv_pre_enable_dp; | 4750 | intel_encoder->pre_enable = chv_pre_enable_dp; |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4b2664bd5b81..b8c8bbd8e5f9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
| @@ -153,6 +153,12 @@ struct intel_encoder { | |||
| 153 | * be set correctly before calling this function. */ | 153 | * be set correctly before calling this function. */ |
| 154 | void (*get_config)(struct intel_encoder *, | 154 | void (*get_config)(struct intel_encoder *, |
| 155 | struct intel_crtc_config *pipe_config); | 155 | struct intel_crtc_config *pipe_config); |
| 156 | /* | ||
| 157 | * Called during system suspend after all pending requests for the | ||
| 158 | * encoder are flushed (for example for DP AUX transactions) and | ||
| 159 | * device interrupts are disabled. | ||
| 160 | */ | ||
| 161 | void (*suspend)(struct intel_encoder *); | ||
| 156 | int crtc_mask; | 162 | int crtc_mask; |
| 157 | enum hpd_pin hpd_pin; | 163 | enum hpd_pin hpd_pin; |
| 158 | }; | 164 | }; |
| @@ -830,8 +836,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector, | |||
| 830 | struct intel_load_detect_pipe *old, | 836 | struct intel_load_detect_pipe *old, |
| 831 | struct drm_modeset_acquire_ctx *ctx); | 837 | struct drm_modeset_acquire_ctx *ctx); |
| 832 | void intel_release_load_detect_pipe(struct drm_connector *connector, | 838 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
| 833 | struct intel_load_detect_pipe *old, | 839 | struct intel_load_detect_pipe *old); |
| 834 | struct drm_modeset_acquire_ctx *ctx); | ||
| 835 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, | 840 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
| 836 | struct drm_i915_gem_object *obj, | 841 | struct drm_i915_gem_object *obj, |
| 837 | struct intel_engine_cs *pipelined); | 842 | struct intel_engine_cs *pipelined); |
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index e211eef4b7e4..32186a656816 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c | |||
| @@ -1323,11 +1323,16 @@ intel_tv_detect(struct drm_connector *connector, bool force) | |||
| 1323 | struct intel_load_detect_pipe tmp; | 1323 | struct intel_load_detect_pipe tmp; |
| 1324 | struct drm_modeset_acquire_ctx ctx; | 1324 | struct drm_modeset_acquire_ctx ctx; |
| 1325 | 1325 | ||
| 1326 | drm_modeset_acquire_init(&ctx, 0); | ||
| 1327 | |||
| 1326 | if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) { | 1328 | if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) { |
| 1327 | type = intel_tv_detect_type(intel_tv, connector); | 1329 | type = intel_tv_detect_type(intel_tv, connector); |
| 1328 | intel_release_load_detect_pipe(connector, &tmp, &ctx); | 1330 | intel_release_load_detect_pipe(connector, &tmp); |
| 1329 | } else | 1331 | } else |
| 1330 | return connector_status_unknown; | 1332 | return connector_status_unknown; |
| 1333 | |||
| 1334 | drm_modeset_drop_locks(&ctx); | ||
| 1335 | drm_modeset_acquire_fini(&ctx); | ||
| 1331 | } else | 1336 | } else |
| 1332 | return connector->status; | 1337 | return connector->status; |
| 1333 | 1338 | ||
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 0013ad0db9ef..f77b7135ee4c 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile | |||
| @@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ | |||
| 76 | evergreen.o evergreen_cs.o evergreen_blit_shaders.o \ | 76 | evergreen.o evergreen_cs.o evergreen_blit_shaders.o \ |
| 77 | evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ | 77 | evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ |
| 78 | atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ | 78 | atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ |
| 79 | si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \ | 79 | si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \ |
| 80 | r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ | 80 | r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ |
| 81 | rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ | 81 | rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ |
| 82 | trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \ | 82 | trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \ |
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 022561e28707..d416bb2ff48d 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c | |||
| @@ -869,6 +869,9 @@ static int ci_set_thermal_temperature_range(struct radeon_device *rdev, | |||
| 869 | WREG32_SMC(CG_THERMAL_CTRL, tmp); | 869 | WREG32_SMC(CG_THERMAL_CTRL, tmp); |
| 870 | #endif | 870 | #endif |
| 871 | 871 | ||
| 872 | rdev->pm.dpm.thermal.min_temp = low_temp; | ||
| 873 | rdev->pm.dpm.thermal.max_temp = high_temp; | ||
| 874 | |||
| 872 | return 0; | 875 | return 0; |
| 873 | } | 876 | } |
| 874 | 877 | ||
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index b625646bf3e2..79a5a5519bd6 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
| @@ -3483,7 +3483,7 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
| 3483 | u32 mc_shared_chmap, mc_arb_ramcfg; | 3483 | u32 mc_shared_chmap, mc_arb_ramcfg; |
| 3484 | u32 hdp_host_path_cntl; | 3484 | u32 hdp_host_path_cntl; |
| 3485 | u32 tmp; | 3485 | u32 tmp; |
| 3486 | int i, j, k; | 3486 | int i, j; |
| 3487 | 3487 | ||
| 3488 | switch (rdev->family) { | 3488 | switch (rdev->family) { |
| 3489 | case CHIP_BONAIRE: | 3489 | case CHIP_BONAIRE: |
| @@ -3544,6 +3544,7 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
| 3544 | (rdev->pdev->device == 0x130B) || | 3544 | (rdev->pdev->device == 0x130B) || |
| 3545 | (rdev->pdev->device == 0x130E) || | 3545 | (rdev->pdev->device == 0x130E) || |
| 3546 | (rdev->pdev->device == 0x1315) || | 3546 | (rdev->pdev->device == 0x1315) || |
| 3547 | (rdev->pdev->device == 0x1318) || | ||
| 3547 | (rdev->pdev->device == 0x131B)) { | 3548 | (rdev->pdev->device == 0x131B)) { |
| 3548 | rdev->config.cik.max_cu_per_sh = 4; | 3549 | rdev->config.cik.max_cu_per_sh = 4; |
| 3549 | rdev->config.cik.max_backends_per_se = 1; | 3550 | rdev->config.cik.max_backends_per_se = 1; |
| @@ -3672,12 +3673,11 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
| 3672 | rdev->config.cik.max_sh_per_se, | 3673 | rdev->config.cik.max_sh_per_se, |
| 3673 | rdev->config.cik.max_backends_per_se); | 3674 | rdev->config.cik.max_backends_per_se); |
| 3674 | 3675 | ||
| 3676 | rdev->config.cik.active_cus = 0; | ||
| 3675 | for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { | 3677 | for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { |
| 3676 | for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { | 3678 | for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { |
| 3677 | for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) { | 3679 | rdev->config.cik.active_cus += |
| 3678 | rdev->config.cik.active_cus += | 3680 | hweight32(cik_get_cu_active_bitmap(rdev, i, j)); |
| 3679 | hweight32(cik_get_cu_active_bitmap(rdev, i, j)); | ||
| 3680 | } | ||
| 3681 | } | 3681 | } |
| 3682 | } | 3682 | } |
| 3683 | 3683 | ||
| @@ -3801,7 +3801,7 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 3801 | radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); | 3801 | radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); |
| 3802 | radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); | 3802 | radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); |
| 3803 | radeon_ring_write(ring, 0xDEADBEEF); | 3803 | radeon_ring_write(ring, 0xDEADBEEF); |
| 3804 | radeon_ring_unlock_commit(rdev, ring); | 3804 | radeon_ring_unlock_commit(rdev, ring, false); |
| 3805 | 3805 | ||
| 3806 | for (i = 0; i < rdev->usec_timeout; i++) { | 3806 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3807 | tmp = RREG32(scratch); | 3807 | tmp = RREG32(scratch); |
| @@ -3920,6 +3920,17 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev, | |||
| 3920 | radeon_ring_write(ring, 0); | 3920 | radeon_ring_write(ring, 0); |
| 3921 | } | 3921 | } |
| 3922 | 3922 | ||
| 3923 | /** | ||
| 3924 | * cik_semaphore_ring_emit - emit a semaphore on the CP ring | ||
| 3925 | * | ||
| 3926 | * @rdev: radeon_device pointer | ||
| 3927 | * @ring: radeon ring buffer object | ||
| 3928 | * @semaphore: radeon semaphore object | ||
| 3929 | * @emit_wait: Is this a sempahore wait? | ||
| 3930 | * | ||
| 3931 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP | ||
| 3932 | * from running ahead of semaphore waits. | ||
| 3933 | */ | ||
| 3923 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, | 3934 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, |
| 3924 | struct radeon_ring *ring, | 3935 | struct radeon_ring *ring, |
| 3925 | struct radeon_semaphore *semaphore, | 3936 | struct radeon_semaphore *semaphore, |
| @@ -3932,6 +3943,12 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev, | |||
| 3932 | radeon_ring_write(ring, lower_32_bits(addr)); | 3943 | radeon_ring_write(ring, lower_32_bits(addr)); |
| 3933 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); | 3944 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); |
| 3934 | 3945 | ||
| 3946 | if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) { | ||
| 3947 | /* Prevent the PFP from running ahead of the semaphore wait */ | ||
| 3948 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | ||
| 3949 | radeon_ring_write(ring, 0x0); | ||
| 3950 | } | ||
| 3951 | |||
| 3935 | return true; | 3952 | return true; |
| 3936 | } | 3953 | } |
| 3937 | 3954 | ||
| @@ -4004,7 +4021,7 @@ int cik_copy_cpdma(struct radeon_device *rdev, | |||
| 4004 | return r; | 4021 | return r; |
| 4005 | } | 4022 | } |
| 4006 | 4023 | ||
| 4007 | radeon_ring_unlock_commit(rdev, ring); | 4024 | radeon_ring_unlock_commit(rdev, ring, false); |
| 4008 | radeon_semaphore_free(rdev, &sem, *fence); | 4025 | radeon_semaphore_free(rdev, &sem, *fence); |
| 4009 | 4026 | ||
| 4010 | return r; | 4027 | return r; |
| @@ -4103,7 +4120,7 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 4103 | ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2); | 4120 | ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2); |
| 4104 | ib.ptr[2] = 0xDEADBEEF; | 4121 | ib.ptr[2] = 0xDEADBEEF; |
| 4105 | ib.length_dw = 3; | 4122 | ib.length_dw = 3; |
| 4106 | r = radeon_ib_schedule(rdev, &ib, NULL); | 4123 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 4107 | if (r) { | 4124 | if (r) { |
| 4108 | radeon_scratch_free(rdev, scratch); | 4125 | radeon_scratch_free(rdev, scratch); |
| 4109 | radeon_ib_free(rdev, &ib); | 4126 | radeon_ib_free(rdev, &ib); |
| @@ -4324,7 +4341,7 @@ static int cik_cp_gfx_start(struct radeon_device *rdev) | |||
| 4324 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 4341 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
| 4325 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ | 4342 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ |
| 4326 | 4343 | ||
| 4327 | radeon_ring_unlock_commit(rdev, ring); | 4344 | radeon_ring_unlock_commit(rdev, ring, false); |
| 4328 | 4345 | ||
| 4329 | return 0; | 4346 | return 0; |
| 4330 | } | 4347 | } |
| @@ -5958,14 +5975,14 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
| 5958 | 5975 | ||
| 5959 | /* update SH_MEM_* regs */ | 5976 | /* update SH_MEM_* regs */ |
| 5960 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5977 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 5961 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5978 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
| 5962 | WRITE_DATA_DST_SEL(0))); | 5979 | WRITE_DATA_DST_SEL(0))); |
| 5963 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | 5980 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
| 5964 | radeon_ring_write(ring, 0); | 5981 | radeon_ring_write(ring, 0); |
| 5965 | radeon_ring_write(ring, VMID(vm->id)); | 5982 | radeon_ring_write(ring, VMID(vm->id)); |
| 5966 | 5983 | ||
| 5967 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); | 5984 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); |
| 5968 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5985 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
| 5969 | WRITE_DATA_DST_SEL(0))); | 5986 | WRITE_DATA_DST_SEL(0))); |
| 5970 | radeon_ring_write(ring, SH_MEM_BASES >> 2); | 5987 | radeon_ring_write(ring, SH_MEM_BASES >> 2); |
| 5971 | radeon_ring_write(ring, 0); | 5988 | radeon_ring_write(ring, 0); |
| @@ -5976,7 +5993,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
| 5976 | radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ | 5993 | radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ |
| 5977 | 5994 | ||
| 5978 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5995 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 5979 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5996 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
| 5980 | WRITE_DATA_DST_SEL(0))); | 5997 | WRITE_DATA_DST_SEL(0))); |
| 5981 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | 5998 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
| 5982 | radeon_ring_write(ring, 0); | 5999 | radeon_ring_write(ring, 0); |
| @@ -5987,7 +6004,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
| 5987 | 6004 | ||
| 5988 | /* bits 0-15 are the VM contexts0-15 */ | 6005 | /* bits 0-15 are the VM contexts0-15 */ |
| 5989 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 6006 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 5990 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 6007 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
| 5991 | WRITE_DATA_DST_SEL(0))); | 6008 | WRITE_DATA_DST_SEL(0))); |
| 5992 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 6009 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
| 5993 | radeon_ring_write(ring, 0); | 6010 | radeon_ring_write(ring, 0); |
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c index bcf480510ac2..192278bc993c 100644 --- a/drivers/gpu/drm/radeon/cik_sdma.c +++ b/drivers/gpu/drm/radeon/cik_sdma.c | |||
| @@ -596,7 +596,7 @@ int cik_copy_dma(struct radeon_device *rdev, | |||
| 596 | return r; | 596 | return r; |
| 597 | } | 597 | } |
| 598 | 598 | ||
| 599 | radeon_ring_unlock_commit(rdev, ring); | 599 | radeon_ring_unlock_commit(rdev, ring, false); |
| 600 | radeon_semaphore_free(rdev, &sem, *fence); | 600 | radeon_semaphore_free(rdev, &sem, *fence); |
| 601 | 601 | ||
| 602 | return r; | 602 | return r; |
| @@ -638,7 +638,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev, | |||
| 638 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); | 638 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); |
| 639 | radeon_ring_write(ring, 1); /* number of DWs to follow */ | 639 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
| 640 | radeon_ring_write(ring, 0xDEADBEEF); | 640 | radeon_ring_write(ring, 0xDEADBEEF); |
| 641 | radeon_ring_unlock_commit(rdev, ring); | 641 | radeon_ring_unlock_commit(rdev, ring, false); |
| 642 | 642 | ||
| 643 | for (i = 0; i < rdev->usec_timeout; i++) { | 643 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 644 | tmp = readl(ptr); | 644 | tmp = readl(ptr); |
| @@ -695,7 +695,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 695 | ib.ptr[4] = 0xDEADBEEF; | 695 | ib.ptr[4] = 0xDEADBEEF; |
| 696 | ib.length_dw = 5; | 696 | ib.length_dw = 5; |
| 697 | 697 | ||
| 698 | r = radeon_ib_schedule(rdev, &ib, NULL); | 698 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 699 | if (r) { | 699 | if (r) { |
| 700 | radeon_ib_free(rdev, &ib); | 700 | radeon_ib_free(rdev, &ib); |
| 701 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 701 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 4fedd14e670a..dbca60c7d097 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
| @@ -2869,7 +2869,7 @@ static int evergreen_cp_start(struct radeon_device *rdev) | |||
| 2869 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | 2869 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
| 2870 | radeon_ring_write(ring, 0); | 2870 | radeon_ring_write(ring, 0); |
| 2871 | radeon_ring_write(ring, 0); | 2871 | radeon_ring_write(ring, 0); |
| 2872 | radeon_ring_unlock_commit(rdev, ring); | 2872 | radeon_ring_unlock_commit(rdev, ring, false); |
| 2873 | 2873 | ||
| 2874 | cp_me = 0xff; | 2874 | cp_me = 0xff; |
| 2875 | WREG32(CP_ME_CNTL, cp_me); | 2875 | WREG32(CP_ME_CNTL, cp_me); |
| @@ -2912,7 +2912,7 @@ static int evergreen_cp_start(struct radeon_device *rdev) | |||
| 2912 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 2912 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
| 2913 | radeon_ring_write(ring, 0x00000010); /* */ | 2913 | radeon_ring_write(ring, 0x00000010); /* */ |
| 2914 | 2914 | ||
| 2915 | radeon_ring_unlock_commit(rdev, ring); | 2915 | radeon_ring_unlock_commit(rdev, ring, false); |
| 2916 | 2916 | ||
| 2917 | return 0; | 2917 | return 0; |
| 2918 | } | 2918 | } |
diff --git a/drivers/gpu/drm/radeon/evergreen_dma.c b/drivers/gpu/drm/radeon/evergreen_dma.c index 478caefe0fef..afaba388c36d 100644 --- a/drivers/gpu/drm/radeon/evergreen_dma.c +++ b/drivers/gpu/drm/radeon/evergreen_dma.c | |||
| @@ -155,7 +155,7 @@ int evergreen_copy_dma(struct radeon_device *rdev, | |||
| 155 | return r; | 155 | return r; |
| 156 | } | 156 | } |
| 157 | 157 | ||
| 158 | radeon_ring_unlock_commit(rdev, ring); | 158 | radeon_ring_unlock_commit(rdev, ring, false); |
| 159 | radeon_semaphore_free(rdev, &sem, *fence); | 159 | radeon_semaphore_free(rdev, &sem, *fence); |
| 160 | 160 | ||
| 161 | return r; | 161 | return r; |
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c index 9ef8c38f2d66..8b58e11b64fa 100644 --- a/drivers/gpu/drm/radeon/kv_dpm.c +++ b/drivers/gpu/drm/radeon/kv_dpm.c | |||
| @@ -1438,14 +1438,14 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate) | |||
| 1438 | return kv_enable_uvd_dpm(rdev, !gate); | 1438 | return kv_enable_uvd_dpm(rdev, !gate); |
| 1439 | } | 1439 | } |
| 1440 | 1440 | ||
| 1441 | static u8 kv_get_vce_boot_level(struct radeon_device *rdev) | 1441 | static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) |
| 1442 | { | 1442 | { |
| 1443 | u8 i; | 1443 | u8 i; |
| 1444 | struct radeon_vce_clock_voltage_dependency_table *table = | 1444 | struct radeon_vce_clock_voltage_dependency_table *table = |
| 1445 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; | 1445 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; |
| 1446 | 1446 | ||
| 1447 | for (i = 0; i < table->count; i++) { | 1447 | for (i = 0; i < table->count; i++) { |
| 1448 | if (table->entries[i].evclk >= 0) /* XXX */ | 1448 | if (table->entries[i].evclk >= evclk) |
| 1449 | break; | 1449 | break; |
| 1450 | } | 1450 | } |
| 1451 | 1451 | ||
| @@ -1468,7 +1468,7 @@ static int kv_update_vce_dpm(struct radeon_device *rdev, | |||
| 1468 | if (pi->caps_stable_p_state) | 1468 | if (pi->caps_stable_p_state) |
| 1469 | pi->vce_boot_level = table->count - 1; | 1469 | pi->vce_boot_level = table->count - 1; |
| 1470 | else | 1470 | else |
| 1471 | pi->vce_boot_level = kv_get_vce_boot_level(rdev); | 1471 | pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); |
| 1472 | 1472 | ||
| 1473 | ret = kv_copy_bytes_to_smc(rdev, | 1473 | ret = kv_copy_bytes_to_smc(rdev, |
| 1474 | pi->dpm_table_start + | 1474 | pi->dpm_table_start + |
| @@ -2726,7 +2726,10 @@ int kv_dpm_init(struct radeon_device *rdev) | |||
| 2726 | pi->caps_sclk_ds = true; | 2726 | pi->caps_sclk_ds = true; |
| 2727 | pi->enable_auto_thermal_throttling = true; | 2727 | pi->enable_auto_thermal_throttling = true; |
| 2728 | pi->disable_nb_ps3_in_battery = false; | 2728 | pi->disable_nb_ps3_in_battery = false; |
| 2729 | pi->bapm_enable = true; | 2729 | if (radeon_bapm == 0) |
| 2730 | pi->bapm_enable = false; | ||
| 2731 | else | ||
| 2732 | pi->bapm_enable = true; | ||
| 2730 | pi->voltage_drop_t = 0; | 2733 | pi->voltage_drop_t = 0; |
| 2731 | pi->caps_sclk_throttle_low_notification = false; | 2734 | pi->caps_sclk_throttle_low_notification = false; |
| 2732 | pi->caps_fps = false; /* true? */ | 2735 | pi->caps_fps = false; /* true? */ |
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 327b85f7fd0d..ba89375f197f 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
| @@ -1505,7 +1505,7 @@ static int cayman_cp_start(struct radeon_device *rdev) | |||
| 1505 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | 1505 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
| 1506 | radeon_ring_write(ring, 0); | 1506 | radeon_ring_write(ring, 0); |
| 1507 | radeon_ring_write(ring, 0); | 1507 | radeon_ring_write(ring, 0); |
| 1508 | radeon_ring_unlock_commit(rdev, ring); | 1508 | radeon_ring_unlock_commit(rdev, ring, false); |
| 1509 | 1509 | ||
| 1510 | cayman_cp_enable(rdev, true); | 1510 | cayman_cp_enable(rdev, true); |
| 1511 | 1511 | ||
| @@ -1547,7 +1547,7 @@ static int cayman_cp_start(struct radeon_device *rdev) | |||
| 1547 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 1547 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
| 1548 | radeon_ring_write(ring, 0x00000010); /* */ | 1548 | radeon_ring_write(ring, 0x00000010); /* */ |
| 1549 | 1549 | ||
| 1550 | radeon_ring_unlock_commit(rdev, ring); | 1550 | radeon_ring_unlock_commit(rdev, ring, false); |
| 1551 | 1551 | ||
| 1552 | /* XXX init other rings */ | 1552 | /* XXX init other rings */ |
| 1553 | 1553 | ||
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 04b5940b8923..4c5ec44ff328 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
| @@ -925,7 +925,7 @@ int r100_copy_blit(struct radeon_device *rdev, | |||
| 925 | if (fence) { | 925 | if (fence) { |
| 926 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); | 926 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
| 927 | } | 927 | } |
| 928 | radeon_ring_unlock_commit(rdev, ring); | 928 | radeon_ring_unlock_commit(rdev, ring, false); |
| 929 | return r; | 929 | return r; |
| 930 | } | 930 | } |
| 931 | 931 | ||
| @@ -958,7 +958,7 @@ void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 958 | RADEON_ISYNC_ANY3D_IDLE2D | | 958 | RADEON_ISYNC_ANY3D_IDLE2D | |
| 959 | RADEON_ISYNC_WAIT_IDLEGUI | | 959 | RADEON_ISYNC_WAIT_IDLEGUI | |
| 960 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | 960 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
| 961 | radeon_ring_unlock_commit(rdev, ring); | 961 | radeon_ring_unlock_commit(rdev, ring, false); |
| 962 | } | 962 | } |
| 963 | 963 | ||
| 964 | 964 | ||
| @@ -3638,7 +3638,7 @@ int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 3638 | } | 3638 | } |
| 3639 | radeon_ring_write(ring, PACKET0(scratch, 0)); | 3639 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
| 3640 | radeon_ring_write(ring, 0xDEADBEEF); | 3640 | radeon_ring_write(ring, 0xDEADBEEF); |
| 3641 | radeon_ring_unlock_commit(rdev, ring); | 3641 | radeon_ring_unlock_commit(rdev, ring, false); |
| 3642 | for (i = 0; i < rdev->usec_timeout; i++) { | 3642 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3643 | tmp = RREG32(scratch); | 3643 | tmp = RREG32(scratch); |
| 3644 | if (tmp == 0xDEADBEEF) { | 3644 | if (tmp == 0xDEADBEEF) { |
| @@ -3700,7 +3700,7 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 3700 | ib.ptr[6] = PACKET2(0); | 3700 | ib.ptr[6] = PACKET2(0); |
| 3701 | ib.ptr[7] = PACKET2(0); | 3701 | ib.ptr[7] = PACKET2(0); |
| 3702 | ib.length_dw = 8; | 3702 | ib.length_dw = 8; |
| 3703 | r = radeon_ib_schedule(rdev, &ib, NULL); | 3703 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 3704 | if (r) { | 3704 | if (r) { |
| 3705 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 3705 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
| 3706 | goto free_ib; | 3706 | goto free_ib; |
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c index 58f0473aa73f..67780374a652 100644 --- a/drivers/gpu/drm/radeon/r200.c +++ b/drivers/gpu/drm/radeon/r200.c | |||
| @@ -121,7 +121,7 @@ int r200_copy_dma(struct radeon_device *rdev, | |||
| 121 | if (fence) { | 121 | if (fence) { |
| 122 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); | 122 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
| 123 | } | 123 | } |
| 124 | radeon_ring_unlock_commit(rdev, ring); | 124 | radeon_ring_unlock_commit(rdev, ring, false); |
| 125 | return r; | 125 | return r; |
| 126 | } | 126 | } |
| 127 | 127 | ||
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 75b30338c226..1bc4704034ce 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
| @@ -295,7 +295,7 @@ void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 295 | radeon_ring_write(ring, | 295 | radeon_ring_write(ring, |
| 296 | R300_GEOMETRY_ROUND_NEAREST | | 296 | R300_GEOMETRY_ROUND_NEAREST | |
| 297 | R300_COLOR_ROUND_NEAREST); | 297 | R300_COLOR_ROUND_NEAREST); |
| 298 | radeon_ring_unlock_commit(rdev, ring); | 298 | radeon_ring_unlock_commit(rdev, ring, false); |
| 299 | } | 299 | } |
| 300 | 300 | ||
| 301 | static void r300_errata(struct radeon_device *rdev) | 301 | static void r300_errata(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 802b19220a21..2828605aef3f 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
| @@ -219,7 +219,7 @@ static void r420_cp_errata_init(struct radeon_device *rdev) | |||
| 219 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); | 219 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
| 220 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); | 220 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
| 221 | radeon_ring_write(ring, 0xDEADBEEF); | 221 | radeon_ring_write(ring, 0xDEADBEEF); |
| 222 | radeon_ring_unlock_commit(rdev, ring); | 222 | radeon_ring_unlock_commit(rdev, ring, false); |
| 223 | } | 223 | } |
| 224 | 224 | ||
| 225 | static void r420_cp_errata_fini(struct radeon_device *rdev) | 225 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
| @@ -232,7 +232,7 @@ static void r420_cp_errata_fini(struct radeon_device *rdev) | |||
| 232 | radeon_ring_lock(rdev, ring, 8); | 232 | radeon_ring_lock(rdev, ring, 8); |
| 233 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | 233 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
| 234 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); | 234 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); |
| 235 | radeon_ring_unlock_commit(rdev, ring); | 235 | radeon_ring_unlock_commit(rdev, ring, false); |
| 236 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); | 236 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
| 237 | } | 237 | } |
| 238 | 238 | ||
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index c70a504d96af..e8bf0ea2dade 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
| @@ -2547,7 +2547,7 @@ int r600_cp_start(struct radeon_device *rdev) | |||
| 2547 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | 2547 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
| 2548 | radeon_ring_write(ring, 0); | 2548 | radeon_ring_write(ring, 0); |
| 2549 | radeon_ring_write(ring, 0); | 2549 | radeon_ring_write(ring, 0); |
| 2550 | radeon_ring_unlock_commit(rdev, ring); | 2550 | radeon_ring_unlock_commit(rdev, ring, false); |
| 2551 | 2551 | ||
| 2552 | cp_me = 0xff; | 2552 | cp_me = 0xff; |
| 2553 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | 2553 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
| @@ -2683,7 +2683,7 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 2683 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 2683 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2684 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | 2684 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
| 2685 | radeon_ring_write(ring, 0xDEADBEEF); | 2685 | radeon_ring_write(ring, 0xDEADBEEF); |
| 2686 | radeon_ring_unlock_commit(rdev, ring); | 2686 | radeon_ring_unlock_commit(rdev, ring, false); |
| 2687 | for (i = 0; i < rdev->usec_timeout; i++) { | 2687 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2688 | tmp = RREG32(scratch); | 2688 | tmp = RREG32(scratch); |
| 2689 | if (tmp == 0xDEADBEEF) | 2689 | if (tmp == 0xDEADBEEF) |
| @@ -2753,6 +2753,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev, | |||
| 2753 | } | 2753 | } |
| 2754 | } | 2754 | } |
| 2755 | 2755 | ||
| 2756 | /** | ||
| 2757 | * r600_semaphore_ring_emit - emit a semaphore on the CP ring | ||
| 2758 | * | ||
| 2759 | * @rdev: radeon_device pointer | ||
| 2760 | * @ring: radeon ring buffer object | ||
| 2761 | * @semaphore: radeon semaphore object | ||
| 2762 | * @emit_wait: Is this a sempahore wait? | ||
| 2763 | * | ||
| 2764 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP | ||
| 2765 | * from running ahead of semaphore waits. | ||
| 2766 | */ | ||
| 2756 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, | 2767 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
| 2757 | struct radeon_ring *ring, | 2768 | struct radeon_ring *ring, |
| 2758 | struct radeon_semaphore *semaphore, | 2769 | struct radeon_semaphore *semaphore, |
| @@ -2768,6 +2779,13 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev, | |||
| 2768 | radeon_ring_write(ring, lower_32_bits(addr)); | 2779 | radeon_ring_write(ring, lower_32_bits(addr)); |
| 2769 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); | 2780 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); |
| 2770 | 2781 | ||
| 2782 | /* PFP_SYNC_ME packet only exists on 7xx+ */ | ||
| 2783 | if (emit_wait && (rdev->family >= CHIP_RV770)) { | ||
| 2784 | /* Prevent the PFP from running ahead of the semaphore wait */ | ||
| 2785 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | ||
| 2786 | radeon_ring_write(ring, 0x0); | ||
| 2787 | } | ||
| 2788 | |||
| 2771 | return true; | 2789 | return true; |
| 2772 | } | 2790 | } |
| 2773 | 2791 | ||
| @@ -2845,7 +2863,7 @@ int r600_copy_cpdma(struct radeon_device *rdev, | |||
| 2845 | return r; | 2863 | return r; |
| 2846 | } | 2864 | } |
| 2847 | 2865 | ||
| 2848 | radeon_ring_unlock_commit(rdev, ring); | 2866 | radeon_ring_unlock_commit(rdev, ring, false); |
| 2849 | radeon_semaphore_free(rdev, &sem, *fence); | 2867 | radeon_semaphore_free(rdev, &sem, *fence); |
| 2850 | 2868 | ||
| 2851 | return r; | 2869 | return r; |
| @@ -3165,7 +3183,7 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 3165 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | 3183 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 3166 | ib.ptr[2] = 0xDEADBEEF; | 3184 | ib.ptr[2] = 0xDEADBEEF; |
| 3167 | ib.length_dw = 3; | 3185 | ib.length_dw = 3; |
| 3168 | r = radeon_ib_schedule(rdev, &ib, NULL); | 3186 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 3169 | if (r) { | 3187 | if (r) { |
| 3170 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 3188 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
| 3171 | goto free_ib; | 3189 | goto free_ib; |
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c index 4969cef44a19..51fd98553eaf 100644 --- a/drivers/gpu/drm/radeon/r600_dma.c +++ b/drivers/gpu/drm/radeon/r600_dma.c | |||
| @@ -261,7 +261,7 @@ int r600_dma_ring_test(struct radeon_device *rdev, | |||
| 261 | radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); | 261 | radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); |
| 262 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); | 262 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); |
| 263 | radeon_ring_write(ring, 0xDEADBEEF); | 263 | radeon_ring_write(ring, 0xDEADBEEF); |
| 264 | radeon_ring_unlock_commit(rdev, ring); | 264 | radeon_ring_unlock_commit(rdev, ring, false); |
| 265 | 265 | ||
| 266 | for (i = 0; i < rdev->usec_timeout; i++) { | 266 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 267 | tmp = readl(ptr); | 267 | tmp = readl(ptr); |
| @@ -368,7 +368,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 368 | ib.ptr[3] = 0xDEADBEEF; | 368 | ib.ptr[3] = 0xDEADBEEF; |
| 369 | ib.length_dw = 4; | 369 | ib.length_dw = 4; |
| 370 | 370 | ||
| 371 | r = radeon_ib_schedule(rdev, &ib, NULL); | 371 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 372 | if (r) { | 372 | if (r) { |
| 373 | radeon_ib_free(rdev, &ib); | 373 | radeon_ib_free(rdev, &ib); |
| 374 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 374 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
| @@ -493,7 +493,7 @@ int r600_copy_dma(struct radeon_device *rdev, | |||
| 493 | return r; | 493 | return r; |
| 494 | } | 494 | } |
| 495 | 495 | ||
| 496 | radeon_ring_unlock_commit(rdev, ring); | 496 | radeon_ring_unlock_commit(rdev, ring, false); |
| 497 | radeon_semaphore_free(rdev, &sem, *fence); | 497 | radeon_semaphore_free(rdev, &sem, *fence); |
| 498 | 498 | ||
| 499 | return r; | 499 | return r; |
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index f94e7a9afe75..0c4a7d8d93e0 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
| @@ -1597,6 +1597,7 @@ | |||
| 1597 | */ | 1597 | */ |
| 1598 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) | 1598 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
| 1599 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) | 1599 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
| 1600 | #define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */ | ||
| 1600 | #define PACKET3_SURFACE_SYNC 0x43 | 1601 | #define PACKET3_SURFACE_SYNC 0x43 |
| 1601 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | 1602 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
| 1602 | # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ | 1603 | # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 9e1732eb402c..b281886f6f51 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
| @@ -105,6 +105,7 @@ extern int radeon_vm_size; | |||
| 105 | extern int radeon_vm_block_size; | 105 | extern int radeon_vm_block_size; |
| 106 | extern int radeon_deep_color; | 106 | extern int radeon_deep_color; |
| 107 | extern int radeon_use_pflipirq; | 107 | extern int radeon_use_pflipirq; |
| 108 | extern int radeon_bapm; | ||
| 108 | 109 | ||
| 109 | /* | 110 | /* |
| 110 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | 111 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| @@ -967,7 +968,7 @@ int radeon_ib_get(struct radeon_device *rdev, int ring, | |||
| 967 | unsigned size); | 968 | unsigned size); |
| 968 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); | 969 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
| 969 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, | 970 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
| 970 | struct radeon_ib *const_ib); | 971 | struct radeon_ib *const_ib, bool hdp_flush); |
| 971 | int radeon_ib_pool_init(struct radeon_device *rdev); | 972 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 972 | void radeon_ib_pool_fini(struct radeon_device *rdev); | 973 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
| 973 | int radeon_ib_ring_tests(struct radeon_device *rdev); | 974 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
| @@ -977,8 +978,10 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, | |||
| 977 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); | 978 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
| 978 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | 979 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 979 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | 980 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 980 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | 981 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
| 981 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | 982 | bool hdp_flush); |
| 983 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, | ||
| 984 | bool hdp_flush); | ||
| 982 | void radeon_ring_undo(struct radeon_ring *ring); | 985 | void radeon_ring_undo(struct radeon_ring *ring); |
| 983 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); | 986 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
| 984 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | 987 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index ee712c199b25..83f382e8e40e 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c | |||
| @@ -132,7 +132,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) | |||
| 132 | * the buffers used for read only, which doubles the range | 132 | * the buffers used for read only, which doubles the range |
| 133 | * to 0 to 31. 32 is reserved for the kernel driver. | 133 | * to 0 to 31. 32 is reserved for the kernel driver. |
| 134 | */ | 134 | */ |
| 135 | priority = (r->flags & 0xf) * 2 + !!r->write_domain; | 135 | priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2 |
| 136 | + !!r->write_domain; | ||
| 136 | 137 | ||
| 137 | /* the first reloc of an UVD job is the msg and that must be in | 138 | /* the first reloc of an UVD job is the msg and that must be in |
| 138 | VRAM, also but everything into VRAM on AGP cards to avoid | 139 | VRAM, also but everything into VRAM on AGP cards to avoid |
| @@ -450,7 +451,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev, | |||
| 450 | radeon_vce_note_usage(rdev); | 451 | radeon_vce_note_usage(rdev); |
| 451 | 452 | ||
| 452 | radeon_cs_sync_rings(parser); | 453 | radeon_cs_sync_rings(parser); |
| 453 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | 454 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
| 454 | if (r) { | 455 | if (r) { |
| 455 | DRM_ERROR("Failed to schedule IB !\n"); | 456 | DRM_ERROR("Failed to schedule IB !\n"); |
| 456 | } | 457 | } |
| @@ -541,9 +542,9 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |||
| 541 | 542 | ||
| 542 | if ((rdev->family >= CHIP_TAHITI) && | 543 | if ((rdev->family >= CHIP_TAHITI) && |
| 543 | (parser->chunk_const_ib_idx != -1)) { | 544 | (parser->chunk_const_ib_idx != -1)) { |
| 544 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); | 545 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true); |
| 545 | } else { | 546 | } else { |
| 546 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | 547 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
| 547 | } | 548 | } |
| 548 | 549 | ||
| 549 | out: | 550 | out: |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index c8ea050c8fa4..6a219bcee66d 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
| @@ -1680,8 +1680,8 @@ int radeon_gpu_reset(struct radeon_device *rdev) | |||
| 1680 | radeon_save_bios_scratch_regs(rdev); | 1680 | radeon_save_bios_scratch_regs(rdev); |
| 1681 | /* block TTM */ | 1681 | /* block TTM */ |
| 1682 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); | 1682 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
| 1683 | radeon_pm_suspend(rdev); | ||
| 1684 | radeon_suspend(rdev); | 1683 | radeon_suspend(rdev); |
| 1684 | radeon_hpd_fini(rdev); | ||
| 1685 | 1685 | ||
| 1686 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | 1686 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 1687 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], | 1687 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
| @@ -1726,9 +1726,39 @@ retry: | |||
| 1726 | } | 1726 | } |
| 1727 | } | 1727 | } |
| 1728 | 1728 | ||
| 1729 | radeon_pm_resume(rdev); | 1729 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
| 1730 | /* do dpm late init */ | ||
| 1731 | r = radeon_pm_late_init(rdev); | ||
| 1732 | if (r) { | ||
| 1733 | rdev->pm.dpm_enabled = false; | ||
| 1734 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); | ||
| 1735 | } | ||
| 1736 | } else { | ||
| 1737 | /* resume old pm late */ | ||
| 1738 | radeon_pm_resume(rdev); | ||
| 1739 | } | ||
| 1740 | |||
| 1741 | /* init dig PHYs, disp eng pll */ | ||
| 1742 | if (rdev->is_atom_bios) { | ||
| 1743 | radeon_atom_encoder_init(rdev); | ||
| 1744 | radeon_atom_disp_eng_pll_init(rdev); | ||
| 1745 | /* turn on the BL */ | ||
| 1746 | if (rdev->mode_info.bl_encoder) { | ||
| 1747 | u8 bl_level = radeon_get_backlight_level(rdev, | ||
| 1748 | rdev->mode_info.bl_encoder); | ||
| 1749 | radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, | ||
| 1750 | bl_level); | ||
| 1751 | } | ||
| 1752 | } | ||
| 1753 | /* reset hpd state */ | ||
| 1754 | radeon_hpd_init(rdev); | ||
| 1755 | |||
| 1730 | drm_helper_resume_force_mode(rdev->ddev); | 1756 | drm_helper_resume_force_mode(rdev->ddev); |
| 1731 | 1757 | ||
| 1758 | /* set the power state here in case we are a PX system or headless */ | ||
| 1759 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) | ||
| 1760 | radeon_pm_compute_clocks(rdev); | ||
| 1761 | |||
| 1732 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); | 1762 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
| 1733 | if (r) { | 1763 | if (r) { |
| 1734 | /* bad news, how to tell it to userspace ? */ | 1764 | /* bad news, how to tell it to userspace ? */ |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 092d067f93e1..8df888908833 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
| @@ -180,6 +180,7 @@ int radeon_vm_size = 8; | |||
| 180 | int radeon_vm_block_size = -1; | 180 | int radeon_vm_block_size = -1; |
| 181 | int radeon_deep_color = 0; | 181 | int radeon_deep_color = 0; |
| 182 | int radeon_use_pflipirq = 2; | 182 | int radeon_use_pflipirq = 2; |
| 183 | int radeon_bapm = -1; | ||
| 183 | 184 | ||
| 184 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); | 185 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
| 185 | module_param_named(no_wb, radeon_no_wb, int, 0444); | 186 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
| @@ -259,6 +260,9 @@ module_param_named(deep_color, radeon_deep_color, int, 0444); | |||
| 259 | MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); | 260 | MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); |
| 260 | module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); | 261 | module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); |
| 261 | 262 | ||
| 263 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); | ||
| 264 | module_param_named(bapm, radeon_bapm, int, 0444); | ||
| 265 | |||
| 262 | static struct pci_device_id pciidlist[] = { | 266 | static struct pci_device_id pciidlist[] = { |
| 263 | radeon_PCI_IDS | 267 | radeon_PCI_IDS |
| 264 | }; | 268 | }; |
diff --git a/drivers/gpu/drm/radeon/radeon_ib.c b/drivers/gpu/drm/radeon/radeon_ib.c index 65b0c213488d..5bf2c0a05827 100644 --- a/drivers/gpu/drm/radeon/radeon_ib.c +++ b/drivers/gpu/drm/radeon/radeon_ib.c | |||
| @@ -107,6 +107,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) | |||
| 107 | * @rdev: radeon_device pointer | 107 | * @rdev: radeon_device pointer |
| 108 | * @ib: IB object to schedule | 108 | * @ib: IB object to schedule |
| 109 | * @const_ib: Const IB to schedule (SI only) | 109 | * @const_ib: Const IB to schedule (SI only) |
| 110 | * @hdp_flush: Whether or not to perform an HDP cache flush | ||
| 110 | * | 111 | * |
| 111 | * Schedule an IB on the associated ring (all asics). | 112 | * Schedule an IB on the associated ring (all asics). |
| 112 | * Returns 0 on success, error on failure. | 113 | * Returns 0 on success, error on failure. |
| @@ -122,7 +123,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) | |||
| 122 | * to SI there was just a DE IB. | 123 | * to SI there was just a DE IB. |
| 123 | */ | 124 | */ |
| 124 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, | 125 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
| 125 | struct radeon_ib *const_ib) | 126 | struct radeon_ib *const_ib, bool hdp_flush) |
| 126 | { | 127 | { |
| 127 | struct radeon_ring *ring = &rdev->ring[ib->ring]; | 128 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
| 128 | int r = 0; | 129 | int r = 0; |
| @@ -176,7 +177,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, | |||
| 176 | if (ib->vm) | 177 | if (ib->vm) |
| 177 | radeon_vm_fence(rdev, ib->vm, ib->fence); | 178 | radeon_vm_fence(rdev, ib->vm, ib->fence); |
| 178 | 179 | ||
| 179 | radeon_ring_unlock_commit(rdev, ring); | 180 | radeon_ring_unlock_commit(rdev, ring, hdp_flush); |
| 180 | return 0; | 181 | return 0; |
| 181 | } | 182 | } |
| 182 | 183 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 23314be49480..164898b0010c 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c | |||
| @@ -460,10 +460,6 @@ static ssize_t radeon_get_dpm_state(struct device *dev, | |||
| 460 | struct radeon_device *rdev = ddev->dev_private; | 460 | struct radeon_device *rdev = ddev->dev_private; |
| 461 | enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; | 461 | enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; |
| 462 | 462 | ||
| 463 | if ((rdev->flags & RADEON_IS_PX) && | ||
| 464 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) | ||
| 465 | return snprintf(buf, PAGE_SIZE, "off\n"); | ||
| 466 | |||
| 467 | return snprintf(buf, PAGE_SIZE, "%s\n", | 463 | return snprintf(buf, PAGE_SIZE, "%s\n", |
| 468 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : | 464 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : |
| 469 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); | 465 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); |
| @@ -477,11 +473,6 @@ static ssize_t radeon_set_dpm_state(struct device *dev, | |||
| 477 | struct drm_device *ddev = dev_get_drvdata(dev); | 473 | struct drm_device *ddev = dev_get_drvdata(dev); |
| 478 | struct radeon_device *rdev = ddev->dev_private; | 474 | struct radeon_device *rdev = ddev->dev_private; |
| 479 | 475 | ||
| 480 | /* Can't set dpm state when the card is off */ | ||
| 481 | if ((rdev->flags & RADEON_IS_PX) && | ||
| 482 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) | ||
| 483 | return -EINVAL; | ||
| 484 | |||
| 485 | mutex_lock(&rdev->pm.mutex); | 476 | mutex_lock(&rdev->pm.mutex); |
| 486 | if (strncmp("battery", buf, strlen("battery")) == 0) | 477 | if (strncmp("battery", buf, strlen("battery")) == 0) |
| 487 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; | 478 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; |
| @@ -495,7 +486,12 @@ static ssize_t radeon_set_dpm_state(struct device *dev, | |||
| 495 | goto fail; | 486 | goto fail; |
| 496 | } | 487 | } |
| 497 | mutex_unlock(&rdev->pm.mutex); | 488 | mutex_unlock(&rdev->pm.mutex); |
| 498 | radeon_pm_compute_clocks(rdev); | 489 | |
| 490 | /* Can't set dpm state when the card is off */ | ||
| 491 | if (!(rdev->flags & RADEON_IS_PX) || | ||
| 492 | (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) | ||
| 493 | radeon_pm_compute_clocks(rdev); | ||
| 494 | |||
| 499 | fail: | 495 | fail: |
| 500 | return count; | 496 | return count; |
| 501 | } | 497 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 5b4e0cf231a0..d65607902537 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c | |||
| @@ -177,16 +177,18 @@ int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsig | |||
| 177 | * | 177 | * |
| 178 | * @rdev: radeon_device pointer | 178 | * @rdev: radeon_device pointer |
| 179 | * @ring: radeon_ring structure holding ring information | 179 | * @ring: radeon_ring structure holding ring information |
| 180 | * @hdp_flush: Whether or not to perform an HDP cache flush | ||
| 180 | * | 181 | * |
| 181 | * Update the wptr (write pointer) to tell the GPU to | 182 | * Update the wptr (write pointer) to tell the GPU to |
| 182 | * execute new commands on the ring buffer (all asics). | 183 | * execute new commands on the ring buffer (all asics). |
| 183 | */ | 184 | */ |
| 184 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) | 185 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
| 186 | bool hdp_flush) | ||
| 185 | { | 187 | { |
| 186 | /* If we are emitting the HDP flush via the ring buffer, we need to | 188 | /* If we are emitting the HDP flush via the ring buffer, we need to |
| 187 | * do it before padding. | 189 | * do it before padding. |
| 188 | */ | 190 | */ |
| 189 | if (rdev->asic->ring[ring->idx]->hdp_flush) | 191 | if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush) |
| 190 | rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); | 192 | rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); |
| 191 | /* We pad to match fetch size */ | 193 | /* We pad to match fetch size */ |
| 192 | while (ring->wptr & ring->align_mask) { | 194 | while (ring->wptr & ring->align_mask) { |
| @@ -196,7 +198,7 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 196 | /* If we are emitting the HDP flush via MMIO, we need to do it after | 198 | /* If we are emitting the HDP flush via MMIO, we need to do it after |
| 197 | * all CPU writes to VRAM finished. | 199 | * all CPU writes to VRAM finished. |
| 198 | */ | 200 | */ |
| 199 | if (rdev->asic->mmio_hdp_flush) | 201 | if (hdp_flush && rdev->asic->mmio_hdp_flush) |
| 200 | rdev->asic->mmio_hdp_flush(rdev); | 202 | rdev->asic->mmio_hdp_flush(rdev); |
| 201 | radeon_ring_set_wptr(rdev, ring); | 203 | radeon_ring_set_wptr(rdev, ring); |
| 202 | } | 204 | } |
| @@ -207,12 +209,14 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 207 | * | 209 | * |
| 208 | * @rdev: radeon_device pointer | 210 | * @rdev: radeon_device pointer |
| 209 | * @ring: radeon_ring structure holding ring information | 211 | * @ring: radeon_ring structure holding ring information |
| 212 | * @hdp_flush: Whether or not to perform an HDP cache flush | ||
| 210 | * | 213 | * |
| 211 | * Call radeon_ring_commit() then unlock the ring (all asics). | 214 | * Call radeon_ring_commit() then unlock the ring (all asics). |
| 212 | */ | 215 | */ |
| 213 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) | 216 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
| 217 | bool hdp_flush) | ||
| 214 | { | 218 | { |
| 215 | radeon_ring_commit(rdev, ring); | 219 | radeon_ring_commit(rdev, ring, hdp_flush); |
| 216 | mutex_unlock(&rdev->ring_lock); | 220 | mutex_unlock(&rdev->ring_lock); |
| 217 | } | 221 | } |
| 218 | 222 | ||
| @@ -372,7 +376,7 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |||
| 372 | radeon_ring_write(ring, data[i]); | 376 | radeon_ring_write(ring, data[i]); |
| 373 | } | 377 | } |
| 374 | 378 | ||
| 375 | radeon_ring_unlock_commit(rdev, ring); | 379 | radeon_ring_unlock_commit(rdev, ring, false); |
| 376 | kfree(data); | 380 | kfree(data); |
| 377 | return 0; | 381 | return 0; |
| 378 | } | 382 | } |
| @@ -400,9 +404,7 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig | |||
| 400 | /* Allocate ring buffer */ | 404 | /* Allocate ring buffer */ |
| 401 | if (ring->ring_obj == NULL) { | 405 | if (ring->ring_obj == NULL) { |
| 402 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | 406 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
| 403 | RADEON_GEM_DOMAIN_GTT, | 407 | RADEON_GEM_DOMAIN_GTT, 0, |
| 404 | (rdev->flags & RADEON_IS_PCIE) ? | ||
| 405 | RADEON_GEM_GTT_WC : 0, | ||
| 406 | NULL, &ring->ring_obj); | 408 | NULL, &ring->ring_obj); |
| 407 | if (r) { | 409 | if (r) { |
| 408 | dev_err(rdev->dev, "(%d) ring create failed\n", r); | 410 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c index dbd6bcde92de..56d9fd66d8ae 100644 --- a/drivers/gpu/drm/radeon/radeon_semaphore.c +++ b/drivers/gpu/drm/radeon/radeon_semaphore.c | |||
| @@ -179,7 +179,7 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev, | |||
| 179 | continue; | 179 | continue; |
| 180 | } | 180 | } |
| 181 | 181 | ||
| 182 | radeon_ring_commit(rdev, &rdev->ring[i]); | 182 | radeon_ring_commit(rdev, &rdev->ring[i], false); |
| 183 | radeon_fence_note_sync(fence, ring); | 183 | radeon_fence_note_sync(fence, ring); |
| 184 | 184 | ||
| 185 | semaphore->gpu_addr += 8; | 185 | semaphore->gpu_addr += 8; |
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c index 5adf4207453d..17bc3dced9f1 100644 --- a/drivers/gpu/drm/radeon/radeon_test.c +++ b/drivers/gpu/drm/radeon/radeon_test.c | |||
| @@ -288,7 +288,7 @@ static int radeon_test_create_and_emit_fence(struct radeon_device *rdev, | |||
| 288 | return r; | 288 | return r; |
| 289 | } | 289 | } |
| 290 | radeon_fence_emit(rdev, fence, ring->idx); | 290 | radeon_fence_emit(rdev, fence, ring->idx); |
| 291 | radeon_ring_unlock_commit(rdev, ring); | 291 | radeon_ring_unlock_commit(rdev, ring, false); |
| 292 | } | 292 | } |
| 293 | return 0; | 293 | return 0; |
| 294 | } | 294 | } |
| @@ -313,7 +313,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
| 313 | goto out_cleanup; | 313 | goto out_cleanup; |
| 314 | } | 314 | } |
| 315 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); | 315 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
| 316 | radeon_ring_unlock_commit(rdev, ringA); | 316 | radeon_ring_unlock_commit(rdev, ringA, false); |
| 317 | 317 | ||
| 318 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1); | 318 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1); |
| 319 | if (r) | 319 | if (r) |
| @@ -325,7 +325,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
| 325 | goto out_cleanup; | 325 | goto out_cleanup; |
| 326 | } | 326 | } |
| 327 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); | 327 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
| 328 | radeon_ring_unlock_commit(rdev, ringA); | 328 | radeon_ring_unlock_commit(rdev, ringA, false); |
| 329 | 329 | ||
| 330 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2); | 330 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2); |
| 331 | if (r) | 331 | if (r) |
| @@ -344,7 +344,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
| 344 | goto out_cleanup; | 344 | goto out_cleanup; |
| 345 | } | 345 | } |
| 346 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); | 346 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); |
| 347 | radeon_ring_unlock_commit(rdev, ringB); | 347 | radeon_ring_unlock_commit(rdev, ringB, false); |
| 348 | 348 | ||
| 349 | r = radeon_fence_wait(fence1, false); | 349 | r = radeon_fence_wait(fence1, false); |
| 350 | if (r) { | 350 | if (r) { |
| @@ -365,7 +365,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
| 365 | goto out_cleanup; | 365 | goto out_cleanup; |
| 366 | } | 366 | } |
| 367 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); | 367 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); |
| 368 | radeon_ring_unlock_commit(rdev, ringB); | 368 | radeon_ring_unlock_commit(rdev, ringB, false); |
| 369 | 369 | ||
| 370 | r = radeon_fence_wait(fence2, false); | 370 | r = radeon_fence_wait(fence2, false); |
| 371 | if (r) { | 371 | if (r) { |
| @@ -408,7 +408,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
| 408 | goto out_cleanup; | 408 | goto out_cleanup; |
| 409 | } | 409 | } |
| 410 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); | 410 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
| 411 | radeon_ring_unlock_commit(rdev, ringA); | 411 | radeon_ring_unlock_commit(rdev, ringA, false); |
| 412 | 412 | ||
| 413 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA); | 413 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA); |
| 414 | if (r) | 414 | if (r) |
| @@ -420,7 +420,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
| 420 | goto out_cleanup; | 420 | goto out_cleanup; |
| 421 | } | 421 | } |
| 422 | radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore); | 422 | radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore); |
| 423 | radeon_ring_unlock_commit(rdev, ringB); | 423 | radeon_ring_unlock_commit(rdev, ringB, false); |
| 424 | r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB); | 424 | r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB); |
| 425 | if (r) | 425 | if (r) |
| 426 | goto out_cleanup; | 426 | goto out_cleanup; |
| @@ -442,7 +442,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
| 442 | goto out_cleanup; | 442 | goto out_cleanup; |
| 443 | } | 443 | } |
| 444 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); | 444 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); |
| 445 | radeon_ring_unlock_commit(rdev, ringC); | 445 | radeon_ring_unlock_commit(rdev, ringC, false); |
| 446 | 446 | ||
| 447 | for (i = 0; i < 30; ++i) { | 447 | for (i = 0; i < 30; ++i) { |
| 448 | mdelay(100); | 448 | mdelay(100); |
| @@ -468,7 +468,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
| 468 | goto out_cleanup; | 468 | goto out_cleanup; |
| 469 | } | 469 | } |
| 470 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); | 470 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); |
| 471 | radeon_ring_unlock_commit(rdev, ringC); | 471 | radeon_ring_unlock_commit(rdev, ringC, false); |
| 472 | 472 | ||
| 473 | mdelay(1000); | 473 | mdelay(1000); |
| 474 | 474 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 6bf55ec85b62..341848a14376 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c | |||
| @@ -646,7 +646,7 @@ static int radeon_uvd_send_msg(struct radeon_device *rdev, | |||
| 646 | ib.ptr[i] = PACKET2(0); | 646 | ib.ptr[i] = PACKET2(0); |
| 647 | ib.length_dw = 16; | 647 | ib.length_dw = 16; |
| 648 | 648 | ||
| 649 | r = radeon_ib_schedule(rdev, &ib, NULL); | 649 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 650 | if (r) | 650 | if (r) |
| 651 | goto err; | 651 | goto err; |
| 652 | ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence); | 652 | ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence); |
diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index f9b70a43aa52..c7190aadbd89 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c | |||
| @@ -368,7 +368,7 @@ int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, | |||
| 368 | for (i = ib.length_dw; i < ib_size_dw; ++i) | 368 | for (i = ib.length_dw; i < ib_size_dw; ++i) |
| 369 | ib.ptr[i] = 0x0; | 369 | ib.ptr[i] = 0x0; |
| 370 | 370 | ||
| 371 | r = radeon_ib_schedule(rdev, &ib, NULL); | 371 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 372 | if (r) { | 372 | if (r) { |
| 373 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 373 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
| 374 | } | 374 | } |
| @@ -425,7 +425,7 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, | |||
| 425 | for (i = ib.length_dw; i < ib_size_dw; ++i) | 425 | for (i = ib.length_dw; i < ib_size_dw; ++i) |
| 426 | ib.ptr[i] = 0x0; | 426 | ib.ptr[i] = 0x0; |
| 427 | 427 | ||
| 428 | r = radeon_ib_schedule(rdev, &ib, NULL); | 428 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 429 | if (r) { | 429 | if (r) { |
| 430 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 430 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
| 431 | } | 431 | } |
| @@ -715,7 +715,7 @@ int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 715 | return r; | 715 | return r; |
| 716 | } | 716 | } |
| 717 | radeon_ring_write(ring, VCE_CMD_END); | 717 | radeon_ring_write(ring, VCE_CMD_END); |
| 718 | radeon_ring_unlock_commit(rdev, ring); | 718 | radeon_ring_unlock_commit(rdev, ring, false); |
| 719 | 719 | ||
| 720 | for (i = 0; i < rdev->usec_timeout; i++) { | 720 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 721 | if (vce_v1_0_get_rptr(rdev, ring) != rptr) | 721 | if (vce_v1_0_get_rptr(rdev, ring) != rptr) |
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index ccae4d9dc3de..088ffdc2f577 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c | |||
| @@ -420,7 +420,7 @@ static int radeon_vm_clear_bo(struct radeon_device *rdev, | |||
| 420 | radeon_asic_vm_pad_ib(rdev, &ib); | 420 | radeon_asic_vm_pad_ib(rdev, &ib); |
| 421 | WARN_ON(ib.length_dw > 64); | 421 | WARN_ON(ib.length_dw > 64); |
| 422 | 422 | ||
| 423 | r = radeon_ib_schedule(rdev, &ib, NULL); | 423 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 424 | if (r) | 424 | if (r) |
| 425 | goto error; | 425 | goto error; |
| 426 | 426 | ||
| @@ -483,6 +483,10 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |||
| 483 | /* add a clone of the bo_va to clear the old address */ | 483 | /* add a clone of the bo_va to clear the old address */ |
| 484 | struct radeon_bo_va *tmp; | 484 | struct radeon_bo_va *tmp; |
| 485 | tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); | 485 | tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); |
| 486 | if (!tmp) { | ||
| 487 | mutex_unlock(&vm->mutex); | ||
| 488 | return -ENOMEM; | ||
| 489 | } | ||
| 486 | tmp->it.start = bo_va->it.start; | 490 | tmp->it.start = bo_va->it.start; |
| 487 | tmp->it.last = bo_va->it.last; | 491 | tmp->it.last = bo_va->it.last; |
| 488 | tmp->vm = vm; | 492 | tmp->vm = vm; |
| @@ -693,7 +697,7 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev, | |||
| 693 | radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj); | 697 | radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj); |
| 694 | radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use); | 698 | radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use); |
| 695 | WARN_ON(ib.length_dw > ndw); | 699 | WARN_ON(ib.length_dw > ndw); |
| 696 | r = radeon_ib_schedule(rdev, &ib, NULL); | 700 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 697 | if (r) { | 701 | if (r) { |
| 698 | radeon_ib_free(rdev, &ib); | 702 | radeon_ib_free(rdev, &ib); |
| 699 | return r; | 703 | return r; |
| @@ -957,7 +961,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev, | |||
| 957 | WARN_ON(ib.length_dw > ndw); | 961 | WARN_ON(ib.length_dw > ndw); |
| 958 | 962 | ||
| 959 | radeon_semaphore_sync_to(ib.semaphore, vm->fence); | 963 | radeon_semaphore_sync_to(ib.semaphore, vm->fence); |
| 960 | r = radeon_ib_schedule(rdev, &ib, NULL); | 964 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
| 961 | if (r) { | 965 | if (r) { |
| 962 | radeon_ib_free(rdev, &ib); | 966 | radeon_ib_free(rdev, &ib); |
| 963 | return r; | 967 | return r; |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 3e21e869015f..8a477bf1fdb3 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
| @@ -124,7 +124,7 @@ void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); | 124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
| 125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); | 125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
| 126 | radeon_ring_write(ring, 0); | 126 | radeon_ring_write(ring, 0); |
| 127 | radeon_ring_unlock_commit(rdev, ring); | 127 | radeon_ring_unlock_commit(rdev, ring, false); |
| 128 | } | 128 | } |
| 129 | 129 | ||
| 130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) | 130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/rv770_dma.c b/drivers/gpu/drm/radeon/rv770_dma.c index bbf2e076ee45..74426ac2bb5c 100644 --- a/drivers/gpu/drm/radeon/rv770_dma.c +++ b/drivers/gpu/drm/radeon/rv770_dma.c | |||
| @@ -90,7 +90,7 @@ int rv770_copy_dma(struct radeon_device *rdev, | |||
| 90 | return r; | 90 | return r; |
| 91 | } | 91 | } |
| 92 | 92 | ||
| 93 | radeon_ring_unlock_commit(rdev, ring); | 93 | radeon_ring_unlock_commit(rdev, ring, false); |
| 94 | radeon_semaphore_free(rdev, &sem, *fence); | 94 | radeon_semaphore_free(rdev, &sem, *fence); |
| 95 | 95 | ||
| 96 | return r; | 96 | return r; |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 011779bd2b3d..a1274a31405c 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
| @@ -3057,7 +3057,7 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
| 3057 | u32 sx_debug_1; | 3057 | u32 sx_debug_1; |
| 3058 | u32 hdp_host_path_cntl; | 3058 | u32 hdp_host_path_cntl; |
| 3059 | u32 tmp; | 3059 | u32 tmp; |
| 3060 | int i, j, k; | 3060 | int i, j; |
| 3061 | 3061 | ||
| 3062 | switch (rdev->family) { | 3062 | switch (rdev->family) { |
| 3063 | case CHIP_TAHITI: | 3063 | case CHIP_TAHITI: |
| @@ -3255,12 +3255,11 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
| 3255 | rdev->config.si.max_sh_per_se, | 3255 | rdev->config.si.max_sh_per_se, |
| 3256 | rdev->config.si.max_cu_per_sh); | 3256 | rdev->config.si.max_cu_per_sh); |
| 3257 | 3257 | ||
| 3258 | rdev->config.si.active_cus = 0; | ||
| 3258 | for (i = 0; i < rdev->config.si.max_shader_engines; i++) { | 3259 | for (i = 0; i < rdev->config.si.max_shader_engines; i++) { |
| 3259 | for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { | 3260 | for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { |
| 3260 | for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { | 3261 | rdev->config.si.active_cus += |
| 3261 | rdev->config.si.active_cus += | 3262 | hweight32(si_get_cu_active_bitmap(rdev, i, j)); |
| 3262 | hweight32(si_get_cu_active_bitmap(rdev, i, j)); | ||
| 3263 | } | ||
| 3264 | } | 3263 | } |
| 3265 | } | 3264 | } |
| 3266 | 3265 | ||
| @@ -3541,7 +3540,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
| 3541 | radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); | 3540 | radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); |
| 3542 | radeon_ring_write(ring, 0xc000); | 3541 | radeon_ring_write(ring, 0xc000); |
| 3543 | radeon_ring_write(ring, 0xe000); | 3542 | radeon_ring_write(ring, 0xe000); |
| 3544 | radeon_ring_unlock_commit(rdev, ring); | 3543 | radeon_ring_unlock_commit(rdev, ring, false); |
| 3545 | 3544 | ||
| 3546 | si_cp_enable(rdev, true); | 3545 | si_cp_enable(rdev, true); |
| 3547 | 3546 | ||
| @@ -3570,7 +3569,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
| 3570 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 3569 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
| 3571 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ | 3570 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ |
| 3572 | 3571 | ||
| 3573 | radeon_ring_unlock_commit(rdev, ring); | 3572 | radeon_ring_unlock_commit(rdev, ring, false); |
| 3574 | 3573 | ||
| 3575 | for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { | 3574 | for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { |
| 3576 | ring = &rdev->ring[i]; | 3575 | ring = &rdev->ring[i]; |
| @@ -3580,7 +3579,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
| 3580 | radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); | 3579 | radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); |
| 3581 | radeon_ring_write(ring, 0); | 3580 | radeon_ring_write(ring, 0); |
| 3582 | 3581 | ||
| 3583 | radeon_ring_unlock_commit(rdev, ring); | 3582 | radeon_ring_unlock_commit(rdev, ring, false); |
| 3584 | } | 3583 | } |
| 3585 | 3584 | ||
| 3586 | return 0; | 3585 | return 0; |
| @@ -5028,7 +5027,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
| 5028 | 5027 | ||
| 5029 | /* flush hdp cache */ | 5028 | /* flush hdp cache */ |
| 5030 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5029 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 5031 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5030 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
| 5032 | WRITE_DATA_DST_SEL(0))); | 5031 | WRITE_DATA_DST_SEL(0))); |
| 5033 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); | 5032 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); |
| 5034 | radeon_ring_write(ring, 0); | 5033 | radeon_ring_write(ring, 0); |
| @@ -5036,7 +5035,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
| 5036 | 5035 | ||
| 5037 | /* bits 0-15 are the VM contexts0-15 */ | 5036 | /* bits 0-15 are the VM contexts0-15 */ |
| 5038 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5037 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 5039 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5038 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
| 5040 | WRITE_DATA_DST_SEL(0))); | 5039 | WRITE_DATA_DST_SEL(0))); |
| 5041 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 5040 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
| 5042 | radeon_ring_write(ring, 0); | 5041 | radeon_ring_write(ring, 0); |
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c index 716505129450..7c22baaf94db 100644 --- a/drivers/gpu/drm/radeon/si_dma.c +++ b/drivers/gpu/drm/radeon/si_dma.c | |||
| @@ -275,7 +275,7 @@ int si_copy_dma(struct radeon_device *rdev, | |||
| 275 | return r; | 275 | return r; |
| 276 | } | 276 | } |
| 277 | 277 | ||
| 278 | radeon_ring_unlock_commit(rdev, ring); | 278 | radeon_ring_unlock_commit(rdev, ring, false); |
| 279 | radeon_semaphore_free(rdev, &sem, *fence); | 279 | radeon_semaphore_free(rdev, &sem, *fence); |
| 280 | 280 | ||
| 281 | return r; | 281 | return r; |
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index 32e50be9c4ac..57f780053b3e 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c | |||
| @@ -1874,16 +1874,22 @@ int trinity_dpm_init(struct radeon_device *rdev) | |||
| 1874 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) | 1874 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) |
| 1875 | pi->at[i] = TRINITY_AT_DFLT; | 1875 | pi->at[i] = TRINITY_AT_DFLT; |
| 1876 | 1876 | ||
| 1877 | /* There are stability issues reported on with | 1877 | if (radeon_bapm == -1) { |
| 1878 | * bapm enabled when switching between AC and battery | 1878 | /* There are stability issues reported on with |
| 1879 | * power. At the same time, some MSI boards hang | 1879 | * bapm enabled when switching between AC and battery |
| 1880 | * if it's not enabled and dpm is enabled. Just enable | 1880 | * power. At the same time, some MSI boards hang |
| 1881 | * it for MSI boards right now. | 1881 | * if it's not enabled and dpm is enabled. Just enable |
| 1882 | */ | 1882 | * it for MSI boards right now. |
| 1883 | if (rdev->pdev->subsystem_vendor == 0x1462) | 1883 | */ |
| 1884 | pi->enable_bapm = true; | 1884 | if (rdev->pdev->subsystem_vendor == 0x1462) |
| 1885 | else | 1885 | pi->enable_bapm = true; |
| 1886 | else | ||
| 1887 | pi->enable_bapm = false; | ||
| 1888 | } else if (radeon_bapm == 0) { | ||
| 1886 | pi->enable_bapm = false; | 1889 | pi->enable_bapm = false; |
| 1890 | } else { | ||
| 1891 | pi->enable_bapm = true; | ||
| 1892 | } | ||
| 1887 | pi->enable_nbps_policy = true; | 1893 | pi->enable_nbps_policy = true; |
| 1888 | pi->enable_sclk_ds = true; | 1894 | pi->enable_sclk_ds = true; |
| 1889 | pi->enable_gfx_power_gating = true; | 1895 | pi->enable_gfx_power_gating = true; |
diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c index be42c8125203..cda391347286 100644 --- a/drivers/gpu/drm/radeon/uvd_v1_0.c +++ b/drivers/gpu/drm/radeon/uvd_v1_0.c | |||
| @@ -124,7 +124,7 @@ int uvd_v1_0_init(struct radeon_device *rdev) | |||
| 124 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); | 124 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); |
| 125 | radeon_ring_write(ring, 3); | 125 | radeon_ring_write(ring, 3); |
| 126 | 126 | ||
| 127 | radeon_ring_unlock_commit(rdev, ring); | 127 | radeon_ring_unlock_commit(rdev, ring, false); |
| 128 | 128 | ||
| 129 | done: | 129 | done: |
| 130 | /* lower clocks again */ | 130 | /* lower clocks again */ |
| @@ -331,7 +331,7 @@ int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
| 331 | } | 331 | } |
| 332 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); | 332 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); |
| 333 | radeon_ring_write(ring, 0xDEADBEEF); | 333 | radeon_ring_write(ring, 0xDEADBEEF); |
| 334 | radeon_ring_unlock_commit(rdev, ring); | 334 | radeon_ring_unlock_commit(rdev, ring, false); |
| 335 | for (i = 0; i < rdev->usec_timeout; i++) { | 335 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 336 | tmp = RREG32(UVD_CONTEXT_ID); | 336 | tmp = RREG32(UVD_CONTEXT_ID); |
| 337 | if (tmp == 0xDEADBEEF) | 337 | if (tmp == 0xDEADBEEF) |
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index 6dfd64b3a604..e973540cd15b 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ | 17 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| 18 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ | 18 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| 19 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ | 19 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| 20 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ | ||
| 20 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ | 21 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| 21 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ | 22 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| 22 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ | 23 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| @@ -164,8 +165,11 @@ | |||
| 164 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 165 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 165 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 166 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 166 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 167 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 168 | {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
| 169 | {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
| 167 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 170 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 168 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 171 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 172 | {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | ||
| 169 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | 173 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ |
| 170 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | 174 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ |
| 171 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | 175 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ |
| @@ -175,6 +179,8 @@ | |||
| 175 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | 179 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ |
| 176 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 180 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 177 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 181 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 182 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
| 183 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
| 178 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \ | 184 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \ |
| 179 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \ | 185 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \ |
| 180 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \ | 186 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \ |
| @@ -297,6 +303,7 @@ | |||
| 297 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ | 303 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
| 298 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 304 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 299 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 305 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 306 | {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ | ||
| 300 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 307 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 301 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 308 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| 302 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 309 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h index 509b2d7a41b7..fea6099608ef 100644 --- a/include/uapi/drm/radeon_drm.h +++ b/include/uapi/drm/radeon_drm.h | |||
| @@ -944,6 +944,7 @@ struct drm_radeon_cs_chunk { | |||
| 944 | }; | 944 | }; |
| 945 | 945 | ||
| 946 | /* drm_radeon_cs_reloc.flags */ | 946 | /* drm_radeon_cs_reloc.flags */ |
| 947 | #define RADEON_RELOC_PRIO_MASK (0xf << 0) | ||
| 947 | 948 | ||
| 948 | struct drm_radeon_cs_reloc { | 949 | struct drm_radeon_cs_reloc { |
| 949 | uint32_t handle; | 950 | uint32_t handle; |
