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authorAbhijeet Kolekar <abhijeet.kolekar@intel.com>2008-12-18 21:37:29 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-01-29 15:59:14 -0500
commit5d49f498a29360592dea4693724fef242278e0d3 (patch)
tree0bc4b1c3623944a925e414c4858f2279c27d5a92
parent4a8a43222db6f04c88def2160a95f978f704b515 (diff)
iwl3945: use iwl-io.h and delete iwl-3945-io.h
The patch deletes iwl-3945-io.h and uses iwl-io.h functions. Signed-off-by: Abhijeet Kolekar <abhijeet.kolekar@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-io.h404
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c162
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c230
4 files changed, 197 insertions, 601 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-io.h b/drivers/net/wireless/iwlwifi/iwl-3945-io.h
deleted file mode 100644
index 0b84815dd69b..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-3945-io.h
+++ /dev/null
@@ -1,404 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Intel Linux Wireless <ilw@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *
27 *****************************************************************************/
28
29#ifndef __iwl3945_io_h__
30#define __iwl3945_io_h__
31
32#include <linux/io.h>
33
34#include "iwl-debug.h"
35
36/*
37 * IO, register, and NIC memory access functions
38 *
39 * NOTE on naming convention and macro usage for these
40 *
41 * A single _ prefix before a an access function means that no state
42 * check or debug information is printed when that function is called.
43 *
44 * A double __ prefix before an access function means that state is checked
45 * and the current line number is printed in addition to any other debug output.
46 *
47 * The non-prefixed name is the #define that maps the caller into a
48 * #define that provides the caller's __LINE__ to the double prefix version.
49 *
50 * If you wish to call the function without any debug or state checking,
51 * you should use the single _ prefix version (as is used by dependent IO
52 * routines, for example _iwl3945_read_direct32 calls the non-check version of
53 * _iwl3945_read32.)
54 *
55 * These declarations are *extremely* useful in quickly isolating code deltas
56 * which result in misconfiguration of the hardware I/O. In combination with
57 * git-bisect and the IO debug level you can quickly determine the specific
58 * commit which breaks the IO sequence to the hardware.
59 *
60 */
61
62#define _iwl3945_write32(priv, ofs, val) iowrite32((val), (priv)->hw_base + (ofs))
63#ifdef CONFIG_IWL3945_DEBUG
64static inline void __iwl3945_write32(const char *f, u32 l, struct iwl_priv *priv,
65 u32 ofs, u32 val)
66{
67 IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
68 _iwl3945_write32(priv, ofs, val);
69}
70#define iwl3945_write32(priv, ofs, val) \
71 __iwl3945_write32(__FILE__, __LINE__, priv, ofs, val)
72#else
73#define iwl3945_write32(priv, ofs, val) _iwl3945_write32(priv, ofs, val)
74#endif
75
76#define _iwl3945_read32(priv, ofs) ioread32((priv)->hw_base + (ofs))
77#ifdef CONFIG_IWL3945_DEBUG
78static inline u32 __iwl3945_read32(char *f, u32 l, struct iwl_priv *priv, u32 ofs)
79{
80 IWL_DEBUG_IO("read_direct32(0x%08X) - %s %d\n", ofs, f, l);
81 return _iwl3945_read32(priv, ofs);
82}
83#define iwl3945_read32(priv, ofs)__iwl3945_read32(__FILE__, __LINE__, priv, ofs)
84#else
85#define iwl3945_read32(p, o) _iwl3945_read32(p, o)
86#endif
87
88static inline int _iwl3945_poll_bit(struct iwl_priv *priv, u32 addr,
89 u32 bits, u32 mask, int timeout)
90{
91 int i = 0;
92
93 do {
94 if ((_iwl3945_read32(priv, addr) & mask) == (bits & mask))
95 return i;
96 udelay(10);
97 i += 10;
98 } while (i < timeout);
99
100 return -ETIMEDOUT;
101}
102#ifdef CONFIG_IWL3945_DEBUG
103static inline int __iwl3945_poll_bit(const char *f, u32 l,
104 struct iwl_priv *priv, u32 addr,
105 u32 bits, u32 mask, int timeout)
106{
107 int ret = _iwl3945_poll_bit(priv, addr, bits, mask, timeout);
108 IWL_DEBUG_IO("poll_bit(0x%08X, 0x%08X, 0x%08X) - %s- %s %d\n",
109 addr, bits, mask,
110 unlikely(ret == -ETIMEDOUT) ? "timeout" : "", f, l);
111 return ret;
112}
113#define iwl3945_poll_bit(priv, addr, bits, mask, timeout) \
114 __iwl3945_poll_bit(__FILE__, __LINE__, priv, addr, bits, mask, timeout)
115#else
116#define iwl3945_poll_bit(p, a, b, m, t) _iwl3945_poll_bit(p, a, b, m, t)
117#endif
118
119static inline void _iwl3945_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
120{
121 _iwl3945_write32(priv, reg, _iwl3945_read32(priv, reg) | mask);
122}
123#ifdef CONFIG_IWL3945_DEBUG
124static inline void __iwl3945_set_bit(const char *f, u32 l,
125 struct iwl_priv *priv, u32 reg, u32 mask)
126{
127 u32 val = _iwl3945_read32(priv, reg) | mask;
128 IWL_DEBUG_IO("set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
129 _iwl3945_write32(priv, reg, val);
130}
131#define iwl3945_set_bit(p, r, m) __iwl3945_set_bit(__FILE__, __LINE__, p, r, m)
132#else
133#define iwl3945_set_bit(p, r, m) _iwl3945_set_bit(p, r, m)
134#endif
135
136static inline void _iwl3945_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
137{
138 _iwl3945_write32(priv, reg, _iwl3945_read32(priv, reg) & ~mask);
139}
140#ifdef CONFIG_IWL3945_DEBUG
141static inline void __iwl3945_clear_bit(const char *f, u32 l,
142 struct iwl_priv *priv, u32 reg, u32 mask)
143{
144 u32 val = _iwl3945_read32(priv, reg) & ~mask;
145 IWL_DEBUG_IO("clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
146 _iwl3945_write32(priv, reg, val);
147}
148#define iwl3945_clear_bit(p, r, m) __iwl3945_clear_bit(__FILE__, __LINE__, p, r, m)
149#else
150#define iwl3945_clear_bit(p, r, m) _iwl3945_clear_bit(p, r, m)
151#endif
152
153static inline int _iwl3945_grab_nic_access(struct iwl_priv *priv)
154{
155 int ret;
156#ifdef CONFIG_IWL3945_DEBUG
157 if (atomic_read(&priv->restrict_refcnt))
158 return 0;
159#endif
160 /* this bit wakes up the NIC */
161 _iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
162 ret = _iwl3945_poll_bit(priv, CSR_GP_CNTRL,
163 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
164 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
165 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50);
166 if (ret < 0) {
167 IWL_ERROR("MAC is in deep sleep!\n");
168 return -EIO;
169 }
170
171#ifdef CONFIG_IWL3945_DEBUG
172 atomic_inc(&priv->restrict_refcnt);
173#endif
174 return 0;
175}
176
177#ifdef CONFIG_IWL3945_DEBUG
178static inline int __iwl3945_grab_nic_access(const char *f, u32 l,
179 struct iwl_priv *priv)
180{
181 if (atomic_read(&priv->restrict_refcnt))
182 IWL_DEBUG_INFO("Grabbing access while already held at "
183 "line %d.\n", l);
184
185 IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l);
186 return _iwl3945_grab_nic_access(priv);
187}
188#define iwl3945_grab_nic_access(priv) \
189 __iwl3945_grab_nic_access(__FILE__, __LINE__, priv)
190#else
191#define iwl3945_grab_nic_access(priv) \
192 _iwl3945_grab_nic_access(priv)
193#endif
194
195static inline void _iwl3945_release_nic_access(struct iwl_priv *priv)
196{
197#ifdef CONFIG_IWL3945_DEBUG
198 if (atomic_dec_and_test(&priv->restrict_refcnt))
199#endif
200 _iwl3945_clear_bit(priv, CSR_GP_CNTRL,
201 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
202}
203#ifdef CONFIG_IWL3945_DEBUG
204static inline void __iwl3945_release_nic_access(const char *f, u32 l,
205 struct iwl_priv *priv)
206{
207 if (atomic_read(&priv->restrict_refcnt) <= 0)
208 IWL_ERROR("Release unheld nic access at line %d.\n", l);
209
210 IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l);
211 _iwl3945_release_nic_access(priv);
212}
213#define iwl3945_release_nic_access(priv) \
214 __iwl3945_release_nic_access(__FILE__, __LINE__, priv)
215#else
216#define iwl3945_release_nic_access(priv) \
217 _iwl3945_release_nic_access(priv)
218#endif
219
220static inline u32 _iwl3945_read_direct32(struct iwl_priv *priv, u32 reg)
221{
222 return _iwl3945_read32(priv, reg);
223}
224#ifdef CONFIG_IWL3945_DEBUG
225static inline u32 __iwl3945_read_direct32(const char *f, u32 l,
226 struct iwl_priv *priv, u32 reg)
227{
228 u32 value = _iwl3945_read_direct32(priv, reg);
229 if (!atomic_read(&priv->restrict_refcnt))
230 IWL_ERROR("Nic access not held from %s %d\n", f, l);
231 IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value,
232 f, l);
233 return value;
234}
235#define iwl3945_read_direct32(priv, reg) \
236 __iwl3945_read_direct32(__FILE__, __LINE__, priv, reg)
237#else
238#define iwl3945_read_direct32 _iwl3945_read_direct32
239#endif
240
241static inline void _iwl3945_write_direct32(struct iwl_priv *priv,
242 u32 reg, u32 value)
243{
244 _iwl3945_write32(priv, reg, value);
245}
246#ifdef CONFIG_IWL3945_DEBUG
247static void __iwl3945_write_direct32(u32 line,
248 struct iwl_priv *priv, u32 reg, u32 value)
249{
250 if (!atomic_read(&priv->restrict_refcnt))
251 IWL_ERROR("Nic access not held from line %d\n", line);
252 _iwl3945_write_direct32(priv, reg, value);
253}
254#define iwl3945_write_direct32(priv, reg, value) \
255 __iwl3945_write_direct32(__LINE__, priv, reg, value)
256#else
257#define iwl3945_write_direct32 _iwl3945_write_direct32
258#endif
259
260static inline void iwl3945_write_reg_buf(struct iwl_priv *priv,
261 u32 reg, u32 len, u32 *values)
262{
263 u32 count = sizeof(u32);
264
265 if ((priv != NULL) && (values != NULL)) {
266 for (; 0 < len; len -= count, reg += count, values++)
267 _iwl3945_write_direct32(priv, reg, *values);
268 }
269}
270
271static inline int _iwl3945_poll_direct_bit(struct iwl_priv *priv,
272 u32 addr, u32 mask, int timeout)
273{
274 return _iwl3945_poll_bit(priv, addr, mask, mask, timeout);
275}
276
277#ifdef CONFIG_IWL3945_DEBUG
278static inline int __iwl3945_poll_direct_bit(const char *f, u32 l,
279 struct iwl_priv *priv,
280 u32 addr, u32 mask, int timeout)
281{
282 int ret = _iwl3945_poll_direct_bit(priv, addr, mask, timeout);
283
284 if (unlikely(ret == -ETIMEDOUT))
285 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - "
286 "timedout - %s %d\n", addr, mask, f, l);
287 else
288 IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) = 0x%08X "
289 "- %s %d\n", addr, mask, ret, f, l);
290 return ret;
291}
292#define iwl3945_poll_direct_bit(priv, addr, mask, timeout) \
293 __iwl3945_poll_direct_bit(__FILE__, __LINE__, priv, addr, mask, timeout)
294#else
295#define iwl3945_poll_direct_bit _iwl3945_poll_direct_bit
296#endif
297
298static inline u32 _iwl3945_read_prph(struct iwl_priv *priv, u32 reg)
299{
300 _iwl3945_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
301 rmb();
302 return _iwl3945_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
303}
304#ifdef CONFIG_IWL3945_DEBUG
305static inline u32 __iwl3945_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
306{
307 if (!atomic_read(&priv->restrict_refcnt))
308 IWL_ERROR("Nic access not held from line %d\n", line);
309 return _iwl3945_read_prph(priv, reg);
310}
311
312#define iwl3945_read_prph(priv, reg) \
313 __iwl3945_read_prph(__LINE__, priv, reg)
314#else
315#define iwl3945_read_prph _iwl3945_read_prph
316#endif
317
318static inline void _iwl3945_write_prph(struct iwl_priv *priv,
319 u32 addr, u32 val)
320{
321 _iwl3945_write_direct32(priv, HBUS_TARG_PRPH_WADDR,
322 ((addr & 0x0000FFFF) | (3 << 24)));
323 wmb();
324 _iwl3945_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
325}
326#ifdef CONFIG_IWL3945_DEBUG
327static inline void __iwl3945_write_prph(u32 line, struct iwl_priv *priv,
328 u32 addr, u32 val)
329{
330 if (!atomic_read(&priv->restrict_refcnt))
331 IWL_ERROR("Nic access from line %d\n", line);
332 _iwl3945_write_prph(priv, addr, val);
333}
334
335#define iwl3945_write_prph(priv, addr, val) \
336 __iwl3945_write_prph(__LINE__, priv, addr, val);
337#else
338#define iwl3945_write_prph _iwl3945_write_prph
339#endif
340
341#define _iwl3945_set_bits_prph(priv, reg, mask) \
342 _iwl3945_write_prph(priv, reg, (_iwl3945_read_prph(priv, reg) | mask))
343#ifdef CONFIG_IWL3945_DEBUG
344static inline void __iwl3945_set_bits_prph(u32 line, struct iwl_priv *priv,
345 u32 reg, u32 mask)
346{
347 if (!atomic_read(&priv->restrict_refcnt))
348 IWL_ERROR("Nic access not held from line %d\n", line);
349
350 _iwl3945_set_bits_prph(priv, reg, mask);
351}
352#define iwl3945_set_bits_prph(priv, reg, mask) \
353 __iwl3945_set_bits_prph(__LINE__, priv, reg, mask)
354#else
355#define iwl3945_set_bits_prph _iwl3945_set_bits_prph
356#endif
357
358#define _iwl3945_set_bits_mask_prph(priv, reg, bits, mask) \
359 _iwl3945_write_prph(priv, reg, ((_iwl3945_read_prph(priv, reg) & mask) | bits))
360
361#ifdef CONFIG_IWL3945_DEBUG
362static inline void __iwl3945_set_bits_mask_prph(u32 line,
363 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
364{
365 if (!atomic_read(&priv->restrict_refcnt))
366 IWL_ERROR("Nic access not held from line %d\n", line);
367 _iwl3945_set_bits_mask_prph(priv, reg, bits, mask);
368}
369#define iwl3945_set_bits_mask_prph(priv, reg, bits, mask) \
370 __iwl3945_set_bits_mask_prph(__LINE__, priv, reg, bits, mask)
371#else
372#define iwl3945_set_bits_mask_prph _iwl3945_set_bits_mask_prph
373#endif
374
375static inline void iwl3945_clear_bits_prph(struct iwl_priv
376 *priv, u32 reg, u32 mask)
377{
378 u32 val = _iwl3945_read_prph(priv, reg);
379 _iwl3945_write_prph(priv, reg, (val & ~mask));
380}
381
382static inline u32 iwl3945_read_targ_mem(struct iwl_priv *priv, u32 addr)
383{
384 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
385 rmb();
386 return iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
387}
388
389static inline void iwl3945_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
390{
391 iwl3945_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
392 wmb();
393 iwl3945_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
394}
395
396static inline void iwl3945_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
397 u32 len, u32 *values)
398{
399 iwl3945_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
400 wmb();
401 for (; 0 < len; len -= sizeof(u32), values++)
402 iwl3945_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
403}
404#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 50e729ed0181..328e55f84d95 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -156,26 +156,26 @@ void iwl3945_disable_events(struct iwl_priv *priv)
156 return; 156 return;
157 } 157 }
158 158
159 ret = iwl3945_grab_nic_access(priv); 159 ret = iwl_grab_nic_access(priv);
160 if (ret) { 160 if (ret) {
161 IWL_WARNING("Can not read from adapter at this time.\n"); 161 IWL_WARNING("Can not read from adapter at this time.\n");
162 return; 162 return;
163 } 163 }
164 164
165 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32))); 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32))); 166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
167 iwl3945_release_nic_access(priv); 167 iwl_release_nic_access(priv);
168 168
169 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { 169 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
170 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n", 170 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
171 disable_ptr); 171 disable_ptr);
172 ret = iwl3945_grab_nic_access(priv); 172 ret = iwl_grab_nic_access(priv);
173 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) 173 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
174 iwl3945_write_targ_mem(priv, 174 iwl_write_targ_mem(priv,
175 disable_ptr + (i * sizeof(u32)), 175 disable_ptr + (i * sizeof(u32)),
176 evt_disable[i]); 176 evt_disable[i]);
177 177
178 iwl3945_release_nic_access(priv); 178 iwl_release_nic_access(priv);
179 } else { 179 } else {
180 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n"); 180 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
181 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n"); 181 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
@@ -925,7 +925,7 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
925 unsigned long flags; 925 unsigned long flags;
926 926
927 spin_lock_irqsave(&priv->lock, flags); 927 spin_lock_irqsave(&priv->lock, flags);
928 rc = iwl3945_grab_nic_access(priv); 928 rc = iwl_grab_nic_access(priv);
929 if (rc) { 929 if (rc) {
930 spin_unlock_irqrestore(&priv->lock, flags); 930 spin_unlock_irqrestore(&priv->lock, flags);
931 return rc; 931 return rc;
@@ -937,23 +937,23 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
937 rc = pci_read_config_dword(priv->pci_dev, 937 rc = pci_read_config_dword(priv->pci_dev,
938 PCI_POWER_SOURCE, &val); 938 PCI_POWER_SOURCE, &val);
939 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { 939 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
940 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 940 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
941 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 941 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
942 ~APMG_PS_CTRL_MSK_PWR_SRC); 942 ~APMG_PS_CTRL_MSK_PWR_SRC);
943 iwl3945_release_nic_access(priv); 943 iwl_release_nic_access(priv);
944 944
945 iwl3945_poll_bit(priv, CSR_GPIO_IN, 945 iwl_poll_bit(priv, CSR_GPIO_IN,
946 CSR_GPIO_IN_VAL_VAUX_PWR_SRC, 946 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
947 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 947 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
948 } else 948 } else
949 iwl3945_release_nic_access(priv); 949 iwl_release_nic_access(priv);
950 } else { 950 } else {
951 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 951 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
952 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 952 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
953 ~APMG_PS_CTRL_MSK_PWR_SRC); 953 ~APMG_PS_CTRL_MSK_PWR_SRC);
954 954
955 iwl3945_release_nic_access(priv); 955 iwl_release_nic_access(priv);
956 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, 956 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
957 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ 957 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
958 } 958 }
959 spin_unlock_irqrestore(&priv->lock, flags); 959 spin_unlock_irqrestore(&priv->lock, flags);
@@ -967,18 +967,18 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
967 unsigned long flags; 967 unsigned long flags;
968 968
969 spin_lock_irqsave(&priv->lock, flags); 969 spin_lock_irqsave(&priv->lock, flags);
970 rc = iwl3945_grab_nic_access(priv); 970 rc = iwl_grab_nic_access(priv);
971 if (rc) { 971 if (rc) {
972 spin_unlock_irqrestore(&priv->lock, flags); 972 spin_unlock_irqrestore(&priv->lock, flags);
973 return rc; 973 return rc;
974 } 974 }
975 975
976 iwl3945_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr); 976 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
977 iwl3945_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), 977 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
978 priv->shared_phys + 978 priv->shared_phys +
979 offsetof(struct iwl3945_shared, rx_read_ptr[0])); 979 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
980 iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), 0); 980 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
981 iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0), 981 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
982 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | 982 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
983 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | 983 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
984 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | 984 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
@@ -989,9 +989,9 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
989 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); 989 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
990 990
991 /* fake read to flush all prev I/O */ 991 /* fake read to flush all prev I/O */
992 iwl3945_read_direct32(priv, FH39_RSSR_CTRL); 992 iwl_read_direct32(priv, FH39_RSSR_CTRL);
993 993
994 iwl3945_release_nic_access(priv); 994 iwl_release_nic_access(priv);
995 spin_unlock_irqrestore(&priv->lock, flags); 995 spin_unlock_irqrestore(&priv->lock, flags);
996 996
997 return 0; 997 return 0;
@@ -1003,30 +1003,30 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
1003 unsigned long flags; 1003 unsigned long flags;
1004 1004
1005 spin_lock_irqsave(&priv->lock, flags); 1005 spin_lock_irqsave(&priv->lock, flags);
1006 rc = iwl3945_grab_nic_access(priv); 1006 rc = iwl_grab_nic_access(priv);
1007 if (rc) { 1007 if (rc) {
1008 spin_unlock_irqrestore(&priv->lock, flags); 1008 spin_unlock_irqrestore(&priv->lock, flags);
1009 return rc; 1009 return rc;
1010 } 1010 }
1011 1011
1012 /* bypass mode */ 1012 /* bypass mode */
1013 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2); 1013 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
1014 1014
1015 /* RA 0 is active */ 1015 /* RA 0 is active */
1016 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); 1016 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1017 1017
1018 /* all 6 fifo are active */ 1018 /* all 6 fifo are active */
1019 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); 1019 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1020 1020
1021 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); 1021 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1022 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); 1022 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1023 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); 1023 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1024 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); 1024 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1025 1025
1026 iwl3945_write_direct32(priv, FH39_TSSR_CBB_BASE, 1026 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1027 priv->shared_phys); 1027 priv->shared_phys);
1028 1028
1029 iwl3945_write_direct32(priv, FH39_TSSR_MSG_CONFIG, 1029 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | 1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | 1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | 1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
@@ -1035,7 +1035,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1036 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 1036 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1037 1037
1038 iwl3945_release_nic_access(priv); 1038 iwl_release_nic_access(priv);
1039 spin_unlock_irqrestore(&priv->lock, flags); 1039 spin_unlock_irqrestore(&priv->lock, flags);
1040 1040
1041 return 0; 1041 return 0;
@@ -1087,12 +1087,12 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
1087 iwl3945_power_init_handle(priv); 1087 iwl3945_power_init_handle(priv);
1088 1088
1089 spin_lock_irqsave(&priv->lock, flags); 1089 spin_lock_irqsave(&priv->lock, flags);
1090 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL); 1090 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1091 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, 1091 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1092 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 1092 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1093 1093
1094 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1094 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1095 rc = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL, 1095 rc = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1096 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 1096 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1097 if (rc < 0) { 1097 if (rc < 0) {
1098 spin_unlock_irqrestore(&priv->lock, flags); 1098 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1100,18 +1100,18 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
1100 return rc; 1100 return rc;
1101 } 1101 }
1102 1102
1103 rc = iwl3945_grab_nic_access(priv); 1103 rc = iwl_grab_nic_access(priv);
1104 if (rc) { 1104 if (rc) {
1105 spin_unlock_irqrestore(&priv->lock, flags); 1105 spin_unlock_irqrestore(&priv->lock, flags);
1106 return rc; 1106 return rc;
1107 } 1107 }
1108 iwl3945_write_prph(priv, APMG_CLK_EN_REG, 1108 iwl_write_prph(priv, APMG_CLK_EN_REG,
1109 APMG_CLK_VAL_DMA_CLK_RQT | 1109 APMG_CLK_VAL_DMA_CLK_RQT |
1110 APMG_CLK_VAL_BSM_CLK_RQT); 1110 APMG_CLK_VAL_BSM_CLK_RQT);
1111 udelay(20); 1111 udelay(20);
1112 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 1112 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1113 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1113 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1114 iwl3945_release_nic_access(priv); 1114 iwl_release_nic_access(priv);
1115 spin_unlock_irqrestore(&priv->lock, flags); 1115 spin_unlock_irqrestore(&priv->lock, flags);
1116 1116
1117 /* Determine HW type */ 1117 /* Determine HW type */
@@ -1127,17 +1127,17 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
1127 IWL_DEBUG_INFO("RTP type \n"); 1127 IWL_DEBUG_INFO("RTP type \n");
1128 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { 1128 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1129 IWL_DEBUG_INFO("3945 RADIO-MB type\n"); 1129 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1130 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1130 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1131 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB); 1131 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1132 } else { 1132 } else {
1133 IWL_DEBUG_INFO("3945 RADIO-MM type\n"); 1133 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1134 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1134 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1135 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM); 1135 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1136 } 1136 }
1137 1137
1138 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) { 1138 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
1139 IWL_DEBUG_INFO("SKU OP mode is mrc\n"); 1139 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1140 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1140 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1141 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC); 1141 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1142 } else 1142 } else
1143 IWL_DEBUG_INFO("SKU OP mode is basic\n"); 1143 IWL_DEBUG_INFO("SKU OP mode is basic\n");
@@ -1145,24 +1145,24 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
1145 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) { 1145 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
1146 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", 1146 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1147 priv->eeprom39.board_revision); 1147 priv->eeprom39.board_revision);
1148 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1148 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1149 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 1149 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1150 } else { 1150 } else {
1151 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", 1151 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1152 priv->eeprom39.board_revision); 1152 priv->eeprom39.board_revision);
1153 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG, 1153 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1154 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 1154 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1155 } 1155 }
1156 1156
1157 if (priv->eeprom39.almgor_m_version <= 1) { 1157 if (priv->eeprom39.almgor_m_version <= 1) {
1158 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1158 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1159 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); 1159 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1160 IWL_DEBUG_INFO("Card M type A version is 0x%X\n", 1160 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1161 priv->eeprom39.almgor_m_version); 1161 priv->eeprom39.almgor_m_version);
1162 } else { 1162 } else {
1163 IWL_DEBUG_INFO("Card M type B version is 0x%X\n", 1163 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1164 priv->eeprom39.almgor_m_version); 1164 priv->eeprom39.almgor_m_version);
1165 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1165 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1166 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); 1166 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1167 } 1167 }
1168 spin_unlock_irqrestore(&priv->lock, flags); 1168 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1194,13 +1194,13 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
1194 iwl3945_rx_queue_update_write_ptr(priv, rxq); 1194 iwl3945_rx_queue_update_write_ptr(priv, rxq);
1195 */ 1195 */
1196 1196
1197 rc = iwl3945_grab_nic_access(priv); 1197 rc = iwl_grab_nic_access(priv);
1198 if (rc) { 1198 if (rc) {
1199 spin_unlock_irqrestore(&priv->lock, flags); 1199 spin_unlock_irqrestore(&priv->lock, flags);
1200 return rc; 1200 return rc;
1201 } 1201 }
1202 iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7); 1202 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1203 iwl3945_release_nic_access(priv); 1203 iwl_release_nic_access(priv);
1204 1204
1205 spin_unlock_irqrestore(&priv->lock, flags); 1205 spin_unlock_irqrestore(&priv->lock, flags);
1206 1206
@@ -1233,24 +1233,24 @@ void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1233 unsigned long flags; 1233 unsigned long flags;
1234 1234
1235 spin_lock_irqsave(&priv->lock, flags); 1235 spin_lock_irqsave(&priv->lock, flags);
1236 if (iwl3945_grab_nic_access(priv)) { 1236 if (iwl_grab_nic_access(priv)) {
1237 spin_unlock_irqrestore(&priv->lock, flags); 1237 spin_unlock_irqrestore(&priv->lock, flags);
1238 iwl3945_hw_txq_ctx_free(priv); 1238 iwl3945_hw_txq_ctx_free(priv);
1239 return; 1239 return;
1240 } 1240 }
1241 1241
1242 /* stop SCD */ 1242 /* stop SCD */
1243 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0); 1243 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1244 1244
1245 /* reset TFD queues */ 1245 /* reset TFD queues */
1246 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) { 1246 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1247 iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0); 1247 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1248 iwl3945_poll_direct_bit(priv, FH39_TSSR_TX_STATUS, 1248 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1249 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), 1249 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1250 1000); 1250 1000);
1251 } 1251 }
1252 1252
1253 iwl3945_release_nic_access(priv); 1253 iwl_release_nic_access(priv);
1254 spin_unlock_irqrestore(&priv->lock, flags); 1254 spin_unlock_irqrestore(&priv->lock, flags);
1255 1255
1256 iwl3945_hw_txq_ctx_free(priv); 1256 iwl3945_hw_txq_ctx_free(priv);
@@ -1265,16 +1265,16 @@ int iwl3945_hw_nic_stop_master(struct iwl_priv *priv)
1265 spin_lock_irqsave(&priv->lock, flags); 1265 spin_lock_irqsave(&priv->lock, flags);
1266 1266
1267 /* set stop master bit */ 1267 /* set stop master bit */
1268 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 1268 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1269 1269
1270 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL); 1270 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
1271 1271
1272 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE == 1272 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1273 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE)) 1273 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1274 IWL_DEBUG_INFO("Card in power save, master is already " 1274 IWL_DEBUG_INFO("Card in power save, master is already "
1275 "stopped\n"); 1275 "stopped\n");
1276 else { 1276 else {
1277 rc = iwl3945_poll_direct_bit(priv, CSR_RESET, 1277 rc = iwl_poll_direct_bit(priv, CSR_RESET,
1278 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 1278 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1279 if (rc < 0) { 1279 if (rc < 0) {
1280 spin_unlock_irqrestore(&priv->lock, flags); 1280 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1297,37 +1297,37 @@ int iwl3945_hw_nic_reset(struct iwl_priv *priv)
1297 1297
1298 spin_lock_irqsave(&priv->lock, flags); 1298 spin_lock_irqsave(&priv->lock, flags);
1299 1299
1300 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1300 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1301 1301
1302 iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL, 1302 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1303 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 1303 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1304 1304
1305 rc = iwl3945_grab_nic_access(priv); 1305 rc = iwl_grab_nic_access(priv);
1306 if (!rc) { 1306 if (!rc) {
1307 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG, 1307 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1308 APMG_CLK_VAL_BSM_CLK_RQT); 1308 APMG_CLK_VAL_BSM_CLK_RQT);
1309 1309
1310 udelay(10); 1310 udelay(10);
1311 1311
1312 iwl3945_set_bit(priv, CSR_GP_CNTRL, 1312 iwl_set_bit(priv, CSR_GP_CNTRL,
1313 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1313 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1314 1314
1315 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0); 1315 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1316 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG, 1316 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1317 0xFFFFFFFF); 1317 0xFFFFFFFF);
1318 1318
1319 /* enable DMA */ 1319 /* enable DMA */
1320 iwl3945_write_prph(priv, APMG_CLK_EN_REG, 1320 iwl_write_prph(priv, APMG_CLK_EN_REG,
1321 APMG_CLK_VAL_DMA_CLK_RQT | 1321 APMG_CLK_VAL_DMA_CLK_RQT |
1322 APMG_CLK_VAL_BSM_CLK_RQT); 1322 APMG_CLK_VAL_BSM_CLK_RQT);
1323 udelay(10); 1323 udelay(10);
1324 1324
1325 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG, 1325 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1326 APMG_PS_CTRL_VAL_RESET_REQ); 1326 APMG_PS_CTRL_VAL_RESET_REQ);
1327 udelay(5); 1327 udelay(5);
1328 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG, 1328 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1329 APMG_PS_CTRL_VAL_RESET_REQ); 1329 APMG_PS_CTRL_VAL_RESET_REQ);
1330 iwl3945_release_nic_access(priv); 1330 iwl_release_nic_access(priv);
1331 } 1331 }
1332 1332
1333 /* Clear the 'host command active' bit... */ 1333 /* Clear the 'host command active' bit... */
@@ -1358,7 +1358,7 @@ static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1358 1358
1359int iwl3945_hw_get_temperature(struct iwl_priv *priv) 1359int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1360{ 1360{
1361 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2); 1361 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1362} 1362}
1363 1363
1364/** 1364/**
@@ -2290,19 +2290,19 @@ int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2290 unsigned long flags; 2290 unsigned long flags;
2291 2291
2292 spin_lock_irqsave(&priv->lock, flags); 2292 spin_lock_irqsave(&priv->lock, flags);
2293 rc = iwl3945_grab_nic_access(priv); 2293 rc = iwl_grab_nic_access(priv);
2294 if (rc) { 2294 if (rc) {
2295 spin_unlock_irqrestore(&priv->lock, flags); 2295 spin_unlock_irqrestore(&priv->lock, flags);
2296 return rc; 2296 return rc;
2297 } 2297 }
2298 2298
2299 iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0), 0); 2299 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2300 rc = iwl3945_poll_direct_bit(priv, FH39_RSSR_STATUS, 2300 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2301 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 2301 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2302 if (rc < 0) 2302 if (rc < 0)
2303 IWL_ERROR("Can't stop Rx DMA.\n"); 2303 IWL_ERROR("Can't stop Rx DMA.\n");
2304 2304
2305 iwl3945_release_nic_access(priv); 2305 iwl_release_nic_access(priv);
2306 spin_unlock_irqrestore(&priv->lock, flags); 2306 spin_unlock_irqrestore(&priv->lock, flags);
2307 2307
2308 return 0; 2308 return 0;
@@ -2319,24 +2319,24 @@ int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl3945_tx_queue *txq
2319 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); 2319 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2320 2320
2321 spin_lock_irqsave(&priv->lock, flags); 2321 spin_lock_irqsave(&priv->lock, flags);
2322 rc = iwl3945_grab_nic_access(priv); 2322 rc = iwl_grab_nic_access(priv);
2323 if (rc) { 2323 if (rc) {
2324 spin_unlock_irqrestore(&priv->lock, flags); 2324 spin_unlock_irqrestore(&priv->lock, flags);
2325 return rc; 2325 return rc;
2326 } 2326 }
2327 iwl3945_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0); 2327 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2328 iwl3945_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0); 2328 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2329 2329
2330 iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 2330 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2331 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | 2331 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2332 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | 2332 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2333 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2333 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2334 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2334 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2335 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2335 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2336 iwl3945_release_nic_access(priv); 2336 iwl_release_nic_access(priv);
2337 2337
2338 /* fake read to flush all prev. writes */ 2338 /* fake read to flush all prev. writes */
2339 iwl3945_read32(priv, FH39_TSSR_CBB_BASE); 2339 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2340 spin_unlock_irqrestore(&priv->lock, flags); 2340 spin_unlock_irqrestore(&priv->lock, flags);
2341 2341
2342 return 0; 2342 return 0;
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index 098ac768ee26..63bf832ef762 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -397,6 +397,6 @@ extern const struct iwl_channel_info *iwl3945_get_channel_info(
397extern int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate); 397extern int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate);
398 398
399/* Requires full declaration of iwl_priv before including */ 399/* Requires full declaration of iwl_priv before including */
400#include "iwl-3945-io.h" 400#include "iwl-io.h"
401 401
402#endif 402#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index f80294e6bd9b..6bbc887449ca 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -1411,7 +1411,7 @@ static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
1411 */ 1411 */
1412static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv) 1412static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
1413{ 1413{
1414 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); 1414 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1415 return 0; 1415 return 0;
1416} 1416}
1417 1417
@@ -1425,7 +1425,7 @@ static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
1425int iwl3945_eeprom_init(struct iwl_priv *priv) 1425int iwl3945_eeprom_init(struct iwl_priv *priv)
1426{ 1426{
1427 u16 *e = (u16 *)&priv->eeprom39; 1427 u16 *e = (u16 *)&priv->eeprom39;
1428 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP); 1428 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
1429 int sz = sizeof(priv->eeprom39); 1429 int sz = sizeof(priv->eeprom39);
1430 int ret; 1430 int ret;
1431 u16 addr; 1431 u16 addr;
@@ -1452,10 +1452,10 @@ int iwl3945_eeprom_init(struct iwl_priv *priv)
1452 for (addr = 0; addr < sz; addr += sizeof(u16)) { 1452 for (addr = 0; addr < sz; addr += sizeof(u16)) {
1453 u32 r; 1453 u32 r;
1454 1454
1455 _iwl3945_write32(priv, CSR_EEPROM_REG, 1455 _iwl_write32(priv, CSR_EEPROM_REG,
1456 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 1456 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
1457 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); 1457 _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1458 ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG, 1458 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
1459 CSR_EEPROM_REG_READ_VALID_MSK, 1459 CSR_EEPROM_REG_READ_VALID_MSK,
1460 IWL_EEPROM_ACCESS_TIMEOUT); 1460 IWL_EEPROM_ACCESS_TIMEOUT);
1461 if (ret < 0) { 1461 if (ret < 0) {
@@ -1463,7 +1463,7 @@ int iwl3945_eeprom_init(struct iwl_priv *priv)
1463 return ret; 1463 return ret;
1464 } 1464 }
1465 1465
1466 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG); 1466 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
1467 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); 1467 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
1468 } 1468 }
1469 1469
@@ -2663,7 +2663,7 @@ static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2663 /* FIXME: This is a workaround for AP */ 2663 /* FIXME: This is a workaround for AP */
2664 if (priv->iw_mode != NL80211_IFTYPE_AP) { 2664 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2665 spin_lock_irqsave(&priv->lock, flags); 2665 spin_lock_irqsave(&priv->lock, flags);
2666 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, 2666 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
2667 CSR_UCODE_SW_BIT_RFKILL); 2667 CSR_UCODE_SW_BIT_RFKILL);
2668 spin_unlock_irqrestore(&priv->lock, flags); 2668 spin_unlock_irqrestore(&priv->lock, flags);
2669 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0); 2669 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
@@ -2673,7 +2673,7 @@ static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2673 } 2673 }
2674 2674
2675 spin_lock_irqsave(&priv->lock, flags); 2675 spin_lock_irqsave(&priv->lock, flags);
2676 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 2676 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2677 2677
2678 clear_bit(STATUS_RF_KILL_SW, &priv->status); 2678 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2679 spin_unlock_irqrestore(&priv->lock, flags); 2679 spin_unlock_irqrestore(&priv->lock, flags);
@@ -2682,9 +2682,9 @@ static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
2682 msleep(10); 2682 msleep(10);
2683 2683
2684 spin_lock_irqsave(&priv->lock, flags); 2684 spin_lock_irqsave(&priv->lock, flags);
2685 iwl3945_read32(priv, CSR_UCODE_DRV_GP1); 2685 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2686 if (!iwl3945_grab_nic_access(priv)) 2686 if (!iwl_grab_nic_access(priv))
2687 iwl3945_release_nic_access(priv); 2687 iwl_release_nic_access(priv);
2688 spin_unlock_irqrestore(&priv->lock, flags); 2688 spin_unlock_irqrestore(&priv->lock, flags);
2689 2689
2690 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { 2690 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
@@ -3151,7 +3151,7 @@ static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
3151 (flags & HW_CARD_DISABLED) ? "Kill" : "On", 3151 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3152 (flags & SW_CARD_DISABLED) ? "Kill" : "On"); 3152 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3153 3153
3154 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, 3154 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
3155 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 3155 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3156 3156
3157 if (flags & HW_CARD_DISABLED) 3157 if (flags & HW_CARD_DISABLED)
@@ -3386,27 +3386,27 @@ int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue
3386 3386
3387 /* If power-saving is in use, make sure device is awake */ 3387 /* If power-saving is in use, make sure device is awake */
3388 if (test_bit(STATUS_POWER_PMI, &priv->status)) { 3388 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3389 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); 3389 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
3390 3390
3391 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 3391 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3392 iwl3945_set_bit(priv, CSR_GP_CNTRL, 3392 iwl_set_bit(priv, CSR_GP_CNTRL,
3393 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 3393 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3394 goto exit_unlock; 3394 goto exit_unlock;
3395 } 3395 }
3396 3396
3397 rc = iwl3945_grab_nic_access(priv); 3397 rc = iwl_grab_nic_access(priv);
3398 if (rc) 3398 if (rc)
3399 goto exit_unlock; 3399 goto exit_unlock;
3400 3400
3401 /* Device expects a multiple of 8 */ 3401 /* Device expects a multiple of 8 */
3402 iwl3945_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR, 3402 iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
3403 q->write & ~0x7); 3403 q->write & ~0x7);
3404 iwl3945_release_nic_access(priv); 3404 iwl_release_nic_access(priv);
3405 3405
3406 /* Else device is assumed to be awake */ 3406 /* Else device is assumed to be awake */
3407 } else 3407 } else
3408 /* Device expects a multiple of 8 */ 3408 /* Device expects a multiple of 8 */
3409 iwl3945_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7); 3409 iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
3410 3410
3411 3411
3412 q->need_update = 0; 3412 q->need_update = 0;
@@ -3843,27 +3843,27 @@ static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
3843 /* wake up nic if it's powered down ... 3843 /* wake up nic if it's powered down ...
3844 * uCode will wake up, and interrupt us again, so next 3844 * uCode will wake up, and interrupt us again, so next
3845 * time we'll skip this part. */ 3845 * time we'll skip this part. */
3846 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); 3846 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
3847 3847
3848 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 3848 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3849 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); 3849 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
3850 iwl3945_set_bit(priv, CSR_GP_CNTRL, 3850 iwl_set_bit(priv, CSR_GP_CNTRL,
3851 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 3851 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3852 return rc; 3852 return rc;
3853 } 3853 }
3854 3854
3855 /* restore this queue's parameters in nic hardware. */ 3855 /* restore this queue's parameters in nic hardware. */
3856 rc = iwl3945_grab_nic_access(priv); 3856 rc = iwl_grab_nic_access(priv);
3857 if (rc) 3857 if (rc)
3858 return rc; 3858 return rc;
3859 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR, 3859 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
3860 txq->q.write_ptr | (txq_id << 8)); 3860 txq->q.write_ptr | (txq_id << 8));
3861 iwl3945_release_nic_access(priv); 3861 iwl_release_nic_access(priv);
3862 3862
3863 /* else not in power-save mode, uCode will never sleep when we're 3863 /* else not in power-save mode, uCode will never sleep when we're
3864 * trying to tx (during RFKILL, we're not trying to tx). */ 3864 * trying to tx (during RFKILL, we're not trying to tx). */
3865 } else 3865 } else
3866 iwl3945_write32(priv, HBUS_TARG_WRPTR, 3866 iwl_write32(priv, HBUS_TARG_WRPTR,
3867 txq->q.write_ptr | (txq_id << 8)); 3867 txq->q.write_ptr | (txq_id << 8));
3868 3868
3869 txq->need_update = 0; 3869 txq->need_update = 0;
@@ -3895,7 +3895,7 @@ static void iwl3945_enable_interrupts(struct iwl_priv *priv)
3895{ 3895{
3896 IWL_DEBUG_ISR("Enabling interrupts\n"); 3896 IWL_DEBUG_ISR("Enabling interrupts\n");
3897 set_bit(STATUS_INT_ENABLED, &priv->status); 3897 set_bit(STATUS_INT_ENABLED, &priv->status);
3898 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); 3898 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
3899} 3899}
3900 3900
3901 3901
@@ -3913,12 +3913,12 @@ static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
3913 clear_bit(STATUS_INT_ENABLED, &priv->status); 3913 clear_bit(STATUS_INT_ENABLED, &priv->status);
3914 3914
3915 /* disable interrupts from uCode/NIC to host */ 3915 /* disable interrupts from uCode/NIC to host */
3916 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); 3916 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
3917 3917
3918 /* acknowledge/clear/reset any interrupts still pending 3918 /* acknowledge/clear/reset any interrupts still pending
3919 * from uCode or flow handler (Rx/Tx DMA) */ 3919 * from uCode or flow handler (Rx/Tx DMA) */
3920 iwl3945_write32(priv, CSR_INT, 0xffffffff); 3920 iwl_write32(priv, CSR_INT, 0xffffffff);
3921 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); 3921 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
3922 IWL_DEBUG_ISR("Disabled interrupts\n"); 3922 IWL_DEBUG_ISR("Disabled interrupts\n");
3923} 3923}
3924 3924
@@ -3959,13 +3959,13 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
3959 return; 3959 return;
3960 } 3960 }
3961 3961
3962 rc = iwl3945_grab_nic_access(priv); 3962 rc = iwl_grab_nic_access(priv);
3963 if (rc) { 3963 if (rc) {
3964 IWL_WARNING("Can not read from adapter at this time.\n"); 3964 IWL_WARNING("Can not read from adapter at this time.\n");
3965 return; 3965 return;
3966 } 3966 }
3967 3967
3968 count = iwl3945_read_targ_mem(priv, base); 3968 count = iwl_read_targ_mem(priv, base);
3969 3969
3970 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { 3970 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
3971 IWL_ERROR("Start IWL Error Log Dump:\n"); 3971 IWL_ERROR("Start IWL Error Log Dump:\n");
@@ -3977,19 +3977,19 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
3977 for (i = ERROR_START_OFFSET; 3977 for (i = ERROR_START_OFFSET;
3978 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; 3978 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
3979 i += ERROR_ELEM_SIZE) { 3979 i += ERROR_ELEM_SIZE) {
3980 desc = iwl3945_read_targ_mem(priv, base + i); 3980 desc = iwl_read_targ_mem(priv, base + i);
3981 time = 3981 time =
3982 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32)); 3982 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
3983 blink1 = 3983 blink1 =
3984 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32)); 3984 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
3985 blink2 = 3985 blink2 =
3986 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32)); 3986 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
3987 ilink1 = 3987 ilink1 =
3988 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32)); 3988 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
3989 ilink2 = 3989 ilink2 =
3990 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32)); 3990 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
3991 data1 = 3991 data1 =
3992 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32)); 3992 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
3993 3993
3994 IWL_ERROR 3994 IWL_ERROR
3995 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", 3995 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
@@ -3997,7 +3997,7 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
3997 ilink1, ilink2, data1); 3997 ilink1, ilink2, data1);
3998 } 3998 }
3999 3999
4000 iwl3945_release_nic_access(priv); 4000 iwl_release_nic_access(priv);
4001 4001
4002} 4002}
4003 4003
@@ -4006,7 +4006,7 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
4006/** 4006/**
4007 * iwl3945_print_event_log - Dump error event log to syslog 4007 * iwl3945_print_event_log - Dump error event log to syslog
4008 * 4008 *
4009 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained! 4009 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
4010 */ 4010 */
4011static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, 4011static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
4012 u32 num_events, u32 mode) 4012 u32 num_events, u32 mode)
@@ -4032,14 +4032,14 @@ static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
4032 /* "time" is actually "data" for mode 0 (no timestamp). 4032 /* "time" is actually "data" for mode 0 (no timestamp).
4033 * place event id # at far right for easier visual parsing. */ 4033 * place event id # at far right for easier visual parsing. */
4034 for (i = 0; i < num_events; i++) { 4034 for (i = 0; i < num_events; i++) {
4035 ev = iwl3945_read_targ_mem(priv, ptr); 4035 ev = iwl_read_targ_mem(priv, ptr);
4036 ptr += sizeof(u32); 4036 ptr += sizeof(u32);
4037 time = iwl3945_read_targ_mem(priv, ptr); 4037 time = iwl_read_targ_mem(priv, ptr);
4038 ptr += sizeof(u32); 4038 ptr += sizeof(u32);
4039 if (mode == 0) 4039 if (mode == 0)
4040 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ 4040 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4041 else { 4041 else {
4042 data = iwl3945_read_targ_mem(priv, ptr); 4042 data = iwl_read_targ_mem(priv, ptr);
4043 ptr += sizeof(u32); 4043 ptr += sizeof(u32);
4044 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); 4044 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4045 } 4045 }
@@ -4062,24 +4062,24 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
4062 return; 4062 return;
4063 } 4063 }
4064 4064
4065 rc = iwl3945_grab_nic_access(priv); 4065 rc = iwl_grab_nic_access(priv);
4066 if (rc) { 4066 if (rc) {
4067 IWL_WARNING("Can not read from adapter at this time.\n"); 4067 IWL_WARNING("Can not read from adapter at this time.\n");
4068 return; 4068 return;
4069 } 4069 }
4070 4070
4071 /* event log header */ 4071 /* event log header */
4072 capacity = iwl3945_read_targ_mem(priv, base); 4072 capacity = iwl_read_targ_mem(priv, base);
4073 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32))); 4073 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
4074 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32))); 4074 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
4075 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32))); 4075 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
4076 4076
4077 size = num_wraps ? capacity : next_entry; 4077 size = num_wraps ? capacity : next_entry;
4078 4078
4079 /* bail out if nothing in log */ 4079 /* bail out if nothing in log */
4080 if (size == 0) { 4080 if (size == 0) {
4081 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); 4081 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
4082 iwl3945_release_nic_access(priv); 4082 iwl_release_nic_access(priv);
4083 return; 4083 return;
4084 } 4084 }
4085 4085
@@ -4095,7 +4095,7 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
4095 /* (then/else) start at top of log */ 4095 /* (then/else) start at top of log */
4096 iwl3945_print_event_log(priv, 0, next_entry, mode); 4096 iwl3945_print_event_log(priv, 0, next_entry, mode);
4097 4097
4098 iwl3945_release_nic_access(priv); 4098 iwl_release_nic_access(priv);
4099} 4099}
4100 4100
4101/** 4101/**
@@ -4167,19 +4167,19 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
4167 /* Ack/clear/reset pending uCode interrupts. 4167 /* Ack/clear/reset pending uCode interrupts.
4168 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 4168 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4169 * and will clear only when CSR_FH_INT_STATUS gets cleared. */ 4169 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
4170 inta = iwl3945_read32(priv, CSR_INT); 4170 inta = iwl_read32(priv, CSR_INT);
4171 iwl3945_write32(priv, CSR_INT, inta); 4171 iwl_write32(priv, CSR_INT, inta);
4172 4172
4173 /* Ack/clear/reset pending flow-handler (DMA) interrupts. 4173 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4174 * Any new interrupts that happen after this, either while we're 4174 * Any new interrupts that happen after this, either while we're
4175 * in this tasklet, or later, will show up in next ISR/tasklet. */ 4175 * in this tasklet, or later, will show up in next ISR/tasklet. */
4176 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); 4176 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4177 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh); 4177 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
4178 4178
4179#ifdef CONFIG_IWL3945_DEBUG 4179#ifdef CONFIG_IWL3945_DEBUG
4180 if (priv->debug_level & IWL_DL_ISR) { 4180 if (priv->debug_level & IWL_DL_ISR) {
4181 /* just for debug */ 4181 /* just for debug */
4182 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); 4182 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4183 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", 4183 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4184 inta, inta_mask, inta_fh); 4184 inta, inta_mask, inta_fh);
4185 } 4185 }
@@ -4258,11 +4258,11 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
4258 if (inta & CSR_INT_BIT_FH_TX) { 4258 if (inta & CSR_INT_BIT_FH_TX) {
4259 IWL_DEBUG_ISR("Tx interrupt\n"); 4259 IWL_DEBUG_ISR("Tx interrupt\n");
4260 4260
4261 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); 4261 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4262 if (!iwl3945_grab_nic_access(priv)) { 4262 if (!iwl_grab_nic_access(priv)) {
4263 iwl3945_write_direct32(priv, FH39_TCSR_CREDIT 4263 iwl_write_direct32(priv, FH39_TCSR_CREDIT
4264 (FH39_SRVC_CHNL), 0x0); 4264 (FH39_SRVC_CHNL), 0x0);
4265 iwl3945_release_nic_access(priv); 4265 iwl_release_nic_access(priv);
4266 } 4266 }
4267 handled |= CSR_INT_BIT_FH_TX; 4267 handled |= CSR_INT_BIT_FH_TX;
4268 } 4268 }
@@ -4283,9 +4283,9 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
4283 4283
4284#ifdef CONFIG_IWL3945_DEBUG 4284#ifdef CONFIG_IWL3945_DEBUG
4285 if (priv->debug_level & (IWL_DL_ISR)) { 4285 if (priv->debug_level & (IWL_DL_ISR)) {
4286 inta = iwl3945_read32(priv, CSR_INT); 4286 inta = iwl_read32(priv, CSR_INT);
4287 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); 4287 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4288 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); 4288 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4289 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " 4289 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4290 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); 4290 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4291 } 4291 }
@@ -4307,12 +4307,12 @@ static irqreturn_t iwl3945_isr(int irq, void *data)
4307 * back-to-back ISRs and sporadic interrupts from our NIC. 4307 * back-to-back ISRs and sporadic interrupts from our NIC.
4308 * If we have something to service, the tasklet will re-enable ints. 4308 * If we have something to service, the tasklet will re-enable ints.
4309 * If we *don't* have something, we'll re-enable before leaving here. */ 4309 * If we *don't* have something, we'll re-enable before leaving here. */
4310 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */ 4310 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
4311 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); 4311 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
4312 4312
4313 /* Discover which interrupts are active/pending */ 4313 /* Discover which interrupts are active/pending */
4314 inta = iwl3945_read32(priv, CSR_INT); 4314 inta = iwl_read32(priv, CSR_INT);
4315 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); 4315 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4316 4316
4317 /* Ignore interrupt if there's nothing in NIC to service. 4317 /* Ignore interrupt if there's nothing in NIC to service.
4318 * This may be due to IRQ shared with another device, 4318 * This may be due to IRQ shared with another device,
@@ -4937,11 +4937,11 @@ static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 le
4937 4937
4938 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 4938 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4939 4939
4940 rc = iwl3945_grab_nic_access(priv); 4940 rc = iwl_grab_nic_access(priv);
4941 if (rc) 4941 if (rc)
4942 return rc; 4942 return rc;
4943 4943
4944 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, 4944 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
4945 IWL39_RTC_INST_LOWER_BOUND); 4945 IWL39_RTC_INST_LOWER_BOUND);
4946 4946
4947 errcnt = 0; 4947 errcnt = 0;
@@ -4949,7 +4949,7 @@ static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 le
4949 /* read data comes through single port, auto-incr addr */ 4949 /* read data comes through single port, auto-incr addr */
4950 /* NOTE: Use the debugless read so we don't flood kernel log 4950 /* NOTE: Use the debugless read so we don't flood kernel log
4951 * if IWL_DL_IO is set */ 4951 * if IWL_DL_IO is set */
4952 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); 4952 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
4953 if (val != le32_to_cpu(*image)) { 4953 if (val != le32_to_cpu(*image)) {
4954 IWL_ERROR("uCode INST section is invalid at " 4954 IWL_ERROR("uCode INST section is invalid at "
4955 "offset 0x%x, is 0x%x, s/b 0x%x\n", 4955 "offset 0x%x, is 0x%x, s/b 0x%x\n",
@@ -4961,7 +4961,7 @@ static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 le
4961 } 4961 }
4962 } 4962 }
4963 4963
4964 iwl3945_release_nic_access(priv); 4964 iwl_release_nic_access(priv);
4965 4965
4966 if (!errcnt) 4966 if (!errcnt)
4967 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n"); 4967 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
@@ -4984,7 +4984,7 @@ static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
4984 4984
4985 IWL_DEBUG_INFO("ucode inst image size is %u\n", len); 4985 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4986 4986
4987 rc = iwl3945_grab_nic_access(priv); 4987 rc = iwl_grab_nic_access(priv);
4988 if (rc) 4988 if (rc)
4989 return rc; 4989 return rc;
4990 4990
@@ -4992,9 +4992,9 @@ static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
4992 /* read data comes through single port, auto-incr addr */ 4992 /* read data comes through single port, auto-incr addr */
4993 /* NOTE: Use the debugless read so we don't flood kernel log 4993 /* NOTE: Use the debugless read so we don't flood kernel log
4994 * if IWL_DL_IO is set */ 4994 * if IWL_DL_IO is set */
4995 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, 4995 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
4996 i + IWL39_RTC_INST_LOWER_BOUND); 4996 i + IWL39_RTC_INST_LOWER_BOUND);
4997 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); 4997 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
4998 if (val != le32_to_cpu(*image)) { 4998 if (val != le32_to_cpu(*image)) {
4999#if 0 /* Enable this if you want to see details */ 4999#if 0 /* Enable this if you want to see details */
5000 IWL_ERROR("uCode INST section is invalid at " 5000 IWL_ERROR("uCode INST section is invalid at "
@@ -5008,7 +5008,7 @@ static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
5008 } 5008 }
5009 } 5009 }
5010 5010
5011 iwl3945_release_nic_access(priv); 5011 iwl_release_nic_access(priv);
5012 5012
5013 return rc; 5013 return rc;
5014} 5014}
@@ -5075,11 +5075,11 @@ static int iwl3945_verify_bsm(struct iwl_priv *priv)
5075 IWL_DEBUG_INFO("Begin verify bsm\n"); 5075 IWL_DEBUG_INFO("Begin verify bsm\n");
5076 5076
5077 /* verify BSM SRAM contents */ 5077 /* verify BSM SRAM contents */
5078 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG); 5078 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
5079 for (reg = BSM_SRAM_LOWER_BOUND; 5079 for (reg = BSM_SRAM_LOWER_BOUND;
5080 reg < BSM_SRAM_LOWER_BOUND + len; 5080 reg < BSM_SRAM_LOWER_BOUND + len;
5081 reg += sizeof(u32), image++) { 5081 reg += sizeof(u32), image++) {
5082 val = iwl3945_read_prph(priv, reg); 5082 val = iwl_read_prph(priv, reg);
5083 if (val != le32_to_cpu(*image)) { 5083 if (val != le32_to_cpu(*image)) {
5084 IWL_ERROR("BSM uCode verification failed at " 5084 IWL_ERROR("BSM uCode verification failed at "
5085 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", 5085 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
@@ -5156,42 +5156,42 @@ static int iwl3945_load_bsm(struct iwl_priv *priv)
5156 inst_len = priv->ucode_init.len; 5156 inst_len = priv->ucode_init.len;
5157 data_len = priv->ucode_init_data.len; 5157 data_len = priv->ucode_init_data.len;
5158 5158
5159 rc = iwl3945_grab_nic_access(priv); 5159 rc = iwl_grab_nic_access(priv);
5160 if (rc) 5160 if (rc)
5161 return rc; 5161 return rc;
5162 5162
5163 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 5163 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5164 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 5164 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5165 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 5165 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5166 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); 5166 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
5167 5167
5168 /* Fill BSM memory with bootstrap instructions */ 5168 /* Fill BSM memory with bootstrap instructions */
5169 for (reg_offset = BSM_SRAM_LOWER_BOUND; 5169 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5170 reg_offset < BSM_SRAM_LOWER_BOUND + len; 5170 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5171 reg_offset += sizeof(u32), image++) 5171 reg_offset += sizeof(u32), image++)
5172 _iwl3945_write_prph(priv, reg_offset, 5172 _iwl_write_prph(priv, reg_offset,
5173 le32_to_cpu(*image)); 5173 le32_to_cpu(*image));
5174 5174
5175 rc = iwl3945_verify_bsm(priv); 5175 rc = iwl3945_verify_bsm(priv);
5176 if (rc) { 5176 if (rc) {
5177 iwl3945_release_nic_access(priv); 5177 iwl_release_nic_access(priv);
5178 return rc; 5178 return rc;
5179 } 5179 }
5180 5180
5181 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 5181 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
5182 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); 5182 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5183 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG, 5183 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
5184 IWL39_RTC_INST_LOWER_BOUND); 5184 IWL39_RTC_INST_LOWER_BOUND);
5185 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); 5185 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
5186 5186
5187 /* Load bootstrap code into instruction SRAM now, 5187 /* Load bootstrap code into instruction SRAM now,
5188 * to prepare to load "initialize" uCode */ 5188 * to prepare to load "initialize" uCode */
5189 iwl3945_write_prph(priv, BSM_WR_CTRL_REG, 5189 iwl_write_prph(priv, BSM_WR_CTRL_REG,
5190 BSM_WR_CTRL_REG_BIT_START); 5190 BSM_WR_CTRL_REG_BIT_START);
5191 5191
5192 /* Wait for load of bootstrap uCode to finish */ 5192 /* Wait for load of bootstrap uCode to finish */
5193 for (i = 0; i < 100; i++) { 5193 for (i = 0; i < 100; i++) {
5194 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG); 5194 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
5195 if (!(done & BSM_WR_CTRL_REG_BIT_START)) 5195 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5196 break; 5196 break;
5197 udelay(10); 5197 udelay(10);
@@ -5205,10 +5205,10 @@ static int iwl3945_load_bsm(struct iwl_priv *priv)
5205 5205
5206 /* Enable future boot loads whenever power management unit triggers it 5206 /* Enable future boot loads whenever power management unit triggers it
5207 * (e.g. when powering back up after power-save shutdown) */ 5207 * (e.g. when powering back up after power-save shutdown) */
5208 iwl3945_write_prph(priv, BSM_WR_CTRL_REG, 5208 iwl_write_prph(priv, BSM_WR_CTRL_REG,
5209 BSM_WR_CTRL_REG_BIT_START_EN); 5209 BSM_WR_CTRL_REG_BIT_START_EN);
5210 5210
5211 iwl3945_release_nic_access(priv); 5211 iwl_release_nic_access(priv);
5212 5212
5213 return 0; 5213 return 0;
5214} 5214}
@@ -5216,7 +5216,7 @@ static int iwl3945_load_bsm(struct iwl_priv *priv)
5216static void iwl3945_nic_start(struct iwl_priv *priv) 5216static void iwl3945_nic_start(struct iwl_priv *priv)
5217{ 5217{
5218 /* Remove all resets to allow NIC to operate */ 5218 /* Remove all resets to allow NIC to operate */
5219 iwl3945_write32(priv, CSR_RESET, 0); 5219 iwl_write32(priv, CSR_RESET, 0);
5220} 5220}
5221 5221
5222/** 5222/**
@@ -5477,24 +5477,24 @@ static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
5477 pdata = priv->ucode_data_backup.p_addr; 5477 pdata = priv->ucode_data_backup.p_addr;
5478 5478
5479 spin_lock_irqsave(&priv->lock, flags); 5479 spin_lock_irqsave(&priv->lock, flags);
5480 rc = iwl3945_grab_nic_access(priv); 5480 rc = iwl_grab_nic_access(priv);
5481 if (rc) { 5481 if (rc) {
5482 spin_unlock_irqrestore(&priv->lock, flags); 5482 spin_unlock_irqrestore(&priv->lock, flags);
5483 return rc; 5483 return rc;
5484 } 5484 }
5485 5485
5486 /* Tell bootstrap uCode where to find image to load */ 5486 /* Tell bootstrap uCode where to find image to load */
5487 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 5487 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5488 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 5488 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5489 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, 5489 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
5490 priv->ucode_data.len); 5490 priv->ucode_data.len);
5491 5491
5492 /* Inst byte count must be last to set up, bit 31 signals uCode 5492 /* Inst byte count must be last to set up, bit 31 signals uCode
5493 * that all new ptr/size info is in place */ 5493 * that all new ptr/size info is in place */
5494 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, 5494 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
5495 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 5495 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5496 5496
5497 iwl3945_release_nic_access(priv); 5497 iwl_release_nic_access(priv);
5498 5498
5499 spin_unlock_irqrestore(&priv->lock, flags); 5499 spin_unlock_irqrestore(&priv->lock, flags);
5500 5500
@@ -5583,15 +5583,15 @@ static void iwl3945_alive_start(struct iwl_priv *priv)
5583 5583
5584 iwl3945_clear_stations_table(priv); 5584 iwl3945_clear_stations_table(priv);
5585 5585
5586 rc = iwl3945_grab_nic_access(priv); 5586 rc = iwl_grab_nic_access(priv);
5587 if (rc) { 5587 if (rc) {
5588 IWL_WARNING("Can not read RFKILL status from adapter\n"); 5588 IWL_WARNING("Can not read RFKILL status from adapter\n");
5589 return; 5589 return;
5590 } 5590 }
5591 5591
5592 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG); 5592 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
5593 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); 5593 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
5594 iwl3945_release_nic_access(priv); 5594 iwl_release_nic_access(priv);
5595 5595
5596 if (rfkill & 0x1) { 5596 if (rfkill & 0x1) {
5597 clear_bit(STATUS_RF_KILL_HW, &priv->status); 5597 clear_bit(STATUS_RF_KILL_HW, &priv->status);
@@ -5695,7 +5695,7 @@ static void __iwl3945_down(struct iwl_priv *priv)
5695 clear_bit(STATUS_EXIT_PENDING, &priv->status); 5695 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5696 5696
5697 /* stop and reset the on-board processor */ 5697 /* stop and reset the on-board processor */
5698 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 5698 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5699 5699
5700 /* tell the device to stop sending interrupts */ 5700 /* tell the device to stop sending interrupts */
5701 spin_lock_irqsave(&priv->lock, flags); 5701 spin_lock_irqsave(&priv->lock, flags);
@@ -5738,24 +5738,24 @@ static void __iwl3945_down(struct iwl_priv *priv)
5738 STATUS_EXIT_PENDING; 5738 STATUS_EXIT_PENDING;
5739 5739
5740 spin_lock_irqsave(&priv->lock, flags); 5740 spin_lock_irqsave(&priv->lock, flags);
5741 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 5741 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5742 spin_unlock_irqrestore(&priv->lock, flags); 5742 spin_unlock_irqrestore(&priv->lock, flags);
5743 5743
5744 iwl3945_hw_txq_ctx_stop(priv); 5744 iwl3945_hw_txq_ctx_stop(priv);
5745 iwl3945_hw_rxq_stop(priv); 5745 iwl3945_hw_rxq_stop(priv);
5746 5746
5747 spin_lock_irqsave(&priv->lock, flags); 5747 spin_lock_irqsave(&priv->lock, flags);
5748 if (!iwl3945_grab_nic_access(priv)) { 5748 if (!iwl_grab_nic_access(priv)) {
5749 iwl3945_write_prph(priv, APMG_CLK_DIS_REG, 5749 iwl_write_prph(priv, APMG_CLK_DIS_REG,
5750 APMG_CLK_VAL_DMA_CLK_RQT); 5750 APMG_CLK_VAL_DMA_CLK_RQT);
5751 iwl3945_release_nic_access(priv); 5751 iwl_release_nic_access(priv);
5752 } 5752 }
5753 spin_unlock_irqrestore(&priv->lock, flags); 5753 spin_unlock_irqrestore(&priv->lock, flags);
5754 5754
5755 udelay(5); 5755 udelay(5);
5756 5756
5757 iwl3945_hw_nic_stop_master(priv); 5757 iwl3945_hw_nic_stop_master(priv);
5758 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 5758 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5759 iwl3945_hw_nic_reset(priv); 5759 iwl3945_hw_nic_reset(priv);
5760 5760
5761 exit: 5761 exit:
@@ -5801,7 +5801,7 @@ static int __iwl3945_up(struct iwl_priv *priv)
5801 } 5801 }
5802 5802
5803 /* If platform's RF_KILL switch is NOT set to KILL */ 5803 /* If platform's RF_KILL switch is NOT set to KILL */
5804 if (iwl3945_read32(priv, CSR_GP_CNTRL) & 5804 if (iwl_read32(priv, CSR_GP_CNTRL) &
5805 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 5805 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5806 clear_bit(STATUS_RF_KILL_HW, &priv->status); 5806 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5807 else { 5807 else {
@@ -5812,7 +5812,7 @@ static int __iwl3945_up(struct iwl_priv *priv)
5812 } 5812 }
5813 } 5813 }
5814 5814
5815 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); 5815 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5816 5816
5817 rc = iwl3945_hw_nic_init(priv); 5817 rc = iwl3945_hw_nic_init(priv);
5818 if (rc) { 5818 if (rc) {
@@ -5821,17 +5821,17 @@ static int __iwl3945_up(struct iwl_priv *priv)
5821 } 5821 }
5822 5822
5823 /* make sure rfkill handshake bits are cleared */ 5823 /* make sure rfkill handshake bits are cleared */
5824 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5824 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5825 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, 5825 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
5826 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 5826 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5827 5827
5828 /* clear (again), then enable host interrupts */ 5828 /* clear (again), then enable host interrupts */
5829 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); 5829 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5830 iwl3945_enable_interrupts(priv); 5830 iwl3945_enable_interrupts(priv);
5831 5831
5832 /* really make sure rfkill handshake bits are cleared */ 5832 /* really make sure rfkill handshake bits are cleared */
5833 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5833 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5834 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5834 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5835 5835
5836 /* Copy original ucode data image from disk into backup cache. 5836 /* Copy original ucode data image from disk into backup cache.
5837 * This will be used to initialize the on-board processor's 5837 * This will be used to initialize the on-board processor's
@@ -7819,11 +7819,11 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
7819 pci_write_config_byte(pdev, 0x41, 0x00); 7819 pci_write_config_byte(pdev, 0x41, 0x00);
7820 7820
7821 /* nic init */ 7821 /* nic init */
7822 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, 7822 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
7823 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 7823 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
7824 7824
7825 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 7825 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
7826 err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL, 7826 err = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
7827 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 7827 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
7828 if (err < 0) { 7828 if (err < 0) {
7829 IWL_DEBUG_INFO("Failed to init the card\n"); 7829 IWL_DEBUG_INFO("Failed to init the card\n");
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 15:30:56 -0400