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authorMichal Simek <michal.simek@xilinx.com>2015-03-09 04:41:04 -0400
committerArnd Bergmann <arnd@arndb.de>2015-03-11 17:57:06 -0400
commit5d1b79d2b2639bb71238e76d73431fada9e38553 (patch)
tree9724a02296ff7d27ee5290505433231d4d3c13e0
parent13a7a6ac0a11197edcd0f756a035f472b42cdf8b (diff)
ARM64: Add new Xilinx ZynqMP SoC
Initial version of device tree for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm64/Kconfig5
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/xilinx/Makefile5
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts47
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi305
-rw-r--r--arch/arm64/configs/defconfig3
6 files changed, 366 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e97331ffb..9f805cf2e0b0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -228,6 +228,11 @@ config ARCH_XGENE
228 help 228 help
229 This enables support for AppliedMicro X-Gene SOC Family 229 This enables support for AppliedMicro X-Gene SOC Family
230 230
231config ARCH_ZYNQMP
232 bool "Xilinx ZynqMP Family"
233 help
234 This enables support for Xilinx ZynqMP Family
235
231endmenu 236endmenu
232 237
233menu "Bus support" 238menu "Bus support"
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350caf049e..ff088ec6ca5f 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@ dts-dirs += cavium
5dts-dirs += exynos 5dts-dirs += exynos
6dts-dirs += freescale 6dts-dirs += freescale
7dts-dirs += mediatek 7dts-dirs += mediatek
8dts-dirs += xilinx
8 9
9subdir-y := $(dts-dirs) 10subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
new file mode 100644
index 000000000000..ae16427f6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
new file mode 100644
index 000000000000..0a3f40ecd06d
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -0,0 +1,47 @@
1/*
2 * dts file for Xilinx ZynqMP ep108 development board
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14/dts-v1/;
15
16/include/ "zynqmp.dtsi"
17
18/ {
19 model = "ZynqMP EP108";
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x0 0x0 0x40000000>;
32 };
33};
34
35&gem0 {
36 status = "okay";
37 phy-handle = <&phy0>;
38 phy-mode = "rgmii-id";
39 phy0: phy@0{
40 reg = <0>;
41 max-speed = <100>;
42 };
43};
44
45&uart0 {
46 status = "okay";
47};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
new file mode 100644
index 000000000000..11e0b00045cf
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -0,0 +1,305 @@
1/*
2 * dts file for Xilinx ZynqMP
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14/ {
15 compatible = "xlnx,zynqmp";
16 #address-cells = <2>;
17 #size-cells = <1>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a53", "arm,armv8";
25 device_type = "cpu";
26 enable-method = "psci";
27 reg = <0x0>;
28 };
29
30 cpu@1 {
31 compatible = "arm,cortex-a53", "arm,armv8";
32 device_type = "cpu";
33 enable-method = "psci";
34 reg = <0x1>;
35 };
36
37 cpu@2 {
38 compatible = "arm,cortex-a53", "arm,armv8";
39 device_type = "cpu";
40 enable-method = "psci";
41 reg = <0x2>;
42 };
43
44 cpu@3 {
45 compatible = "arm,cortex-a53", "arm,armv8";
46 device_type = "cpu";
47 enable-method = "psci";
48 reg = <0x3>;
49 };
50 };
51
52 pmu {
53 compatible = "arm,armv8-pmuv3";
54 interrupts = <0 143 4>,
55 <0 144 4>,
56 <0 145 4>,
57 <0 146 4>;
58 };
59
60 psci {
61 compatible = "arm,psci-0.2";
62 method = "smc";
63 };
64
65 timer {
66 compatible = "arm,armv8-timer";
67 interrupt-parent = <&gic>;
68 interrupts = <1 13 0xf01>,
69 <1 14 0xf01>,
70 <1 11 0xf01>,
71 <1 10 0xf01>;
72 };
73
74 amba_apu {
75 compatible = "simple-bus";
76 #address-cells = <2>;
77 #size-cells = <1>;
78 ranges;
79
80 gic: interrupt-controller@f9010000 {
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 reg = <0x0 0xf9010000 0x10000>,
84 <0x0 0xf902f000 0x2000>,
85 <0x0 0xf9040000 0x20000>,
86 <0x0 0xf906f000 0x2000>;
87 interrupt-controller;
88 interrupt-parent = <&gic>;
89 interrupts = <1 9 0xf04>;
90 };
91 };
92
93 amba {
94 compatible = "simple-bus";
95 #address-cells = <2>;
96 #size-cells = <1>;
97 ranges;
98
99 misc_clk: misc_clk {
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <25000000>;
103 };
104
105 ttc0: timer@ff110000 {
106 compatible = "cdns,ttc";
107 status = "disabled";
108 interrupt-parent = <&gic>;
109 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
110 reg = <0x0 0xff110000 0x1000>;
111 clocks = <&misc_clk>;
112 timer-width = <32>;
113 };
114
115 ttc1: timer@ff120000 {
116 compatible = "cdns,ttc";
117 status = "disabled";
118 interrupt-parent = <&gic>;
119 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
120 reg = <0x0 0xff120000 0x1000>;
121 clocks = <&misc_clk>;
122 timer-width = <32>;
123 };
124
125 ttc2: timer@ff130000 {
126 compatible = "cdns,ttc";
127 status = "disabled";
128 interrupt-parent = <&gic>;
129 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
130 reg = <0x0 0xff130000 0x1000>;
131 clocks = <&misc_clk>;
132 timer-width = <32>;
133 };
134
135 ttc3: timer@ff140000 {
136 compatible = "cdns,ttc";
137 status = "disabled";
138 interrupt-parent = <&gic>;
139 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
140 reg = <0x0 0xff140000 0x1000>;
141 clocks = <&misc_clk>;
142 timer-width = <32>;
143 };
144
145 uart0: serial@ff000000 {
146 compatible = "cdns,uart-r1p8";
147 status = "disabled";
148 interrupt-parent = <&gic>;
149 interrupts = <0 21 4>;
150 reg = <0x0 0xff000000 0x1000>;
151 clock-names = "uart_clk", "pclk";
152 clocks = <&misc_clk &misc_clk>;
153 };
154
155 uart1: serial@ff010000 {
156 compatible = "cdns,uart-r1p8";
157 status = "disabled";
158 interrupt-parent = <&gic>;
159 interrupts = <0 22 4>;
160 reg = <0x0 0xff010000 0x1000>;
161 clock-names = "uart_clk", "pclk";
162 clocks = <&misc_clk &misc_clk>;
163 };
164
165 gpio: gpio@ff0a0000 {
166 compatible = "xlnx,zynq-gpio-1.0";
167 status = "disabled";
168 #gpio-cells = <0x2>;
169 clocks = <&misc_clk>;
170 interrupt-parent = <&gic>;
171 interrupts = <0 16 4>;
172 reg = <0x0 0xff0a0000 0x1000>;
173 };
174
175 gem0: ethernet@ff0b0000 {
176 compatible = "cdns,gem";
177 status = "disabled";
178 interrupt-parent = <&gic>;
179 interrupts = <0 57 4>, <0 57 4>;
180 reg = <0x0 0xff0b0000 0x1000>;
181 clock-names = "pclk", "hclk", "tx_clk";
182 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 };
186
187 gem1: ethernet@ff0c0000 {
188 compatible = "cdns,gem";
189 status = "disabled";
190 interrupt-parent = <&gic>;
191 interrupts = <0 59 4>, <0 59 4>;
192 reg = <0x0 0xff0c0000 0x1000>;
193 clock-names = "pclk", "hclk", "tx_clk";
194 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
198
199 gem2: ethernet@ff0d0000 {
200 compatible = "cdns,gem";
201 status = "disabled";
202 interrupt-parent = <&gic>;
203 interrupts = <0 61 4>, <0 61 4>;
204 reg = <0x0 0xff0d0000 0x1000>;
205 clock-names = "pclk", "hclk", "tx_clk";
206 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210
211 gem3: ethernet@ff0e0000 {
212 compatible = "cdns,gem";
213 status = "disabled";
214 interrupt-parent = <&gic>;
215 interrupts = <0 63 4>, <0 63 4>;
216 reg = <0x0 0xff0e0000 0x1000>;
217 clock-names = "pclk", "hclk", "tx_clk";
218 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 spi0: spi@ff040000 {
224 compatible = "cdns,spi-r1p6";
225 status = "disabled";
226 interrupt-parent = <&gic>;
227 interrupts = <0 19 4>;
228 reg = <0x0 0xff040000 0x1000>;
229 clock-names = "ref_clk", "pclk";
230 clocks = <&misc_clk &misc_clk>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 };
234
235 spi1: spi@ff050000 {
236 compatible = "cdns,spi-r1p6";
237 status = "disabled";
238 interrupt-parent = <&gic>;
239 interrupts = <0 20 4>;
240 reg = <0x0 0xff050000 0x1000>;
241 clock-names = "ref_clk", "pclk";
242 clocks = <&misc_clk &misc_clk>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 };
246
247 i2c_clk: i2c_clk {
248 compatible = "fixed-clock";
249 #clock-cells = <0x0>;
250 clock-frequency = <111111111>;
251 };
252
253 i2c0: i2c@ff020000 {
254 compatible = "cdns,i2c-r1p10";
255 status = "disabled";
256 interrupt-parent = <&gic>;
257 interrupts = <0 17 4>;
258 reg = <0x0 0xff020000 0x1000>;
259 clocks = <&i2c_clk>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 };
263
264 i2c1: i2c@ff030000 {
265 compatible = "cdns,i2c-r1p10";
266 status = "disabled";
267 interrupt-parent = <&gic>;
268 interrupts = <0 18 4>;
269 reg = <0x0 0xff030000 0x1000>;
270 clocks = <&i2c_clk>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 };
274
275 sdhci0: sdhci@ff160000 {
276 compatible = "arasan,sdhci-8.9a";
277 status = "disabled";
278 interrupt-parent = <&gic>;
279 interrupts = <0 48 4>;
280 reg = <0x0 0xff160000 0x1000>;
281 clock-names = "clk_xin", "clk_ahb";
282 clocks = <&misc_clk>, <&misc_clk>;
283 };
284
285 sdhci1: sdhci@ff170000 {
286 compatible = "arasan,sdhci-8.9a";
287 status = "disabled";
288 interrupt-parent = <&gic>;
289 interrupts = <0 49 4>;
290 reg = <0x0 0xff170000 0x1000>;
291 clock-names = "clk_xin", "clk_ahb";
292 clocks = <&misc_clk>, <&misc_clk>;
293 };
294
295 watchdog0: watchdog@fd4d0000 {
296 compatible = "cdns,wdt-r1p2";
297 status = "disabled";
298 clocks= <&misc_clk>;
299 interrupt-parent = <&gic>;
300 interrupts = <0 52 1>;
301 reg = <0x0 0xfd4d0000 0x1000>;
302 timeout-sec = <10>;
303 };
304 };
305};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index be1f12a5a5f0..c34bfa002303 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -36,6 +36,7 @@ CONFIG_ARCH_MEDIATEK=y
36CONFIG_ARCH_THUNDER=y 36CONFIG_ARCH_THUNDER=y
37CONFIG_ARCH_VEXPRESS=y 37CONFIG_ARCH_VEXPRESS=y
38CONFIG_ARCH_XGENE=y 38CONFIG_ARCH_XGENE=y
39CONFIG_ARCH_ZYNQMP=y
39CONFIG_PCI=y 40CONFIG_PCI=y
40CONFIG_PCI_MSI=y 41CONFIG_PCI_MSI=y
41CONFIG_PCI_XGENE=y 42CONFIG_PCI_XGENE=y
@@ -94,6 +95,8 @@ CONFIG_SERIAL_8250_MT6577=y
94CONFIG_SERIAL_AMBA_PL011=y 95CONFIG_SERIAL_AMBA_PL011=y
95CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 96CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
96CONFIG_SERIAL_OF_PLATFORM=y 97CONFIG_SERIAL_OF_PLATFORM=y
98CONFIG_SERIAL_XILINX_PS_UART=y
99CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
97CONFIG_VIRTIO_CONSOLE=y 100CONFIG_VIRTIO_CONSOLE=y
98# CONFIG_HW_RANDOM is not set 101# CONFIG_HW_RANDOM is not set
99CONFIG_SPI=y 102CONFIG_SPI=y
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-02 20:55:18 -0400