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authorBen Skeggs <bskeggs@redhat.com>2015-01-13 18:57:36 -0500
committerBen Skeggs <bskeggs@redhat.com>2015-01-21 21:17:43 -0500
commit5ce3bf3c72436c49fbd9a5b71d7d278665f4bf55 (patch)
treef2aaba0aa92d945db18b68c93f53723ab4659807
parentebb58dc2ef8c62d1affa28160f57faa7b0e1dc02 (diff)
drm/nouveau/mmu: rename from vmmgr (no binary change)
Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/device.h4
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/device.h2
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h2
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h2
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h (renamed from drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h)46
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_chan.c14
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ttm.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/engctx.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c36
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c20
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c)140
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c)28
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h19
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c)32
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c)36
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c)36
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c)32
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h19
43 files changed, 319 insertions, 319 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index e73a16dd97fa..93acd5153bee 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -29,7 +29,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
29/*XXX*/ 29/*XXX*/
30#include <subdev/bios.h> 30#include <subdev/bios.h>
31#include <subdev/fb.h> 31#include <subdev/fb.h>
32#include <subdev/vm.h> 32#include <subdev/mmu.h>
33#include <subdev/bar.h> 33#include <subdev/bar.h>
34#include <subdev/gpio.h> 34#include <subdev/gpio.h>
35#include <subdev/clk.h> 35#include <subdev/clk.h>
@@ -40,7 +40,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
40#define nvkm_device(a) nv_device(nvkm_object((a))) 40#define nvkm_device(a) nv_device(nvkm_object((a)))
41#define nvkm_bios(a) nouveau_bios(nvkm_device(a)) 41#define nvkm_bios(a) nouveau_bios(nvkm_device(a))
42#define nvkm_fb(a) nouveau_fb(nvkm_device(a)) 42#define nvkm_fb(a) nouveau_fb(nvkm_device(a))
43#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a)) 43#define nvkm_mmu(a) nouveau_mmu(nvkm_device(a))
44#define nvkm_bar(a) nouveau_bar(nvkm_device(a)) 44#define nvkm_bar(a) nouveau_bar(nvkm_device(a))
45#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a)) 45#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a))
46#define nvkm_clk(a) nouveau_clk(nvkm_device(a)) 46#define nvkm_clk(a) nouveau_clk(nvkm_device(a))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index a2828ac6a65e..82625c5d68d7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -33,7 +33,7 @@ enum nv_subdev_type {
33 NVDEV_SUBDEV_FB, 33 NVDEV_SUBDEV_FB,
34 NVDEV_SUBDEV_LTC, 34 NVDEV_SUBDEV_LTC,
35 NVDEV_SUBDEV_INSTMEM, 35 NVDEV_SUBDEV_INSTMEM,
36 NVDEV_SUBDEV_VM, 36 NVDEV_SUBDEV_MMU,
37 NVDEV_SUBDEV_BAR, 37 NVDEV_SUBDEV_BAR,
38 NVDEV_SUBDEV_PMU, 38 NVDEV_SUBDEV_PMU,
39 NVDEV_SUBDEV_VOLT, 39 NVDEV_SUBDEV_VOLT,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
index dbc6a3e6dd44..9d696e4747e7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
@@ -4,7 +4,7 @@
4#include <core/object.h> 4#include <core/object.h>
5#include <core/gpuobj.h> 5#include <core/gpuobj.h>
6 6
7#include <subdev/vm.h> 7#include <subdev/mmu.h>
8 8
9#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng)) 9#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng))
10#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var)) 10#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
index 889603fbb0cf..0277585c9067 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
@@ -5,7 +5,7 @@
5#include <core/device.h> 5#include <core/device.h>
6#include <core/mm.h> 6#include <core/mm.h>
7 7
8#include <subdev/vm.h> 8#include <subdev/mmu.h>
9 9
10/* memory type/access flags, do not match hardware values */ 10/* memory type/access flags, do not match hardware values */
11#define NV_MEM_ACCESS_RO 1 11#define NV_MEM_ACCESS_RO 1
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
index d56585f1cd8c..2c3b29967ea4 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
@@ -22,8 +22,8 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#ifndef __NOUVEAU_VM_H__ 25#ifndef __NOUVEAU_MMU_H__
26#define __NOUVEAU_VM_H__ 26#define __NOUVEAU_MMU_H__
27 27
28#include <core/object.h> 28#include <core/object.h>
29#include <core/subdev.h> 29#include <core/subdev.h>
@@ -53,7 +53,7 @@ struct nouveau_vma {
53}; 53};
54 54
55struct nouveau_vm { 55struct nouveau_vm {
56 struct nouveau_vmmgr *vmm; 56 struct nouveau_mmu *mmu;
57 struct nouveau_mm mm; 57 struct nouveau_mm mm;
58 struct kref refcount; 58 struct kref refcount;
59 59
@@ -65,7 +65,7 @@ struct nouveau_vm {
65 u32 lpde; 65 u32 lpde;
66}; 66};
67 67
68struct nouveau_vmmgr { 68struct nouveau_mmu {
69 struct nouveau_subdev base; 69 struct nouveau_subdev base;
70 70
71 u64 limit; 71 u64 limit;
@@ -74,7 +74,7 @@ struct nouveau_vmmgr {
74 u8 spg_shift; 74 u8 spg_shift;
75 u8 lpg_shift; 75 u8 lpg_shift;
76 76
77 int (*create)(struct nouveau_vmmgr *, u64 offset, u64 length, 77 int (*create)(struct nouveau_mmu *, u64 offset, u64 length,
78 u64 mm_offset, struct nouveau_vm **); 78 u64 mm_offset, struct nouveau_vm **);
79 79
80 void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, 80 void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
@@ -88,37 +88,37 @@ struct nouveau_vmmgr {
88 void (*flush)(struct nouveau_vm *); 88 void (*flush)(struct nouveau_vm *);
89}; 89};
90 90
91static inline struct nouveau_vmmgr * 91static inline struct nouveau_mmu *
92nouveau_vmmgr(void *obj) 92nouveau_mmu(void *obj)
93{ 93{
94 return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VM); 94 return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU);
95} 95}
96 96
97#define nouveau_vmmgr_create(p,e,o,i,f,d) \ 97#define nouveau_mmu_create(p,e,o,i,f,d) \
98 nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) 98 nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d))
99#define nouveau_vmmgr_destroy(p) \ 99#define nouveau_mmu_destroy(p) \
100 nouveau_subdev_destroy(&(p)->base) 100 nouveau_subdev_destroy(&(p)->base)
101#define nouveau_vmmgr_init(p) \ 101#define nouveau_mmu_init(p) \
102 nouveau_subdev_init(&(p)->base) 102 nouveau_subdev_init(&(p)->base)
103#define nouveau_vmmgr_fini(p,s) \ 103#define nouveau_mmu_fini(p,s) \
104 nouveau_subdev_fini(&(p)->base, (s)) 104 nouveau_subdev_fini(&(p)->base, (s))
105 105
106#define _nouveau_vmmgr_dtor _nouveau_subdev_dtor 106#define _nouveau_mmu_dtor _nouveau_subdev_dtor
107#define _nouveau_vmmgr_init _nouveau_subdev_init 107#define _nouveau_mmu_init _nouveau_subdev_init
108#define _nouveau_vmmgr_fini _nouveau_subdev_fini 108#define _nouveau_mmu_fini _nouveau_subdev_fini
109 109
110extern struct nouveau_oclass nv04_vmmgr_oclass; 110extern struct nouveau_oclass nv04_mmu_oclass;
111extern struct nouveau_oclass nv41_vmmgr_oclass; 111extern struct nouveau_oclass nv41_mmu_oclass;
112extern struct nouveau_oclass nv44_vmmgr_oclass; 112extern struct nouveau_oclass nv44_mmu_oclass;
113extern struct nouveau_oclass nv50_vmmgr_oclass; 113extern struct nouveau_oclass nv50_mmu_oclass;
114extern struct nouveau_oclass nvc0_vmmgr_oclass; 114extern struct nouveau_oclass nvc0_mmu_oclass;
115 115
116int nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64, 116int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64,
117 struct nouveau_vm **); 117 struct nouveau_vm **);
118void nv04_vmmgr_dtor(struct nouveau_object *); 118void nv04_mmu_dtor(struct nouveau_object *);
119 119
120/* nouveau_vm.c */ 120/* nouveau_vm.c */
121int nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length, 121int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length,
122 u64 mm_offset, u32 block, struct nouveau_vm **); 122 u64 mm_offset, u32 block, struct nouveau_vm **);
123int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, 123int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length,
124 u64 mm_offset, struct nouveau_vm **); 124 u64 mm_offset, struct nouveau_vm **);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index d96fe3524dbd..d2f0929c2d73 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -193,7 +193,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
193 int max_size; 193 int max_size;
194 194
195 if (drm->client.vm) 195 if (drm->client.vm)
196 lpg_shift = drm->client.vm->vmm->lpg_shift; 196 lpg_shift = drm->client.vm->mmu->lpg_shift;
197 max_size = INT_MAX & ~((1 << lpg_shift) - 1); 197 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
198 198
199 if (size <= 0 || size > max_size) { 199 if (size <= 0 || size > max_size) {
@@ -220,7 +220,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
220 nvbo->page_shift = 12; 220 nvbo->page_shift = 12;
221 if (drm->client.vm) { 221 if (drm->client.vm) {
222 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) 222 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
223 nvbo->page_shift = drm->client.vm->vmm->lpg_shift; 223 nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
224 } 224 }
225 225
226 nouveau_bo_fixup_align(nvbo, flags, &align, &size); 226 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
@@ -1240,7 +1240,7 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1240 list_for_each_entry(vma, &nvbo->vma_list, head) { 1240 list_for_each_entry(vma, &nvbo->vma_list, head) {
1241 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && 1241 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1242 (new_mem->mem_type == TTM_PL_VRAM || 1242 (new_mem->mem_type == TTM_PL_VRAM ||
1243 nvbo->page_shift != vma->vm->vmm->lpg_shift)) { 1243 nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
1244 nouveau_vm_map(vma, new_mem->mm_node); 1244 nouveau_vm_map(vma, new_mem->mm_node);
1245 } else { 1245 } else {
1246 nouveau_vm_unmap(vma); 1246 nouveau_vm_unmap(vma);
@@ -1639,7 +1639,7 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1639 1639
1640 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM && 1640 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1641 (nvbo->bo.mem.mem_type == TTM_PL_VRAM || 1641 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1642 nvbo->page_shift != vma->vm->vmm->lpg_shift)) 1642 nvbo->page_shift != vma->vm->mmu->lpg_shift))
1643 nouveau_vm_map(vma, nvbo->bo.mem.mm_node); 1643 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1644 1644
1645 list_add_tail(&vma->head, &nvbo->vma_list); 1645 list_add_tail(&vma->head, &nvbo->vma_list);
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index aff9099aae6c..80302530ead7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -88,7 +88,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
88 u32 handle, u32 size, struct nouveau_channel **pchan) 88 u32 handle, u32 size, struct nouveau_channel **pchan)
89{ 89{
90 struct nouveau_cli *cli = (void *)nvif_client(&device->base); 90 struct nouveau_cli *cli = (void *)nvif_client(&device->base);
91 struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); 91 struct nouveau_mmu *mmu = nvkm_mmu(device);
92 struct nv_dma_v0 args = {}; 92 struct nv_dma_v0 args = {};
93 struct nouveau_channel *chan; 93 struct nouveau_channel *chan;
94 u32 target; 94 u32 target;
@@ -136,7 +136,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
136 args.target = NV_DMA_V0_TARGET_VM; 136 args.target = NV_DMA_V0_TARGET_VM;
137 args.access = NV_DMA_V0_ACCESS_VM; 137 args.access = NV_DMA_V0_ACCESS_VM;
138 args.start = 0; 138 args.start = 0;
139 args.limit = cli->vm->vmm->limit - 1; 139 args.limit = cli->vm->mmu->limit - 1;
140 } else 140 } else
141 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 141 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
142 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 142 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
@@ -165,7 +165,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
165 args.target = NV_DMA_V0_TARGET_VM; 165 args.target = NV_DMA_V0_TARGET_VM;
166 args.access = NV_DMA_V0_ACCESS_RDWR; 166 args.access = NV_DMA_V0_ACCESS_RDWR;
167 args.start = 0; 167 args.start = 0;
168 args.limit = vmm->limit - 1; 168 args.limit = mmu->limit - 1;
169 } 169 }
170 } 170 }
171 171
@@ -281,7 +281,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
281{ 281{
282 struct nvif_device *device = chan->device; 282 struct nvif_device *device = chan->device;
283 struct nouveau_cli *cli = (void *)nvif_client(&device->base); 283 struct nouveau_cli *cli = (void *)nvif_client(&device->base);
284 struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); 284 struct nouveau_mmu *mmu = nvkm_mmu(device);
285 struct nouveau_software_chan *swch; 285 struct nouveau_software_chan *swch;
286 struct nv_dma_v0 args = {}; 286 struct nv_dma_v0 args = {};
287 int ret, i; 287 int ret, i;
@@ -294,7 +294,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
294 args.target = NV_DMA_V0_TARGET_VM; 294 args.target = NV_DMA_V0_TARGET_VM;
295 args.access = NV_DMA_V0_ACCESS_VM; 295 args.access = NV_DMA_V0_ACCESS_VM;
296 args.start = 0; 296 args.start = 0;
297 args.limit = cli->vm->vmm->limit - 1; 297 args.limit = cli->vm->mmu->limit - 1;
298 } else { 298 } else {
299 args.target = NV_DMA_V0_TARGET_VRAM; 299 args.target = NV_DMA_V0_TARGET_VRAM;
300 args.access = NV_DMA_V0_ACCESS_RDWR; 300 args.access = NV_DMA_V0_ACCESS_RDWR;
@@ -312,7 +312,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
312 args.target = NV_DMA_V0_TARGET_VM; 312 args.target = NV_DMA_V0_TARGET_VM;
313 args.access = NV_DMA_V0_ACCESS_VM; 313 args.access = NV_DMA_V0_ACCESS_VM;
314 args.start = 0; 314 args.start = 0;
315 args.limit = cli->vm->vmm->limit - 1; 315 args.limit = cli->vm->mmu->limit - 1;
316 } else 316 } else
317 if (chan->drm->agp.stat == ENABLED) { 317 if (chan->drm->agp.stat == ENABLED) {
318 args.target = NV_DMA_V0_TARGET_AGP; 318 args.target = NV_DMA_V0_TARGET_AGP;
@@ -324,7 +324,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
324 args.target = NV_DMA_V0_TARGET_VM; 324 args.target = NV_DMA_V0_TARGET_VM;
325 args.access = NV_DMA_V0_ACCESS_RDWR; 325 args.access = NV_DMA_V0_ACCESS_RDWR;
326 args.start = 0; 326 args.start = 0;
327 args.limit = vmm->limit - 1; 327 args.limit = mmu->limit - 1;
328 } 328 }
329 329
330 ret = nvif_object_init(chan->object, NULL, gart, 330 ret = nvif_object_init(chan->object, NULL, gart,
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h
index be3d5947c6be..a94dcdaccf59 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.h
+++ b/drivers/gpu/drm/nouveau/nouveau_display.h
@@ -1,7 +1,7 @@
1#ifndef __NOUVEAU_DISPLAY_H__ 1#ifndef __NOUVEAU_DISPLAY_H__
2#define __NOUVEAU_DISPLAY_H__ 2#define __NOUVEAU_DISPLAY_H__
3 3
4#include <subdev/vm.h> 4#include <subdev/mmu.h>
5 5
6#include "nouveau_drm.h" 6#include "nouveau_drm.h"
7 7
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 2e0d1d998ca6..aa8321706103 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -203,13 +203,13 @@ const struct ttm_mem_type_manager_func nouveau_gart_manager = {
203}; 203};
204 204
205/*XXX*/ 205/*XXX*/
206#include <subdev/vm/nv04.h> 206#include <subdev/mmu/nv04.h>
207static int 207static int
208nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) 208nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
209{ 209{
210 struct nouveau_drm *drm = nouveau_bdev(man->bdev); 210 struct nouveau_drm *drm = nouveau_bdev(man->bdev);
211 struct nouveau_vmmgr *vmm = nvkm_vmmgr(&drm->device); 211 struct nouveau_mmu *mmu = nvkm_mmu(&drm->device);
212 struct nv04_vmmgr_priv *priv = (void *)vmm; 212 struct nv04_mmu_priv *priv = (void *)mmu;
213 struct nouveau_vm *vm = NULL; 213 struct nouveau_vm *vm = NULL;
214 nouveau_vm_ref(priv->vm, &vm, NULL); 214 nouveau_vm_ref(priv->vm, &vm, NULL);
215 man->priv = vm; 215 man->priv = vm;
@@ -354,7 +354,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
354 u32 bits; 354 u32 bits;
355 int ret; 355 int ret;
356 356
357 bits = nvkm_vmmgr(&drm->device)->dma_bits; 357 bits = nvkm_mmu(&drm->device)->dma_bits;
358 if (nv_device_is_pci(nvkm_device(&drm->device))) { 358 if (nv_device_is_pci(nvkm_device(&drm->device))) {
359 if (drm->agp.stat == ENABLED || 359 if (drm->agp.stat == ENABLED ||
360 !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) 360 !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
@@ -401,7 +401,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
401 401
402 /* GART init */ 402 /* GART init */
403 if (drm->agp.stat != ENABLED) { 403 if (drm->agp.stat != ENABLED) {
404 drm->gem.gart_available = nvkm_vmmgr(&drm->device)->limit; 404 drm->gem.gart_available = nvkm_mmu(&drm->device)->limit;
405 } else { 405 } else {
406 drm->gem.gart_available = drm->agp.size; 406 drm->gem.gart_available = drm->agp.size;
407 } 407 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
index 16f09b1280dc..892baa461575 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
@@ -28,7 +28,7 @@
28#include <core/client.h> 28#include <core/client.h>
29#include <core/engctx.h> 29#include <core/engctx.h>
30 30
31#include <subdev/vm.h> 31#include <subdev/mmu.h>
32 32
33static inline int 33static inline int
34nouveau_engctx_exists(struct nouveau_object *parent, 34nouveau_engctx_exists(struct nouveau_object *parent,
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
index 0fa64576b8d6..68a4232d35cc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
@@ -27,7 +27,7 @@
27 27
28#include <subdev/instmem.h> 28#include <subdev/instmem.h>
29#include <subdev/bar.h> 29#include <subdev/bar.h>
30#include <subdev/vm.h> 30#include <subdev/mmu.h>
31 31
32void 32void
33nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj) 33nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
index 13c05e09ff87..6ae64969e2e5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
@@ -27,7 +27,7 @@
27#include <engine/copy.h> 27#include <engine/copy.h>
28 28
29#include <subdev/fb.h> 29#include <subdev/fb.h>
30#include <subdev/vm.h> 30#include <subdev/mmu.h>
31 31
32#include <core/client.h> 32#include <core/client.h>
33#include <core/enum.h> 33#include <core/enum.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index e141dff31553..eb9f387d7356 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -218,7 +218,7 @@ static const u64 disable_map[] = {
218 [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE, 218 [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE,
219 [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE, 219 [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE,
220 [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE, 220 [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE,
221 [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE, 221 [NVDEV_SUBDEV_MMU] = NV_DEVICE_V0_DISABLE_CORE,
222 [NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE, 222 [NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE,
223 [NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE, 223 [NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE,
224 [NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE, 224 [NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 763572fcb7d4..130d225377ee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -37,7 +37,7 @@
37#include <subdev/ltc.h> 37#include <subdev/ltc.h>
38#include <subdev/ibus.h> 38#include <subdev/ibus.h>
39#include <subdev/instmem.h> 39#include <subdev/instmem.h>
40#include <subdev/vm.h> 40#include <subdev/mmu.h>
41#include <subdev/bar.h> 41#include <subdev/bar.h>
42#include <subdev/pmu.h> 42#include <subdev/pmu.h>
43#include <subdev/volt.h> 43#include <subdev/volt.h>
@@ -75,7 +75,7 @@ gm100_identify(struct nouveau_device *device)
75 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; 75 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
78 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 78 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
79 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 79 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
80 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 80 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
81 81
@@ -119,7 +119,7 @@ gm100_identify(struct nouveau_device *device)
119 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; 119 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
120 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 120 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
121 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 121 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
122 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 122 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
123 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 123 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
124 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 124 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
125#if 0 125#if 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index dff51984ea94..7f98385acec7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -31,7 +31,7 @@
31#include <subdev/timer.h> 31#include <subdev/timer.h>
32#include <subdev/fb.h> 32#include <subdev/fb.h>
33#include <subdev/instmem.h> 33#include <subdev/instmem.h>
34#include <subdev/vm.h> 34#include <subdev/mmu.h>
35 35
36#include <engine/device.h> 36#include <engine/device.h>
37#include <engine/dmaobj.h> 37#include <engine/dmaobj.h>
@@ -55,7 +55,7 @@ nv04_identify(struct nouveau_device *device)
55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
56 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; 56 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
57 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 57 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
58 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 58 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
60 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 60 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
61 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 61 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
@@ -73,7 +73,7 @@ nv04_identify(struct nouveau_device *device)
73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
74 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; 74 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
76 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 76 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
78 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 78 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
79 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index af63f5b95f01..6a7ece0fc789 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -32,7 +32,7 @@
32#include <subdev/timer.h> 32#include <subdev/timer.h>
33#include <subdev/fb.h> 33#include <subdev/fb.h>
34#include <subdev/instmem.h> 34#include <subdev/instmem.h>
35#include <subdev/vm.h> 35#include <subdev/mmu.h>
36 36
37#include <engine/device.h> 37#include <engine/device.h>
38#include <engine/dmaobj.h> 38#include <engine/dmaobj.h>
@@ -57,7 +57,7 @@ nv10_identify(struct nouveau_device *device)
57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
58 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 58 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
59 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 59 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
60 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 60 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
61 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 61 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
62 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -74,7 +74,7 @@ nv10_identify(struct nouveau_device *device)
74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
75 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 75 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
76 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 76 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
77 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 77 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -93,7 +93,7 @@ nv10_identify(struct nouveau_device *device)
93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
94 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 94 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
95 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 95 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
96 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 96 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
99 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 99 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -112,7 +112,7 @@ nv10_identify(struct nouveau_device *device)
112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
113 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; 113 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
114 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 114 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
115 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 115 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
118 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 118 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -131,7 +131,7 @@ nv10_identify(struct nouveau_device *device)
131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
132 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 132 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
133 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
134 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 137 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -150,7 +150,7 @@ nv10_identify(struct nouveau_device *device)
150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
151 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 151 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
152 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 152 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
153 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 153 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
156 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 156 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -169,7 +169,7 @@ nv10_identify(struct nouveau_device *device)
169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
170 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; 170 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
171 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 171 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
172 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 172 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
175 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 175 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -188,7 +188,7 @@ nv10_identify(struct nouveau_device *device)
188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
189 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 189 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
190 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 190 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
191 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 191 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
194 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 194 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index eddeb126c7ec..e3b17fde89e6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -33,7 +33,7 @@
33#include <subdev/timer.h> 33#include <subdev/timer.h>
34#include <subdev/fb.h> 34#include <subdev/fb.h>
35#include <subdev/instmem.h> 35#include <subdev/instmem.h>
36#include <subdev/vm.h> 36#include <subdev/mmu.h>
37 37
38#include <engine/device.h> 38#include <engine/device.h>
39#include <engine/dmaobj.h> 39#include <engine/dmaobj.h>
@@ -58,7 +58,7 @@ nv20_identify(struct nouveau_device *device)
58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
59 device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; 59 device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
60 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -77,7 +77,7 @@ nv20_identify(struct nouveau_device *device)
77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
78 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; 78 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
79 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -96,7 +96,7 @@ nv20_identify(struct nouveau_device *device)
96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
97 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; 97 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -115,7 +115,7 @@ nv20_identify(struct nouveau_device *device)
115 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 115 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
116 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; 116 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
117 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 117 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
118 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 118 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
120 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 120 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
121 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 121 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 6fe2d130a2ce..8f67f4d402d7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -32,7 +32,7 @@
32#include <subdev/timer.h> 32#include <subdev/timer.h>
33#include <subdev/fb.h> 33#include <subdev/fb.h>
34#include <subdev/instmem.h> 34#include <subdev/instmem.h>
35#include <subdev/vm.h> 35#include <subdev/mmu.h>
36 36
37#include <engine/device.h> 37#include <engine/device.h>
38#include <engine/dmaobj.h> 38#include <engine/dmaobj.h>
@@ -58,7 +58,7 @@ nv30_identify(struct nouveau_device *device)
58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
59 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; 59 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
60 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -77,7 +77,7 @@ nv30_identify(struct nouveau_device *device)
77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
78 device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; 78 device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
79 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -96,7 +96,7 @@ nv30_identify(struct nouveau_device *device)
96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
97 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; 97 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -116,7 +116,7 @@ nv30_identify(struct nouveau_device *device)
116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
117 device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; 117 device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
118 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 118 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
119 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 119 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
121 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 121 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
122 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 122 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -136,7 +136,7 @@ nv30_identify(struct nouveau_device *device)
136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
137 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 137 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
138 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 138 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
139 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 139 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
141 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 141 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
142 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 142 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index d85edd87cec8..49c68d7c093c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -24,7 +24,7 @@
24 24
25#include <subdev/bios.h> 25#include <subdev/bios.h>
26#include <subdev/bus.h> 26#include <subdev/bus.h>
27#include <subdev/vm.h> 27#include <subdev/mmu.h>
28#include <subdev/gpio.h> 28#include <subdev/gpio.h>
29#include <subdev/i2c.h> 29#include <subdev/i2c.h>
30#include <subdev/clk.h> 30#include <subdev/clk.h>
@@ -34,7 +34,7 @@
34#include <subdev/timer.h> 34#include <subdev/timer.h>
35#include <subdev/fb.h> 35#include <subdev/fb.h>
36#include <subdev/instmem.h> 36#include <subdev/instmem.h>
37#include <subdev/vm.h> 37#include <subdev/mmu.h>
38#include <subdev/volt.h> 38#include <subdev/volt.h>
39 39
40#include <engine/device.h> 40#include <engine/device.h>
@@ -63,7 +63,7 @@ nv40_identify(struct nouveau_device *device)
63 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 63 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
64 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; 64 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
65 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 65 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
66 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 66 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
69 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 69 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -86,7 +86,7 @@ nv40_identify(struct nouveau_device *device)
86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
87 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; 87 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
88 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 88 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
89 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 89 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
92 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 92 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -109,7 +109,7 @@ nv40_identify(struct nouveau_device *device)
109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
110 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; 110 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
112 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 112 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
113 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 113 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
114 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 114 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
115 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 115 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -132,7 +132,7 @@ nv40_identify(struct nouveau_device *device)
132 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 132 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
133 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; 133 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
134 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 134 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
135 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 135 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
138 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 138 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -155,7 +155,7 @@ nv40_identify(struct nouveau_device *device)
155 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 155 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
156 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; 156 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
157 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 157 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
158 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 158 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
159 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 159 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
160 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 160 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
161 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 161 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -178,7 +178,7 @@ nv40_identify(struct nouveau_device *device)
178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
179 device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; 179 device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
180 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 180 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
181 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 181 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
182 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 182 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
183 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 183 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
184 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 184 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -201,7 +201,7 @@ nv40_identify(struct nouveau_device *device)
201 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 201 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
202 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; 202 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
203 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 203 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
204 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 204 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
206 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 206 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
207 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 207 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -224,7 +224,7 @@ nv40_identify(struct nouveau_device *device)
224 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 224 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
225 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; 225 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
226 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 226 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
227 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 227 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
228 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 228 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
229 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 229 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
230 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 230 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -247,7 +247,7 @@ nv40_identify(struct nouveau_device *device)
247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
248 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; 248 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
249 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 249 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
250 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 250 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
253 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 253 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -270,7 +270,7 @@ nv40_identify(struct nouveau_device *device)
270 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 270 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
271 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 271 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
272 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 272 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
273 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 273 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
276 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 276 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -293,7 +293,7 @@ nv40_identify(struct nouveau_device *device)
293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
294 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; 294 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
295 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 295 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
296 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 296 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
299 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 299 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -316,7 +316,7 @@ nv40_identify(struct nouveau_device *device)
316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
317 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 317 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
318 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 318 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
319 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 319 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
320 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 320 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
321 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 321 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
322 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 322 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -339,7 +339,7 @@ nv40_identify(struct nouveau_device *device)
339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
340 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; 340 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
341 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 341 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
342 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 342 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
343 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 343 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
344 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 344 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
345 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 345 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -362,7 +362,7 @@ nv40_identify(struct nouveau_device *device)
362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
363 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 363 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
364 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 364 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
365 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 365 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
367 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 367 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
368 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 368 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -385,7 +385,7 @@ nv40_identify(struct nouveau_device *device)
385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
386 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 386 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
387 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 387 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
388 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 388 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
389 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 389 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
390 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 390 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
391 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 391 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -408,7 +408,7 @@ nv40_identify(struct nouveau_device *device)
408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
409 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 409 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
410 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; 410 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
411 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 411 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
412 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 412 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
413 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 413 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
414 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 414 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 867b79a0679a..f9afee4f844d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -35,7 +35,7 @@
35#include <subdev/timer.h> 35#include <subdev/timer.h>
36#include <subdev/fb.h> 36#include <subdev/fb.h>
37#include <subdev/instmem.h> 37#include <subdev/instmem.h>
38#include <subdev/vm.h> 38#include <subdev/mmu.h>
39#include <subdev/bar.h> 39#include <subdev/bar.h>
40#include <subdev/pmu.h> 40#include <subdev/pmu.h>
41#include <subdev/volt.h> 41#include <subdev/volt.h>
@@ -73,7 +73,7 @@ nv50_identify(struct nouveau_device *device)
73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
74 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; 74 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
76 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 76 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
77 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 77 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
78 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 78 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
79 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 79 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -99,7 +99,7 @@ nv50_identify(struct nouveau_device *device)
99 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 99 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
100 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 100 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
101 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 101 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
102 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 102 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
103 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 103 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
104 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 104 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -128,7 +128,7 @@ nv50_identify(struct nouveau_device *device)
128 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 128 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
129 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 129 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
130 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 130 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
131 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 131 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
132 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 132 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
133 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 133 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
134 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 134 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -157,7 +157,7 @@ nv50_identify(struct nouveau_device *device)
157 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 157 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
158 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 158 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
159 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 159 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
160 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 160 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
161 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 161 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
162 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 162 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
163 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 163 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -186,7 +186,7 @@ nv50_identify(struct nouveau_device *device)
186 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 186 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
187 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 187 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
188 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 188 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
189 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 189 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
190 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 190 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
191 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 191 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -215,7 +215,7 @@ nv50_identify(struct nouveau_device *device)
215 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 215 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
216 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 216 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
217 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 217 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
218 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 218 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
219 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 219 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
220 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 220 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
221 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 221 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -244,7 +244,7 @@ nv50_identify(struct nouveau_device *device)
244 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 244 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
245 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 245 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
246 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 246 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
247 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 247 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
248 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 248 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
249 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 249 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
250 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 250 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -273,7 +273,7 @@ nv50_identify(struct nouveau_device *device)
273 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 273 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
274 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 274 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
275 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 275 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
276 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 276 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
277 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 277 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
278 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 278 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
279 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 279 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -302,7 +302,7 @@ nv50_identify(struct nouveau_device *device)
302 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 302 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
303 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; 303 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
304 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 304 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
305 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 305 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
306 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 306 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
307 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 307 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
308 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 308 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -331,7 +331,7 @@ nv50_identify(struct nouveau_device *device)
331 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 331 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
332 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; 332 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
333 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 333 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
334 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 334 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
335 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 335 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
336 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 336 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
337 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 337 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -360,7 +360,7 @@ nv50_identify(struct nouveau_device *device)
360 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 360 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
361 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; 361 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
362 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 362 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
363 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 363 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
364 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 364 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
365 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; 365 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -391,7 +391,7 @@ nv50_identify(struct nouveau_device *device)
391 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 391 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
392 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; 392 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
393 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 393 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
394 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 394 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
395 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 395 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
396 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; 396 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
397 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 397 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -421,7 +421,7 @@ nv50_identify(struct nouveau_device *device)
421 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 421 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
422 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; 422 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
423 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 423 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
424 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 424 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
425 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 425 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
426 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; 426 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
427 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 427 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -451,7 +451,7 @@ nv50_identify(struct nouveau_device *device)
451 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 451 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
452 device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; 452 device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
453 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 453 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
454 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 454 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
455 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 455 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
456 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; 456 device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
457 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 457 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index d54d6ac4cea5..0db51092732a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -37,7 +37,7 @@
37#include <subdev/ltc.h> 37#include <subdev/ltc.h>
38#include <subdev/ibus.h> 38#include <subdev/ibus.h>
39#include <subdev/instmem.h> 39#include <subdev/instmem.h>
40#include <subdev/vm.h> 40#include <subdev/mmu.h>
41#include <subdev/bar.h> 41#include <subdev/bar.h>
42#include <subdev/pmu.h> 42#include <subdev/pmu.h>
43#include <subdev/volt.h> 43#include <subdev/volt.h>
@@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device)
75 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 75 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
78 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 78 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
79 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 79 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
80 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 80 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
81 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 81 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -108,7 +108,7 @@ nvc0_identify(struct nouveau_device *device)
108 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 108 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
109 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 109 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
110 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 110 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
111 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 111 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
112 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 112 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
113 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 113 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
114 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 114 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -141,7 +141,7 @@ nvc0_identify(struct nouveau_device *device)
141 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 141 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
142 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 142 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
143 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 143 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
144 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 144 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
145 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 145 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
146 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 146 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
147 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 147 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -173,7 +173,7 @@ nvc0_identify(struct nouveau_device *device)
173 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 173 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
174 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 174 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
175 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 175 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
176 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 176 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
177 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 177 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
178 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 178 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
179 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 179 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -206,7 +206,7 @@ nvc0_identify(struct nouveau_device *device)
206 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 206 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
207 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 207 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
208 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 208 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
209 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 209 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
210 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 210 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
211 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 211 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
212 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 212 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -238,7 +238,7 @@ nvc0_identify(struct nouveau_device *device)
238 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 238 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
239 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 239 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
240 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 240 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
241 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 241 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
242 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 242 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
243 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 243 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
244 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 244 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -270,7 +270,7 @@ nvc0_identify(struct nouveau_device *device)
270 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 270 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
271 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 271 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
272 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 272 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
273 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 273 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
274 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 274 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
275 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 275 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
276 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 276 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -303,7 +303,7 @@ nvc0_identify(struct nouveau_device *device)
303 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 303 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
304 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 304 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
305 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 305 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
306 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 306 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
307 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 307 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
308 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 308 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
309 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 309 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -335,7 +335,7 @@ nvc0_identify(struct nouveau_device *device)
335 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 335 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
336 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 336 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
337 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 337 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
338 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 338 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
339 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 339 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
340 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 340 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
341 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 341 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 39b3fe32b9fb..a565bc8b6636 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -37,7 +37,7 @@
37#include <subdev/ltc.h> 37#include <subdev/ltc.h>
38#include <subdev/ibus.h> 38#include <subdev/ibus.h>
39#include <subdev/instmem.h> 39#include <subdev/instmem.h>
40#include <subdev/vm.h> 40#include <subdev/mmu.h>
41#include <subdev/bar.h> 41#include <subdev/bar.h>
42#include <subdev/pmu.h> 42#include <subdev/pmu.h>
43#include <subdev/volt.h> 43#include <subdev/volt.h>
@@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device)
75 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 75 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
78 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 78 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
79 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 79 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
80 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; 80 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
81 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 81 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -109,7 +109,7 @@ nve0_identify(struct nouveau_device *device)
109 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 109 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
110 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 110 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
112 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 112 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
113 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 113 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
114 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 114 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -143,7 +143,7 @@ nve0_identify(struct nouveau_device *device)
143 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 143 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
144 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 144 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
145 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 145 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
146 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 146 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
147 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 147 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
148 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; 148 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
149 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 149 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -171,7 +171,7 @@ nve0_identify(struct nouveau_device *device)
171 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 171 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
172 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; 172 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
173 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 173 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
174 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 174 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
175 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; 175 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
176 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 176 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
177 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; 177 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
@@ -199,7 +199,7 @@ nve0_identify(struct nouveau_device *device)
199 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 199 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
200 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 200 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
201 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 201 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
202 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 202 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
203 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 203 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
204 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 204 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -233,7 +233,7 @@ nve0_identify(struct nouveau_device *device)
233 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 233 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
234 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 234 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
235 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 235 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
236 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 236 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
237 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 237 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
238 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 238 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
239 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 239 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -267,7 +267,7 @@ nve0_identify(struct nouveau_device *device)
267 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 267 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
268 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 268 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
269 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 269 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
270 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 270 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
271 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 271 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
272 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 272 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
273 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 273 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -300,7 +300,7 @@ nve0_identify(struct nouveau_device *device)
300 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 300 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
301 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 301 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
302 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 302 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
303 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 303 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
304 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 304 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
305 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 305 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
306 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 306 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
index 20c9dbfe3b2e..8089310f1157 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
@@ -26,7 +26,7 @@
26#include <nvif/class.h> 26#include <nvif/class.h>
27 27
28#include <subdev/fb.h> 28#include <subdev/fb.h>
29#include <subdev/vm/nv04.h> 29#include <subdev/mmu/nv04.h>
30 30
31#include "priv.h" 31#include "priv.h"
32 32
@@ -62,8 +62,8 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
62 } 62 }
63 63
64 if (priv->clone) { 64 if (priv->clone) {
65 struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj); 65 struct nv04_mmu_priv *mmu = nv04_mmu(dmaobj);
66 struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0]; 66 struct nouveau_gpuobj *pgt = mmu->vm->pgt[0].obj[0];
67 if (!dmaobj->start) 67 if (!dmaobj->start)
68 return nouveau_gpuobj_dup(parent, pgt, pgpuobj); 68 return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
69 offset = nv_ro32(pgt, 8 + (offset >> 10)); 69 offset = nv_ro32(pgt, 8 + (offset >> 10));
@@ -88,7 +88,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
88 struct nouveau_object **pobject) 88 struct nouveau_object **pobject)
89{ 89{
90 struct nouveau_dmaeng *dmaeng = (void *)engine; 90 struct nouveau_dmaeng *dmaeng = (void *)engine;
91 struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine); 91 struct nv04_mmu_priv *mmu = nv04_mmu(engine);
92 struct nv04_dmaobj_priv *priv; 92 struct nv04_dmaobj_priv *priv;
93 int ret; 93 int ret;
94 94
@@ -98,7 +98,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
98 return ret; 98 return ret;
99 99
100 if (priv->base.target == NV_MEM_TARGET_VM) { 100 if (priv->base.target == NV_MEM_TARGET_VM) {
101 if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) 101 if (nv_object(mmu)->oclass == &nv04_mmu_oclass)
102 priv->clone = true; 102 priv->clone = true;
103 priv->base.target = NV_MEM_TARGET_PCI; 103 priv->base.target = NV_MEM_TARGET_PCI;
104 priv->base.access = NV_MEM_ACCESS_RW; 104 priv->base.access = NV_MEM_ACCESS_RW;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index e8ef8cb058cd..e5d1e969945e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -35,7 +35,7 @@
35#include <subdev/timer.h> 35#include <subdev/timer.h>
36#include <subdev/bar.h> 36#include <subdev/bar.h>
37#include <subdev/fb.h> 37#include <subdev/fb.h>
38#include <subdev/vm.h> 38#include <subdev/mmu.h>
39 39
40#include <engine/dmaobj.h> 40#include <engine/dmaobj.h>
41#include <engine/fifo.h> 41#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index c9c168035b4d..bf2b9e2df3d0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -35,7 +35,7 @@
35#include <subdev/timer.h> 35#include <subdev/timer.h>
36#include <subdev/bar.h> 36#include <subdev/bar.h>
37#include <subdev/fb.h> 37#include <subdev/fb.h>
38#include <subdev/vm.h> 38#include <subdev/mmu.h>
39 39
40#include <engine/dmaobj.h> 40#include <engine/dmaobj.h>
41 41
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
index 38e0aa26f1cd..896e17b56f45 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
@@ -29,7 +29,7 @@
29#include <core/enum.h> 29#include <core/enum.h>
30 30
31#include <subdev/fb.h> 31#include <subdev/fb.h>
32#include <subdev/vm.h> 32#include <subdev/mmu.h>
33#include <subdev/timer.h> 33#include <subdev/timer.h>
34 34
35#include <engine/fifo.h> 35#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
index 7ed9e89c3435..86b7735242e1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
@@ -34,7 +34,7 @@
34#include <nvif/class.h> 34#include <nvif/class.h>
35 35
36#include <subdev/fb.h> 36#include <subdev/fb.h>
37#include <subdev/vm.h> 37#include <subdev/mmu.h>
38#include <subdev/bar.h> 38#include <subdev/bar.h>
39#include <subdev/timer.h> 39#include <subdev/timer.h>
40#include <subdev/mc.h> 40#include <subdev/mc.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
index cae33f86b11a..b62c301b31a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
@@ -25,7 +25,7 @@
25#include <core/os.h> 25#include <core/os.h>
26#include <core/engctx.h> 26#include <core/engctx.h>
27 27
28#include <subdev/vm.h> 28#include <subdev/mmu.h>
29#include <subdev/bar.h> 29#include <subdev/bar.h>
30#include <subdev/timer.h> 30#include <subdev/timer.h>
31 31
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
index e9cc8b116a24..97c8343e1a08 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
@@ -25,7 +25,7 @@
25#include <core/os.h> 25#include <core/os.h>
26#include <core/engctx.h> 26#include <core/engctx.h>
27 27
28#include <subdev/vm.h> 28#include <subdev/mmu.h>
29#include <subdev/bar.h> 29#include <subdev/bar.h>
30#include <subdev/timer.h> 30#include <subdev/timer.h>
31 31
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index 55090f73bab4..dbcea4930a1d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -15,5 +15,5 @@ include $(src)/nvkm/subdev/mxm/Kbuild
15include $(src)/nvkm/subdev/pmu/Kbuild 15include $(src)/nvkm/subdev/pmu/Kbuild
16include $(src)/nvkm/subdev/therm/Kbuild 16include $(src)/nvkm/subdev/therm/Kbuild
17include $(src)/nvkm/subdev/timer/Kbuild 17include $(src)/nvkm/subdev/timer/Kbuild
18include $(src)/nvkm/subdev/vm/Kbuild 18include $(src)/nvkm/subdev/mmu/Kbuild
19include $(src)/nvkm/subdev/volt/Kbuild 19include $(src)/nvkm/subdev/volt/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
index 188c638411b2..1b37afe4a4ea 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
@@ -25,7 +25,7 @@
25#include <core/object.h> 25#include <core/object.h>
26 26
27#include <subdev/fb.h> 27#include <subdev/fb.h>
28#include <subdev/vm.h> 28#include <subdev/mmu.h>
29 29
30#include "priv.h" 30#include "priv.h"
31 31
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
index f748ba49dfc8..6d0dd6a01e64 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
@@ -26,7 +26,7 @@
26 26
27#include <subdev/timer.h> 27#include <subdev/timer.h>
28#include <subdev/fb.h> 28#include <subdev/fb.h>
29#include <subdev/vm.h> 29#include <subdev/mmu.h>
30 30
31#include "priv.h" 31#include "priv.h"
32 32
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
index 8320ee0509c3..c7ac57ba8e35 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
@@ -26,7 +26,7 @@
26 26
27#include <subdev/timer.h> 27#include <subdev/timer.h>
28#include <subdev/fb.h> 28#include <subdev/fb.h>
29#include <subdev/vm.h> 29#include <subdev/mmu.h>
30 30
31#include "priv.h" 31#include "priv.h"
32 32
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
new file mode 100644
index 000000000000..729e27f2cbd4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
@@ -0,0 +1,6 @@
1nvkm-y += nvkm/subdev/mmu/base.o
2nvkm-y += nvkm/subdev/mmu/nv04.o
3nvkm-y += nvkm/subdev/mmu/nv41.o
4nvkm-y += nvkm/subdev/mmu/nv44.o
5nvkm-y += nvkm/subdev/mmu/nv50.o
6nvkm-y += nvkm/subdev/mmu/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
index f75a683bd47a..e3cb186c440b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
@@ -26,20 +26,20 @@
26#include <core/mm.h> 26#include <core/mm.h>
27 27
28#include <subdev/fb.h> 28#include <subdev/fb.h>
29#include <subdev/vm.h> 29#include <subdev/mmu.h>
30 30
31void 31void
32nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) 32nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
33{ 33{
34 struct nouveau_vm *vm = vma->vm; 34 struct nouveau_vm *vm = vma->vm;
35 struct nouveau_vmmgr *vmm = vm->vmm; 35 struct nouveau_mmu *mmu = vm->mmu;
36 struct nouveau_mm_node *r; 36 struct nouveau_mm_node *r;
37 int big = vma->node->type != vmm->spg_shift; 37 int big = vma->node->type != mmu->spg_shift;
38 u32 offset = vma->node->offset + (delta >> 12); 38 u32 offset = vma->node->offset + (delta >> 12);
39 u32 bits = vma->node->type - 12; 39 u32 bits = vma->node->type - 12;
40 u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; 40 u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
41 u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; 41 u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
42 u32 max = 1 << (vmm->pgt_bits - bits); 42 u32 max = 1 << (mmu->pgt_bits - bits);
43 u32 end, len; 43 u32 end, len;
44 44
45 delta = 0; 45 delta = 0;
@@ -55,7 +55,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
55 end = max; 55 end = max;
56 len = end - pte; 56 len = end - pte;
57 57
58 vmm->map(vma, pgt, node, pte, len, phys, delta); 58 mmu->map(vma, pgt, node, pte, len, phys, delta);
59 59
60 num -= len; 60 num -= len;
61 pte += len; 61 pte += len;
@@ -69,7 +69,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
69 } 69 }
70 } 70 }
71 71
72 vmm->flush(vm); 72 mmu->flush(vm);
73} 73}
74 74
75static void 75static void
@@ -77,14 +77,14 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
77 struct nouveau_mem *mem) 77 struct nouveau_mem *mem)
78{ 78{
79 struct nouveau_vm *vm = vma->vm; 79 struct nouveau_vm *vm = vma->vm;
80 struct nouveau_vmmgr *vmm = vm->vmm; 80 struct nouveau_mmu *mmu = vm->mmu;
81 int big = vma->node->type != vmm->spg_shift; 81 int big = vma->node->type != mmu->spg_shift;
82 u32 offset = vma->node->offset + (delta >> 12); 82 u32 offset = vma->node->offset + (delta >> 12);
83 u32 bits = vma->node->type - 12; 83 u32 bits = vma->node->type - 12;
84 u32 num = length >> vma->node->type; 84 u32 num = length >> vma->node->type;
85 u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; 85 u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
86 u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; 86 u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
87 u32 max = 1 << (vmm->pgt_bits - bits); 87 u32 max = 1 << (mmu->pgt_bits - bits);
88 unsigned m, sglen; 88 unsigned m, sglen;
89 u32 end, len; 89 u32 end, len;
90 int i; 90 int i;
@@ -102,7 +102,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
102 for (m = 0; m < len; m++) { 102 for (m = 0; m < len; m++) {
103 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 103 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
104 104
105 vmm->map_sg(vma, pgt, mem, pte, 1, &addr); 105 mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
106 num--; 106 num--;
107 pte++; 107 pte++;
108 108
@@ -117,7 +117,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
117 for (; m < sglen; m++) { 117 for (; m < sglen; m++) {
118 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 118 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
119 119
120 vmm->map_sg(vma, pgt, mem, pte, 1, &addr); 120 mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
121 num--; 121 num--;
122 pte++; 122 pte++;
123 if (num == 0) 123 if (num == 0)
@@ -127,7 +127,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
127 127
128 } 128 }
129finish: 129finish:
130 vmm->flush(vm); 130 mmu->flush(vm);
131} 131}
132 132
133static void 133static void
@@ -135,15 +135,15 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
135 struct nouveau_mem *mem) 135 struct nouveau_mem *mem)
136{ 136{
137 struct nouveau_vm *vm = vma->vm; 137 struct nouveau_vm *vm = vma->vm;
138 struct nouveau_vmmgr *vmm = vm->vmm; 138 struct nouveau_mmu *mmu = vm->mmu;
139 dma_addr_t *list = mem->pages; 139 dma_addr_t *list = mem->pages;
140 int big = vma->node->type != vmm->spg_shift; 140 int big = vma->node->type != mmu->spg_shift;
141 u32 offset = vma->node->offset + (delta >> 12); 141 u32 offset = vma->node->offset + (delta >> 12);
142 u32 bits = vma->node->type - 12; 142 u32 bits = vma->node->type - 12;
143 u32 num = length >> vma->node->type; 143 u32 num = length >> vma->node->type;
144 u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; 144 u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
145 u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; 145 u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
146 u32 max = 1 << (vmm->pgt_bits - bits); 146 u32 max = 1 << (mmu->pgt_bits - bits);
147 u32 end, len; 147 u32 end, len;
148 148
149 while (num) { 149 while (num) {
@@ -154,7 +154,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
154 end = max; 154 end = max;
155 len = end - pte; 155 len = end - pte;
156 156
157 vmm->map_sg(vma, pgt, mem, pte, len, list); 157 mmu->map_sg(vma, pgt, mem, pte, len, list);
158 158
159 num -= len; 159 num -= len;
160 pte += len; 160 pte += len;
@@ -165,7 +165,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
165 } 165 }
166 } 166 }
167 167
168 vmm->flush(vm); 168 mmu->flush(vm);
169} 169}
170 170
171void 171void
@@ -184,14 +184,14 @@ void
184nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) 184nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
185{ 185{
186 struct nouveau_vm *vm = vma->vm; 186 struct nouveau_vm *vm = vma->vm;
187 struct nouveau_vmmgr *vmm = vm->vmm; 187 struct nouveau_mmu *mmu = vm->mmu;
188 int big = vma->node->type != vmm->spg_shift; 188 int big = vma->node->type != mmu->spg_shift;
189 u32 offset = vma->node->offset + (delta >> 12); 189 u32 offset = vma->node->offset + (delta >> 12);
190 u32 bits = vma->node->type - 12; 190 u32 bits = vma->node->type - 12;
191 u32 num = length >> vma->node->type; 191 u32 num = length >> vma->node->type;
192 u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; 192 u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
193 u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; 193 u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
194 u32 max = 1 << (vmm->pgt_bits - bits); 194 u32 max = 1 << (mmu->pgt_bits - bits);
195 u32 end, len; 195 u32 end, len;
196 196
197 while (num) { 197 while (num) {
@@ -202,7 +202,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
202 end = max; 202 end = max;
203 len = end - pte; 203 len = end - pte;
204 204
205 vmm->unmap(pgt, pte, len); 205 mmu->unmap(pgt, pte, len);
206 206
207 num -= len; 207 num -= len;
208 pte += len; 208 pte += len;
@@ -212,7 +212,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
212 } 212 }
213 } 213 }
214 214
215 vmm->flush(vm); 215 mmu->flush(vm);
216} 216}
217 217
218void 218void
@@ -224,7 +224,7 @@ nouveau_vm_unmap(struct nouveau_vma *vma)
224static void 224static void
225nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) 225nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
226{ 226{
227 struct nouveau_vmmgr *vmm = vm->vmm; 227 struct nouveau_mmu *mmu = vm->mmu;
228 struct nouveau_vm_pgd *vpgd; 228 struct nouveau_vm_pgd *vpgd;
229 struct nouveau_vm_pgt *vpgt; 229 struct nouveau_vm_pgt *vpgt;
230 struct nouveau_gpuobj *pgt; 230 struct nouveau_gpuobj *pgt;
@@ -239,47 +239,47 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
239 vpgt->obj[big] = NULL; 239 vpgt->obj[big] = NULL;
240 240
241 list_for_each_entry(vpgd, &vm->pgd_list, head) { 241 list_for_each_entry(vpgd, &vm->pgd_list, head) {
242 vmm->map_pgt(vpgd->obj, pde, vpgt->obj); 242 mmu->map_pgt(vpgd->obj, pde, vpgt->obj);
243 } 243 }
244 244
245 mutex_unlock(&nv_subdev(vmm)->mutex); 245 mutex_unlock(&nv_subdev(mmu)->mutex);
246 nouveau_gpuobj_ref(NULL, &pgt); 246 nouveau_gpuobj_ref(NULL, &pgt);
247 mutex_lock(&nv_subdev(vmm)->mutex); 247 mutex_lock(&nv_subdev(mmu)->mutex);
248 } 248 }
249} 249}
250 250
251static int 251static int
252nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) 252nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
253{ 253{
254 struct nouveau_vmmgr *vmm = vm->vmm; 254 struct nouveau_mmu *mmu = vm->mmu;
255 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; 255 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
256 struct nouveau_vm_pgd *vpgd; 256 struct nouveau_vm_pgd *vpgd;
257 struct nouveau_gpuobj *pgt; 257 struct nouveau_gpuobj *pgt;
258 int big = (type != vmm->spg_shift); 258 int big = (type != mmu->spg_shift);
259 u32 pgt_size; 259 u32 pgt_size;
260 int ret; 260 int ret;
261 261
262 pgt_size = (1 << (vmm->pgt_bits + 12)) >> type; 262 pgt_size = (1 << (mmu->pgt_bits + 12)) >> type;
263 pgt_size *= 8; 263 pgt_size *= 8;
264 264
265 mutex_unlock(&nv_subdev(vmm)->mutex); 265 mutex_unlock(&nv_subdev(mmu)->mutex);
266 ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000, 266 ret = nouveau_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000,
267 NVOBJ_FLAG_ZERO_ALLOC, &pgt); 267 NVOBJ_FLAG_ZERO_ALLOC, &pgt);
268 mutex_lock(&nv_subdev(vmm)->mutex); 268 mutex_lock(&nv_subdev(mmu)->mutex);
269 if (unlikely(ret)) 269 if (unlikely(ret))
270 return ret; 270 return ret;
271 271
272 /* someone beat us to filling the PDE while we didn't have the lock */ 272 /* someone beat us to filling the PDE while we didn't have the lock */
273 if (unlikely(vpgt->refcount[big]++)) { 273 if (unlikely(vpgt->refcount[big]++)) {
274 mutex_unlock(&nv_subdev(vmm)->mutex); 274 mutex_unlock(&nv_subdev(mmu)->mutex);
275 nouveau_gpuobj_ref(NULL, &pgt); 275 nouveau_gpuobj_ref(NULL, &pgt);
276 mutex_lock(&nv_subdev(vmm)->mutex); 276 mutex_lock(&nv_subdev(mmu)->mutex);
277 return 0; 277 return 0;
278 } 278 }
279 279
280 vpgt->obj[big] = pgt; 280 vpgt->obj[big] = pgt;
281 list_for_each_entry(vpgd, &vm->pgd_list, head) { 281 list_for_each_entry(vpgd, &vm->pgd_list, head) {
282 vmm->map_pgt(vpgd->obj, pde, vpgt->obj); 282 mmu->map_pgt(vpgd->obj, pde, vpgt->obj);
283 } 283 }
284 284
285 return 0; 285 return 0;
@@ -289,26 +289,26 @@ int
289nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, 289nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
290 u32 access, struct nouveau_vma *vma) 290 u32 access, struct nouveau_vma *vma)
291{ 291{
292 struct nouveau_vmmgr *vmm = vm->vmm; 292 struct nouveau_mmu *mmu = vm->mmu;
293 u32 align = (1 << page_shift) >> 12; 293 u32 align = (1 << page_shift) >> 12;
294 u32 msize = size >> 12; 294 u32 msize = size >> 12;
295 u32 fpde, lpde, pde; 295 u32 fpde, lpde, pde;
296 int ret; 296 int ret;
297 297
298 mutex_lock(&nv_subdev(vmm)->mutex); 298 mutex_lock(&nv_subdev(mmu)->mutex);
299 ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, 299 ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
300 &vma->node); 300 &vma->node);
301 if (unlikely(ret != 0)) { 301 if (unlikely(ret != 0)) {
302 mutex_unlock(&nv_subdev(vmm)->mutex); 302 mutex_unlock(&nv_subdev(mmu)->mutex);
303 return ret; 303 return ret;
304 } 304 }
305 305
306 fpde = (vma->node->offset >> vmm->pgt_bits); 306 fpde = (vma->node->offset >> mmu->pgt_bits);
307 lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; 307 lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
308 308
309 for (pde = fpde; pde <= lpde; pde++) { 309 for (pde = fpde; pde <= lpde; pde++) {
310 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; 310 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
311 int big = (vma->node->type != vmm->spg_shift); 311 int big = (vma->node->type != mmu->spg_shift);
312 312
313 if (likely(vpgt->refcount[big])) { 313 if (likely(vpgt->refcount[big])) {
314 vpgt->refcount[big]++; 314 vpgt->refcount[big]++;
@@ -320,11 +320,11 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
320 if (pde != fpde) 320 if (pde != fpde)
321 nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1); 321 nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1);
322 nouveau_mm_free(&vm->mm, &vma->node); 322 nouveau_mm_free(&vm->mm, &vma->node);
323 mutex_unlock(&nv_subdev(vmm)->mutex); 323 mutex_unlock(&nv_subdev(mmu)->mutex);
324 return ret; 324 return ret;
325 } 325 }
326 } 326 }
327 mutex_unlock(&nv_subdev(vmm)->mutex); 327 mutex_unlock(&nv_subdev(mmu)->mutex);
328 328
329 vma->vm = NULL; 329 vma->vm = NULL;
330 nouveau_vm_ref(vm, &vma->vm, NULL); 330 nouveau_vm_ref(vm, &vma->vm, NULL);
@@ -337,24 +337,24 @@ void
337nouveau_vm_put(struct nouveau_vma *vma) 337nouveau_vm_put(struct nouveau_vma *vma)
338{ 338{
339 struct nouveau_vm *vm = vma->vm; 339 struct nouveau_vm *vm = vma->vm;
340 struct nouveau_vmmgr *vmm = vm->vmm; 340 struct nouveau_mmu *mmu = vm->mmu;
341 u32 fpde, lpde; 341 u32 fpde, lpde;
342 342
343 if (unlikely(vma->node == NULL)) 343 if (unlikely(vma->node == NULL))
344 return; 344 return;
345 fpde = (vma->node->offset >> vmm->pgt_bits); 345 fpde = (vma->node->offset >> mmu->pgt_bits);
346 lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; 346 lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
347 347
348 mutex_lock(&nv_subdev(vmm)->mutex); 348 mutex_lock(&nv_subdev(mmu)->mutex);
349 nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde); 349 nouveau_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde);
350 nouveau_mm_free(&vm->mm, &vma->node); 350 nouveau_mm_free(&vm->mm, &vma->node);
351 mutex_unlock(&nv_subdev(vmm)->mutex); 351 mutex_unlock(&nv_subdev(mmu)->mutex);
352 352
353 nouveau_vm_ref(NULL, &vma->vm, NULL); 353 nouveau_vm_ref(NULL, &vma->vm, NULL);
354} 354}
355 355
356int 356int
357nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, 357nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
358 u64 mm_offset, u32 block, struct nouveau_vm **pvm) 358 u64 mm_offset, u32 block, struct nouveau_vm **pvm)
359{ 359{
360 struct nouveau_vm *vm; 360 struct nouveau_vm *vm;
@@ -366,10 +366,10 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
366 return -ENOMEM; 366 return -ENOMEM;
367 367
368 INIT_LIST_HEAD(&vm->pgd_list); 368 INIT_LIST_HEAD(&vm->pgd_list);
369 vm->vmm = vmm; 369 vm->mmu = mmu;
370 kref_init(&vm->refcount); 370 kref_init(&vm->refcount);
371 vm->fpde = offset >> (vmm->pgt_bits + 12); 371 vm->fpde = offset >> (mmu->pgt_bits + 12);
372 vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); 372 vm->lpde = (offset + length - 1) >> (mmu->pgt_bits + 12);
373 373
374 vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); 374 vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt));
375 if (!vm->pgt) { 375 if (!vm->pgt) {
@@ -394,14 +394,14 @@ int
394nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length, 394nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length,
395 u64 mm_offset, struct nouveau_vm **pvm) 395 u64 mm_offset, struct nouveau_vm **pvm)
396{ 396{
397 struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); 397 struct nouveau_mmu *mmu = nouveau_mmu(device);
398 return vmm->create(vmm, offset, length, mm_offset, pvm); 398 return mmu->create(mmu, offset, length, mm_offset, pvm);
399} 399}
400 400
401static int 401static int
402nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) 402nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
403{ 403{
404 struct nouveau_vmmgr *vmm = vm->vmm; 404 struct nouveau_mmu *mmu = vm->mmu;
405 struct nouveau_vm_pgd *vpgd; 405 struct nouveau_vm_pgd *vpgd;
406 int i; 406 int i;
407 407
@@ -414,25 +414,25 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
414 414
415 nouveau_gpuobj_ref(pgd, &vpgd->obj); 415 nouveau_gpuobj_ref(pgd, &vpgd->obj);
416 416
417 mutex_lock(&nv_subdev(vmm)->mutex); 417 mutex_lock(&nv_subdev(mmu)->mutex);
418 for (i = vm->fpde; i <= vm->lpde; i++) 418 for (i = vm->fpde; i <= vm->lpde; i++)
419 vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj); 419 mmu->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
420 list_add(&vpgd->head, &vm->pgd_list); 420 list_add(&vpgd->head, &vm->pgd_list);
421 mutex_unlock(&nv_subdev(vmm)->mutex); 421 mutex_unlock(&nv_subdev(mmu)->mutex);
422 return 0; 422 return 0;
423} 423}
424 424
425static void 425static void
426nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) 426nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
427{ 427{
428 struct nouveau_vmmgr *vmm = vm->vmm; 428 struct nouveau_mmu *mmu = vm->mmu;
429 struct nouveau_vm_pgd *vpgd, *tmp; 429 struct nouveau_vm_pgd *vpgd, *tmp;
430 struct nouveau_gpuobj *pgd = NULL; 430 struct nouveau_gpuobj *pgd = NULL;
431 431
432 if (!mpgd) 432 if (!mpgd)
433 return; 433 return;
434 434
435 mutex_lock(&nv_subdev(vmm)->mutex); 435 mutex_lock(&nv_subdev(mmu)->mutex);
436 list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { 436 list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
437 if (vpgd->obj == mpgd) { 437 if (vpgd->obj == mpgd) {
438 pgd = vpgd->obj; 438 pgd = vpgd->obj;
@@ -441,7 +441,7 @@ nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
441 break; 441 break;
442 } 442 }
443 } 443 }
444 mutex_unlock(&nv_subdev(vmm)->mutex); 444 mutex_unlock(&nv_subdev(mmu)->mutex);
445 445
446 nouveau_gpuobj_ref(NULL, &pgd); 446 nouveau_gpuobj_ref(NULL, &pgd);
447} 447}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
index ed45437167f2..a317d8f13570 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
@@ -70,26 +70,26 @@ nv04_vm_flush(struct nouveau_vm *vm)
70 ******************************************************************************/ 70 ******************************************************************************/
71 71
72int 72int
73nv04_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, u64 mmstart, 73nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart,
74 struct nouveau_vm **pvm) 74 struct nouveau_vm **pvm)
75{ 75{
76 return -EINVAL; 76 return -EINVAL;
77} 77}
78 78
79/******************************************************************************* 79/*******************************************************************************
80 * VMMGR subdev 80 * MMU subdev
81 ******************************************************************************/ 81 ******************************************************************************/
82 82
83static int 83static int
84nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 84nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
85 struct nouveau_oclass *oclass, void *data, u32 size, 85 struct nouveau_oclass *oclass, void *data, u32 size,
86 struct nouveau_object **pobject) 86 struct nouveau_object **pobject)
87{ 87{
88 struct nv04_vmmgr_priv *priv; 88 struct nv04_mmu_priv *priv;
89 struct nouveau_gpuobj *dma; 89 struct nouveau_gpuobj *dma;
90 int ret; 90 int ret;
91 91
92 ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIGART", 92 ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART",
93 "pcigart", &priv); 93 "pcigart", &priv);
94 *pobject = nv_object(priv); 94 *pobject = nv_object(priv);
95 if (ret) 95 if (ret)
@@ -125,9 +125,9 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
125} 125}
126 126
127void 127void
128nv04_vmmgr_dtor(struct nouveau_object *object) 128nv04_mmu_dtor(struct nouveau_object *object)
129{ 129{
130 struct nv04_vmmgr_priv *priv = (void *)object; 130 struct nv04_mmu_priv *priv = (void *)object;
131 if (priv->vm) { 131 if (priv->vm) {
132 nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); 132 nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
133 nouveau_vm_ref(NULL, &priv->vm, NULL); 133 nouveau_vm_ref(NULL, &priv->vm, NULL);
@@ -136,16 +136,16 @@ nv04_vmmgr_dtor(struct nouveau_object *object)
136 pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, 136 pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
137 priv->nullp, priv->null); 137 priv->nullp, priv->null);
138 } 138 }
139 nouveau_vmmgr_destroy(&priv->base); 139 nouveau_mmu_destroy(&priv->base);
140} 140}
141 141
142struct nouveau_oclass 142struct nouveau_oclass
143nv04_vmmgr_oclass = { 143nv04_mmu_oclass = {
144 .handle = NV_SUBDEV(VM, 0x04), 144 .handle = NV_SUBDEV(MMU, 0x04),
145 .ofuncs = &(struct nouveau_ofuncs) { 145 .ofuncs = &(struct nouveau_ofuncs) {
146 .ctor = nv04_vmmgr_ctor, 146 .ctor = nv04_mmu_ctor,
147 .dtor = nv04_vmmgr_dtor, 147 .dtor = nv04_mmu_dtor,
148 .init = _nouveau_vmmgr_init, 148 .init = _nouveau_mmu_init,
149 .fini = _nouveau_vmmgr_fini, 149 .fini = _nouveau_mmu_fini,
150 }, 150 },
151}; 151};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
new file mode 100644
index 000000000000..919b254ef6a1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
@@ -0,0 +1,19 @@
1#ifndef __NV04_MMU_PRIV__
2#define __NV04_MMU_PRIV__
3
4#include <subdev/mmu.h>
5
6struct nv04_mmu_priv {
7 struct nouveau_mmu base;
8 struct nouveau_vm *vm;
9 dma_addr_t null;
10 void *nullp;
11};
12
13static inline struct nv04_mmu_priv *
14nv04_mmu(void *obj)
15{
16 return (void *)nouveau_mmu(obj);
17}
18
19#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
index 064c76262876..61af036f1252 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
@@ -26,7 +26,7 @@
26#include <core/option.h> 26#include <core/option.h>
27 27
28#include <subdev/timer.h> 28#include <subdev/timer.h>
29#include <subdev/vm.h> 29#include <subdev/mmu.h>
30 30
31#include "nv04.h" 31#include "nv04.h"
32 32
@@ -67,7 +67,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
67static void 67static void
68nv41_vm_flush(struct nouveau_vm *vm) 68nv41_vm_flush(struct nouveau_vm *vm)
69{ 69{
70 struct nv04_vmmgr_priv *priv = (void *)vm->vmm; 70 struct nv04_mmu_priv *priv = (void *)vm->mmu;
71 71
72 mutex_lock(&nv_subdev(priv)->mutex); 72 mutex_lock(&nv_subdev(priv)->mutex);
73 nv_wr32(priv, 0x100810, 0x00000022); 73 nv_wr32(priv, 0x100810, 0x00000022);
@@ -80,25 +80,25 @@ nv41_vm_flush(struct nouveau_vm *vm)
80} 80}
81 81
82/******************************************************************************* 82/*******************************************************************************
83 * VMMGR subdev 83 * MMU subdev
84 ******************************************************************************/ 84 ******************************************************************************/
85 85
86static int 86static int
87nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 87nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
88 struct nouveau_oclass *oclass, void *data, u32 size, 88 struct nouveau_oclass *oclass, void *data, u32 size,
89 struct nouveau_object **pobject) 89 struct nouveau_object **pobject)
90{ 90{
91 struct nouveau_device *device = nv_device(parent); 91 struct nouveau_device *device = nv_device(parent);
92 struct nv04_vmmgr_priv *priv; 92 struct nv04_mmu_priv *priv;
93 int ret; 93 int ret;
94 94
95 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || 95 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
96 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { 96 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
97 return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, 97 return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
98 data, size, pobject); 98 data, size, pobject);
99 } 99 }
100 100
101 ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", 101 ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
102 "pciegart", &priv); 102 "pciegart", &priv);
103 *pobject = nv_object(priv); 103 *pobject = nv_object(priv);
104 if (ret) 104 if (ret)
@@ -131,13 +131,13 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
131} 131}
132 132
133static int 133static int
134nv41_vmmgr_init(struct nouveau_object *object) 134nv41_mmu_init(struct nouveau_object *object)
135{ 135{
136 struct nv04_vmmgr_priv *priv = (void *)object; 136 struct nv04_mmu_priv *priv = (void *)object;
137 struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; 137 struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0];
138 int ret; 138 int ret;
139 139
140 ret = nouveau_vmmgr_init(&priv->base); 140 ret = nouveau_mmu_init(&priv->base);
141 if (ret) 141 if (ret)
142 return ret; 142 return ret;
143 143
@@ -148,12 +148,12 @@ nv41_vmmgr_init(struct nouveau_object *object)
148} 148}
149 149
150struct nouveau_oclass 150struct nouveau_oclass
151nv41_vmmgr_oclass = { 151nv41_mmu_oclass = {
152 .handle = NV_SUBDEV(VM, 0x41), 152 .handle = NV_SUBDEV(MMU, 0x41),
153 .ofuncs = &(struct nouveau_ofuncs) { 153 .ofuncs = &(struct nouveau_ofuncs) {
154 .ctor = nv41_vmmgr_ctor, 154 .ctor = nv41_mmu_ctor,
155 .dtor = nv04_vmmgr_dtor, 155 .dtor = nv04_mmu_dtor,
156 .init = nv41_vmmgr_init, 156 .init = nv41_mmu_init,
157 .fini = _nouveau_vmmgr_fini, 157 .fini = _nouveau_mmu_fini,
158 }, 158 },
159}; 159};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
index fae1f67d5948..f5319e3e7fe5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
@@ -26,7 +26,7 @@
26#include <core/option.h> 26#include <core/option.h>
27 27
28#include <subdev/timer.h> 28#include <subdev/timer.h>
29#include <subdev/vm.h> 29#include <subdev/mmu.h>
30 30
31#include "nv04.h" 31#include "nv04.h"
32 32
@@ -87,7 +87,7 @@ static void
87nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 87nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
88 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 88 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
89{ 89{
90 struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm; 90 struct nv04_mmu_priv *priv = (void *)vma->vm->mmu;
91 u32 tmp[4]; 91 u32 tmp[4];
92 int i; 92 int i;
93 93
@@ -117,7 +117,7 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
117static void 117static void
118nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) 118nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
119{ 119{
120 struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt); 120 struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt);
121 121
122 if (pte & 3) { 122 if (pte & 3) {
123 u32 max = 4 - (pte & 3); 123 u32 max = 4 - (pte & 3);
@@ -142,7 +142,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
142static void 142static void
143nv44_vm_flush(struct nouveau_vm *vm) 143nv44_vm_flush(struct nouveau_vm *vm)
144{ 144{
145 struct nv04_vmmgr_priv *priv = (void *)vm->vmm; 145 struct nv04_mmu_priv *priv = (void *)vm->mmu;
146 nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); 146 nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
147 nv_wr32(priv, 0x100808, 0x00000020); 147 nv_wr32(priv, 0x100808, 0x00000020);
148 if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001)) 148 if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
@@ -151,25 +151,25 @@ nv44_vm_flush(struct nouveau_vm *vm)
151} 151}
152 152
153/******************************************************************************* 153/*******************************************************************************
154 * VMMGR subdev 154 * MMU subdev
155 ******************************************************************************/ 155 ******************************************************************************/
156 156
157static int 157static int
158nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 158nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
159 struct nouveau_oclass *oclass, void *data, u32 size, 159 struct nouveau_oclass *oclass, void *data, u32 size,
160 struct nouveau_object **pobject) 160 struct nouveau_object **pobject)
161{ 161{
162 struct nouveau_device *device = nv_device(parent); 162 struct nouveau_device *device = nv_device(parent);
163 struct nv04_vmmgr_priv *priv; 163 struct nv04_mmu_priv *priv;
164 int ret; 164 int ret;
165 165
166 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || 166 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
167 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { 167 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
168 return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, 168 return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
169 data, size, pobject); 169 data, size, pobject);
170 } 170 }
171 171
172 ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", 172 ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
173 "pciegart", &priv); 173 "pciegart", &priv);
174 *pobject = nv_object(priv); 174 *pobject = nv_object(priv);
175 if (ret) 175 if (ret)
@@ -208,14 +208,14 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
208} 208}
209 209
210static int 210static int
211nv44_vmmgr_init(struct nouveau_object *object) 211nv44_mmu_init(struct nouveau_object *object)
212{ 212{
213 struct nv04_vmmgr_priv *priv = (void *)object; 213 struct nv04_mmu_priv *priv = (void *)object;
214 struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; 214 struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0];
215 u32 addr; 215 u32 addr;
216 int ret; 216 int ret;
217 217
218 ret = nouveau_vmmgr_init(&priv->base); 218 ret = nouveau_mmu_init(&priv->base);
219 if (ret) 219 if (ret)
220 return ret; 220 return ret;
221 221
@@ -238,12 +238,12 @@ nv44_vmmgr_init(struct nouveau_object *object)
238} 238}
239 239
240struct nouveau_oclass 240struct nouveau_oclass
241nv44_vmmgr_oclass = { 241nv44_mmu_oclass = {
242 .handle = NV_SUBDEV(VM, 0x44), 242 .handle = NV_SUBDEV(MMU, 0x44),
243 .ofuncs = &(struct nouveau_ofuncs) { 243 .ofuncs = &(struct nouveau_ofuncs) {
244 .ctor = nv44_vmmgr_ctor, 244 .ctor = nv44_mmu_ctor,
245 .dtor = nv04_vmmgr_dtor, 245 .dtor = nv04_mmu_dtor,
246 .init = nv44_vmmgr_init, 246 .init = nv44_mmu_init,
247 .fini = _nouveau_vmmgr_fini, 247 .fini = _nouveau_mmu_fini,
248 }, 248 },
249}; 249};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index a4aa81a2173b..6ddc65dc684d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -28,10 +28,10 @@
28#include <subdev/timer.h> 28#include <subdev/timer.h>
29#include <subdev/fb.h> 29#include <subdev/fb.h>
30#include <subdev/bar.h> 30#include <subdev/bar.h>
31#include <subdev/vm.h> 31#include <subdev/mmu.h>
32 32
33struct nv50_vmmgr_priv { 33struct nv50_mmu_priv {
34 struct nouveau_vmmgr base; 34 struct nouveau_mmu base;
35}; 35};
36 36
37static void 37static void
@@ -86,8 +86,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
86 86
87 /* IGPs don't have real VRAM, re-target to stolen system memory */ 87 /* IGPs don't have real VRAM, re-target to stolen system memory */
88 target = 0; 88 target = 0;
89 if (nouveau_fb(vma->vm->vmm)->ram->stolen) { 89 if (nouveau_fb(vma->vm->mmu)->ram->stolen) {
90 phys += nouveau_fb(vma->vm->vmm)->ram->stolen; 90 phys += nouveau_fb(vma->vm->mmu)->ram->stolen;
91 target = 3; 91 target = 3;
92 } 92 }
93 93
@@ -151,7 +151,7 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
151static void 151static void
152nv50_vm_flush(struct nouveau_vm *vm) 152nv50_vm_flush(struct nouveau_vm *vm)
153{ 153{
154 struct nv50_vmmgr_priv *priv = (void *)vm->vmm; 154 struct nv50_mmu_priv *priv = (void *)vm->mmu;
155 struct nouveau_bar *bar = nouveau_bar(priv); 155 struct nouveau_bar *bar = nouveau_bar(priv);
156 struct nouveau_engine *engine; 156 struct nouveau_engine *engine;
157 int i, vme; 157 int i, vme;
@@ -191,25 +191,25 @@ nv50_vm_flush(struct nouveau_vm *vm)
191} 191}
192 192
193static int 193static int
194nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, 194nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
195 u64 mm_offset, struct nouveau_vm **pvm) 195 u64 mm_offset, struct nouveau_vm **pvm)
196{ 196{
197 u32 block = (1 << (vmm->pgt_bits + 12)); 197 u32 block = (1 << (mmu->pgt_bits + 12));
198 if (block > length) 198 if (block > length)
199 block = length; 199 block = length;
200 200
201 return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm); 201 return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm);
202} 202}
203 203
204static int 204static int
205nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 205nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
206 struct nouveau_oclass *oclass, void *data, u32 size, 206 struct nouveau_oclass *oclass, void *data, u32 size,
207 struct nouveau_object **pobject) 207 struct nouveau_object **pobject)
208{ 208{
209 struct nv50_vmmgr_priv *priv; 209 struct nv50_mmu_priv *priv;
210 int ret; 210 int ret;
211 211
212 ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); 212 ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
213 *pobject = nv_object(priv); 213 *pobject = nv_object(priv);
214 if (ret) 214 if (ret)
215 return ret; 215 return ret;
@@ -229,12 +229,12 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
229} 229}
230 230
231struct nouveau_oclass 231struct nouveau_oclass
232nv50_vmmgr_oclass = { 232nv50_mmu_oclass = {
233 .handle = NV_SUBDEV(VM, 0x50), 233 .handle = NV_SUBDEV(MMU, 0x50),
234 .ofuncs = &(struct nouveau_ofuncs) { 234 .ofuncs = &(struct nouveau_ofuncs) {
235 .ctor = nv50_vmmgr_ctor, 235 .ctor = nv50_mmu_ctor,
236 .dtor = _nouveau_vmmgr_dtor, 236 .dtor = _nouveau_mmu_dtor,
237 .init = _nouveau_vmmgr_init, 237 .init = _nouveau_mmu_init,
238 .fini = _nouveau_vmmgr_fini, 238 .fini = _nouveau_mmu_fini,
239 }, 239 },
240}; 240};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
index c0a3389204fa..bd695c59aac7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
@@ -27,12 +27,12 @@
27 27
28#include <subdev/timer.h> 28#include <subdev/timer.h>
29#include <subdev/fb.h> 29#include <subdev/fb.h>
30#include <subdev/vm.h> 30#include <subdev/mmu.h>
31#include <subdev/ltc.h> 31#include <subdev/ltc.h>
32#include <subdev/bar.h> 32#include <subdev/bar.h>
33 33
34struct nvc0_vmmgr_priv { 34struct nvc0_mmu_priv {
35 struct nouveau_vmmgr base; 35 struct nouveau_mmu base;
36}; 36};
37 37
38 38
@@ -116,7 +116,7 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
116 pte <<= 3; 116 pte <<= 3;
117 117
118 if (mem->tag) { 118 if (mem->tag) {
119 struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->vmm); 119 struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu);
120 u32 tag = mem->tag->offset + (delta >> 17); 120 u32 tag = mem->tag->offset + (delta >> 17);
121 phys |= (u64)tag << (32 + 12); 121 phys |= (u64)tag << (32 + 12);
122 next |= (u64)1 << (32 + 12); 122 next |= (u64)1 << (32 + 12);
@@ -162,7 +162,7 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
162static void 162static void
163nvc0_vm_flush(struct nouveau_vm *vm) 163nvc0_vm_flush(struct nouveau_vm *vm)
164{ 164{
165 struct nvc0_vmmgr_priv *priv = (void *)vm->vmm; 165 struct nvc0_mmu_priv *priv = (void *)vm->mmu;
166 struct nouveau_bar *bar = nouveau_bar(priv); 166 struct nouveau_bar *bar = nouveau_bar(priv);
167 struct nouveau_vm_pgd *vpgd; 167 struct nouveau_vm_pgd *vpgd;
168 u32 type; 168 u32 type;
@@ -196,21 +196,21 @@ nvc0_vm_flush(struct nouveau_vm *vm)
196} 196}
197 197
198static int 198static int
199nvc0_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, 199nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
200 u64 mm_offset, struct nouveau_vm **pvm) 200 u64 mm_offset, struct nouveau_vm **pvm)
201{ 201{
202 return nouveau_vm_create(vmm, offset, length, mm_offset, 4096, pvm); 202 return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm);
203} 203}
204 204
205static int 205static int
206nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 206nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
207 struct nouveau_oclass *oclass, void *data, u32 size, 207 struct nouveau_oclass *oclass, void *data, u32 size,
208 struct nouveau_object **pobject) 208 struct nouveau_object **pobject)
209{ 209{
210 struct nvc0_vmmgr_priv *priv; 210 struct nvc0_mmu_priv *priv;
211 int ret; 211 int ret;
212 212
213 ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); 213 ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
214 *pobject = nv_object(priv); 214 *pobject = nv_object(priv);
215 if (ret) 215 if (ret)
216 return ret; 216 return ret;
@@ -230,12 +230,12 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
230} 230}
231 231
232struct nouveau_oclass 232struct nouveau_oclass
233nvc0_vmmgr_oclass = { 233nvc0_mmu_oclass = {
234 .handle = NV_SUBDEV(VM, 0xc0), 234 .handle = NV_SUBDEV(MMU, 0xc0),
235 .ofuncs = &(struct nouveau_ofuncs) { 235 .ofuncs = &(struct nouveau_ofuncs) {
236 .ctor = nvc0_vmmgr_ctor, 236 .ctor = nvc0_mmu_ctor,
237 .dtor = _nouveau_vmmgr_dtor, 237 .dtor = _nouveau_mmu_dtor,
238 .init = _nouveau_vmmgr_init, 238 .init = _nouveau_mmu_init,
239 .fini = _nouveau_vmmgr_fini, 239 .fini = _nouveau_mmu_fini,
240 }, 240 },
241}; 241};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
deleted file mode 100644
index b0290c056630..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
+++ /dev/null
@@ -1,6 +0,0 @@
1nvkm-y += nvkm/subdev/vm/base.o
2nvkm-y += nvkm/subdev/vm/nv04.o
3nvkm-y += nvkm/subdev/vm/nv41.o
4nvkm-y += nvkm/subdev/vm/nv44.o
5nvkm-y += nvkm/subdev/vm/nv50.o
6nvkm-y += nvkm/subdev/vm/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h
deleted file mode 100644
index ec42d4bc86a6..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef __NV04_VMMGR_PRIV__
2#define __NV04_VMMGR_PRIV__
3
4#include <subdev/vm.h>
5
6struct nv04_vmmgr_priv {
7 struct nouveau_vmmgr base;
8 struct nouveau_vm *vm;
9 dma_addr_t null;
10 void *nullp;
11};
12
13static inline struct nv04_vmmgr_priv *
14nv04_vmmgr(void *obj)
15{
16 return (void *)nouveau_vmmgr(obj);
17}
18
19#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 14:36:58 -0400