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authorLarry Finger <Larry.Finger@lwfinger.net>2014-09-26 17:40:25 -0400
committerJohn W. Linville <linville@tuxdriver.com>2014-09-30 13:17:15 -0400
commit5c99f04fec93068147a3e95b439b345f203ac5b9 (patch)
treed0dd2086ff7f0ca5588d5fedec2f9b3a6f03ef4a
parent0529c6b8176135bcae1ab66bed6c1288456fbdec (diff)
rtlwifi: rtl8723be: Update driver to match Realtek release of 06/28/14
This patch updates the driver to match the latest Realtek release, and it is an important step in getting the internal code source at Realtek to match the code in the kernel. The primary reason for this is to make it easier for Realtek to maintain the kernel source without requiring an intermediate like me. In this process of merging the two source repositories, there are a lot of changes in both, and this commit is rather large. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/trx.c4
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/mac.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/trx.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/fw.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hw.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/phy.c18
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/trx.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/def.h178
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/dm.c243
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/dm.h30
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/fw.c193
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/fw.h200
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/hw.c1319
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/hw.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/led.c6
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/phy.c1783
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/phy.h110
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h131
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/reg.h1135
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/rf.c144
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/sw.c40
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/table.c1053
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/table.h2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/trx.c307
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/trx.h34
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c8
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h22
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c19
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8821ae/hw.c3
-rw-r--r--drivers/net/wireless/rtlwifi/wifi.h8
30 files changed, 3833 insertions, 3167 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
index 8f04817cb7ec..c14012330900 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
@@ -125,7 +125,7 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
125 u32 rssi, total_rssi = 0; 125 u32 rssi, total_rssi = 0;
126 bool is_cck_rate; 126 bool is_cck_rate;
127 127
128 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc); 128 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc->rxmcs);
129 pstats->packet_matchbssid = packet_match_bssid; 129 pstats->packet_matchbssid = packet_match_bssid;
130 pstats->packet_toself = packet_toself; 130 pstats->packet_toself = packet_toself;
131 pstats->is_cck = is_cck_rate; 131 pstats->is_cck = is_cck_rate;
@@ -361,7 +361,7 @@ bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
361 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc); 361 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
362 stats->is_ht = (bool)GET_RX_DESC_RXHT(pdesc); 362 stats->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
363 363
364 stats->is_cck = RX_HAL_IS_CCK_RATE(pdesc); 364 stats->is_cck = RX_HAL_IS_CCK_RATE(pdesc->rxmcs);
365 365
366 rx_status->freq = hw->conf.chandef.chan->center_freq; 366 rx_status->freq = hw->conf.chandef.chan->center_freq;
367 rx_status->band = hw->conf.chandef.chan->band; 367 rx_status->band = hw->conf.chandef.chan->band;
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
index e26312fb4356..4da400817a85 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -786,7 +786,7 @@ static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
786 bool is_cck_rate; 786 bool is_cck_rate;
787 u8 *pdesc = (u8 *)p_desc; 787 u8 *pdesc = (u8 *)p_desc;
788 788
789 is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc); 789 is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs);
790 pstats->packet_matchbssid = packet_match_bssid; 790 pstats->packet_matchbssid = packet_match_bssid;
791 pstats->packet_toself = packet_toself; 791 pstats->packet_toself = packet_toself;
792 pstats->packet_beacon = packet_beacon; 792 pstats->packet_beacon = packet_beacon;
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
index 99c2ab5dfceb..8efbcc7af250 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
@@ -127,7 +127,7 @@ static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw,
127 u32 rssi, total_rssi = 0; 127 u32 rssi, total_rssi = 0;
128 bool is_cck_rate; 128 bool is_cck_rate;
129 129
130 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc); 130 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc->rxmcs);
131 pstats->packet_matchbssid = packet_match_bssid; 131 pstats->packet_matchbssid = packet_match_bssid;
132 pstats->packet_toself = packet_toself; 132 pstats->packet_toself = packet_toself;
133 pstats->packet_beacon = packet_beacon; 133 pstats->packet_beacon = packet_beacon;
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h b/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h
index ad70f2b3d9f0..9d1fe25db953 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h
@@ -34,7 +34,6 @@
34#define FW_8192C_END_ADDRESS 0x3FFF 34#define FW_8192C_END_ADDRESS 0x3FFF
35#define FW_8192C_PAGE_SIZE 4096 35#define FW_8192C_PAGE_SIZE 4096
36#define FW_8192C_POLLING_DELAY 5 36#define FW_8192C_POLLING_DELAY 5
37#define FW_8192C_POLLING_TIMEOUT_COUNT 1000
38 37
39#define IS_FW_HEADER_EXIST(_pfwhdr) \ 38#define IS_FW_HEADER_EXIST(_pfwhdr) \
40 ((_pfwhdr->signature&0xFFFF) == 0x2300 ||\ 39 ((_pfwhdr->signature&0xFFFF) == 0x2300 ||\
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
index 9e1671c7962f..aa085462d0e9 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
@@ -963,7 +963,7 @@ int rtl8723e_hw_init(struct ieee80211_hw *hw)
963 goto exit; 963 goto exit;
964 } 964 }
965 965
966 err = rtl8723_download_fw(hw, false, FW_8192C_POLLING_TIMEOUT_COUNT); 966 err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT);
967 if (err) { 967 if (err) {
968 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 968 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
969 "Failed to download FW. Init HW without FW now..\n"); 969 "Failed to download FW. Init HW without FW now..\n");
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
index 1e2fa9300350..d367097f490b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
@@ -1157,16 +1157,6 @@ static bool _rtl8723e_phy_simularity_compare(struct ieee80211_hw *hw,
1157 1157
1158} 1158}
1159 1159
1160static void rtl8723_phy_save_adda_registers(struct ieee80211_hw *hw,
1161 u32 *addareg, u32 *addabackup,
1162 u32 registernum)
1163{
1164 u32 i;
1165
1166 for (i = 0; i < registernum; i++)
1167 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1168}
1169
1170static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, 1160static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw,
1171 long result[][8], u8 t, bool is2t) 1161 long result[][8], u8 t, bool is2t)
1172{ 1162{
@@ -1192,8 +1182,8 @@ static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw,
1192 if (t == 0) { 1182 if (t == 0) {
1193 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD); 1183 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1194 1184
1195 rtl8723_phy_save_adda_registers(hw, adda_reg, 1185 rtl8723_save_adda_registers(hw, adda_reg,
1196 rtlphy->adda_backup, 16); 1186 rtlphy->adda_backup, 16);
1197 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg, 1187 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg,
1198 rtlphy->iqk_mac_backup); 1188 rtlphy->iqk_mac_backup);
1199 } 1189 }
@@ -1472,8 +1462,8 @@ void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1472 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, 1462 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1473 final_candidate, 1463 final_candidate,
1474 (reg_ea4 == 0)); 1464 (reg_ea4 == 0));
1475 rtl8723_phy_save_adda_registers(hw, iqk_bb_reg, 1465 rtl8723_save_adda_registers(hw, iqk_bb_reg,
1476 rtlphy->iqk_bb_backup, 10); 1466 rtlphy->iqk_bb_backup, 10);
1477} 1467}
1478 1468
1479void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw) 1469void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c b/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c
index ca84150b3b3e..1da2367ef37e 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c
@@ -463,7 +463,7 @@ bool rtl8723e_rx_query_desc(struct ieee80211_hw *hw,
463 status->rx_is40Mhzpacket = (bool)GET_RX_DESC_BW(pdesc); 463 status->rx_is40Mhzpacket = (bool)GET_RX_DESC_BW(pdesc);
464 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc); 464 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
465 465
466 status->is_cck = RTL8723E_RX_HAL_IS_CCK_RATE(status->rate); 466 status->is_cck = RX_HAL_IS_CCK_RATE(status->rate);
467 467
468 rx_status->freq = hw->conf.chandef.chan->center_freq; 468 rx_status->freq = hw->conf.chandef.chan->center_freq;
469 rx_status->band = hw->conf.chandef.chan->band; 469 rx_status->band = hw->conf.chandef.chan->band;
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/def.h b/drivers/net/wireless/rtlwifi/rtl8723be/def.h
index 3c30b74e983d..025ea5c0f3f6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/def.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/def.h
@@ -26,158 +26,24 @@
26#ifndef __RTL8723BE_DEF_H__ 26#ifndef __RTL8723BE_DEF_H__
27#define __RTL8723BE_DEF_H__ 27#define __RTL8723BE_DEF_H__
28 28
29#define HAL_RETRY_LIMIT_INFRA 48
30#define HAL_RETRY_LIMIT_AP_ADHOC 7
31
32#define RESET_DELAY_8185 20
33
34#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
35#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
36
37#define NUM_OF_FIRMWARE_QUEUE 10
38#define NUM_OF_PAGES_IN_FW 0x100
39#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
40#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
41#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
42#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
43#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
44#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
45#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
46#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
47#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
48#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
49
50#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
51#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
52#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
53#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
54#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
55
56#define MAX_LINES_HWCONFIG_TXT 1000
57#define MAX_BYTES_LINE_HWCONFIG_TXT 256
58
59#define SW_THREE_WIRE 0
60#define HW_THREE_WIRE 2
61
62#define BT_DEMO_BOARD 0
63#define BT_QA_BOARD 1
64#define BT_FPGA 2
65
66#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 29#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
67#define HAL_PRIME_CHNL_OFFSET_LOWER 1 30#define HAL_PRIME_CHNL_OFFSET_LOWER 1
68#define HAL_PRIME_CHNL_OFFSET_UPPER 2 31#define HAL_PRIME_CHNL_OFFSET_UPPER 2
69 32
70#define MAX_H2C_QUEUE_NUM 10
71 33
72#define RX_MPDU_QUEUE 0 34#define RX_MPDU_QUEUE 0
73#define RX_CMD_QUEUE 1 35#define CHIP_8723B (BIT(1) | BIT(2))
74#define RX_MAX_QUEUE 2 36#define NORMAL_CHIP BIT(3)
75#define AC2QUEUEID(_AC) (_AC) 37#define CHIP_VENDOR_SMIC BIT(8)
76 38/* Currently only for RTL8723B */
77#define C2H_RX_CMD_HDR_LEN 8 39#define EXT_VENDOR_ID (BIT(18) | BIT(19))
78#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
79 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
80#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
81 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
82#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
83 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
84#define GET_C2H_CMD_CONTINUE(__prxhdr) \
85 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
86#define GET_C2H_CMD_CONTENT(__prxhdr) \
87 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
88
89#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
90 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
91#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
92 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
93#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
94 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
95#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
96 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
97#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
98 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
99#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
100 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
101#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
102 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
103#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
104 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
105#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
106 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
107
108#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
109#define CHIP_BONDING_92C_1T2R 0x1
110
111#define CHIP_8723 BIT(0)
112#define CHIP_8723B (BIT(1) | BIT(2))
113#define NORMAL_CHIP BIT(3)
114#define RF_TYPE_1T1R (~(BIT(4) | BIT(5) | BIT(6)))
115#define RF_TYPE_1T2R BIT(4)
116#define RF_TYPE_2T2R BIT(5)
117#define CHIP_VENDOR_UMC BIT(7)
118#define B_CUT_VERSION BIT(12)
119#define C_CUT_VERSION BIT(13)
120#define D_CUT_VERSION ((BIT(12) | BIT(13)))
121#define E_CUT_VERSION BIT(14)
122#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
123
124/* MASK */
125#define IC_TYPE_MASK (BIT(0) | BIT(1) | BIT(2))
126#define CHIP_TYPE_MASK BIT(3)
127#define RF_TYPE_MASK (BIT(4) | BIT(5) | BIT(6))
128#define MANUFACTUER_MASK BIT(7)
129#define ROM_VERSION_MASK (BIT(11) | BIT(10) | BIT(9) | BIT(8))
130#define CUT_VERSION_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
131
132/* Get element */
133#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
134#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
135#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
136#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
137#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
138#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
139
140#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ?\
141 true : false)
142#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\
143 true : false)
144#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ?\
145 true : false)
146#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
147#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
148 ? true : false)
149#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
150 ? true : false)
151enum rf_optype {
152 RF_OP_BY_SW_3WIRE = 0,
153 RF_OP_BY_FW,
154 RF_OP_MAX
155};
156
157enum rf_power_state {
158 RF_ON,
159 RF_OFF,
160 RF_SLEEP,
161 RF_SHUT_DOWN,
162};
163
164enum power_save_mode {
165 POWER_SAVE_MODE_ACTIVE,
166 POWER_SAVE_MODE_SAVE,
167};
168 40
169enum power_polocy_config { 41enum rx_packet_type {
170 POWERCFG_MAX_POWER_SAVINGS, 42 NORMAL_RX,
171 POWERCFG_GLOBAL_POWER_SAVINGS, 43 TX_REPORT1,
172 POWERCFG_LOCAL_POWER_SAVINGS, 44 TX_REPORT2,
173 POWERCFG_LENOVO, 45 HIS_REPORT,
174}; 46 C2H_PACKET,
175
176enum interface_select_pci {
177 INTF_SEL1_MINICARD = 0,
178 INTF_SEL0_PCIE = 1,
179 INTF_SEL2_RSV = 2,
180 INTF_SEL3_RSV = 3,
181}; 47};
182 48
183enum rtl_desc_qsel { 49enum rtl_desc_qsel {
@@ -222,27 +88,5 @@ enum rtl_desc8723e_rate {
222 DESC92C_RATEMCS13 = 0x19, 88 DESC92C_RATEMCS13 = 0x19,
223 DESC92C_RATEMCS14 = 0x1a, 89 DESC92C_RATEMCS14 = 0x1a,
224 DESC92C_RATEMCS15 = 0x1b, 90 DESC92C_RATEMCS15 = 0x1b,
225 DESC92C_RATEMCS15_SG = 0x1c,
226 DESC92C_RATEMCS32 = 0x20,
227}; 91};
228
229enum rx_packet_type {
230 NORMAL_RX,
231 TX_REPORT1,
232 TX_REPORT2,
233 HIS_REPORT,
234};
235
236struct phy_sts_cck_8723e_t {
237 u8 adc_pwdb_X[4];
238 u8 sq_rpt;
239 u8 cck_agc_rpt;
240};
241
242struct h2c_cmd_8723e {
243 u8 element_id;
244 u32 cmd_len;
245 u8 *p_cmdbuffer;
246};
247
248#endif 92#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/dm.c b/drivers/net/wireless/rtlwifi/rtl8723be/dm.c
index 13d53a1df789..dd7eb4371f49 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/dm.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/dm.c
@@ -32,7 +32,6 @@
32#include "dm.h" 32#include "dm.h"
33#include "../rtl8723com/dm_common.h" 33#include "../rtl8723com/dm_common.h"
34#include "fw.h" 34#include "fw.h"
35#include "../rtl8723com/fw_common.h"
36#include "trx.h" 35#include "trx.h"
37#include "../btcoexist/rtl_btc.h" 36#include "../btcoexist/rtl_btc.h"
38 37
@@ -209,7 +208,7 @@ void rtl8723be_dm_txpower_track_adjust(struct ieee80211_hw *hw, u8 type,
209 pwr_val = TXPWRTRACK_MAX_IDX; 208 pwr_val = TXPWRTRACK_MAX_IDX;
210 209
211 *poutwrite_val = pwr_val | (pwr_val << 8) | 210 *poutwrite_val = pwr_val | (pwr_val << 8) |
212 (pwr_val << 16) | (pwr_val << 24); 211 (pwr_val << 16) | (pwr_val << 24);
213} 212}
214 213
215static void rtl8723be_dm_diginit(struct ieee80211_hw *hw) 214static void rtl8723be_dm_diginit(struct ieee80211_hw *hw)
@@ -218,8 +217,7 @@ static void rtl8723be_dm_diginit(struct ieee80211_hw *hw)
218 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 217 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
219 218
220 dm_digtable->dig_enable_flag = true; 219 dm_digtable->dig_enable_flag = true;
221 dm_digtable->cur_igvalue = rtl_get_bbreg(hw, 220 dm_digtable->cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f);
222 ROFDM0_XAAGCCORE1, 0x7f);
223 dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW; 221 dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
224 dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH; 222 dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
225 dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW; 223 dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
@@ -234,8 +232,8 @@ static void rtl8723be_dm_diginit(struct ieee80211_hw *hw)
234 dm_digtable->forbidden_igi = DM_DIG_MIN; 232 dm_digtable->forbidden_igi = DM_DIG_MIN;
235 dm_digtable->large_fa_hit = 0; 233 dm_digtable->large_fa_hit = 0;
236 dm_digtable->recover_cnt = 0; 234 dm_digtable->recover_cnt = 0;
237 dm_digtable->dig_min_0 = DM_DIG_MIN; 235 dm_digtable->dig_dynamic_min = DM_DIG_MIN;
238 dm_digtable->dig_min_1 = DM_DIG_MIN; 236 dm_digtable->dig_dynamic_min_1 = DM_DIG_MIN;
239 dm_digtable->media_connect_0 = false; 237 dm_digtable->media_connect_0 = false;
240 dm_digtable->media_connect_1 = false; 238 dm_digtable->media_connect_1 = false;
241 rtlpriv->dm.dm_initialgain_enable = true; 239 rtlpriv->dm.dm_initialgain_enable = true;
@@ -245,18 +243,18 @@ static void rtl8723be_dm_diginit(struct ieee80211_hw *hw)
245void rtl8723be_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 243void rtl8723be_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
246{ 244{
247 struct rtl_priv *rtlpriv = rtl_priv(hw); 245 struct rtl_priv *rtlpriv = rtl_priv(hw);
248 struct rate_adaptive *ra = &(rtlpriv->ra); 246 struct rate_adaptive *p_ra = &rtlpriv->ra;
249 247
250 ra->ratr_state = DM_RATR_STA_INIT; 248 p_ra->ratr_state = DM_RATR_STA_INIT;
251 ra->pre_ratr_state = DM_RATR_STA_INIT; 249 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
252 250
253 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) 251 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
254 rtlpriv->dm.useramask = true; 252 rtlpriv->dm.useramask = true;
255 else 253 else
256 rtlpriv->dm.useramask = false; 254 rtlpriv->dm.useramask = false;
257 255
258 ra->high_rssi_thresh_for_ra = 50; 256 p_ra->high_rssi_thresh_for_ra = 50;
259 ra->low_rssi_thresh_for_ra40m = 20; 257 p_ra->low_rssi_thresh_for_ra40m = 20;
260} 258}
261 259
262static void rtl8723be_dm_init_txpower_tracking(struct ieee80211_hw *hw) 260static void rtl8723be_dm_init_txpower_tracking(struct ieee80211_hw *hw)
@@ -279,7 +277,7 @@ static void rtl8723be_dm_init_txpower_tracking(struct ieee80211_hw *hw)
279 277
280 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 278 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
281 " rtlpriv->dm.txpower_tracking = %d\n", 279 " rtlpriv->dm.txpower_tracking = %d\n",
282 rtlpriv->dm.txpower_tracking); 280 rtlpriv->dm.txpower_tracking);
283} 281}
284 282
285static void rtl8723be_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw) 283static void rtl8723be_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
@@ -287,6 +285,7 @@ static void rtl8723be_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
287 struct rtl_priv *rtlpriv = rtl_priv(hw); 285 struct rtl_priv *rtlpriv = rtl_priv(hw);
288 286
289 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap; 287 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
288
290 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, 0x800); 289 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, 0x800);
291 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL; 290 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
292} 291}
@@ -308,7 +307,7 @@ void rtl8723be_dm_init(struct ieee80211_hw *hw)
308static void rtl8723be_dm_find_minimum_rssi(struct ieee80211_hw *hw) 307static void rtl8723be_dm_find_minimum_rssi(struct ieee80211_hw *hw)
309{ 308{
310 struct rtl_priv *rtlpriv = rtl_priv(hw); 309 struct rtl_priv *rtlpriv = rtl_priv(hw);
311 struct dig_t *rtl_dm_dig = &(rtlpriv->dm_digtable); 310 struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
312 struct rtl_mac *mac = rtl_mac(rtlpriv); 311 struct rtl_mac *mac = rtl_mac(rtlpriv);
313 312
314 /* Determine the minimum RSSI */ 313 /* Determine the minimum RSSI */
@@ -325,20 +324,20 @@ static void rtl8723be_dm_find_minimum_rssi(struct ieee80211_hw *hw)
325 rtlpriv->dm.entry_min_undec_sm_pwdb; 324 rtlpriv->dm.entry_min_undec_sm_pwdb;
326 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, 325 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
327 "AP Client PWDB = 0x%lx\n", 326 "AP Client PWDB = 0x%lx\n",
328 rtlpriv->dm.entry_min_undec_sm_pwdb); 327 rtlpriv->dm.entry_min_undec_sm_pwdb);
329 } else { 328 } else {
330 rtl_dm_dig->min_undec_pwdb_for_dm = 329 rtl_dm_dig->min_undec_pwdb_for_dm =
331 rtlpriv->dm.undec_sm_pwdb; 330 rtlpriv->dm.undec_sm_pwdb;
332 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, 331 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
333 "STA Default Port PWDB = 0x%x\n", 332 "STA Default Port PWDB = 0x%x\n",
334 rtl_dm_dig->min_undec_pwdb_for_dm); 333 rtl_dm_dig->min_undec_pwdb_for_dm);
335 } 334 }
336 } else { 335 } else {
337 rtl_dm_dig->min_undec_pwdb_for_dm = 336 rtl_dm_dig->min_undec_pwdb_for_dm =
338 rtlpriv->dm.entry_min_undec_sm_pwdb; 337 rtlpriv->dm.entry_min_undec_sm_pwdb;
339 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, 338 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
340 "AP Ext Port or disconnet PWDB = 0x%x\n", 339 "AP Ext Port or disconnet PWDB = 0x%x\n",
341 rtl_dm_dig->min_undec_pwdb_for_dm); 340 rtl_dm_dig->min_undec_pwdb_for_dm);
342 } 341 }
343 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n", 342 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n",
344 rtl_dm_dig->min_undec_pwdb_for_dm); 343 rtl_dm_dig->min_undec_pwdb_for_dm);
@@ -347,6 +346,7 @@ static void rtl8723be_dm_find_minimum_rssi(struct ieee80211_hw *hw)
347static void rtl8723be_dm_check_rssi_monitor(struct ieee80211_hw *hw) 346static void rtl8723be_dm_check_rssi_monitor(struct ieee80211_hw *hw)
348{ 347{
349 struct rtl_priv *rtlpriv = rtl_priv(hw); 348 struct rtl_priv *rtlpriv = rtl_priv(hw);
349 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
350 struct rtl_sta_info *drv_priv; 350 struct rtl_sta_info *drv_priv;
351 u8 h2c_parameter[3] = { 0 }; 351 u8 h2c_parameter[3] = { 0 };
352 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; 352 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
@@ -367,69 +367,78 @@ static void rtl8723be_dm_check_rssi_monitor(struct ieee80211_hw *hw)
367 367
368 /* If associated entry is found */ 368 /* If associated entry is found */
369 if (tmp_entry_max_pwdb != 0) { 369 if (tmp_entry_max_pwdb != 0) {
370 rtlpriv->dm.entry_max_undec_sm_pwdb = tmp_entry_max_pwdb; 370 rtlpriv->dm.entry_max_undec_sm_pwdb =
371 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 371 tmp_entry_max_pwdb;
372 "EntryMaxPWDB = 0x%lx(%ld)\n", 372 RTPRINT(rtlpriv, FDM, DM_PWDB,
373 "EntryMaxPWDB = 0x%lx(%ld)\n",
373 tmp_entry_max_pwdb, tmp_entry_max_pwdb); 374 tmp_entry_max_pwdb, tmp_entry_max_pwdb);
374 } else { 375 } else {
375 rtlpriv->dm.entry_max_undec_sm_pwdb = 0; 376 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
376 } 377 }
377 /* If associated entry is found */ 378 /* If associated entry is found */
378 if (tmp_entry_min_pwdb != 0xff) { 379 if (tmp_entry_min_pwdb != 0xff) {
379 rtlpriv->dm.entry_min_undec_sm_pwdb = tmp_entry_min_pwdb; 380 rtlpriv->dm.entry_min_undec_sm_pwdb =
380 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 381 tmp_entry_min_pwdb;
381 "EntryMinPWDB = 0x%lx(%ld)\n", 382 RTPRINT(rtlpriv, FDM, DM_PWDB,
383 "EntryMinPWDB = 0x%lx(%ld)\n",
382 tmp_entry_min_pwdb, tmp_entry_min_pwdb); 384 tmp_entry_min_pwdb, tmp_entry_min_pwdb);
383 } else { 385 } else {
384 rtlpriv->dm.entry_min_undec_sm_pwdb = 0; 386 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
385 } 387 }
386 /* Indicate Rx signal strength to FW. */ 388 /* Indicate Rx signal strength to FW. */
387 if (rtlpriv->dm.useramask) { 389 if (rtlpriv->dm.useramask) {
388 h2c_parameter[2] = (u8) (rtlpriv->dm.undec_sm_pwdb & 0xFF); 390 h2c_parameter[2] =
391 (u8)(rtlpriv->dm.undec_sm_pwdb & 0xFF);
389 h2c_parameter[1] = 0x20; 392 h2c_parameter[1] = 0x20;
390 h2c_parameter[0] = 0; 393 h2c_parameter[0] = 0;
391 rtl8723be_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter); 394 rtl8723be_fill_h2c_cmd(hw, H2C_RSSIBE_REPORT, 3, h2c_parameter);
392 } else { 395 } else {
393 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undec_sm_pwdb); 396 rtl_write_byte(rtlpriv, 0x4fe,
397 rtlpriv->dm.undec_sm_pwdb);
394 } 398 }
395 rtl8723be_dm_find_minimum_rssi(hw); 399 rtl8723be_dm_find_minimum_rssi(hw);
396 rtlpriv->dm_digtable.rssi_val_min = 400 dm_digtable->rssi_val_min =
397 rtlpriv->dm_digtable.min_undec_pwdb_for_dm; 401 rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
398} 402}
399 403
400void rtl8723be_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi) 404void rtl8723be_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
401{ 405{
402 struct rtl_priv *rtlpriv = rtl_priv(hw); 406 struct rtl_priv *rtlpriv = rtl_priv(hw);
407 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
403 408
404 if (rtlpriv->dm_digtable.cur_igvalue != current_igi) { 409 if (dm_digtable->stop_dig)
410 return;
411
412 if (dm_digtable->cur_igvalue != current_igi) {
405 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi); 413 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi);
406 if (rtlpriv->phy.rf_type != RF_1T1R) 414 if (rtlpriv->phy.rf_type != RF_1T1R)
407 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, current_igi); 415 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1,
416 0x7f, current_igi);
408 } 417 }
409 rtlpriv->dm_digtable.pre_igvalue = rtlpriv->dm_digtable.cur_igvalue; 418 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
410 rtlpriv->dm_digtable.cur_igvalue = current_igi; 419 dm_digtable->cur_igvalue = current_igi;
411} 420}
412 421
413static void rtl8723be_dm_dig(struct ieee80211_hw *hw) 422static void rtl8723be_dm_dig(struct ieee80211_hw *hw)
414{ 423{
415 struct rtl_priv *rtlpriv = rtl_priv(hw); 424 struct rtl_priv *rtlpriv = rtl_priv(hw);
425 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
416 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 426 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
417 struct dig_t *dm_digtable = &(rtlpriv->dm_digtable);
418 u8 dig_dynamic_min, dig_maxofmin; 427 u8 dig_dynamic_min, dig_maxofmin;
419 bool firstconnect, firstdisconnect; 428 bool bfirstconnect, bfirstdisconnect;
420 u8 dm_dig_max, dm_dig_min; 429 u8 dm_dig_max, dm_dig_min;
421 u8 current_igi = dm_digtable->cur_igvalue; 430 u8 current_igi = dm_digtable->cur_igvalue;
422 u8 offset; 431 u8 offset;
423 432
424 /* AP, BT */ 433 /* AP,BT */
425 if (mac->act_scanning) 434 if (mac->act_scanning)
426 return; 435 return;
427 436
428 dig_dynamic_min = dm_digtable->dig_min_0; 437 dig_dynamic_min = dm_digtable->dig_dynamic_min;
429 firstconnect = (mac->link_state >= MAC80211_LINKED) && 438 bfirstconnect = (mac->link_state >= MAC80211_LINKED) &&
430 !dm_digtable->media_connect_0; 439 !dm_digtable->media_connect_0;
431 firstdisconnect = (mac->link_state < MAC80211_LINKED) && 440 bfirstdisconnect = (mac->link_state < MAC80211_LINKED) &&
432 dm_digtable->media_connect_0; 441 (dm_digtable->media_connect_0);
433 442
434 dm_dig_max = 0x5a; 443 dm_dig_max = 0x5a;
435 dm_dig_min = DM_DIG_MIN; 444 dm_dig_min = DM_DIG_MIN;
@@ -457,6 +466,7 @@ static void rtl8723be_dm_dig(struct ieee80211_hw *hw)
457 } else { 466 } else {
458 dig_dynamic_min = dm_dig_min; 467 dig_dynamic_min = dm_dig_min;
459 } 468 }
469
460 } else { 470 } else {
461 dm_digtable->rx_gain_max = dm_dig_max; 471 dm_digtable->rx_gain_max = dm_dig_max;
462 dig_dynamic_min = dm_dig_min; 472 dig_dynamic_min = dm_dig_min;
@@ -506,7 +516,7 @@ static void rtl8723be_dm_dig(struct ieee80211_hw *hw)
506 dm_digtable->rx_gain_min = dm_digtable->rx_gain_max; 516 dm_digtable->rx_gain_min = dm_digtable->rx_gain_max;
507 517
508 if (mac->link_state >= MAC80211_LINKED) { 518 if (mac->link_state >= MAC80211_LINKED) {
509 if (firstconnect) { 519 if (bfirstconnect) {
510 if (dm_digtable->rssi_val_min <= dig_maxofmin) 520 if (dm_digtable->rssi_val_min <= dig_maxofmin)
511 current_igi = dm_digtable->rssi_val_min; 521 current_igi = dm_digtable->rssi_val_min;
512 else 522 else
@@ -522,7 +532,7 @@ static void rtl8723be_dm_dig(struct ieee80211_hw *hw)
522 current_igi -= 2; 532 current_igi -= 2;
523 } 533 }
524 } else { 534 } else {
525 if (firstdisconnect) { 535 if (bfirstdisconnect) {
526 current_igi = dm_digtable->rx_gain_min; 536 current_igi = dm_digtable->rx_gain_min;
527 } else { 537 } else {
528 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 538 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
@@ -542,14 +552,15 @@ static void rtl8723be_dm_dig(struct ieee80211_hw *hw)
542 rtl8723be_dm_write_dig(hw, current_igi); 552 rtl8723be_dm_write_dig(hw, current_igi);
543 dm_digtable->media_connect_0 = 553 dm_digtable->media_connect_0 =
544 ((mac->link_state >= MAC80211_LINKED) ? true : false); 554 ((mac->link_state >= MAC80211_LINKED) ? true : false);
545 dm_digtable->dig_min_0 = dig_dynamic_min; 555 dm_digtable->dig_dynamic_min = dig_dynamic_min;
546} 556}
547 557
548static void rtl8723be_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 558static void rtl8723be_dm_false_alarm_counter_statistics(
559 struct ieee80211_hw *hw)
549{ 560{
550 u32 ret_value; 561 u32 ret_value;
551 struct rtl_priv *rtlpriv = rtl_priv(hw); 562 struct rtl_priv *rtlpriv = rtl_priv(hw);
552 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 563 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
553 564
554 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); 565 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
555 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); 566 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
@@ -615,16 +626,14 @@ static void rtl8723be_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
615 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2); 626 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
616 627
617 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 628 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
618 "cnt_parity_fail = %d, cnt_rate_illegal = %d, " 629 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
619 "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
620 falsealm_cnt->cnt_parity_fail, 630 falsealm_cnt->cnt_parity_fail,
621 falsealm_cnt->cnt_rate_illegal, 631 falsealm_cnt->cnt_rate_illegal,
622 falsealm_cnt->cnt_crc8_fail, 632 falsealm_cnt->cnt_crc8_fail,
623 falsealm_cnt->cnt_mcs_fail); 633 falsealm_cnt->cnt_mcs_fail);
624 634
625 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 635 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
626 "cnt_ofdm_fail = %x, cnt_cck_fail = %x," 636 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
627 " cnt_all = %x\n",
628 falsealm_cnt->cnt_ofdm_fail, 637 falsealm_cnt->cnt_ofdm_fail,
629 falsealm_cnt->cnt_cck_fail, 638 falsealm_cnt->cnt_cck_fail,
630 falsealm_cnt->cnt_all); 639 falsealm_cnt->cnt_all);
@@ -690,7 +699,7 @@ static void rtl8723be_dm_tx_power_track_set_power(struct ieee80211_hw *hw,
690 u8 rfpath, u8 idx) 699 u8 rfpath, u8 idx)
691{ 700{
692 struct rtl_priv *rtlpriv = rtl_priv(hw); 701 struct rtl_priv *rtlpriv = rtl_priv(hw);
693 struct rtl_phy *rtlphy = &(rtlpriv->phy); 702 struct rtl_phy *rtlphy = &rtlpriv->phy;
694 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 703 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
695 u8 swing_idx_ofdm_limit = 36; 704 u8 swing_idx_ofdm_limit = 36;
696 705
@@ -762,7 +771,8 @@ static void rtl8723be_dm_tx_power_track_set_power(struct ieee80211_hw *hw,
762 } 771 }
763} 772}
764 773
765static void txpwr_track_cb_therm(struct ieee80211_hw *hw) 774static void rtl8723be_dm_txpower_tracking_callback_thermalmeter(
775 struct ieee80211_hw *hw)
766{ 776{
767 struct rtl_priv *rtlpriv = rtl_priv(hw); 777 struct rtl_priv *rtlpriv = rtl_priv(hw);
768 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 778 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
@@ -773,30 +783,29 @@ static void txpwr_track_cb_therm(struct ieee80211_hw *hw)
773 int i = 0; 783 int i = 0;
774 784
775 u8 ofdm_min_index = 6; 785 u8 ofdm_min_index = 6;
776 u8 index = 0; 786 u8 index_for_channel = 0;
777 787
778 char delta_swing_table_idx_tup_a[] = { 788 char delta_swing_table_idx_tup_a[TXSCALE_TABLE_SIZE] = {
779 0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 789 0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5,
780 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 790 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10,
781 10, 11, 11, 12, 12, 13, 14, 15}; 791 10, 11, 11, 12, 12, 13, 14, 15};
782 char delta_swing_table_idx_tdown_a[] = { 792 char delta_swing_table_idx_tdown_a[TXSCALE_TABLE_SIZE] = {
783 0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 793 0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5,
784 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 794 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9,
785 9, 10, 10, 11, 12, 13, 14, 15}; 795 9, 10, 10, 11, 12, 13, 14, 15};
786 796
787 /*Initilization ( 7 steps in total)*/ 797 /*Initilization ( 7 steps in total )*/
788 rtlpriv->dm.txpower_trackinginit = true; 798 rtlpriv->dm.txpower_trackinginit = true;
789 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 799 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
790 "rtl8723be_dm_txpower_tracking" 800 "rtl8723be_dm_txpower_tracking_callback_thermalmeter\n");
791 "_callback_thermalmeter\n");
792 801
793 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xfc00); 802 thermalvalue = (u8)rtl_get_rfreg(hw,
803 RF90_PATH_A, RF_T_METER, 0xfc00);
794 if (!rtlpriv->dm.txpower_track_control || thermalvalue == 0 || 804 if (!rtlpriv->dm.txpower_track_control || thermalvalue == 0 ||
795 rtlefuse->eeprom_thermalmeter == 0xFF) 805 rtlefuse->eeprom_thermalmeter == 0xFF)
796 return; 806 return;
797 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 807 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
798 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x " 808 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
799 "eeprom_thermalmeter 0x%x\n",
800 thermalvalue, rtldm->thermalvalue, 809 thermalvalue, rtldm->thermalvalue,
801 rtlefuse->eeprom_thermalmeter); 810 rtlefuse->eeprom_thermalmeter);
802 /*3 Initialize ThermalValues of RFCalibrateInfo*/ 811 /*3 Initialize ThermalValues of RFCalibrateInfo*/
@@ -833,9 +842,7 @@ static void txpwr_track_cb_therm(struct ieee80211_hw *hw)
833 (rtlpriv->dm.thermalvalue_iqk - thermalvalue); 842 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
834 843
835 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 844 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
836 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x " 845 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
837 "eeprom_thermalmeter 0x%x delta 0x%x "
838 "delta_lck 0x%x delta_iqk 0x%x\n",
839 thermalvalue, rtlpriv->dm.thermalvalue, 846 thermalvalue, rtlpriv->dm.thermalvalue,
840 rtlefuse->eeprom_thermalmeter, delta, delta_lck, delta_iqk); 847 rtlefuse->eeprom_thermalmeter, delta, delta_lck, delta_iqk);
841 /* 6 If necessary, do LCK.*/ 848 /* 6 If necessary, do LCK.*/
@@ -905,10 +912,10 @@ static void txpwr_track_cb_therm(struct ieee80211_hw *hw)
905 rtldm->done_txpower = true; 912 rtldm->done_txpower = true;
906 if (thermalvalue > rtlefuse->eeprom_thermalmeter) 913 if (thermalvalue > rtlefuse->eeprom_thermalmeter)
907 rtl8723be_dm_tx_power_track_set_power(hw, BBSWING, 0, 914 rtl8723be_dm_tx_power_track_set_power(hw, BBSWING, 0,
908 index); 915 index_for_channel);
909 else 916 else
910 rtl8723be_dm_tx_power_track_set_power(hw, BBSWING, 0, 917 rtl8723be_dm_tx_power_track_set_power(hw, BBSWING, 0,
911 index); 918 index_for_channel);
912 919
913 rtldm->swing_idx_cck_base = rtldm->swing_idx_cck; 920 rtldm->swing_idx_cck_base = rtldm->swing_idx_cck;
914 rtldm->swing_idx_ofdm_base[RF90_PATH_A] = 921 rtldm->swing_idx_ofdm_base[RF90_PATH_A] =
@@ -923,6 +930,7 @@ static void txpwr_track_cb_therm(struct ieee80211_hw *hw)
923 930
924 rtldm->txpowercount = 0; 931 rtldm->txpowercount = 0;
925 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "end\n"); 932 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "end\n");
933
926} 934}
927 935
928void rtl8723be_dm_check_txpower_tracking(struct ieee80211_hw *hw) 936void rtl8723be_dm_check_txpower_tracking(struct ieee80211_hw *hw)
@@ -943,7 +951,7 @@ void rtl8723be_dm_check_txpower_tracking(struct ieee80211_hw *hw)
943 } else { 951 } else {
944 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 952 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
945 "Schedule TxPowerTracking !!\n"); 953 "Schedule TxPowerTracking !!\n");
946 txpwr_track_cb_therm(hw); 954 rtl8723be_dm_txpower_tracking_callback_thermalmeter(hw);
947 tm_trigger = 0; 955 tm_trigger = 0;
948 } 956 }
949} 957}
@@ -953,11 +961,11 @@ static void rtl8723be_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
953 struct rtl_priv *rtlpriv = rtl_priv(hw); 961 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 962 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
955 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 963 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
956 struct rate_adaptive *ra = &(rtlpriv->ra); 964 struct rate_adaptive *p_ra = &rtlpriv->ra;
957 struct ieee80211_sta *sta = NULL; 965 u32 low_rssithresh_for_ra = p_ra->low2high_rssi_thresh_for_ra40m;
958 u32 low_rssithresh_for_ra = ra->low2high_rssi_thresh_for_ra40m; 966 u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
959 u32 high_rssithresh_for_ra = ra->high_rssi_thresh_for_ra;
960 u8 go_up_gap = 5; 967 u8 go_up_gap = 5;
968 struct ieee80211_sta *sta = NULL;
961 969
962 if (is_hal_stop(rtlhal)) { 970 if (is_hal_stop(rtlhal)) {
963 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 971 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
@@ -972,8 +980,8 @@ static void rtl8723be_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
972 } 980 }
973 981
974 if (mac->link_state == MAC80211_LINKED && 982 if (mac->link_state == MAC80211_LINKED &&
975 mac->opmode == NL80211_IFTYPE_STATION) { 983 mac->opmode == NL80211_IFTYPE_STATION) {
976 switch (ra->pre_ratr_state) { 984 switch (p_ra->pre_ratr_state) {
977 case DM_RATR_STA_MIDDLE: 985 case DM_RATR_STA_MIDDLE:
978 high_rssithresh_for_ra += go_up_gap; 986 high_rssithresh_for_ra += go_up_gap;
979 break; 987 break;
@@ -987,31 +995,31 @@ static void rtl8723be_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
987 995
988 if (rtlpriv->dm.undec_sm_pwdb > 996 if (rtlpriv->dm.undec_sm_pwdb >
989 (long)high_rssithresh_for_ra) 997 (long)high_rssithresh_for_ra)
990 ra->ratr_state = DM_RATR_STA_HIGH; 998 p_ra->ratr_state = DM_RATR_STA_HIGH;
991 else if (rtlpriv->dm.undec_sm_pwdb > 999 else if (rtlpriv->dm.undec_sm_pwdb >
992 (long)low_rssithresh_for_ra) 1000 (long)low_rssithresh_for_ra)
993 ra->ratr_state = DM_RATR_STA_MIDDLE; 1001 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
994 else 1002 else
995 ra->ratr_state = DM_RATR_STA_LOW; 1003 p_ra->ratr_state = DM_RATR_STA_LOW;
996 1004
997 if (ra->pre_ratr_state != ra->ratr_state) { 1005 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
998 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1006 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
999 "RSSI = %ld\n", 1007 "RSSI = %ld\n",
1000 rtlpriv->dm.undec_sm_pwdb); 1008 rtlpriv->dm.undec_sm_pwdb);
1001 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1009 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1002 "RSSI_LEVEL = %d\n", ra->ratr_state); 1010 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
1003 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1011 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1004 "PreState = %d, CurState = %d\n", 1012 "PreState = %d, CurState = %d\n",
1005 ra->pre_ratr_state, ra->ratr_state); 1013 p_ra->pre_ratr_state, p_ra->ratr_state);
1006 1014
1007 rcu_read_lock(); 1015 rcu_read_lock();
1008 sta = rtl_find_sta(hw, mac->bssid); 1016 sta = rtl_find_sta(hw, mac->bssid);
1009 if (sta) 1017 if (sta)
1010 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 1018 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1011 ra->ratr_state); 1019 p_ra->ratr_state);
1012 rcu_read_unlock(); 1020 rcu_read_unlock();
1013 1021
1014 ra->pre_ratr_state = ra->ratr_state; 1022 p_ra->pre_ratr_state = p_ra->ratr_state;
1015 } 1023 }
1016 } 1024 }
1017} 1025}
@@ -1020,10 +1028,6 @@ static bool rtl8723be_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
1020{ 1028{
1021 struct rtl_priv *rtlpriv = rtl_priv(hw); 1029 struct rtl_priv *rtlpriv = rtl_priv(hw);
1022 1030
1023 if (rtlpriv->cfg->ops->get_btc_status()) {
1024 if (rtlpriv->btcoexist.btc_ops->btc_is_disable_edca_turbo(rtlpriv))
1025 return true;
1026 }
1027 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B) 1031 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
1028 return true; 1032 return true;
1029 1033
@@ -1034,6 +1038,7 @@ static void rtl8723be_dm_check_edca_turbo(struct ieee80211_hw *hw)
1034{ 1038{
1035 struct rtl_priv *rtlpriv = rtl_priv(hw); 1039 struct rtl_priv *rtlpriv = rtl_priv(hw);
1036 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1040 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1041
1037 static u64 last_txok_cnt; 1042 static u64 last_txok_cnt;
1038 static u64 last_rxok_cnt; 1043 static u64 last_rxok_cnt;
1039 u64 cur_txok_cnt = 0; 1044 u64 cur_txok_cnt = 0;
@@ -1042,22 +1047,22 @@ static void rtl8723be_dm_check_edca_turbo(struct ieee80211_hw *hw)
1042 u32 edca_be_dl = 0x6ea42b;/*not sure*/ 1047 u32 edca_be_dl = 0x6ea42b;/*not sure*/
1043 u32 edca_be = 0x5ea42b; 1048 u32 edca_be = 0x5ea42b;
1044 u32 iot_peer = 0; 1049 u32 iot_peer = 0;
1045 bool is_cur_rdlstate; 1050 bool b_is_cur_rdlstate;
1046 bool last_is_cur_rdlstate = false; 1051 bool b_last_is_cur_rdlstate = false;
1047 bool bias_on_rx = false; 1052 bool b_bias_on_rx = false;
1048 bool edca_turbo_on = false; 1053 bool b_edca_turbo_on = false;
1049 1054
1050 last_is_cur_rdlstate = rtlpriv->dm.is_cur_rdlstate; 1055 b_last_is_cur_rdlstate = rtlpriv->dm.is_cur_rdlstate;
1051 1056
1052 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 1057 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
1053 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 1058 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
1054 1059
1055 iot_peer = rtlpriv->mac80211.vendor; 1060 iot_peer = rtlpriv->mac80211.vendor;
1056 bias_on_rx = (iot_peer == PEER_RAL || iot_peer == PEER_ATH) ? 1061 b_bias_on_rx = (iot_peer == PEER_RAL || iot_peer == PEER_ATH) ?
1057 true : false; 1062 true : false;
1058 edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) && 1063 b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
1059 (!rtlpriv->dm.disable_framebursting)) ? 1064 (!rtlpriv->dm.disable_framebursting)) ?
1060 true : false; 1065 true : false;
1061 1066
1062 if ((iot_peer == PEER_CISCO) && 1067 if ((iot_peer == PEER_CISCO) &&
1063 (mac->mode == WIRELESS_MODE_N_24G)) { 1068 (mac->mode == WIRELESS_MODE_N_24G)) {
@@ -1067,23 +1072,23 @@ static void rtl8723be_dm_check_edca_turbo(struct ieee80211_hw *hw)
1067 if (rtl8723be_dm_is_edca_turbo_disable(hw)) 1072 if (rtl8723be_dm_is_edca_turbo_disable(hw))
1068 goto exit; 1073 goto exit;
1069 1074
1070 if (edca_turbo_on) { 1075 if (b_edca_turbo_on) {
1071 if (bias_on_rx) 1076 if (b_bias_on_rx)
1072 is_cur_rdlstate = (cur_txok_cnt > cur_rxok_cnt * 4) ? 1077 b_is_cur_rdlstate = (cur_txok_cnt > cur_rxok_cnt * 4) ?
1073 false : true; 1078 false : true;
1074 else 1079 else
1075 is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ? 1080 b_is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ?
1076 true : false; 1081 true : false;
1077 1082
1078 edca_be = (is_cur_rdlstate) ? edca_be_dl : edca_be_ul; 1083 edca_be = (b_is_cur_rdlstate) ? edca_be_dl : edca_be_ul;
1079 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, edca_be); 1084 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, edca_be);
1080 rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate; 1085 rtlpriv->dm.is_cur_rdlstate = b_is_cur_rdlstate;
1081 rtlpriv->dm.current_turbo_edca = true; 1086 rtlpriv->dm.current_turbo_edca = true;
1082 } else { 1087 } else {
1083 if (rtlpriv->dm.current_turbo_edca) { 1088 if (rtlpriv->dm.current_turbo_edca) {
1084 u8 tmp = AC0_BE; 1089 u8 tmp = AC0_BE;
1085 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 1090 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
1086 &tmp); 1091 (u8 *)(&tmp));
1087 } 1092 }
1088 rtlpriv->dm.current_turbo_edca = false; 1093 rtlpriv->dm.current_turbo_edca = false;
1089 } 1094 }
@@ -1097,13 +1102,14 @@ exit:
1097static void rtl8723be_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 1102static void rtl8723be_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
1098{ 1103{
1099 struct rtl_priv *rtlpriv = rtl_priv(hw); 1104 struct rtl_priv *rtlpriv = rtl_priv(hw);
1105 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1100 u8 cur_cck_cca_thresh; 1106 u8 cur_cck_cca_thresh;
1101 1107
1102 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) { 1108 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
1103 if (rtlpriv->dm_digtable.rssi_val_min > 25) { 1109 if (dm_digtable->rssi_val_min > 25) {
1104 cur_cck_cca_thresh = 0xcd; 1110 cur_cck_cca_thresh = 0xcd;
1105 } else if ((rtlpriv->dm_digtable.rssi_val_min <= 25) && 1111 } else if ((dm_digtable->rssi_val_min <= 25) &&
1106 (rtlpriv->dm_digtable.rssi_val_min > 10)) { 1112 (dm_digtable->rssi_val_min > 10)) {
1107 cur_cck_cca_thresh = 0x83; 1113 cur_cck_cca_thresh = 0x83;
1108 } else { 1114 } else {
1109 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000) 1115 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
@@ -1118,14 +1124,13 @@ static void rtl8723be_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
1118 cur_cck_cca_thresh = 0x40; 1124 cur_cck_cca_thresh = 0x40;
1119 } 1125 }
1120 1126
1121 if (rtlpriv->dm_digtable.cur_cck_cca_thres != cur_cck_cca_thresh) 1127 if (dm_digtable->cur_cck_cca_thres != cur_cck_cca_thresh)
1122 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh); 1128 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
1123 1129
1124 rtlpriv->dm_digtable.pre_cck_cca_thres = rtlpriv->dm_digtable.cur_cck_cca_thres; 1130 dm_digtable->pre_cck_cca_thres = dm_digtable->cur_cck_cca_thres;
1125 rtlpriv->dm_digtable.cur_cck_cca_thres = cur_cck_cca_thresh; 1131 dm_digtable->cur_cck_cca_thres = cur_cck_cca_thresh;
1126 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 1132 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
1127 "CCK cca thresh hold =%x\n", 1133 "CCK cca thresh hold =%x\n", dm_digtable->cur_cck_cca_thres);
1128 rtlpriv->dm_digtable.cur_cck_cca_thres);
1129} 1134}
1130 1135
1131static void rtl8723be_dm_dynamic_edcca(struct ieee80211_hw *hw) 1136static void rtl8723be_dm_dynamic_edcca(struct ieee80211_hw *hw)
@@ -1173,8 +1178,7 @@ static void rtl8723be_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
1173 if (rtlpriv->cfg->ops->get_btc_status()) { 1178 if (rtlpriv->cfg->ops->get_btc_status()) {
1174 if (!rtlpriv->btcoexist.btc_ops->btc_is_bt_disabled(rtlpriv)) { 1179 if (!rtlpriv->btcoexist.btc_ops->btc_is_bt_disabled(rtlpriv)) {
1175 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1180 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
1176 "odm_DynamicATCSwitch(): Disable" 1181 "odm_DynamicATCSwitch(): Disable CFO tracking for BT!!\n");
1177 " CFO tracking for BT!!\n");
1178 return; 1182 return;
1179 } 1183 }
1180 } 1184 }
@@ -1207,9 +1211,8 @@ static void rtl8723be_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
1207 if (cfo_ave_diff > 20 && rtldm->large_cfo_hit == 0) { 1211 if (cfo_ave_diff > 20 && rtldm->large_cfo_hit == 0) {
1208 rtldm->large_cfo_hit = 1; 1212 rtldm->large_cfo_hit = 1;
1209 return; 1213 return;
1210 } else { 1214 } else
1211 rtldm->large_cfo_hit = 0; 1215 rtldm->large_cfo_hit = 0;
1212 }
1213 1216
1214 rtldm->cfo_ave_pre = cfo_ave; 1217 rtldm->cfo_ave_pre = cfo_ave;
1215 1218
@@ -1263,20 +1266,20 @@ static void rtl8723be_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
1263static void rtl8723be_dm_common_info_self_update(struct ieee80211_hw *hw) 1266static void rtl8723be_dm_common_info_self_update(struct ieee80211_hw *hw)
1264{ 1267{
1265 struct rtl_priv *rtlpriv = rtl_priv(hw); 1268 struct rtl_priv *rtlpriv = rtl_priv(hw);
1266 struct rtl_sta_info *drv_priv;
1267 u8 cnt = 0; 1269 u8 cnt = 0;
1270 struct rtl_sta_info *drv_priv;
1268 1271
1269 rtlpriv->dm.one_entry_only = false; 1272 rtlpriv->dm.one_entry_only = false;
1270 1273
1271 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION && 1274 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
1272 rtlpriv->mac80211.link_state >= MAC80211_LINKED) { 1275 rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
1273 rtlpriv->dm.one_entry_only = true; 1276 rtlpriv->dm.one_entry_only = true;
1274 return; 1277 return;
1275 } 1278 }
1276 1279
1277 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP || 1280 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1278 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC || 1281 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
1279 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) { 1282 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
1280 spin_lock_bh(&rtlpriv->locks.entry_list_lock); 1283 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1281 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) { 1284 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1282 cnt++; 1285 cnt++;
@@ -1305,8 +1308,8 @@ void rtl8723be_dm_watchdog(struct ieee80211_hw *hw)
1305 fw_ps_awake = false; 1308 fw_ps_awake = false;
1306 1309
1307 if ((ppsc->rfpwr_state == ERFON) && 1310 if ((ppsc->rfpwr_state == ERFON) &&
1308 ((!fw_current_inpsmode) && fw_ps_awake) && 1311 ((!fw_current_inpsmode) && fw_ps_awake) &&
1309 (!ppsc->rfchange_inprogress)) { 1312 (!ppsc->rfchange_inprogress)) {
1310 rtl8723be_dm_common_info_self_update(hw); 1313 rtl8723be_dm_common_info_self_update(hw);
1311 rtl8723be_dm_false_alarm_counter_statistics(hw); 1314 rtl8723be_dm_false_alarm_counter_statistics(hw);
1312 rtl8723be_dm_check_rssi_monitor(hw); 1315 rtl8723be_dm_check_rssi_monitor(hw);
@@ -1318,8 +1321,6 @@ void rtl8723be_dm_watchdog(struct ieee80211_hw *hw)
1318 rtl8723be_dm_dynamic_atc_switch(hw); 1321 rtl8723be_dm_dynamic_atc_switch(hw);
1319 rtl8723be_dm_check_txpower_tracking(hw); 1322 rtl8723be_dm_check_txpower_tracking(hw);
1320 rtl8723be_dm_dynamic_txpower(hw); 1323 rtl8723be_dm_dynamic_txpower(hw);
1321 if (rtlpriv->cfg->ops->get_btc_status())
1322 rtlpriv->btcoexist.btc_ops->btc_periodical(rtlpriv);
1323 } 1324 }
1324 rtlpriv->dm.dbginfo.num_qry_beacon_pkt = 0; 1325 rtlpriv->dm.dbginfo.num_qry_beacon_pkt = 0;
1325} 1326}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/dm.h b/drivers/net/wireless/rtlwifi/rtl8723be/dm.h
index c6c2f2a78a66..e4c0e8ae6f47 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/dm.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/dm.h
@@ -141,7 +141,7 @@
141#define DM_REG_TX_CCK_BBON_11N 0xE78 141#define DM_REG_TX_CCK_BBON_11N 0xE78
142#define DM_REG_OFDM_RFON_11N 0xE7C 142#define DM_REG_OFDM_RFON_11N 0xE7C
143#define DM_REG_OFDM_BBON_11N 0xE80 143#define DM_REG_OFDM_BBON_11N 0xE80
144#define DM_REG_TX2RX_11N 0xE84 144#define DM_REG_TX2RX_11N 0xE84
145#define DM_REG_TX2TX_11N 0xE88 145#define DM_REG_TX2TX_11N 0xE88
146#define DM_REG_RX_CCK_11N 0xE8C 146#define DM_REG_RX_CCK_11N 0xE8C
147#define DM_REG_RX_OFDM_11N 0xED0 147#define DM_REG_RX_OFDM_11N 0xED0
@@ -202,6 +202,7 @@
202#define DM_DIG_BACKOFF_MIN -4 202#define DM_DIG_BACKOFF_MIN -4
203#define DM_DIG_BACKOFF_DEFAULT 10 203#define DM_DIG_BACKOFF_DEFAULT 10
204 204
205#define RXPATHSELECTION_SS_TH_LOW 30
205#define RXPATHSELECTION_DIFF_TH 18 206#define RXPATHSELECTION_DIFF_TH 18
206 207
207#define DM_RATR_STA_INIT 0 208#define DM_RATR_STA_INIT 0
@@ -212,6 +213,8 @@
212#define CTS2SELF_THVAL 30 213#define CTS2SELF_THVAL 30
213#define REGC38_TH 20 214#define REGC38_TH 20
214 215
216#define WAIOTTHVAL 25
217
215#define TXHIGHPWRLEVEL_NORMAL 0 218#define TXHIGHPWRLEVEL_NORMAL 0
216#define TXHIGHPWRLEVEL_LEVEL1 1 219#define TXHIGHPWRLEVEL_LEVEL1 1
217#define TXHIGHPWRLEVEL_LEVEL2 2 220#define TXHIGHPWRLEVEL_LEVEL2 2
@@ -231,22 +234,6 @@
231#define CFO_THRESHOLD_XTAL 10 /* kHz */ 234#define CFO_THRESHOLD_XTAL 10 /* kHz */
232#define CFO_THRESHOLD_ATC 80 /* kHz */ 235#define CFO_THRESHOLD_ATC 80 /* kHz */
233 236
234enum FAT_STATE {
235 FAT_NORMAL_STATE = 0,
236 FAT_TRAINING_STATE = 1,
237};
238
239enum tag_dynamic_init_gain_operation_type_definition {
240 DIG_TYPE_THRESH_HIGH = 0,
241 DIG_TYPE_THRESH_LOW = 1,
242 DIG_TYPE_BACKOFF = 2,
243 DIG_TYPE_RX_GAIN_MIN = 3,
244 DIG_TYPE_RX_GAIN_MAX = 4,
245 DIG_TYPE_ENABLE = 5,
246 DIG_TYPE_DISABLE = 6,
247 DIG_OP_TYPE_MAX
248};
249
250enum dm_1r_cca_e { 237enum dm_1r_cca_e {
251 CCA_1R = 0, 238 CCA_1R = 0,
252 CCA_2R = 1, 239 CCA_2R = 1,
@@ -292,12 +279,17 @@ enum pwr_track_control_method {
292#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1) 279#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
293#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1) 280#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
294#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1) 281#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
282#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
283 ((((struct rtl_priv *)(_priv))->mac80211.opmode == \
284 NL80211_IFTYPE_ADHOC) ? \
285 (((struct rtl_priv *)(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) :\
286 (((struct rtl_priv *)(_priv))->dm.undecorated_smoothed_pwdb))
295 287
296void rtl8723be_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, u8 *pdesc, 288void rtl8723be_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, u8 *pdesc,
297 u32 mac_id); 289 u32 mac_id);
298void rtl8723be_dm_ant_sel_statistics(struct ieee80211_hw *hw, u8 antsel_tr_mux, 290void rtl8723be_dm_ant_sel_statistics(struct ieee80211_hw *hw, u8 antsel_tr_mux,
299 u32 mac_id, u32 rx_pwdb_all); 291 u32 mac_id, u32 rx_pwdb_all);
300void rtl8723be_dm_fast_antenna_trainning_callback(unsigned long data); 292void rtl8723be_dm_fast_antenna_training_callback(unsigned long data);
301void rtl8723be_dm_init(struct ieee80211_hw *hw); 293void rtl8723be_dm_init(struct ieee80211_hw *hw);
302void rtl8723be_dm_watchdog(struct ieee80211_hw *hw); 294void rtl8723be_dm_watchdog(struct ieee80211_hw *hw);
303void rtl8723be_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi); 295void rtl8723be_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
@@ -305,6 +297,4 @@ void rtl8723be_dm_check_txpower_tracking(struct ieee80211_hw *hw);
305void rtl8723be_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 297void rtl8723be_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
306void rtl8723be_dm_txpower_track_adjust(struct ieee80211_hw *hw, u8 type, 298void rtl8723be_dm_txpower_track_adjust(struct ieee80211_hw *hw, u8 type,
307 u8 *pdirection, u32 *poutwrite_val); 299 u8 *pdirection, u32 *poutwrite_val);
308void rtl8723be_dm_init_edca_turbo(struct ieee80211_hw *hw);
309
310#endif 300#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/fw.c b/drivers/net/wireless/rtlwifi/rtl8723be/fw.c
index f856be6fc138..0c07992985b9 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/fw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/fw.c
@@ -55,8 +55,8 @@ static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
55 bool isfw_read = false; 55 bool isfw_read = false;
56 u8 buf_index = 0; 56 u8 buf_index = 0;
57 bool bwrite_sucess = false; 57 bool bwrite_sucess = false;
58 u8 wait_h2c_limit = 100; 58 u8 wait_h2c_limmit = 100;
59 u8 wait_writeh2c_limit = 100; 59 u8 wait_writeh2c_limmit = 100;
60 u8 boxcontent[4], boxextcontent[4]; 60 u8 boxcontent[4], boxextcontent[4];
61 u32 h2c_waitcounter = 0; 61 u32 h2c_waitcounter = 0;
62 unsigned long flag; 62 unsigned long flag;
@@ -68,8 +68,8 @@ static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
68 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); 68 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
69 if (rtlhal->h2c_setinprogress) { 69 if (rtlhal->h2c_setinprogress) {
70 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 70 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
71 "H2C set in progress! Wait to set.." 71 "H2C set in progress! Wait to set..element_id(%d).\n",
72 "element_id(%d).\n", element_id); 72 element_id);
73 73
74 while (rtlhal->h2c_setinprogress) { 74 while (rtlhal->h2c_setinprogress) {
75 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, 75 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
@@ -92,14 +92,15 @@ static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
92 break; 92 break;
93 } 93 }
94 } 94 }
95
95 while (!bwrite_sucess) { 96 while (!bwrite_sucess) {
96 wait_writeh2c_limit--; 97 wait_writeh2c_limmit--;
97 if (wait_writeh2c_limit == 0) { 98 if (wait_writeh2c_limmit == 0) {
98 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 99 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
99 "Write H2C fail because no trigger " 100 "Write H2C fail because no trigger for FW INT!\n");
100 "for FW INT!\n");
101 break; 101 break;
102 } 102 }
103
103 boxnum = rtlhal->last_hmeboxnum; 104 boxnum = rtlhal->last_hmeboxnum;
104 switch (boxnum) { 105 switch (boxnum) {
105 case 0: 106 case 0:
@@ -120,39 +121,43 @@ static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
120 break; 121 break;
121 default: 122 default:
122 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 123 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
123 "switch case not processed\n"); 124 "switch case not process\n");
124 break; 125 break;
125 } 126 }
127
126 isfw_read = _rtl8723be_check_fw_read_last_h2c(hw, boxnum); 128 isfw_read = _rtl8723be_check_fw_read_last_h2c(hw, boxnum);
127 while (!isfw_read) { 129 while (!isfw_read) {
128 wait_h2c_limit--; 130 wait_h2c_limmit--;
129 if (wait_h2c_limit == 0) { 131 if (wait_h2c_limmit == 0) {
130 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 132 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
131 "Wating too long for FW read " 133 "Waiting too long for FW read clear HMEBox(%d)!\n",
132 "clear HMEBox(%d)!\n", boxnum); 134 boxnum);
133 break; 135 break;
134 } 136 }
137
135 udelay(10); 138 udelay(10);
136 139
137 isfw_read = _rtl8723be_check_fw_read_last_h2c(hw, 140 isfw_read = _rtl8723be_check_fw_read_last_h2c(hw,
138 boxnum); 141 boxnum);
139 u1b_tmp = rtl_read_byte(rtlpriv, 0x130); 142 u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
140 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 143 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
141 "Wating for FW read clear HMEBox(%d)!!! 0x130 = %2x\n", 144 "Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
142 boxnum, u1b_tmp); 145 boxnum, u1b_tmp);
143 } 146 }
147
144 if (!isfw_read) { 148 if (!isfw_read) {
145 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 149 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
146 "Write H2C register BOX[%d] fail!!!!! " 150 "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
147 "Fw do not read.\n", boxnum); 151 boxnum);
148 break; 152 break;
149 } 153 }
154
150 memset(boxcontent, 0, sizeof(boxcontent)); 155 memset(boxcontent, 0, sizeof(boxcontent));
151 memset(boxextcontent, 0, sizeof(boxextcontent)); 156 memset(boxextcontent, 0, sizeof(boxextcontent));
152 boxcontent[0] = element_id; 157 boxcontent[0] = element_id;
153 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 158 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
154 "Write element_id box_reg(%4x) = %2x\n", 159 "Write element_id box_reg(%4x) = %2x\n",
155 box_reg, element_id); 160 box_reg, element_id);
156 161
157 switch (cmd_len) { 162 switch (cmd_len) {
158 case 1: 163 case 1:
@@ -181,6 +186,7 @@ static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
181 rtl_write_byte(rtlpriv, box_extreg + idx, 186 rtl_write_byte(rtlpriv, box_extreg + idx,
182 boxextcontent[idx]); 187 boxextcontent[idx]);
183 } 188 }
189
184 for (idx = 0; idx < 4; idx++) { 190 for (idx = 0; idx < 4; idx++) {
185 rtl_write_byte(rtlpriv, box_reg + idx, 191 rtl_write_byte(rtlpriv, box_reg + idx,
186 boxcontent[idx]); 192 boxcontent[idx]);
@@ -191,6 +197,7 @@ static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
191 "switch case not process\n"); 197 "switch case not process\n");
192 break; 198 break;
193 } 199 }
200
194 bwrite_sucess = true; 201 bwrite_sucess = true;
195 202
196 rtlhal->last_hmeboxnum = boxnum + 1; 203 rtlhal->last_hmeboxnum = boxnum + 1;
@@ -199,8 +206,9 @@ static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
199 206
200 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 207 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
201 "pHalData->last_hmeboxnum = %d\n", 208 "pHalData->last_hmeboxnum = %d\n",
202 rtlhal->last_hmeboxnum); 209 rtlhal->last_hmeboxnum);
203 } 210 }
211
204 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); 212 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
205 rtlhal->h2c_setinprogress = false; 213 rtlhal->h2c_setinprogress = false;
206 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); 214 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
@@ -219,6 +227,7 @@ void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
219 "return H2C cmd because of Fw download fail!!!\n"); 227 "return H2C cmd because of Fw download fail!!!\n");
220 return; 228 return;
221 } 229 }
230
222 memset(tmp_cmdbuf, 0, 8); 231 memset(tmp_cmdbuf, 0, 8);
223 memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len); 232 memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
224 _rtl8723be_fill_h2c_command(hw, element_id, cmd_len, 233 _rtl8723be_fill_h2c_command(hw, element_id, cmd_len,
@@ -229,17 +238,17 @@ void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
229void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode) 238void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
230{ 239{
231 struct rtl_priv *rtlpriv = rtl_priv(hw); 240 struct rtl_priv *rtlpriv = rtl_priv(hw);
232 u8 u1_h2c_set_pwrmode[H2C_8723BE_PWEMODE_LENGTH] = { 0 }; 241 u8 u1_h2c_set_pwrmode[H2C_PWEMODE_LENGTH] = { 0 };
233 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 242 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
234 u8 rlbm, power_state = 0; 243 u8 rlbm, power_state = 0;
235 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode); 244 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
236 245
237 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0)); 246 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
238 rlbm = 0;/*YJ, temp, 120316. FW now not support RLBM = 2.*/ 247 rlbm = 0;/*YJ,temp,120316. FW now not support RLBM=2.*/
239 SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm); 248 SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
240 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 249 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
241 (rtlpriv->mac80211.p2p) ? 250 (rtlpriv->mac80211.p2p) ?
242 ppsc->smart_ps : 1); 251 ppsc->smart_ps : 1);
243 SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode, 252 SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
244 ppsc->reg_max_lps_awakeintvl); 253 ppsc->reg_max_lps_awakeintvl);
245 SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0); 254 SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
@@ -251,44 +260,26 @@ void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
251 260
252 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, 261 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
253 "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n", 262 "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
254 u1_h2c_set_pwrmode, H2C_8723BE_PWEMODE_LENGTH); 263 u1_h2c_set_pwrmode, H2C_PWEMODE_LENGTH);
255 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_SETPWRMODE, 264 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_SETPWRMODE, H2C_PWEMODE_LENGTH,
256 H2C_8723BE_PWEMODE_LENGTH,
257 u1_h2c_set_pwrmode); 265 u1_h2c_set_pwrmode);
258} 266}
259 267
260static bool _rtl8723be_cmd_send_packet(struct ieee80211_hw *hw, 268void rtl8723be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus)
261 struct sk_buff *skb)
262{ 269{
263 struct rtl_priv *rtlpriv = rtl_priv(hw); 270 u8 parm[3] = { 0, 0, 0 };
264 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 271 /* parm[0]: bit0=0-->Disconnect, bit0=1-->Connect
265 struct rtl8192_tx_ring *ring; 272 * bit1=0-->update Media Status to MACID
266 struct rtl_tx_desc *pdesc; 273 * bit1=1-->update Media Status from MACID to MACID_End
267 struct sk_buff *pskb = NULL; 274 * parm[1]: MACID, if this is INFRA_STA, MacID = 0
268 u8 own; 275 * parm[2]: MACID_End
269 unsigned long flags; 276 */
270 277 SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
271 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 278 SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
272 279
273 pskb = __skb_dequeue(&ring->queue); 280 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_MSRRPT, 3, parm);
274 if (pskb)
275 kfree_skb(pskb);
276
277 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
278
279 pdesc = &ring->desc[0];
280 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc, true, HW_DESC_OWN);
281
282 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
283
284 __skb_queue_tail(&ring->queue, skb);
285
286 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
287
288 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
289
290 return true;
291} 281}
282
292#define BEACON_PG 0 /* ->1 */ 283#define BEACON_PG 0 /* ->1 */
293#define PSPOLL_PG 2 284#define PSPOLL_PG 2
294#define NULL_PG 3 285#define NULL_PG 3
@@ -407,7 +398,7 @@ static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
407}; 398};
408 399
409void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, 400void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
410 bool dl_finished) 401 bool b_dl_finished)
411{ 402{
412 struct rtl_priv *rtlpriv = rtl_priv(hw); 403 struct rtl_priv *rtlpriv = rtl_priv(hw);
413 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 404 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@@ -416,7 +407,7 @@ void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
416 u32 totalpacketlen; 407 u32 totalpacketlen;
417 bool rtstatus; 408 bool rtstatus;
418 u8 u1rsvdpageloc[5] = { 0 }; 409 u8 u1rsvdpageloc[5] = { 0 };
419 bool dlok = false; 410 bool b_dlok = false;
420 411
421 u8 *beacon; 412 u8 *beacon;
422 u8 *p_pspoll; 413 u8 *p_pspoll;
@@ -466,43 +457,40 @@ void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
466 totalpacketlen = TOTAL_RESERVED_PKT_LEN; 457 totalpacketlen = TOTAL_RESERVED_PKT_LEN;
467 458
468 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, 459 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
469 "rtl8723be_set_fw_rsvdpagepkt(): " 460 "rtl8723be_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
470 "HW_VAR_SET_TX_CMD: ALL\n",
471 &reserved_page_packet[0], totalpacketlen); 461 &reserved_page_packet[0], totalpacketlen);
472 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, 462 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
473 "rtl8723be_set_fw_rsvdpagepkt(): " 463 "rtl8723be_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
474 "HW_VAR_SET_TX_CMD: ALL\n", u1rsvdpageloc, 3); 464 u1rsvdpageloc, 3);
475
476 465
477 skb = dev_alloc_skb(totalpacketlen); 466 skb = dev_alloc_skb(totalpacketlen);
478 memcpy((u8 *)skb_put(skb, totalpacketlen), 467 memcpy((u8 *)skb_put(skb, totalpacketlen),
479 &reserved_page_packet, totalpacketlen); 468 &reserved_page_packet, totalpacketlen);
480 469
481 rtstatus = _rtl8723be_cmd_send_packet(hw, skb); 470 rtstatus = rtl8723_cmd_send_packet(hw, skb);
482 471
483 if (rtstatus) 472 if (rtstatus)
484 dlok = true; 473 b_dlok = true;
485 474
486 if (dlok) { 475 if (b_dlok) {
487 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 476 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
488 "Set RSVD page location to Fw.\n"); 477 "Set RSVD page location to Fw.\n");
489 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, "H2C_RSVDPAGE:\n", 478 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, "H2C_RSVDPAGE:\n",
490 u1rsvdpageloc, 3); 479 u1rsvdpageloc, 3);
491 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_RSVDPAGE, 480 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RSVDPAGE,
492 sizeof(u1rsvdpageloc), u1rsvdpageloc); 481 sizeof(u1rsvdpageloc), u1rsvdpageloc);
493 } else { 482 } else
494 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 483 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
495 "Set RSVD page location to Fw FAIL!!!!!!.\n"); 484 "Set RSVD page location to Fw FAIL!!!!!!.\n");
496 }
497} 485}
498 486
499/*Should check FW support p2p or not.*/ 487/*Should check FW support p2p or not.*/
500static void rtl8723be_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, 488static void rtl8723be_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
501 u8 ctwindow) 489 u8 ctwindow)
502{ 490{
503 u8 u1_ctwindow_period[1] = {ctwindow}; 491 u8 u1_ctwindow_period[1] = { ctwindow};
504 492
505 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_P2P_PS_CTW_CMD, 1, 493 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_P2P_PS_CTW_CMD, 1,
506 u1_ctwindow_period); 494 u1_ctwindow_period);
507} 495}
508 496
@@ -521,7 +509,7 @@ void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
521 switch (p2p_ps_state) { 509 switch (p2p_ps_state) {
522 case P2P_PS_DISABLE: 510 case P2P_PS_DISABLE:
523 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n"); 511 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
524 memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t)); 512 memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
525 break; 513 break;
526 case P2P_PS_ENABLE: 514 case P2P_PS_ENABLE:
527 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n"); 515 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
@@ -532,7 +520,7 @@ void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
532 rtl8723be_set_p2p_ctw_period_cmd(hw, ctwindow); 520 rtl8723be_set_p2p_ctw_period_cmd(hw, ctwindow);
533 } 521 }
534 /* hw only support 2 set of NoA */ 522 /* hw only support 2 set of NoA */
535 for (i = 0; i < p2pinfo->noa_num; i++) { 523 for (i = 0 ; i < p2pinfo->noa_num ; i++) {
536 /* To control the register setting 524 /* To control the register setting
537 * for which NOA 525 * for which NOA
538 */ 526 */
@@ -563,6 +551,7 @@ void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
563 rtl_write_dword(rtlpriv, 0x5EC, 551 rtl_write_dword(rtlpriv, 0x5EC,
564 p2pinfo->noa_count_type[i]); 552 p2pinfo->noa_count_type[i]);
565 } 553 }
554
566 if ((p2pinfo->opp_ps == 1) || 555 if ((p2pinfo->opp_ps == 1) ||
567 (p2pinfo->noa_num > 0)) { 556 (p2pinfo->noa_num > 0)) {
568 /* rst p2p circuit */ 557 /* rst p2p circuit */
@@ -591,30 +580,60 @@ void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
591 default: 580 default:
592 break; 581 break;
593 } 582 }
594 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_P2P_PS_OFFLOAD, 1, 583
584 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_P2P_PS_OFFLOAD, 1,
595 (u8 *)p2p_ps_offload); 585 (u8 *)p2p_ps_offload);
596} 586}
597 587
598void rtl8723be_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) 588static void _rtl8723be_c2h_content_parsing(struct ieee80211_hw *hw,
589 u8 c2h_cmd_id,
590 u8 c2h_cmd_len, u8 *tmp_buf)
599{ 591{
600 u8 u1_joinbssrpt_parm[1] = { 0 }; 592 struct rtl_priv *rtlpriv = rtl_priv(hw);
601
602 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
603 593
604 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_JOINBSSRPT, 1, 594 switch (c2h_cmd_id) {
605 u1_joinbssrpt_parm); 595 case C2H_8723B_DBG:
596 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
597 "[C2H], C2H_8723BE_DBG!!\n");
598 break;
599 case C2H_8723B_TX_REPORT:
600 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
601 "[C2H], C2H_8723BE_TX_REPORT!\n");
602 break;
603 case C2H_8723B_BT_INFO:
604 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
605 "[C2H], C2H_8723BE_BT_INFO!!\n");
606 rtlpriv->btcoexist.btc_ops->btc_btinfo_notify(rtlpriv, tmp_buf,
607 c2h_cmd_len);
608 break;
609 case C2H_8723B_BT_MP:
610 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
611 "[C2H], C2H_8723BE_BT_MP!!\n");
612 break;
613 default:
614 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
615 "[C2H], Unkown packet!! CmdId(%#X)!\n", c2h_cmd_id);
616 break;
617 }
606} 618}
607 619
608void rtl8723be_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw, 620void rtl8723be_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len)
609 u8 ap_offload_enable)
610{ 621{
611 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 622 struct rtl_priv *rtlpriv = rtl_priv(hw);
612 u8 u1_apoffload_parm[H2C_8723BE_AP_OFFLOAD_LENGTH] = { 0 }; 623 u8 c2h_cmd_id = 0, c2h_cmd_seq = 0, c2h_cmd_len = 0;
624 u8 *tmp_buf = NULL;
625
626 c2h_cmd_id = buffer[0];
627 c2h_cmd_seq = buffer[1];
628 c2h_cmd_len = len - 2;
629 tmp_buf = buffer + 2;
630
631 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
632 "[C2H packet], c2hCmdId=0x%x, c2hCmdSeq=0x%x, c2hCmdLen=%d\n",
633 c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len);
613 634
614 SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable); 635 RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_TRACE,
615 SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid); 636 "[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
616 SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
617 637
618 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_AP_OFFLOAD, 638 _rtl8723be_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
619 H2C_8723BE_AP_OFFLOAD_LENGTH, u1_apoffload_parm);
620} 639}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/fw.h b/drivers/net/wireless/rtlwifi/rtl8723be/fw.h
index 31eec281e446..067429669bda 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/fw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/fw.h
@@ -30,50 +30,23 @@
30#define FW_8192C_END_ADDRESS 0x5FFF 30#define FW_8192C_END_ADDRESS 0x5FFF
31#define FW_8192C_PAGE_SIZE 4096 31#define FW_8192C_PAGE_SIZE 4096
32#define FW_8192C_POLLING_DELAY 5 32#define FW_8192C_POLLING_DELAY 5
33#define FW_8192C_POLLING_TIMEOUT_COUNT 6000
34 33
35#define IS_FW_HEADER_EXIST(_pfwhdr) \
36 ((_pfwhdr->signature&0xFFF0) == 0x5300)
37#define USE_OLD_WOWLAN_DEBUG_FW 0 34#define USE_OLD_WOWLAN_DEBUG_FW 0
38 35
39#define H2C_8723BE_RSVDPAGE_LOC_LEN 5 36#define H2C_PWEMODE_LENGTH 5
40#define H2C_8723BE_PWEMODE_LENGTH 5
41#define H2C_8723BE_JOINBSSRPT_LENGTH 1
42#define H2C_8723BE_AP_OFFLOAD_LENGTH 3
43#define H2C_8723BE_WOWLAN_LENGTH 3
44#define H2C_8723BE_KEEP_ALIVE_CTRL_LENGTH 3
45#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
46#define H2C_8723BE_REMOTE_WAKE_CTRL_LEN 1
47#else
48#define H2C_8723BE_REMOTE_WAKE_CTRL_LEN 3
49#endif
50#define H2C_8723BE_AOAC_GLOBAL_INFO_LEN 2
51#define H2C_8723BE_AOAC_RSVDPAGE_LOC_LEN 7
52
53 37
54/* Fw PS state for RPWM. 38/* Fw PS state for RPWM.
55*BIT[2:0] = HW state 39*BIT[2:0] = HW state
56*BIT[3] = Protocol PS state, 1: register active state , 0: register sleep state 40*BIT[3] = Protocol PS state, 1: register active state , 0: register sleep state
57*BIT[4] = sub-state 41*BIT[4] = sub-state
58*/ 42*/
59#define FW_PS_GO_ON BIT(0)
60#define FW_PS_TX_NULL BIT(1)
61#define FW_PS_RF_ON BIT(2) 43#define FW_PS_RF_ON BIT(2)
62#define FW_PS_REGISTER_ACTIVE BIT(3) 44#define FW_PS_REGISTER_ACTIVE BIT(3)
63 45
64#define FW_PS_DPS BIT(0)
65#define FW_PS_LCLK (FW_PS_DPS)
66#define FW_PS_RF_OFF BIT(1)
67#define FW_PS_ALL_ON BIT(2)
68#define FW_PS_ST_ACTIVE BIT(3)
69#define FW_PS_ISR_ENABLE BIT(4)
70#define FW_PS_IMR_ENABLE BIT(5)
71
72
73#define FW_PS_ACK BIT(6) 46#define FW_PS_ACK BIT(6)
74#define FW_PS_TOGGLE BIT(7) 47#define FW_PS_TOGGLE BIT(7)
75 48
76 /* 88E RPWM value*/ 49 /* 8723BE RPWM value*/
77 /* BIT[0] = 1: 32k, 0: 40M*/ 50 /* BIT[0] = 1: 32k, 0: 40M*/
78#define FW_PS_CLOCK_OFF BIT(0) /* 32k*/ 51#define FW_PS_CLOCK_OFF BIT(0) /* 32k*/
79#define FW_PS_CLOCK_ON 0 /*40M*/ 52#define FW_PS_CLOCK_ON 0 /*40M*/
@@ -83,75 +56,61 @@
83/*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/ 56/*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/
84#define FW_PS_STATE_INT_MASK (0x3F) 57#define FW_PS_STATE_INT_MASK (0x3F)
85 58
86#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x)) 59#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
87#define FW_PS_STATE_HW(x) (FW_PS_STATE_HW_MASK & (x))
88#define FW_PS_STATE_INT(x) (FW_PS_STATE_INT_MASK & (x))
89#define FW_PS_ISR_VAL(x) ((x) & 0x70)
90#define FW_PS_IMR_MASK(x) ((x) & 0xDF)
91#define FW_PS_KEEP_IMR(x) ((x) & 0x20)
92
93
94#define FW_PS_STATE_S0 (FW_PS_DPS)
95#define FW_PS_STATE_S1 (FW_PS_LCLK)
96#define FW_PS_STATE_S2 (FW_PS_RF_OFF)
97#define FW_PS_STATE_S3 (FW_PS_ALL_ON)
98#define FW_PS_STATE_S4 ((FW_PS_ST_ACTIVE) | (FW_PS_ALL_ON))
99 60
100/* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/ 61/* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/
101#define FW_PS_STATE_ALL_ON_88E (FW_PS_CLOCK_ON) 62#define FW_PS_STATE_ALL_ON (FW_PS_CLOCK_ON)
102/* (FW_PS_RF_ON)*/ 63/* (FW_PS_RF_ON)*/
103#define FW_PS_STATE_RF_ON_88E (FW_PS_CLOCK_ON) 64#define FW_PS_STATE_RF_ON (FW_PS_CLOCK_ON)
104/* 0x0*/ 65/* 0x0*/
105#define FW_PS_STATE_RF_OFF_88E (FW_PS_CLOCK_ON) 66#define FW_PS_STATE_RF_OFF (FW_PS_CLOCK_ON)
106/* (FW_PS_STATE_RF_OFF)*/ 67/* (FW_PS_STATE_RF_OFF)*/
107#define FW_PS_STATE_RF_OFF_LOW_PWR_88E (FW_PS_CLOCK_OFF) 68#define FW_PS_STATE_RF_OFF_LOW_PWR (FW_PS_CLOCK_OFF)
108 69
109#define FW_PS_STATE_ALL_ON_92C (FW_PS_STATE_S4)
110#define FW_PS_STATE_RF_ON_92C (FW_PS_STATE_S3)
111#define FW_PS_STATE_RF_OFF_92C (FW_PS_STATE_S2)
112#define FW_PS_STATE_RF_OFF_LOW_PWR_92C (FW_PS_STATE_S1)
113 70
114 71/* For 8723BE H2C PwrMode Cmd ID 5.*/
115/* For 88E H2C PwrMode Cmd ID 5.*/
116#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE)) 72#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
117#define FW_PWR_STATE_RF_OFF 0 73#define FW_PWR_STATE_RF_OFF 0
118 74
119#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK) 75#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
120#define FW_PS_IS_CLK_ON(x) ((x) & (FW_PS_RF_OFF | FW_PS_ALL_ON))
121#define FW_PS_IS_RF_ON(x) ((x) & (FW_PS_ALL_ON))
122#define FW_PS_IS_ACTIVE(x) ((x) & (FW_PS_ST_ACTIVE))
123#define FW_PS_IS_CPWM_INT(x) ((x) & 0x40)
124
125#define FW_CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
126 76
127#define IS_IN_LOW_POWER_STATE_88E(fwpsstate) \ 77#define IS_IN_LOW_POWER_STATE(__fwpsstate) \
128 (FW_PS_STATE(fwpsstate) == FW_PS_CLOCK_OFF) 78 (FW_PS_STATE(__fwpsstate) == FW_PS_CLOCK_OFF)
129 79
130#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE)) 80#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
131#define FW_PWR_STATE_RF_OFF 0 81#define FW_PWR_STATE_RF_OFF 0
132 82
133#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0)) 83enum rtl8723b_h2c_cmd {
134 84 H2C_8723B_RSVDPAGE = 0,
135#define SET_88E_H2CCMD_WOWLAN_FUNC_ENABLE(__ph2ccmd, __val) \ 85 H2C_8723B_MSRRPT = 1,
136 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 1, __val) 86 H2C_8723B_SCAN = 2,
137#define SET_88E_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__ph2ccmd, __val) \ 87 H2C_8723B_KEEP_ALIVE_CTRL = 3,
138 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 1, 1, __val) 88 H2C_8723B_DISCONNECT_DECISION = 4,
139#define SET_88E_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__ph2ccmd, __val) \ 89 H2C_8723B_BCN_RSVDPAGE = 9,
140 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 2, 1, __val) 90 H2C_8723B_PROBERSP_RSVDPAGE = 10,
141#define SET_88E_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__ph2ccmd, __val) \ 91
142 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 3, 1, __val) 92 H2C_8723B_SETPWRMODE = 0x20,
143#define SET_88E_H2CCMD_WOWLAN_ALL_PKT_DROP(__ph2ccmd, __val) \ 93 H2C_8723B_PS_LPS_PARA = 0x23,
144 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 4, 1, __val) 94 H2C_8723B_P2P_PS_OFFLOAD = 0x24,
145#define SET_88E_H2CCMD_WOWLAN_GPIO_ACTIVE(__ph2ccmd, __val) \ 95
146 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 5, 1, __val) 96 H2C_8723B_RA_MASK = 0x40,
147#define SET_88E_H2CCMD_WOWLAN_REKEY_WAKE_UP(__ph2ccmd, __val) \ 97 H2C_RSSIBE_REPORT = 0x42,
148 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 6, 1, __val) 98 /*Not defined CTW CMD for P2P yet*/
149#define SET_88E_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__ph2ccmd, __val) \ 99 H2C_8723B_P2P_PS_CTW_CMD,
150 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 7, 1, __val) 100 MAX_8723B_H2CCMD
151#define SET_88E_H2CCMD_WOWLAN_GPIONUM(__ph2ccmd, __val) \ 101};
152 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val) 102
153#define SET_88E_H2CCMD_WOWLAN_GPIO_DURATION(__ph2ccmd, __val) \ 103enum rtl8723b_c2h_evt {
154 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val) 104 C2H_8723B_DBG = 0,
105 C2H_8723B_LB = 1,
106 C2H_8723B_TXBF = 2,
107 C2H_8723B_TX_REPORT = 3,
108 C2H_8723B_BT_INFO = 9,
109 C2H_8723B_BT_MP = 11,
110 MAX_8723B_C2HEVENT
111};
112
113#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
155 114
156 115
157#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \ 116#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
@@ -169,8 +128,11 @@
169#define GET_88E_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd) \ 128#define GET_88E_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd) \
170 LE_BITS_TO_1BYTE(__ph2ccmd, 0, 8) 129 LE_BITS_TO_1BYTE(__ph2ccmd, 0, 8)
171 130
172#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \ 131#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__ph2ccmd, __val) \
173 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val) 132 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 1, __val)
133#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__ph2ccmd, __val) \
134 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 1, 1, __val)
135
174#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \ 136#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
175 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val) 137 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
176#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \ 138#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
@@ -178,71 +140,13 @@
178#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \ 140#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
179 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val) 141 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
180 142
181/* AP_OFFLOAD */
182#define SET_H2CCMD_AP_OFFLOAD_ON(__ph2ccmd, __val) \
183 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
184#define SET_H2CCMD_AP_OFFLOAD_HIDDEN(__ph2ccmd, __val) \
185 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
186#define SET_H2CCMD_AP_OFFLOAD_DENYANY(__ph2ccmd, __val) \
187 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
188#define SET_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__ph2ccmd, __val) \
189 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+3, 0, 8, __val)
190 143
191/* Keep Alive Control*/
192#define SET_88E_H2CCMD_KEEP_ALIVE_ENABLE(__ph2ccmd, __val) \
193 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 1, __val)
194#define SET_88E_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__ph2ccmd, __val)\
195 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 1, 1, __val)
196#define SET_88E_H2CCMD_KEEP_ALIVE_PERIOD(__ph2ccmd, __val) \
197 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
198
199/*REMOTE_WAKE_CTRL */
200#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_EN(__ph2ccmd, __val) \
201 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 1, __val)
202#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
203#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__ph2ccmd, __val)\
204 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 1, 1, __val)
205#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__ph2ccmd, __val)\
206 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 2, 1, __val)
207#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__ph2ccmd, __val)\
208 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 3, 1, __val)
209#else
210#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_PAIRWISE_ENC_ALG(__ph2ccmd, __val)\
211 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
212#define SET_88E_H2CCMD_REMOTE_WAKE_CTRL_GROUP_ENC_ALG(__ph2ccmd, __val) \
213 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
214#endif
215
216/* GTK_OFFLOAD */
217#define SET_88E_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__ph2ccmd, __val)\
218 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
219#define SET_88E_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__ph2ccmd, __val) \
220 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
221
222/* AOAC_RSVDPAGE_LOC */
223#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_REM_WAKE_CTRL_INFO(__ph2ccmd, __val)\
224 SET_BITS_TO_LE_1BYTE((__ph2ccmd), 0, 8, __val)
225#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__ph2ccmd, __val) \
226 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
227#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__ph2ccmd, __val) \
228 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
229#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__ph2ccmd, __val) \
230 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+3, 0, 8, __val)
231#define SET_88E_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__ph2ccmd, __val) \
232 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+4, 0, 8, __val)
233
234void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
235void rtl8723be_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
236 u8 ap_offload_enable);
237void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, 144void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
238 u32 cmd_len, u8 *p_cmdbuffer); 145 u32 cmd_len, u8 *p_cmdbuffer);
239void rtl8723be_firmware_selfreset(struct ieee80211_hw *hw); 146void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
240void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, 147void rtl8723be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus);
241 bool dl_finished); 148void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
242void rtl8723be_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus); 149void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
243int rtl8723be_download_fw(struct ieee80211_hw *hw, 150void rtl8723be_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len);
244 bool buse_wake_on_wlan_fw);
245void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
246 u8 p2p_ps_state);
247 151
248#endif 152#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
index d296b5ca9db1..6dad28e77bbb 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
@@ -33,6 +33,7 @@
33#include "reg.h" 33#include "reg.h"
34#include "def.h" 34#include "def.h"
35#include "phy.h" 35#include "phy.h"
36#include "../rtl8723com/phy_common.h"
36#include "dm.h" 37#include "dm.h"
37#include "../rtl8723com/dm_common.h" 38#include "../rtl8723com/dm_common.h"
38#include "fw.h" 39#include "fw.h"
@@ -50,7 +51,9 @@ static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
50 struct rtl_priv *rtlpriv = rtl_priv(hw); 51 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
52 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 53 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
54 unsigned long flags;
53 55
56 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
54 while (skb_queue_len(&ring->queue)) { 57 while (skb_queue_len(&ring->queue)) {
55 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 58 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
56 struct sk_buff *skb = __skb_dequeue(&ring->queue); 59 struct sk_buff *skb = __skb_dequeue(&ring->queue);
@@ -62,6 +65,7 @@ static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
62 kfree_skb(skb); 65 kfree_skb(skb);
63 ring->idx = (ring->idx + 1) % ring->entries; 66 ring->idx = (ring->idx + 1) % ring->entries;
64 } 67 }
68 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
65} 69}
66 70
67static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 71static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
@@ -73,7 +77,7 @@ static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
73 rtlpci->reg_bcn_ctrl_val |= set_bits; 77 rtlpci->reg_bcn_ctrl_val |= set_bits;
74 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 78 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
75 79
76 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 80 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
77} 81}
78 82
79static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw) 83static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
@@ -113,15 +117,15 @@ static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
113} 117}
114 118
115static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val, 119static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
116 bool need_turn_off_ckk) 120 bool b_need_turn_off_ckk)
117{ 121{
118 struct rtl_priv *rtlpriv = rtl_priv(hw); 122 struct rtl_priv *rtlpriv = rtl_priv(hw);
119 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
120 bool support_remote_wake_up; 124 bool b_support_remote_wake_up;
121 u32 count = 0, isr_regaddr, content; 125 u32 count = 0, isr_regaddr, content;
122 bool schedule_timer = need_turn_off_ckk; 126 bool b_schedule_timer = b_need_turn_off_ckk;
123 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 127 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
124 (u8 *)(&support_remote_wake_up)); 128 (u8 *)(&b_support_remote_wake_up));
125 129
126 if (!rtlhal->fw_ready) 130 if (!rtlhal->fw_ready)
127 return; 131 return;
@@ -146,9 +150,10 @@ static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
146 break; 150 break;
147 } 151 }
148 } 152 }
149 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) { 153
154 if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
150 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 155 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
151 &rpwm_val); 156 (u8 *)(&rpwm_val));
152 if (FW_PS_IS_ACK(rpwm_val)) { 157 if (FW_PS_IS_ACK(rpwm_val)) {
153 isr_regaddr = REG_HISR; 158 isr_regaddr = REG_HISR;
154 content = rtl_read_dword(rtlpriv, isr_regaddr); 159 content = rtl_read_dword(rtlpriv, isr_regaddr);
@@ -160,20 +165,19 @@ static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
160 165
161 if (content & IMR_CPWM) { 166 if (content & IMR_CPWM) {
162 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 167 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
163 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E; 168 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
164 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 169 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
165 "Receive CPWM INT!!! Set " 170 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
166 "pHalData->FwPSState = %X\n",
167 rtlhal->fw_ps_state); 171 rtlhal->fw_ps_state);
168 } 172 }
169 } 173 }
174
170 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 175 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
171 rtlhal->fw_clk_change_in_progress = false; 176 rtlhal->fw_clk_change_in_progress = false;
172 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 177 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
173 if (schedule_timer) { 178 if (b_schedule_timer)
174 mod_timer(&rtlpriv->works.fw_clockoff_timer, 179 mod_timer(&rtlpriv->works.fw_clockoff_timer,
175 jiffies + MSECS(10)); 180 jiffies + MSECS(10));
176 }
177 } else { 181 } else {
178 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 182 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
179 rtlhal->fw_clk_change_in_progress = false; 183 rtlhal->fw_clk_change_in_progress = false;
@@ -188,7 +192,7 @@ static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
189 struct rtl8192_tx_ring *ring; 193 struct rtl8192_tx_ring *ring;
190 enum rf_pwrstate rtstate; 194 enum rf_pwrstate rtstate;
191 bool schedule_timer = false; 195 bool b_schedule_timer = false;
192 u8 queue; 196 u8 queue;
193 197
194 if (!rtlhal->fw_ready) 198 if (!rtlhal->fw_ready)
@@ -204,17 +208,18 @@ static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
204 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 208 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
205 ring = &rtlpci->tx_ring[queue]; 209 ring = &rtlpci->tx_ring[queue];
206 if (skb_queue_len(&ring->queue)) { 210 if (skb_queue_len(&ring->queue)) {
207 schedule_timer = true; 211 b_schedule_timer = true;
208 break; 212 break;
209 } 213 }
210 } 214 }
211 if (schedule_timer) { 215
216 if (b_schedule_timer) {
212 mod_timer(&rtlpriv->works.fw_clockoff_timer, 217 mod_timer(&rtlpriv->works.fw_clockoff_timer,
213 jiffies + MSECS(10)); 218 jiffies + MSECS(10));
214 return; 219 return;
215 } 220 }
216 if (FW_PS_STATE(rtlhal->fw_ps_state) != 221
217 FW_PS_STATE_RF_OFF_LOW_PWR_88E) { 222 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
218 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
219 if (!rtlhal->fw_clk_change_in_progress) { 224 if (!rtlhal->fw_clk_change_in_progress) {
220 rtlhal->fw_clk_change_in_progress = true; 225 rtlhal->fw_clk_change_in_progress = true;
@@ -222,7 +227,7 @@ static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
222 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
223 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
224 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
225 &rpwm_val); 230 (u8 *)(&rpwm_val));
226 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_clk_change_in_progress = false; 232 rtlhal->fw_clk_change_in_progress = false;
228 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
@@ -232,12 +237,13 @@ static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
232 jiffies + MSECS(10)); 237 jiffies + MSECS(10));
233 } 238 }
234 } 239 }
240
235} 241}
236 242
237static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw) 243static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
238{ 244{
239 u8 rpwm_val = 0; 245 u8 rpwm_val = 0;
240 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK); 246 rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
241 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true); 247 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
242} 248}
243 249
@@ -250,21 +256,23 @@ static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
250 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
251 257
252 if (ppsc->low_power_enable) { 258 if (ppsc->low_power_enable) {
253 rpwm_val = (FW_PS_STATE_ALL_ON_88E | FW_PS_ACK);/* RF on */ 259 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
254 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false); 260 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
255 rtlhal->allow_sw_to_change_hwclc = false; 261 rtlhal->allow_sw_to_change_hwclc = false;
256 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
257 &fw_pwrmode); 263 (u8 *)(&fw_pwrmode));
258 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
259 (u8 *)(&fw_current_inps)); 265 (u8 *)(&fw_current_inps));
260 } else { 266 } else {
261 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */ 267 rpwm_val = FW_PS_STATE_ALL_ON; /* RF on */
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
269 (u8 *)(&rpwm_val));
263 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
264 &fw_pwrmode); 271 (u8 *)(&fw_pwrmode));
265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
266 (u8 *)(&fw_current_inps)); 273 (u8 *)(&fw_current_inps));
267 } 274 }
275
268} 276}
269 277
270static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw) 278static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
@@ -276,22 +284,23 @@ static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
276 u8 rpwm_val; 284 u8 rpwm_val;
277 285
278 if (ppsc->low_power_enable) { 286 if (ppsc->low_power_enable) {
279 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */ 287 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
280 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 288 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
281 (u8 *)(&fw_current_inps)); 289 (u8 *)(&fw_current_inps));
282 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 290 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
283 &ppsc->fwctrl_psmode); 291 (u8 *)(&ppsc->fwctrl_psmode));
284 rtlhal->allow_sw_to_change_hwclc = true; 292 rtlhal->allow_sw_to_change_hwclc = true;
285 _rtl8723be_set_fw_clock_off(hw, rpwm_val); 293 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
286
287 } else { 294 } else {
288 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */ 295 rpwm_val = FW_PS_STATE_RF_OFF; /* RF off */
289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 296 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
290 (u8 *)(&fw_current_inps)); 297 (u8 *)(&fw_current_inps));
291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 298 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
292 &ppsc->fwctrl_psmode); 299 (u8 *)(&ppsc->fwctrl_psmode));
293 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
301 (u8 *)(&rpwm_val));
294 } 302 }
303
295} 304}
296 305
297void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 306void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
@@ -307,13 +316,13 @@ void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
307 case HW_VAR_RF_STATE: 316 case HW_VAR_RF_STATE:
308 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 317 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
309 break; 318 break;
310 case HW_VAR_FWLPS_RF_ON: { 319 case HW_VAR_FWLPS_RF_ON:{
311 enum rf_pwrstate rfstate; 320 enum rf_pwrstate rfState;
312 u32 val_rcr; 321 u32 val_rcr;
313 322
314 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 323 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
315 (u8 *)(&rfstate)); 324 (u8 *)(&rfState));
316 if (rfstate == ERFOFF) { 325 if (rfState == ERFOFF) {
317 *((bool *)(val)) = true; 326 *((bool *)(val)) = true;
318 } else { 327 } else {
319 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 328 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
@@ -323,11 +332,12 @@ void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
323 else 332 else
324 *((bool *)(val)) = true; 333 *((bool *)(val)) = true;
325 } 334 }
326 break; } 335 }
336 break;
327 case HW_VAR_FW_PSMODE_STATUS: 337 case HW_VAR_FW_PSMODE_STATUS:
328 *((bool *)(val)) = ppsc->fw_current_inpsmode; 338 *((bool *)(val)) = ppsc->fw_current_inpsmode;
329 break; 339 break;
330 case HW_VAR_CORRECT_TSF: { 340 case HW_VAR_CORRECT_TSF:{
331 u64 tsf; 341 u64 tsf;
332 u32 *ptsf_low = (u32 *)&tsf; 342 u32 *ptsf_low = (u32 *)&tsf;
333 u32 *ptsf_high = ((u32 *)&tsf) + 1; 343 u32 *ptsf_high = ((u32 *)&tsf) + 1;
@@ -336,15 +346,65 @@ void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
336 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 346 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
337 347
338 *((u64 *)(val)) = tsf; 348 *((u64 *)(val)) = tsf;
339 349 }
340 break; } 350 break;
341 default: 351 default:
342 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 352 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
343 "switch case not process %x\n", variable); 353 "switch case not process %x\n", variable);
344 break; 354 break;
345 } 355 }
346} 356}
347 357
358static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
359{
360 struct rtl_priv *rtlpriv = rtl_priv(hw);
361 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
362 u8 count = 0, dlbcn_count = 0;
363 bool b_recover = false;
364
365 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
366 rtl_write_byte(rtlpriv, REG_CR + 1,
367 (tmp_regcr | BIT(0)));
368
369 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
370 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
371
372 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
373 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
374 if (tmp_reg422 & BIT(6))
375 b_recover = true;
376
377 do {
378 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
379 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
380 (bcnvalid_reg | BIT(0)));
381 _rtl8723be_return_beacon_queue_skb(hw);
382
383 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
384 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
385 count = 0;
386 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
387 count++;
388 udelay(10);
389 bcnvalid_reg = rtl_read_byte(rtlpriv,
390 REG_TDECTRL + 2);
391 }
392 dlbcn_count++;
393 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
394
395 if (bcnvalid_reg & BIT(0))
396 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
397
398 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
399 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
400
401 if (b_recover)
402 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
403
404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
406}
407
348void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 408void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
349{ 409{
350 struct rtl_priv *rtlpriv = rtl_priv(hw); 410 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -359,22 +419,24 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
359 for (idx = 0; idx < ETH_ALEN; idx++) 419 for (idx = 0; idx < ETH_ALEN; idx++)
360 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]); 420 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
361 break; 421 break;
362 case HW_VAR_BASIC_RATE: { 422 case HW_VAR_BASIC_RATE:{
363 u16 rate_cfg = ((u16 *)val)[0]; 423 u16 b_rate_cfg = ((u16 *)val)[0];
364 u8 rate_index = 0; 424 u8 rate_index = 0;
365 rate_cfg = rate_cfg & 0x15f; 425 b_rate_cfg = b_rate_cfg & 0x15f;
366 rate_cfg |= 0x01; 426 b_rate_cfg |= 0x01;
367 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 427 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
368 rtl_write_byte(rtlpriv, REG_RRSR + 1, (rate_cfg >> 8) & 0xff); 428 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
369 while (rate_cfg > 0x1) { 429 while (b_rate_cfg > 0x1) {
370 rate_cfg = (rate_cfg >> 1); 430 b_rate_cfg = (b_rate_cfg >> 1);
371 rate_index++; 431 rate_index++;
372 } 432 }
373 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index); 433 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
374 break; } 434 }
435 break;
375 case HW_VAR_BSSID: 436 case HW_VAR_BSSID:
376 for (idx = 0; idx < ETH_ALEN; idx++) 437 for (idx = 0; idx < ETH_ALEN; idx++)
377 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]); 438 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
439
378 break; 440 break;
379 case HW_VAR_SIFS: 441 case HW_VAR_SIFS:
380 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 442 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
@@ -389,7 +451,7 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
389 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 451 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
390 *((u16 *)val)); 452 *((u16 *)val));
391 break; 453 break;
392 case HW_VAR_SLOT_TIME: { 454 case HW_VAR_SLOT_TIME:{
393 u8 e_aci; 455 u8 e_aci;
394 456
395 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 457 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
@@ -399,12 +461,13 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
399 461
400 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 462 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
401 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 463 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
402 &e_aci); 464 (u8 *)(&e_aci));
403 } 465 }
404 break; } 466 }
405 case HW_VAR_ACK_PREAMBLE: { 467 break;
468 case HW_VAR_ACK_PREAMBLE:{
406 u8 reg_tmp; 469 u8 reg_tmp;
407 u8 short_preamble = (bool)*val; 470 u8 short_preamble = (bool)(*(u8 *)val);
408 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2); 471 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
409 if (short_preamble) { 472 if (short_preamble) {
410 reg_tmp |= 0x02; 473 reg_tmp |= 0x02;
@@ -413,15 +476,16 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
413 reg_tmp &= 0xFD; 476 reg_tmp &= 0xFD;
414 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp); 477 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
415 } 478 }
416 break; } 479 }
480 break;
417 case HW_VAR_WPA_CONFIG: 481 case HW_VAR_WPA_CONFIG:
418 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 482 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
419 break; 483 break;
420 case HW_VAR_AMPDU_MIN_SPACE: { 484 case HW_VAR_AMPDU_MIN_SPACE:{
421 u8 min_spacing_to_set; 485 u8 min_spacing_to_set;
422 u8 sec_min_space; 486 u8 sec_min_space;
423 487
424 min_spacing_to_set = *val; 488 min_spacing_to_set = *((u8 *)val);
425 if (min_spacing_to_set <= 7) { 489 if (min_spacing_to_set <= 7) {
426 sec_min_space = 0; 490 sec_min_space = 0;
427 491
@@ -435,26 +499,28 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
435 499
436 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 500 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
437 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 501 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
438 mac->min_space_cfg); 502 mac->min_space_cfg);
439 503
440 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 504 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
441 mac->min_space_cfg); 505 mac->min_space_cfg);
442 } 506 }
443 break; } 507 }
444 case HW_VAR_SHORTGI_DENSITY: { 508 break;
509 case HW_VAR_SHORTGI_DENSITY:{
445 u8 density_to_set; 510 u8 density_to_set;
446 511
447 density_to_set = *val; 512 density_to_set = *((u8 *)val);
448 mac->min_space_cfg |= (density_to_set << 3); 513 mac->min_space_cfg |= (density_to_set << 3);
449 514
450 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 515 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
451 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 516 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
452 mac->min_space_cfg); 517 mac->min_space_cfg);
453 518
454 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 519 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
455 mac->min_space_cfg); 520 mac->min_space_cfg);
456 break; } 521 }
457 case HW_VAR_AMPDU_FACTOR: { 522 break;
523 case HW_VAR_AMPDU_FACTOR:{
458 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 524 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
459 u8 factor_toset; 525 u8 factor_toset;
460 u8 *p_regtoset = NULL; 526 u8 *p_regtoset = NULL;
@@ -462,7 +528,7 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
462 528
463 p_regtoset = regtoset_normal; 529 p_regtoset = regtoset_normal;
464 530
465 factor_toset = *val; 531 factor_toset = *((u8 *)val);
466 if (factor_toset <= 3) { 532 if (factor_toset <= 3) {
467 factor_toset = (1 << (factor_toset + 2)); 533 factor_toset = (1 << (factor_toset + 2));
468 if (factor_toset > 0xf) 534 if (factor_toset > 0xf)
@@ -483,22 +549,26 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
483 rtl_write_byte(rtlpriv, 549 rtl_write_byte(rtlpriv,
484 (REG_AGGLEN_LMT + index), 550 (REG_AGGLEN_LMT + index),
485 p_regtoset[index]); 551 p_regtoset[index]);
552
486 } 553 }
554
487 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 555 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
488 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 556 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
489 factor_toset); 557 factor_toset);
490 } 558 }
491 break; } 559 }
492 case HW_VAR_AC_PARAM: { 560 break;
493 u8 e_aci = *val; 561 case HW_VAR_AC_PARAM:{
562 u8 e_aci = *((u8 *)val);
494 rtl8723_dm_init_edca_turbo(hw); 563 rtl8723_dm_init_edca_turbo(hw);
495 564
496 if (rtlpci->acm_method != EACMWAY2_SW) 565 if (rtlpci->acm_method != EACMWAY2_SW)
497 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, 566 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
498 &e_aci); 567 (u8 *)(&e_aci));
499 break; } 568 }
500 case HW_VAR_ACM_CTRL: { 569 break;
501 u8 e_aci = *val; 570 case HW_VAR_ACM_CTRL:{
571 u8 e_aci = *((u8 *)val);
502 union aci_aifsn *p_aci_aifsn = 572 union aci_aifsn *p_aci_aifsn =
503 (union aci_aifsn *)(&(mac->ac[0].aifs)); 573 (union aci_aifsn *)(&(mac->ac[0].aifs));
504 u8 acm = p_aci_aifsn->f.acm; 574 u8 acm = p_aci_aifsn->f.acm;
@@ -520,8 +590,8 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
520 break; 590 break;
521 default: 591 default:
522 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 592 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
523 "HW_VAR_ACM_CTRL acm set " 593 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
524 "failed: eACI is %d\n", acm); 594 acm);
525 break; 595 break;
526 } 596 }
527 } else { 597 } else {
@@ -536,27 +606,30 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
536 acm_ctrl &= (~ACMHW_BEQEN); 606 acm_ctrl &= (~ACMHW_BEQEN);
537 break; 607 break;
538 default: 608 default:
539 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 609 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
540 "switch case not process\n"); 610 "switch case not process\n");
541 break; 611 break;
542 } 612 }
543 } 613 }
614
544 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 615 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
545 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] " 616 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
546 "Write 0x%X\n", acm_ctrl); 617 acm_ctrl);
547 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 618 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
548 break; } 619 }
620 break;
549 case HW_VAR_RCR: 621 case HW_VAR_RCR:
550 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 622 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
551 rtlpci->receive_config = ((u32 *)(val))[0]; 623 rtlpci->receive_config = ((u32 *)(val))[0];
552 break; 624 break;
553 case HW_VAR_RETRY_LIMIT: { 625 case HW_VAR_RETRY_LIMIT:{
554 u8 retry_limit = *val; 626 u8 retry_limit = ((u8 *)(val))[0];
555 627
556 rtl_write_word(rtlpriv, REG_RL, 628 rtl_write_word(rtlpriv, REG_RL,
557 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 629 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
558 retry_limit << RETRY_LIMIT_LONG_SHIFT); 630 retry_limit << RETRY_LIMIT_LONG_SHIFT);
559 break; } 631 }
632 break;
560 case HW_VAR_DUAL_TSF_RST: 633 case HW_VAR_DUAL_TSF_RST:
561 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 634 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
562 break; 635 break;
@@ -564,25 +637,27 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
564 rtlefuse->efuse_usedbytes = *((u16 *)val); 637 rtlefuse->efuse_usedbytes = *((u16 *)val);
565 break; 638 break;
566 case HW_VAR_EFUSE_USAGE: 639 case HW_VAR_EFUSE_USAGE:
567 rtlefuse->efuse_usedpercentage = *val; 640 rtlefuse->efuse_usedpercentage = *((u8 *)val);
568 break; 641 break;
569 case HW_VAR_IO_CMD: 642 case HW_VAR_IO_CMD:
570 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val)); 643 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
571 break; 644 break;
572 case HW_VAR_SET_RPWM: { 645 case HW_VAR_SET_RPWM:{
573 u8 rpwm_val; 646 u8 rpwm_val;
574 647
575 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 648 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
576 udelay(1); 649 udelay(1);
577 650
578 if (rpwm_val & BIT(7)) { 651 if (rpwm_val & BIT(7)) {
579 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 652 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
580 } else { 653 } else {
581 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7)); 654 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
655 ((*(u8 *)val) | BIT(7)));
582 } 656 }
583 break; } 657 }
658 break;
584 case HW_VAR_H2C_FW_PWRMODE: 659 case HW_VAR_H2C_FW_PWRMODE:
585 rtl8723be_set_fw_pwrmode_cmd(hw, *val); 660 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
586 break; 661 break;
587 case HW_VAR_FW_PSMODE_STATUS: 662 case HW_VAR_FW_PSMODE_STATUS:
588 ppsc->fw_current_inpsmode = *((bool *)val); 663 ppsc->fw_current_inpsmode = *((bool *)val);
@@ -590,85 +665,38 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
590 case HW_VAR_RESUME_CLK_ON: 665 case HW_VAR_RESUME_CLK_ON:
591 _rtl8723be_set_fw_ps_rf_on(hw); 666 _rtl8723be_set_fw_ps_rf_on(hw);
592 break; 667 break;
593 case HW_VAR_FW_LPS_ACTION: { 668 case HW_VAR_FW_LPS_ACTION:{
594 bool enter_fwlps = *((bool *)val); 669 bool b_enter_fwlps = *((bool *)val);
595 670
596 if (enter_fwlps) 671 if (b_enter_fwlps)
597 _rtl8723be_fwlps_enter(hw); 672 _rtl8723be_fwlps_enter(hw);
598 else 673 else
599 _rtl8723be_fwlps_leave(hw); 674 _rtl8723be_fwlps_leave(hw);
600 675 }
601 break; } 676 break;
602 case HW_VAR_H2C_FW_JOINBSSRPT: { 677 case HW_VAR_H2C_FW_JOINBSSRPT:{
603 u8 mstatus = *val; 678 u8 mstatus = (*(u8 *)val);
604 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
605 u8 count = 0, dlbcn_count = 0;
606 bool recover = false;
607 679
608 if (mstatus == RT_MEDIA_CONNECT) { 680 if (mstatus == RT_MEDIA_CONNECT) {
609 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 681 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
610 682 _rtl8723be_download_rsvd_page(hw);
611 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 683 }
612 rtl_write_byte(rtlpriv, REG_CR + 1, 684 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
613 (tmp_regcr | BIT(0)));
614
615 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
616 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
617
618 tmp_reg422 = rtl_read_byte(rtlpriv,
619 REG_FWHW_TXQ_CTRL + 2);
620 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
621 tmp_reg422 & (~BIT(6)));
622 if (tmp_reg422 & BIT(6))
623 recover = true;
624
625 do {
626 bcnvalid_reg = rtl_read_byte(rtlpriv,
627 REG_TDECTRL + 2);
628 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
629 (bcnvalid_reg | BIT(0)));
630 _rtl8723be_return_beacon_queue_skb(hw);
631
632 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
633 bcnvalid_reg = rtl_read_byte(rtlpriv,
634 REG_TDECTRL + 2);
635 count = 0;
636 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
637 count++;
638 udelay(10);
639 bcnvalid_reg = rtl_read_byte(rtlpriv,
640 REG_TDECTRL + 2);
641 }
642 dlbcn_count++;
643 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
644
645 if (bcnvalid_reg & BIT(0))
646 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
647
648 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
649 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
650
651 if (recover) {
652 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
653 tmp_reg422);
654 }
655 rtl_write_byte(rtlpriv, REG_CR + 1,
656 (tmp_regcr & ~(BIT(0))));
657 } 685 }
658 rtl8723be_set_fw_joinbss_report_cmd(hw, *val); 686 break;
659 break; }
660 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 687 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
661 rtl8723be_set_p2p_ps_offload_cmd(hw, *val); 688 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
662 break; 689 break;
663 case HW_VAR_AID: { 690 case HW_VAR_AID:{
664 u16 u2btmp; 691 u16 u2btmp;
665 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 692 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
666 u2btmp &= 0xC000; 693 u2btmp &= 0xC000;
667 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 694 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
668 (u2btmp | mac->assoc_id)); 695 (u2btmp | mac->assoc_id));
669 break; } 696 }
670 case HW_VAR_CORRECT_TSF: { 697 break;
671 u8 btype_ibss = *val; 698 case HW_VAR_CORRECT_TSF:{
699 u8 btype_ibss = ((u8 *)(val))[0];
672 700
673 if (btype_ibss) 701 if (btype_ibss)
674 _rtl8723be_stop_tx_beacon(hw); 702 _rtl8723be_stop_tx_beacon(hw);
@@ -684,16 +712,17 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
684 712
685 if (btype_ibss) 713 if (btype_ibss)
686 _rtl8723be_resume_tx_beacon(hw); 714 _rtl8723be_resume_tx_beacon(hw);
687 break; } 715 }
688 case HW_VAR_KEEP_ALIVE: { 716 break;
717 case HW_VAR_KEEP_ALIVE:{
689 u8 array[2]; 718 u8 array[2];
690 array[0] = 0xff; 719 array[0] = 0xff;
691 array[1] = *val; 720 array[1] = *((u8 *)val);
692 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_KEEP_ALIVE_CTRL, 721 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
693 2, array); 722 }
694 break; } 723 break;
695 default: 724 default:
696 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 725 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
697 "switch case not process %x\n", 726 "switch case not process %x\n",
698 variable); 727 variable);
699 break; 728 break;
@@ -704,7 +733,7 @@ static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
704{ 733{
705 struct rtl_priv *rtlpriv = rtl_priv(hw); 734 struct rtl_priv *rtlpriv = rtl_priv(hw);
706 bool status = true; 735 bool status = true;
707 int count = 0; 736 long count = 0;
708 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 737 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
709 _LLT_OP(_LLT_WRITE_ACCESS); 738 _LLT_OP(_LLT_WRITE_ACCESS);
710 739
@@ -717,8 +746,8 @@ static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
717 746
718 if (count > POLLING_LLT_THRESHOLD) { 747 if (count > POLLING_LLT_THRESHOLD) {
719 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 748 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
720 "Failed to polling write LLT done at " 749 "Failed to polling write LLT done at address %d!\n",
721 "address %d!\n", address); 750 address);
722 status = false; 751 status = false;
723 break; 752 break;
724 } 753 }
@@ -732,10 +761,10 @@ static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
732 struct rtl_priv *rtlpriv = rtl_priv(hw); 761 struct rtl_priv *rtlpriv = rtl_priv(hw);
733 unsigned short i; 762 unsigned short i;
734 u8 txpktbuf_bndy; 763 u8 txpktbuf_bndy;
735 u8 maxpage; 764 u8 maxPage;
736 bool status; 765 bool status;
737 766
738 maxpage = 255; 767 maxPage = 255;
739 txpktbuf_bndy = 245; 768 txpktbuf_bndy = 245;
740 769
741 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, 770 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
@@ -754,17 +783,19 @@ static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
754 if (!status) 783 if (!status)
755 return status; 784 return status;
756 } 785 }
786
757 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 787 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
758 788
759 if (!status) 789 if (!status)
760 return status; 790 return status;
761 791
762 for (i = txpktbuf_bndy; i < maxpage; i++) { 792 for (i = txpktbuf_bndy; i < maxPage; i++) {
763 status = _rtl8723be_llt_write(hw, i, (i + 1)); 793 status = _rtl8723be_llt_write(hw, i, (i + 1));
764 if (!status) 794 if (!status)
765 return status; 795 return status;
766 } 796 }
767 status = _rtl8723be_llt_write(hw, maxpage, txpktbuf_bndy); 797
798 status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
768 if (!status) 799 if (!status)
769 return status; 800 return status;
770 801
@@ -796,11 +827,9 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
796{ 827{
797 struct rtl_priv *rtlpriv = rtl_priv(hw); 828 struct rtl_priv *rtlpriv = rtl_priv(hw);
798 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 829 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
799 830 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
800 unsigned char bytetmp; 831 unsigned char bytetmp;
801 unsigned short wordtmp; 832 unsigned short wordtmp;
802 u16 retry = 0;
803 bool mac_func_enable;
804 833
805 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 834 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
806 835
@@ -808,12 +837,6 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
808 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 837 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
809 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 838 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
810 839
811 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
812 if (bytetmp == 0xFF)
813 mac_func_enable = true;
814 else
815 mac_func_enable = false;
816
817 /* HW Power on sequence */ 840 /* HW Power on sequence */
818 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 841 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
819 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 842 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
@@ -822,6 +845,10 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
822 "init MAC Fail as power on failure\n"); 845 "init MAC Fail as power on failure\n");
823 return false; 846 return false;
824 } 847 }
848
849 bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
850 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
851
825 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 852 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
826 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 853 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
827 854
@@ -838,25 +865,21 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
838 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3); 865 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
839 if (bytetmp & BIT(0)) { 866 if (bytetmp & BIT(0)) {
840 bytetmp = rtl_read_byte(rtlpriv, 0x7c); 867 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
841 bytetmp |= BIT(6); 868 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
842 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
843 } 869 }
870
844 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 871 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
845 bytetmp |= BIT(3); 872 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
846 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp);
847 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 873 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
848 bytetmp &= ~BIT(4); 874 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
849 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
850
851 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+3);
852 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+3, bytetmp | 0x77);
853 875
854 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 876 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
855 877
856 if (!mac_func_enable) { 878 if (!rtlhal->mac_func_enable) {
857 if (!_rtl8723be_llt_table_init(hw)) 879 if (_rtl8723be_llt_table_init(hw) == false)
858 return false; 880 return false;
859 } 881 }
882
860 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 883 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
861 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 884 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
862 885
@@ -874,8 +897,6 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
874 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 897 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
875 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 898 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
876 899
877 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
878
879 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 900 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
880 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 901 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
881 DMA_BIT_MASK(32)); 902 DMA_BIT_MASK(32));
@@ -902,57 +923,213 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
902 923
903 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 924 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
904 925
905 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 926 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
906 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
907 927
908 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3); 928 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
909 929
910 do { 930 /* <20130114, Kordan> The following setting is
911 retry++; 931 * only for DPDT and Fixed board type.
912 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 932 * TODO: A better solution is configure it
913 } while ((retry < 200) && (bytetmp & BIT(7))); 933 * according EFUSE during the run-time.
914 934 */
915 _rtl8723be_gen_refresh_led_state(hw); 935 rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
916 936 rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
917 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 937 rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
938 rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
939 rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
940 rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
941 rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
942 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
918 943
919 bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 944 bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
920 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & ~BIT(2)); 945 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
921 946
947 _rtl8723be_gen_refresh_led_state(hw);
922 return true; 948 return true;
923} 949}
924 950
925static void _rtl8723be_hw_configure(struct ieee80211_hw *hw) 951static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
926{ 952{
927 struct rtl_priv *rtlpriv = rtl_priv(hw); 953 struct rtl_priv *rtlpriv = rtl_priv(hw);
928 u8 reg_bw_opmode; 954 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
929 u32 reg_ratr, reg_prsr; 955 u32 reg_rrsr;
956
957 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
958 /* Init value for RRSR. */
959 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
960
961 /* ARFB table 9 for 11ac 5G 2SS */
962 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
963
964 /* ARFB table 10 for 11ac 5G 1SS */
965 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
966
967 /* CF-End setting. */
968 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
969
970 /* 0x456 = 0x70, sugguested by Zhilin */
971 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
972
973 /* Set retry limit */
974 rtl_write_word(rtlpriv, REG_RL, 0x0707);
975
976 /* Set Data / Response auto rate fallack retry count */
977 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
978 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
979 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
980 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
981
982 rtlpci->reg_bcn_ctrl_val = 0x1d;
983 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
984
985 /* TBTT prohibit hold time. Suggested by designer TimChen. */
986 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
987
988 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
989
990 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
991 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
930 992
931 reg_bw_opmode = BW_OPMODE_20MHZ; 993 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
932 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
933 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
934 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
935 994
936 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 995 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
937 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 996
997 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
998}
999
1000static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1001{
1002 u16 read_addr = addr & 0xfffc;
1003 u8 ret = 0, tmp = 0, count = 0;
1004
1005 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1006 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1007 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1008 count = 0;
1009 while (tmp && count < 20) {
1010 udelay(10);
1011 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1012 count++;
1013 }
1014 if (0 == tmp) {
1015 read_addr = REG_DBI_RDATA + addr % 4;
1016 ret = rtl_read_byte(rtlpriv, read_addr);
1017 }
1018
1019 return ret;
1020}
1021
1022static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1023{
1024 u8 tmp = 0, count = 0;
1025 u16 write_addr = 0, remainder = addr % 4;
1026
1027 /* Write DBI 1Byte Data */
1028 write_addr = REG_DBI_WDATA + remainder;
1029 rtl_write_byte(rtlpriv, write_addr, data);
1030
1031 /* Write DBI 2Byte Address & Write Enable */
1032 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1033 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1034
1035 /* Write DBI Write Flag */
1036 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1037
1038 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1039 count = 0;
1040 while (tmp && count < 20) {
1041 udelay(10);
1042 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1043 count++;
1044 }
1045}
1046
1047static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1048{
1049 u16 ret = 0;
1050 u8 tmp = 0, count = 0;
1051
1052 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1053 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1054 count = 0;
1055 while (tmp && count < 20) {
1056 udelay(10);
1057 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1058 count++;
1059 }
1060
1061 if (0 == tmp)
1062 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1063
1064 return ret;
1065}
1066
1067static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1068{
1069 u8 tmp = 0, count = 0;
1070
1071 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1072 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1073 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1074 count = 0;
1075 while (tmp && count < 20) {
1076 udelay(10);
1077 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1078 count++;
1079 }
938} 1080}
939 1081
940static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw) 1082static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
941{ 1083{
942 struct rtl_priv *rtlpriv = rtl_priv(hw); 1084 struct rtl_priv *rtlpriv = rtl_priv(hw);
943 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1085 u8 tmp8 = 0;
1086 u16 tmp16 = 0;
944 1087
945 rtl_write_byte(rtlpriv, 0x34b, 0x93); 1088 /* <Roger_Notes> Overwrite following ePHY parameter for
946 rtl_write_word(rtlpriv, 0x350, 0x870c); 1089 * some platform compatibility issue,
947 rtl_write_byte(rtlpriv, 0x352, 0x1); 1090 * especially when CLKReq is enabled, 2012.11.09.
1091 */
1092 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1093 if (tmp16 != 0x0663)
1094 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
948 1095
949 if (ppsc->support_backdoor) 1096 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
950 rtl_write_byte(rtlpriv, 0x349, 0x1b); 1097 if (tmp16 != 0x7544)
951 else 1098 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
952 rtl_write_byte(rtlpriv, 0x349, 0x03); 1099
1100 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1101 if (tmp16 != 0xB880)
1102 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1103
1104 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1105 if (tmp16 != 0x4000)
1106 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1107
1108 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1109 if (tmp16 != 0x9003)
1110 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1111
1112 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1113 if (tmp16 != 0x0D03)
1114 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1115
1116 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1117 if (tmp16 != 0x4037)
1118 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
953 1119
954 rtl_write_word(rtlpriv, 0x350, 0x2718); 1120 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
955 rtl_write_byte(rtlpriv, 0x352, 0x1); 1121 if (tmp16 != 0x0070)
1122 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1123
1124 /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1125 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1126 _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7));
1127
1128 /* Configuration Space offset 0x719 Bit3 is for L1
1129 * BIT4 is for clock request
1130 */
1131 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1132 _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
956} 1133}
957 1134
958void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw) 1135void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
@@ -962,30 +1139,208 @@ void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
962 1139
963 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1140 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
964 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1141 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
965 rtlpriv->sec.pairwise_enc_algorithm, 1142 rtlpriv->sec.pairwise_enc_algorithm,
966 rtlpriv->sec.group_enc_algorithm); 1143 rtlpriv->sec.group_enc_algorithm);
967 1144
968 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1145 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
969 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1146 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
970 "not open hw encryption\n"); 1147 "not open hw encryption\n");
971 return; 1148 return;
972 } 1149 }
1150
973 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1151 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
974 1152
975 if (rtlpriv->sec.use_defaultkey) { 1153 if (rtlpriv->sec.use_defaultkey) {
976 sec_reg_value |= SCR_TXUSEDK; 1154 sec_reg_value |= SCR_TXUSEDK;
977 sec_reg_value |= SCR_RXUSEDK; 1155 sec_reg_value |= SCR_RXUSEDK;
978 } 1156 }
1157
979 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1158 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
980 1159
981 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1160 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
982 1161
983 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "The SECR-value %x\n", 1162 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
984 sec_reg_value); 1163 "The SECR-value %x\n", sec_reg_value);
985 1164
986 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1165 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
987} 1166}
988 1167
1168static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1169{
1170 struct rtl_priv *rtlpriv = rtl_priv(hw);
1171 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1172 u8 u1b_tmp;
1173
1174 rtlhal->mac_func_enable = false;
1175 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1176 /* 1. Run LPS WL RFOFF flow */
1177 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1178 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1179
1180 /* 2. 0x1F[7:0] = 0 */
1181 /* turn off RF */
1182 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1183 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1184 rtlhal->fw_ready) {
1185 rtl8723be_firmware_selfreset(hw);
1186 }
1187
1188 /* Reset MCU. Suggested by Filen. */
1189 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1190 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1191
1192 /* g. MCUFWDL 0x80[1:0]=0 */
1193 /* reset MCU ready status */
1194 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1195
1196 /* HW card disable configuration. */
1197 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1198 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1199
1200 /* Reset MCU IO Wrapper */
1201 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1202 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1203 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1204 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1205
1206 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1207 /* lock ISO/CLK/Power control register */
1208 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1209}
1210
1211static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1212{
1213 u8 tmp;
1214
1215 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1216 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1217 if (!(tmp & BIT(2))) {
1218 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1219 mdelay(100); /* Suggested by DD Justin_tsai. */
1220 }
1221
1222 /* read reg 0x350 Bit[25] if 1 : RX hang
1223 * read reg 0x350 Bit[24] if 1 : TX hang
1224 */
1225 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1226 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1227 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1228 "CheckPcieDMAHang8723BE(): true!!\n");
1229 return true;
1230 }
1231 return false;
1232}
1233
1234static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1235 bool mac_power_on)
1236{
1237 u8 tmp;
1238 bool release_mac_rx_pause;
1239 u8 backup_pcie_dma_pause;
1240
1241 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1242 "ResetPcieInterfaceDMA8723BE()\n");
1243
1244 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1245 * released by SD1 Alan.
1246 * 2013.05.07, by tynli.
1247 */
1248
1249 /* 1. disable register write lock
1250 * write 0x1C bit[1:0] = 2'h0
1251 * write 0xCC bit[2] = 1'b1
1252 */
1253 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1254 tmp &= ~(BIT(1) | BIT(0));
1255 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1256 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1257 tmp |= BIT(2);
1258 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1259
1260 /* 2. Check and pause TRX DMA
1261 * write 0x284 bit[18] = 1'b1
1262 * write 0x301 = 0xFF
1263 */
1264 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1265 if (tmp & BIT(2)) {
1266 /* Already pause before the function for another purpose. */
1267 release_mac_rx_pause = false;
1268 } else {
1269 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1270 release_mac_rx_pause = true;
1271 }
1272
1273 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1274 if (backup_pcie_dma_pause != 0xFF)
1275 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1276
1277 if (mac_power_on) {
1278 /* 3. reset TRX function
1279 * write 0x100 = 0x00
1280 */
1281 rtl_write_byte(rtlpriv, REG_CR, 0);
1282 }
1283
1284 /* 4. Reset PCIe DMA
1285 * write 0x003 bit[0] = 0
1286 */
1287 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1288 tmp &= ~(BIT(0));
1289 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1290
1291 /* 5. Enable PCIe DMA
1292 * write 0x003 bit[0] = 1
1293 */
1294 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1295 tmp |= BIT(0);
1296 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1297
1298 if (mac_power_on) {
1299 /* 6. enable TRX function
1300 * write 0x100 = 0xFF
1301 */
1302 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1303
1304 /* We should init LLT & RQPN and
1305 * prepare Tx/Rx descrptor address later
1306 * because MAC function is reset.
1307 */
1308 }
1309
1310 /* 7. Restore PCIe autoload down bit
1311 * write 0xF8 bit[17] = 1'b1
1312 */
1313 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1314 tmp |= BIT(1);
1315 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1316
1317 /* In MAC power on state, BB and RF maybe in ON state,
1318 * if we release TRx DMA here
1319 * it will cause packets to be started to Tx/Rx,
1320 * so we release Tx/Rx DMA later.
1321 */
1322 if (!mac_power_on) {
1323 /* 8. release TRX DMA
1324 * write 0x284 bit[18] = 1'b0
1325 * write 0x301 = 0x00
1326 */
1327 if (release_mac_rx_pause) {
1328 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1329 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1330 (tmp & (~BIT(2))));
1331 }
1332 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1333 backup_pcie_dma_pause);
1334 }
1335
1336 /* 9. lock system register
1337 * write 0xCC bit[2] = 1'b0
1338 */
1339 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1340 tmp &= ~(BIT(2));
1341 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1342}
1343
989int rtl8723be_hw_init(struct ieee80211_hw *hw) 1344int rtl8723be_hw_init(struct ieee80211_hw *hw)
990{ 1345{
991 struct rtl_priv *rtlpriv = rtl_priv(hw); 1346 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -1003,33 +1358,51 @@ int rtl8723be_hw_init(struct ieee80211_hw *hw)
1003 local_save_flags(flags); 1358 local_save_flags(flags);
1004 local_irq_enable(); 1359 local_irq_enable();
1005 1360
1361 rtlhal->fw_ready = false;
1006 rtlpriv->rtlhal.being_init_adapter = true; 1362 rtlpriv->rtlhal.being_init_adapter = true;
1007 rtlpriv->intf_ops->disable_aspm(hw); 1363 rtlpriv->intf_ops->disable_aspm(hw);
1364
1365 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1366 if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1367 rtlhal->mac_func_enable = true;
1368 } else {
1369 rtlhal->mac_func_enable = false;
1370 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1371 }
1372
1373 if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1374 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1375 rtlhal->mac_func_enable);
1376 rtlhal->mac_func_enable = false;
1377 }
1378 if (rtlhal->mac_func_enable) {
1379 _rtl8723be_poweroff_adapter(hw);
1380 rtlhal->mac_func_enable = false;
1381 }
1008 rtstatus = _rtl8723be_init_mac(hw); 1382 rtstatus = _rtl8723be_init_mac(hw);
1009 if (!rtstatus) { 1383 if (!rtstatus) {
1010 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); 1384 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1011 err = 1; 1385 err = 1;
1012 goto exit; 1386 goto exit;
1013 } 1387 }
1388
1014 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG); 1389 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1015 tmp_u1b &= 0x7F; 1390 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1016 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1017 1391
1018 err = rtl8723_download_fw(hw, true, FW_8192C_POLLING_TIMEOUT_COUNT); 1392 err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1019 if (err) { 1393 if (err) {
1020 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1394 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1021 "Failed to download FW. Init HW without FW now..\n"); 1395 "Failed to download FW. Init HW without FW now..\n");
1022 err = 1; 1396 err = 1;
1023 rtlhal->fw_ready = false;
1024 goto exit; 1397 goto exit;
1025 } else {
1026 rtlhal->fw_ready = true;
1027 } 1398 }
1399 rtlhal->fw_ready = true;
1400
1028 rtlhal->last_hmeboxnum = 0; 1401 rtlhal->last_hmeboxnum = 0;
1029 rtl8723be_phy_mac_config(hw); 1402 rtl8723be_phy_mac_config(hw);
1030 /* because last function modify RCR, so we update 1403 /* because last function modify RCR, so we update
1031 * rcr var here, or TP will unstable for receive_config 1404 * rcr var here, or TP will unstable for receive_config
1032 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1405 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1033 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1406 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1034 */ 1407 */
1035 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 1408 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
@@ -1037,7 +1410,6 @@ int rtl8723be_hw_init(struct ieee80211_hw *hw)
1037 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 1410 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1038 1411
1039 rtl8723be_phy_bb_config(hw); 1412 rtl8723be_phy_bb_config(hw);
1040 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1041 rtl8723be_phy_rf_config(hw); 1413 rtl8723be_phy_rf_config(hw);
1042 1414
1043 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1415 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
@@ -1047,10 +1419,8 @@ int rtl8723be_hw_init(struct ieee80211_hw *hw)
1047 rtlphy->rfreg_chnlval[0] &= 0xFFF03FF; 1419 rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1048 rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11)); 1420 rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1049 1421
1050 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1051 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1052 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1053 _rtl8723be_hw_configure(hw); 1422 _rtl8723be_hw_configure(hw);
1423 rtlhal->mac_func_enable = true;
1054 rtl_cam_reset_all_entry(hw); 1424 rtl_cam_reset_all_entry(hw);
1055 rtl8723be_enable_hw_security_config(hw); 1425 rtl8723be_enable_hw_security_config(hw);
1056 1426
@@ -1062,36 +1432,32 @@ int rtl8723be_hw_init(struct ieee80211_hw *hw)
1062 1432
1063 rtl8723be_bt_hw_init(hw); 1433 rtl8723be_bt_hw_init(hw);
1064 1434
1065 rtl_set_bbreg(hw, 0x64, BIT(20), 0);
1066 rtl_set_bbreg(hw, 0x64, BIT(24), 0);
1067
1068 rtl_set_bbreg(hw, 0x40, BIT(4), 0);
1069 rtl_set_bbreg(hw, 0x40, BIT(3), 1);
1070
1071 rtl_set_bbreg(hw, 0x944, BIT(0)|BIT(1), 0x3);
1072 rtl_set_bbreg(hw, 0x930, 0xff, 0x77);
1073
1074 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1);
1075
1076 rtl_set_bbreg(hw, 0xb2c, 0xffffffff, 0x80000000);
1077
1078 if (ppsc->rfpwr_state == ERFON) { 1435 if (ppsc->rfpwr_state == ERFON) {
1436 rtl8723be_phy_set_rfpath_switch(hw, 1);
1437 /* when use 1ant NIC, iqk will disturb BT music
1438 * root cause is not clear now, is something
1439 * related with 'mdelay' and Reg[0x948]
1440 */
1441 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1442 !rtlpriv->cfg->ops->get_btc_status()) {
1443 rtl8723be_phy_iq_calibrate(hw, false);
1444 rtlphy->iqk_initialized = true;
1445 }
1079 rtl8723be_dm_check_txpower_tracking(hw); 1446 rtl8723be_dm_check_txpower_tracking(hw);
1080 rtl8723be_phy_lc_calibrate(hw); 1447 rtl8723be_phy_lc_calibrate(hw);
1081 } 1448 }
1082 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1449 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1083 if (!(tmp_u1b & BIT(0))) { 1450
1084 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1451 /* Release Rx DMA. */
1085 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1452 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1086 } 1453 if (tmp_u1b & BIT(2)) {
1087 if (!(tmp_u1b & BIT(4))) { 1454 /* Release Rx DMA if needed */
1088 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1455 tmp_u1b &= (~BIT(2));
1089 tmp_u1b &= 0x0F; 1456 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1090 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1091 udelay(10);
1092 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1093 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1094 } 1457 }
1458 /* Release Tx/Rx PCIE DMA. */
1459 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1460
1095 rtl8723be_dm_init(hw); 1461 rtl8723be_dm_init(hw);
1096exit: 1462exit:
1097 local_irq_restore(flags); 1463 local_irq_restore(flags);
@@ -1104,43 +1470,29 @@ static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1104 struct rtl_priv *rtlpriv = rtl_priv(hw); 1470 struct rtl_priv *rtlpriv = rtl_priv(hw);
1105 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1471 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1106 enum version_8723e version = VERSION_UNKNOWN; 1472 enum version_8723e version = VERSION_UNKNOWN;
1107 u8 count = 0;
1108 u8 value8;
1109 u32 value32; 1473 u32 value32;
1110 1474
1111 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0);
1112
1113 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 2);
1114 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 2, value8 | BIT(0));
1115
1116 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
1117 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, value8 | BIT(0));
1118
1119 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
1120 while (((value8 & BIT(0))) && (count++ < 100)) {
1121 udelay(10);
1122 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
1123 }
1124 count = 0;
1125 value8 = rtl_read_byte(rtlpriv, REG_ROM_VERSION);
1126 while ((value8 == 0) && (count++ < 50)) {
1127 value8 = rtl_read_byte(rtlpriv, REG_ROM_VERSION);
1128 mdelay(1);
1129 }
1130 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1); 1475 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1131 if ((value32 & (CHIP_8723B)) != CHIP_8723B) 1476 if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1132 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unkown chip version\n"); 1477 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unkown chip version\n");
1133 else 1478 else
1134 version = (enum version_8723e) VERSION_TEST_CHIP_1T1R_8723B; 1479 version = (enum version_8723e)CHIP_8723B;
1135 1480
1136 rtlphy->rf_type = RF_1T1R; 1481 rtlphy->rf_type = RF_1T1R;
1482
1483 /* treat rtl8723be chip as MP version in default */
1484 version = (enum version_8723e)(version | NORMAL_CHIP);
1485
1486 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1487 /* cut version */
1488 version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1489 /* Manufacture */
1490 if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1491 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1137 1492
1138 value8 = rtl_read_byte(rtlpriv, REG_ROM_VERSION);
1139 if (value8 >= 0x02)
1140 version |= BIT(3);
1141 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1493 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1142 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ? 1494 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1143 "RF_2T2R" : "RF_1T1R"); 1495 "RF_2T2R" : "RF_1T1R");
1144 1496
1145 return version; 1497 return version;
1146} 1498}
@@ -1151,43 +1503,29 @@ static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1151 struct rtl_priv *rtlpriv = rtl_priv(hw); 1503 struct rtl_priv *rtlpriv = rtl_priv(hw);
1152 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1504 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1153 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1505 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1506 u8 mode = MSR_NOLINK;
1154 1507
1155 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1156 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1157 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1158
1159 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1160 type == NL80211_IFTYPE_STATION) {
1161 _rtl8723be_stop_tx_beacon(hw);
1162 _rtl8723be_enable_bcn_sub_func(hw);
1163 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1164 _rtl8723be_resume_tx_beacon(hw);
1165 _rtl8723be_disable_bcn_sub_func(hw);
1166 } else {
1167 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1168 "Set HW_VAR_MEDIA_STATUS: "
1169 "No such media status(%x).\n", type);
1170 }
1171 switch (type) { 1508 switch (type) {
1172 case NL80211_IFTYPE_UNSPECIFIED: 1509 case NL80211_IFTYPE_UNSPECIFIED:
1173 bt_msr |= MSR_NOLINK; 1510 mode = MSR_NOLINK;
1174 ledaction = LED_CTL_LINK;
1175 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1511 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1176 "Set Network type to NO LINK!\n"); 1512 "Set Network type to NO LINK!\n");
1177 break; 1513 break;
1178 case NL80211_IFTYPE_ADHOC: 1514 case NL80211_IFTYPE_ADHOC:
1179 bt_msr |= MSR_ADHOC; 1515 case NL80211_IFTYPE_MESH_POINT:
1516 mode = MSR_ADHOC;
1180 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1181 "Set Network type to Ad Hoc!\n"); 1518 "Set Network type to Ad Hoc!\n");
1182 break; 1519 break;
1183 case NL80211_IFTYPE_STATION: 1520 case NL80211_IFTYPE_STATION:
1184 bt_msr |= MSR_INFRA; 1521 mode = MSR_INFRA;
1185 ledaction = LED_CTL_LINK; 1522 ledaction = LED_CTL_LINK;
1186 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1523 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1187 "Set Network type to STA!\n"); 1524 "Set Network type to STA!\n");
1188 break; 1525 break;
1189 case NL80211_IFTYPE_AP: 1526 case NL80211_IFTYPE_AP:
1190 bt_msr |= MSR_AP; 1527 mode = MSR_AP;
1528 ledaction = LED_CTL_LINK;
1191 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1529 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1192 "Set Network type to AP!\n"); 1530 "Set Network type to AP!\n");
1193 break; 1531 break;
@@ -1196,9 +1534,33 @@ static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1196 "Network type %d not support!\n", type); 1534 "Network type %d not support!\n", type);
1197 return 1; 1535 return 1;
1198 } 1536 }
1199 rtl_write_byte(rtlpriv, (MSR), bt_msr); 1537
1538 /* MSR_INFRA == Link in infrastructure network;
1539 * MSR_ADHOC == Link in ad hoc network;
1540 * Therefore, check link state is necessary.
1541 *
1542 * MSR_AP == AP mode; link state is not cared here.
1543 */
1544 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1545 mode = MSR_NOLINK;
1546 ledaction = LED_CTL_NO_LINK;
1547 }
1548
1549 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1550 _rtl8723be_stop_tx_beacon(hw);
1551 _rtl8723be_enable_bcn_sub_func(hw);
1552 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1553 _rtl8723be_resume_tx_beacon(hw);
1554 _rtl8723be_disable_bcn_sub_func(hw);
1555 } else {
1556 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1557 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1558 mode);
1559 }
1560
1561 rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1200 rtlpriv->cfg->ops->led_control(hw, ledaction); 1562 rtlpriv->cfg->ops->led_control(hw, ledaction);
1201 if ((bt_msr & MSR_MASK) == MSR_AP) 1563 if (mode == MSR_AP)
1202 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1564 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1203 else 1565 else
1204 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1566 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
@@ -1225,6 +1587,7 @@ void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1225 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1587 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1226 (u8 *)(&reg_rcr)); 1588 (u8 *)(&reg_rcr));
1227 } 1589 }
1590
1228} 1591}
1229 1592
1230int rtl8723be_set_network_type(struct ieee80211_hw *hw, 1593int rtl8723be_set_network_type(struct ieee80211_hw *hw,
@@ -1241,6 +1604,7 @@ int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1241 } else { 1604 } else {
1242 rtl8723be_set_check_bssid(hw, false); 1605 rtl8723be_set_check_bssid(hw, false);
1243 } 1606 }
1607
1244 return 0; 1608 return 0;
1245} 1609}
1246 1610
@@ -1250,6 +1614,7 @@ int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1250void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci) 1614void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1251{ 1615{
1252 struct rtl_priv *rtlpriv = rtl_priv(hw); 1616 struct rtl_priv *rtlpriv = rtl_priv(hw);
1617
1253 rtl8723_dm_init_edca_turbo(hw); 1618 rtl8723_dm_init_edca_turbo(hw);
1254 switch (aci) { 1619 switch (aci) {
1255 case AC1_BK: 1620 case AC1_BK:
@@ -1269,20 +1634,32 @@ void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1269 } 1634 }
1270} 1635}
1271 1636
1637static void rtl8723be_clear_interrupt(struct ieee80211_hw *hw)
1638{
1639 struct rtl_priv *rtlpriv = rtl_priv(hw);
1640 u32 tmp;
1641
1642 tmp = rtl_read_dword(rtlpriv, REG_HISR);
1643 rtl_write_dword(rtlpriv, REG_HISR, tmp);
1644
1645 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1646 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1647
1648 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1649 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1650}
1651
1272void rtl8723be_enable_interrupt(struct ieee80211_hw *hw) 1652void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1273{ 1653{
1274 struct rtl_priv *rtlpriv = rtl_priv(hw); 1654 struct rtl_priv *rtlpriv = rtl_priv(hw);
1275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1655 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1276 1656
1657 rtl8723be_clear_interrupt(hw);/*clear it here first*/
1658
1277 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1659 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1278 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1660 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1279 rtlpci->irq_enabled = true; 1661 rtlpci->irq_enabled = true;
1280 /* there are some C2H CMDs have been sent 1662
1281 * before system interrupt is enabled, e.g., C2H, CPWM.
1282 * So we need to clear all C2H events that FW has notified,
1283 * otherwise FW won't schedule any commands anymore.
1284 */
1285 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1286 /*enable system interrupt*/ 1663 /*enable system interrupt*/
1287 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF); 1664 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1288} 1665}
@@ -1295,48 +1672,7 @@ void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1295 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 1672 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1296 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 1673 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1297 rtlpci->irq_enabled = false; 1674 rtlpci->irq_enabled = false;
1298 synchronize_irq(rtlpci->pdev->irq); 1675 /*synchronize_irq(rtlpci->pdev->irq);*/
1299}
1300
1301static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1302{
1303 struct rtl_priv *rtlpriv = rtl_priv(hw);
1304 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1305 u8 u1b_tmp;
1306
1307 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1308 /* 1. Run LPS WL RFOFF flow */
1309 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1310 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1311
1312 /* 2. 0x1F[7:0] = 0 */
1313 /* turn off RF */
1314 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1315 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1316 rtlhal->fw_ready)
1317 rtl8723be_firmware_selfreset(hw);
1318
1319 /* Reset MCU. Suggested by Filen. */
1320 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1321 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1322
1323 /* g. MCUFWDL 0x80[1:0]= 0 */
1324 /* reset MCU ready status */
1325 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1326
1327 /* HW card disable configuration. */
1328 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1329 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1330
1331 /* Reset MCU IO Wrapper */
1332 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1333 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1334 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1335 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1336
1337 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1338 /* lock ISO/CLK/Power control register */
1339 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1340} 1676}
1341 1677
1342void rtl8723be_card_disable(struct ieee80211_hw *hw) 1678void rtl8723be_card_disable(struct ieee80211_hw *hw)
@@ -1443,10 +1779,9 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1443 u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0; 1779 u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1444 1780
1445 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1781 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1446 "hal_ReadPowerValueFromPROM8723BE(): " 1782 "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1447 "PROMContent[0x%x]= 0x%x\n",
1448 (addr + 1), hwinfo[addr + 1]); 1783 (addr + 1), hwinfo[addr + 1]);
1449 if (0xFF == hwinfo[addr + 1]) /*YJ, add, 120316*/ 1784 if (0xFF == hwinfo[addr + 1]) /*YJ,add,120316*/
1450 autoload_fail = true; 1785 autoload_fail = true;
1451 1786
1452 if (autoload_fail) { 1787 if (autoload_fail) {
@@ -1454,7 +1789,7 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1454 "auto load fail : Use Default value!\n"); 1789 "auto load fail : Use Default value!\n");
1455 for (path = 0; path < MAX_RF_PATH; path++) { 1790 for (path = 0; path < MAX_RF_PATH; path++) {
1456 /* 2.4G default value */ 1791 /* 2.4G default value */
1457 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { 1792 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1458 pw2g->index_cck_base[path][group] = 0x2D; 1793 pw2g->index_cck_base[path][group] = 0x2D;
1459 pw2g->index_bw40_base[path][group] = 0x2D; 1794 pw2g->index_bw40_base[path][group] = 0x2D;
1460 } 1795 }
@@ -1472,12 +1807,14 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1472 } 1807 }
1473 return; 1808 return;
1474 } 1809 }
1810
1475 for (path = 0; path < MAX_RF_PATH; path++) { 1811 for (path = 0; path < MAX_RF_PATH; path++) {
1476 /*2.4G default value*/ 1812 /*2.4G default value*/
1477 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { 1813 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1478 pw2g->index_cck_base[path][group] = hwinfo[addr++]; 1814 pw2g->index_cck_base[path][group] = hwinfo[addr++];
1479 if (pw2g->index_cck_base[path][group] == 0xFF) 1815 if (pw2g->index_cck_base[path][group] == 0xFF)
1480 pw2g->index_cck_base[path][group] = 0x2D; 1816 pw2g->index_cck_base[path][group] = 0x2D;
1817
1481 } 1818 }
1482 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { 1819 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1483 pw2g->index_bw40_base[path][group] = hwinfo[addr++]; 1820 pw2g->index_bw40_base[path][group] = hwinfo[addr++];
@@ -1494,8 +1831,10 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1494 (hwinfo[addr] & 0xf0) >> 4; 1831 (hwinfo[addr] & 0xf0) >> 4;
1495 /*bit sign number to 8 bit sign number*/ 1832 /*bit sign number to 8 bit sign number*/
1496 if (pw2g->bw20_diff[path][cnt] & BIT(3)) 1833 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1497 pw2g->bw20_diff[path][cnt] |= 0xF0; 1834 pw2g->bw20_diff[path][cnt] |=
1835 0xF0;
1498 } 1836 }
1837
1499 if (hwinfo[addr] == 0xFF) { 1838 if (hwinfo[addr] == 0xFF) {
1500 pw2g->ofdm_diff[path][cnt] = 0x04; 1839 pw2g->ofdm_diff[path][cnt] = 0x04;
1501 } else { 1840 } else {
@@ -1518,6 +1857,7 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1518 pw2g->bw40_diff[path][cnt] |= 1857 pw2g->bw40_diff[path][cnt] |=
1519 0xF0; 1858 0xF0;
1520 } 1859 }
1860
1521 if (hwinfo[addr] == 0xFF) { 1861 if (hwinfo[addr] == 0xFF) {
1522 pw2g->bw20_diff[path][cnt] = 0xFE; 1862 pw2g->bw20_diff[path][cnt] = 0xFE;
1523 } else { 1863 } else {
@@ -1538,9 +1878,10 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1538 pw2g->ofdm_diff[path][cnt] |= 1878 pw2g->ofdm_diff[path][cnt] |=
1539 0xF0; 1879 0xF0;
1540 } 1880 }
1541 if (hwinfo[addr] == 0xFF) { 1881
1882 if (hwinfo[addr] == 0xFF)
1542 pw2g->cck_diff[path][cnt] = 0xFE; 1883 pw2g->cck_diff[path][cnt] = 0xFE;
1543 } else { 1884 else {
1544 pw2g->cck_diff[path][cnt] = 1885 pw2g->cck_diff[path][cnt] =
1545 (hwinfo[addr] & 0x0f); 1886 (hwinfo[addr] & 0x0f);
1546 if (pw2g->cck_diff[path][cnt] & BIT(3)) 1887 if (pw2g->cck_diff[path][cnt] & BIT(3))
@@ -1550,12 +1891,14 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1550 addr++; 1891 addr++;
1551 } 1892 }
1552 } 1893 }
1894
1553 /*5G default value*/ 1895 /*5G default value*/
1554 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) { 1896 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1555 pw5g->index_bw40_base[path][group] = hwinfo[addr++]; 1897 pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1556 if (pw5g->index_bw40_base[path][group] == 0xFF) 1898 if (pw5g->index_bw40_base[path][group] == 0xFF)
1557 pw5g->index_bw40_base[path][group] = 0xFE; 1899 pw5g->index_bw40_base[path][group] = 0xFE;
1558 } 1900 }
1901
1559 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) { 1902 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1560 if (cnt == 0) { 1903 if (cnt == 0) {
1561 pw5g->bw40_diff[path][cnt] = 0; 1904 pw5g->bw40_diff[path][cnt] = 0;
@@ -1569,9 +1912,10 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1569 pw5g->bw20_diff[path][cnt] |= 1912 pw5g->bw20_diff[path][cnt] |=
1570 0xF0; 1913 0xF0;
1571 } 1914 }
1572 if (hwinfo[addr] == 0xFF) { 1915
1916 if (hwinfo[addr] == 0xFF)
1573 pw5g->ofdm_diff[path][cnt] = 0x04; 1917 pw5g->ofdm_diff[path][cnt] = 0x04;
1574 } else { 1918 else {
1575 pw5g->ofdm_diff[path][0] = 1919 pw5g->ofdm_diff[path][0] =
1576 (hwinfo[addr] & 0x0f); 1920 (hwinfo[addr] & 0x0f);
1577 if (pw5g->ofdm_diff[path][cnt] & BIT(3)) 1921 if (pw5g->ofdm_diff[path][cnt] & BIT(3))
@@ -1588,6 +1932,7 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1588 if (pw5g->bw40_diff[path][cnt] & BIT(3)) 1932 if (pw5g->bw40_diff[path][cnt] & BIT(3))
1589 pw5g->bw40_diff[path][cnt] |= 0xF0; 1933 pw5g->bw40_diff[path][cnt] |= 0xF0;
1590 } 1934 }
1935
1591 if (hwinfo[addr] == 0xFF) { 1936 if (hwinfo[addr] == 0xFF) {
1592 pw5g->bw20_diff[path][cnt] = 0xFE; 1937 pw5g->bw20_diff[path][cnt] = 0xFE;
1593 } else { 1938 } else {
@@ -1599,6 +1944,7 @@ static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1599 addr++; 1944 addr++;
1600 } 1945 }
1601 } 1946 }
1947
1602 if (hwinfo[addr] == 0xFF) { 1948 if (hwinfo[addr] == 0xFF) {
1603 pw5g->ofdm_diff[path][1] = 0xFE; 1949 pw5g->ofdm_diff[path][1] = 0xFE;
1604 pw5g->ofdm_diff[path][2] = 0xFE; 1950 pw5g->ofdm_diff[path][2] = 0xFE;
@@ -1654,14 +2000,16 @@ static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1654 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2000 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1655 pw2g.ofdm_diff[rf_path][i]; 2001 pw2g.ofdm_diff[rf_path][i];
1656 } 2002 }
2003
1657 for (i = 0; i < 14; i++) { 2004 for (i = 0; i < 14; i++) {
1658 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 2005 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1659 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = " 2006 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1660 "[0x%x / 0x%x ]\n", rf_path, i, 2007 rf_path, i,
1661 rtlefuse->txpwrlevel_cck[rf_path][i], 2008 rtlefuse->txpwrlevel_cck[rf_path][i],
1662 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]); 2009 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1663 } 2010 }
1664 } 2011 }
2012
1665 if (!autoload_fail) 2013 if (!autoload_fail)
1666 rtlefuse->eeprom_thermalmeter = 2014 rtlefuse->eeprom_thermalmeter =
1667 hwinfo[EEPROM_THERMAL_METER_88E]; 2015 hwinfo[EEPROM_THERMAL_METER_88E];
@@ -1672,8 +2020,9 @@ static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1672 rtlefuse->apk_thermalmeterignore = true; 2020 rtlefuse->apk_thermalmeterignore = true;
1673 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 2021 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1674 } 2022 }
2023
1675 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 2024 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1676 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 2025 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1677 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 2026 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1678 2027
1679 if (!autoload_fail) { 2028 if (!autoload_fail) {
@@ -1684,7 +2033,7 @@ static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1684 } else { 2033 } else {
1685 rtlefuse->eeprom_regulatory = 0; 2034 rtlefuse->eeprom_regulatory = 0;
1686 } 2035 }
1687 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 2036 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1688 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2037 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1689} 2038}
1690 2039
@@ -1744,6 +2093,7 @@ static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
1744 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 2093 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1745 rtlefuse->autoload_failflag = false; 2094 rtlefuse->autoload_failflag = false;
1746 } 2095 }
2096
1747 if (rtlefuse->autoload_failflag) 2097 if (rtlefuse->autoload_failflag)
1748 return; 2098 return;
1749 2099
@@ -1959,100 +2309,10 @@ void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
1959 _rtl8723be_hal_customized_behavior(hw); 2309 _rtl8723be_hal_customized_behavior(hw);
1960} 2310}
1961 2311
1962static void rtl8723be_update_hal_rate_table(struct ieee80211_hw *hw,
1963 struct ieee80211_sta *sta)
1964{
1965 struct rtl_priv *rtlpriv = rtl_priv(hw);
1966 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1967 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1968 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1969 u32 ratr_value;
1970 u8 ratr_index = 0;
1971 u8 nmode = mac->ht_enable;
1972 u8 mimo_ps = IEEE80211_SMPS_OFF;
1973 u16 shortgi_rate;
1974 u32 tmp_ratr_value;
1975 u8 curtxbw_40mhz = mac->bw_40;
1976 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1977 1 : 0;
1978 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1979 1 : 0;
1980 enum wireless_mode wirelessmode = mac->mode;
1981
1982 if (rtlhal->current_bandtype == BAND_ON_5G)
1983 ratr_value = sta->supp_rates[1] << 4;
1984 else
1985 ratr_value = sta->supp_rates[0];
1986 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1987 ratr_value = 0xfff;
1988 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1989 sta->ht_cap.mcs.rx_mask[0] << 12);
1990 switch (wirelessmode) {
1991 case WIRELESS_MODE_B:
1992 if (ratr_value & 0x0000000c)
1993 ratr_value &= 0x0000000d;
1994 else
1995 ratr_value &= 0x0000000f;
1996 break;
1997 case WIRELESS_MODE_G:
1998 ratr_value &= 0x00000FF5;
1999 break;
2000 case WIRELESS_MODE_N_24G:
2001 case WIRELESS_MODE_N_5G:
2002 nmode = 1;
2003 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2004 ratr_value &= 0x0007F005;
2005 } else {
2006 u32 ratr_mask;
2007
2008 if (get_rf_type(rtlphy) == RF_1T2R ||
2009 get_rf_type(rtlphy) == RF_1T1R)
2010 ratr_mask = 0x000ff005;
2011 else
2012 ratr_mask = 0x0f0ff005;
2013 ratr_value &= ratr_mask;
2014 }
2015 break;
2016 default:
2017 if (rtlphy->rf_type == RF_1T2R)
2018 ratr_value &= 0x000ff0ff;
2019 else
2020 ratr_value &= 0x0f0ff0ff;
2021 break;
2022 }
2023 if ((rtlpriv->btcoexist.bt_coexistence) &&
2024 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2025 (rtlpriv->btcoexist.bt_cur_state) &&
2026 (rtlpriv->btcoexist.bt_ant_isolation) &&
2027 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2028 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2029 ratr_value &= 0x0fffcfc0;
2030 else
2031 ratr_value &= 0x0FFFFFFF;
2032
2033 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2034 (!curtxbw_40mhz && curshortgi_20mhz))) {
2035 ratr_value |= 0x10000000;
2036 tmp_ratr_value = (ratr_value >> 12);
2037
2038 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2039 if ((1 << shortgi_rate) & tmp_ratr_value)
2040 break;
2041 }
2042 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2043 (shortgi_rate << 4) | (shortgi_rate);
2044 }
2045 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2046
2047 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2048 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2049}
2050
2051static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, 2312static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2052 u8 rate_index) 2313 u8 rate_index)
2053{ 2314{
2054 u8 ret = 0; 2315 u8 ret = 0;
2055
2056 switch (rate_index) { 2316 switch (rate_index) {
2057 case RATR_INX_WIRELESS_NGB: 2317 case RATR_INX_WIRELESS_NGB:
2058 ret = 1; 2318 ret = 1;
@@ -2091,16 +2351,15 @@ static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2091 u32 ratr_bitmap; 2351 u32 ratr_bitmap;
2092 u8 ratr_index; 2352 u8 ratr_index;
2093 u8 curtxbw_40mhz = (sta->ht_cap.cap & 2353 u8 curtxbw_40mhz = (sta->ht_cap.cap &
2094 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0; 2354 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2095 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2355 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2096 1 : 0; 2356 1 : 0;
2097 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2357 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2098 1 : 0; 2358 1 : 0;
2099 enum wireless_mode wirelessmode = 0; 2359 enum wireless_mode wirelessmode = 0;
2100 bool shortgi = false; 2360 bool shortgi = false;
2101 u8 rate_mask[7]; 2361 u8 rate_mask[7];
2102 u8 macid = 0; 2362 u8 macid = 0;
2103 u8 mimo_ps = IEEE80211_SMPS_OFF;
2104 2363
2105 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 2364 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2106 wirelessmode = sta_entry->wireless_mode; 2365 wirelessmode = sta_entry->wireless_mode;
@@ -2136,55 +2395,40 @@ static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2136 else 2395 else
2137 ratr_bitmap &= 0x00000ff5; 2396 ratr_bitmap &= 0x00000ff5;
2138 break; 2397 break;
2139 case WIRELESS_MODE_A:
2140 ratr_index = RATR_INX_WIRELESS_A;
2141 ratr_bitmap &= 0x00000ff0;
2142 break;
2143 case WIRELESS_MODE_N_24G: 2398 case WIRELESS_MODE_N_24G:
2144 case WIRELESS_MODE_N_5G: 2399 case WIRELESS_MODE_N_5G:
2145 ratr_index = RATR_INX_WIRELESS_NGB; 2400 ratr_index = RATR_INX_WIRELESS_NGB;
2146 2401 if (rtlphy->rf_type == RF_1T1R) {
2147 if (mimo_ps == IEEE80211_SMPS_STATIC || 2402 if (curtxbw_40mhz) {
2148 mimo_ps == IEEE80211_SMPS_DYNAMIC) { 2403 if (rssi_level == 1)
2149 if (rssi_level == 1) 2404 ratr_bitmap &= 0x000f0000;
2150 ratr_bitmap &= 0x00070000; 2405 else if (rssi_level == 2)
2151 else if (rssi_level == 2) 2406 ratr_bitmap &= 0x000ff000;
2152 ratr_bitmap &= 0x0007f000; 2407 else
2153 else 2408 ratr_bitmap &= 0x000ff015;
2154 ratr_bitmap &= 0x0007f005; 2409 } else {
2410 if (rssi_level == 1)
2411 ratr_bitmap &= 0x000f0000;
2412 else if (rssi_level == 2)
2413 ratr_bitmap &= 0x000ff000;
2414 else
2415 ratr_bitmap &= 0x000ff005;
2416 }
2155 } else { 2417 } else {
2156 if (rtlphy->rf_type == RF_1T1R) { 2418 if (curtxbw_40mhz) {
2157 if (curtxbw_40mhz) { 2419 if (rssi_level == 1)
2158 if (rssi_level == 1) 2420 ratr_bitmap &= 0x0f8f0000;
2159 ratr_bitmap &= 0x000f0000; 2421 else if (rssi_level == 2)
2160 else if (rssi_level == 2) 2422 ratr_bitmap &= 0x0f8ff000;
2161 ratr_bitmap &= 0x000ff000; 2423 else
2162 else 2424 ratr_bitmap &= 0x0f8ff015;
2163 ratr_bitmap &= 0x000ff015;
2164 } else {
2165 if (rssi_level == 1)
2166 ratr_bitmap &= 0x000f0000;
2167 else if (rssi_level == 2)
2168 ratr_bitmap &= 0x000ff000;
2169 else
2170 ratr_bitmap &= 0x000ff005;
2171 }
2172 } else { 2425 } else {
2173 if (curtxbw_40mhz) { 2426 if (rssi_level == 1)
2174 if (rssi_level == 1) 2427 ratr_bitmap &= 0x0f8f0000;
2175 ratr_bitmap &= 0x0f8f0000; 2428 else if (rssi_level == 2)
2176 else if (rssi_level == 2) 2429 ratr_bitmap &= 0x0f8ff000;
2177 ratr_bitmap &= 0x0f8ff000; 2430 else
2178 else 2431 ratr_bitmap &= 0x0f8ff005;
2179 ratr_bitmap &= 0x0f8ff015;
2180 } else {
2181 if (rssi_level == 1)
2182 ratr_bitmap &= 0x0f8f0000;
2183 else if (rssi_level == 2)
2184 ratr_bitmap &= 0x0f8ff000;
2185 else
2186 ratr_bitmap &= 0x0f8ff005;
2187 }
2188 } 2432 }
2189 } 2433 }
2190 if ((curtxbw_40mhz && curshortgi_40mhz) || 2434 if ((curtxbw_40mhz && curshortgi_40mhz) ||
@@ -2204,18 +2448,17 @@ static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2204 ratr_bitmap &= 0x0f0ff0ff; 2448 ratr_bitmap &= 0x0f0ff0ff;
2205 break; 2449 break;
2206 } 2450 }
2451
2207 sta_entry->ratr_index = ratr_index; 2452 sta_entry->ratr_index = ratr_index;
2208 2453
2209 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2454 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2210 "ratr_bitmap :%x\n", ratr_bitmap); 2455 "ratr_bitmap :%x\n", ratr_bitmap);
2211 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); 2456 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2457 (ratr_index << 28);
2212 rate_mask[0] = macid; 2458 rate_mask[0] = macid;
2213 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) | 2459 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2214 (shortgi ? 0x80 : 0x00); 2460 (shortgi ? 0x80 : 0x00);
2215 rate_mask[2] = curtxbw_40mhz; 2461 rate_mask[2] = curtxbw_40mhz;
2216 /* if (prox_priv->proxim_modeinfo->power_output > 0)
2217 * rate_mask[2] |= BIT(6);
2218 */
2219 2462
2220 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 2463 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2221 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 2464 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
@@ -2229,7 +2472,7 @@ static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2229 rate_mask[2], rate_mask[3], 2472 rate_mask[2], rate_mask[3],
2230 rate_mask[4], rate_mask[5], 2473 rate_mask[4], rate_mask[5],
2231 rate_mask[6]); 2474 rate_mask[6]);
2232 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_RA_MASK, 7, rate_mask); 2475 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2233 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); 2476 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2234} 2477}
2235 2478
@@ -2240,8 +2483,6 @@ void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2240 struct rtl_priv *rtlpriv = rtl_priv(hw); 2483 struct rtl_priv *rtlpriv = rtl_priv(hw);
2241 if (rtlpriv->dm.useramask) 2484 if (rtlpriv->dm.useramask)
2242 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level); 2485 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level);
2243 else
2244 rtl8723be_update_hal_rate_table(hw, sta);
2245} 2486}
2246 2487
2247void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw) 2488void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
@@ -2265,7 +2506,7 @@ bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2265 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2506 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2266 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2507 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2267 u8 u1tmp; 2508 u8 u1tmp;
2268 bool actuallyset = false; 2509 bool b_actuallyset = false;
2269 2510
2270 if (rtlpriv->rtlhal.being_init_adapter) 2511 if (rtlpriv->rtlhal.being_init_adapter)
2271 return false; 2512 return false;
@@ -2281,6 +2522,7 @@ bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2281 ppsc->rfchange_inprogress = true; 2522 ppsc->rfchange_inprogress = true;
2282 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2523 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2283 } 2524 }
2525
2284 cur_rfstate = ppsc->rfpwr_state; 2526 cur_rfstate = ppsc->rfpwr_state;
2285 2527
2286 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 2528 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
@@ -2293,24 +2535,23 @@ bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2293 else 2535 else
2294 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 2536 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2295 2537
2296 if (ppsc->hwradiooff && 2538 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2297 (e_rfpowerstate_toset == ERFON)) {
2298 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2539 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2299 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2540 "GPIOChangeRF - HW Radio ON, RF ON\n");
2300 2541
2301 e_rfpowerstate_toset = ERFON; 2542 e_rfpowerstate_toset = ERFON;
2302 ppsc->hwradiooff = false; 2543 ppsc->hwradiooff = false;
2303 actuallyset = true; 2544 b_actuallyset = true;
2304 } else if (!ppsc->hwradiooff && 2545 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2305 (e_rfpowerstate_toset == ERFOFF)) {
2306 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2546 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2307 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2547 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2308 2548
2309 e_rfpowerstate_toset = ERFOFF; 2549 e_rfpowerstate_toset = ERFOFF;
2310 ppsc->hwradiooff = true; 2550 ppsc->hwradiooff = true;
2311 actuallyset = true; 2551 b_actuallyset = true;
2312 } 2552 }
2313 if (actuallyset) { 2553
2554 if (b_actuallyset) {
2314 spin_lock(&rtlpriv->locks.rf_ps_lock); 2555 spin_lock(&rtlpriv->locks.rf_ps_lock);
2315 ppsc->rfchange_inprogress = false; 2556 ppsc->rfchange_inprogress = false;
2316 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2557 spin_unlock(&rtlpriv->locks.rf_ps_lock);
@@ -2322,8 +2563,10 @@ bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2322 ppsc->rfchange_inprogress = false; 2563 ppsc->rfchange_inprogress = false;
2323 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2564 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2324 } 2565 }
2566
2325 *valid = 1; 2567 *valid = 1;
2326 return !ppsc->hwradiooff; 2568 return !ppsc->hwradiooff;
2569
2327} 2570}
2328 2571
2329void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index, 2572void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
@@ -2364,6 +2607,7 @@ void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2364 rtlpriv->sec.key_len[idx] = 0; 2607 rtlpriv->sec.key_len[idx] = 0;
2365 } 2608 }
2366 } 2609 }
2610
2367 } else { 2611 } else {
2368 switch (enc_algo) { 2612 switch (enc_algo) {
2369 case WEP40_ENCRYPTION: 2613 case WEP40_ENCRYPTION:
@@ -2379,7 +2623,7 @@ void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2379 enc_algo = CAM_AES; 2623 enc_algo = CAM_AES;
2380 break; 2624 break;
2381 default: 2625 default:
2382 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2626 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2383 "switch case not process\n"); 2627 "switch case not process\n");
2384 enc_algo = CAM_TKIP; 2628 enc_algo = CAM_TKIP;
2385 break; 2629 break;
@@ -2399,22 +2643,22 @@ void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2399 if (entry_id >= TOTAL_CAM_ENTRY) { 2643 if (entry_id >= TOTAL_CAM_ENTRY) {
2400 RT_TRACE(rtlpriv, COMP_SEC, 2644 RT_TRACE(rtlpriv, COMP_SEC,
2401 DBG_EMERG, 2645 DBG_EMERG,
2402 "Can not find free" 2646 "Can not find free hw security cam entry\n");
2403 " hw security cam "
2404 "entry\n");
2405 return; 2647 return;
2406 } 2648 }
2407 } else { 2649 } else {
2408 entry_id = CAM_PAIRWISE_KEY_POSITION; 2650 entry_id = CAM_PAIRWISE_KEY_POSITION;
2409 } 2651 }
2652
2410 key_index = PAIRWISE_KEYIDX; 2653 key_index = PAIRWISE_KEYIDX;
2411 is_pairwise = true; 2654 is_pairwise = true;
2412 } 2655 }
2413 } 2656 }
2657
2414 if (rtlpriv->sec.key_len[key_index] == 0) { 2658 if (rtlpriv->sec.key_len[key_index] == 0) {
2415 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2659 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2416 "delete one entry, entry_id is %d\n", 2660 "delete one entry, entry_id is %d\n",
2417 entry_id); 2661 entry_id);
2418 if (mac->opmode == NL80211_IFTYPE_AP) 2662 if (mac->opmode == NL80211_IFTYPE_AP)
2419 rtl_cam_del_entry(hw, p_macaddr); 2663 rtl_cam_del_entry(hw, p_macaddr);
2420 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2664 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
@@ -2423,12 +2667,12 @@ void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2423 "add one entry\n"); 2667 "add one entry\n");
2424 if (is_pairwise) { 2668 if (is_pairwise) {
2425 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2669 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2426 "set Pairwise key\n"); 2670 "set Pairwiase key\n");
2427 2671
2428 rtl_cam_add_one_entry(hw, macaddr, key_index, 2672 rtl_cam_add_one_entry(hw, macaddr, key_index,
2429 entry_id, enc_algo, 2673 entry_id, enc_algo,
2430 CAM_CONFIG_NO_USEDK, 2674 CAM_CONFIG_NO_USEDK,
2431 rtlpriv->sec.key_buf[key_index]); 2675 rtlpriv->sec.key_buf[key_index]);
2432 } else { 2676 } else {
2433 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2677 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2434 "set group key\n"); 2678 "set group key\n");
@@ -2443,10 +2687,11 @@ void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2443 rtlpriv->sec.key_buf 2687 rtlpriv->sec.key_buf
2444 [entry_id]); 2688 [entry_id]);
2445 } 2689 }
2690
2446 rtl_cam_add_one_entry(hw, macaddr, key_index, 2691 rtl_cam_add_one_entry(hw, macaddr, key_index,
2447 entry_id, enc_algo, 2692 entry_id, enc_algo,
2448 CAM_CONFIG_NO_USEDK, 2693 CAM_CONFIG_NO_USEDK,
2449 rtlpriv->sec.key_buf[entry_id]); 2694 rtlpriv->sec.key_buf[entry_id]);
2450 } 2695 }
2451 } 2696 }
2452 } 2697 }
@@ -2465,7 +2710,7 @@ void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2465 rtlpriv->btcoexist.btc_info.btcoexist = 1; 2710 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2466 else 2711 else
2467 rtlpriv->btcoexist.btc_info.btcoexist = 0; 2712 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2468 value = hwinfo[RF_OPTION4]; 2713 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2469 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B; 2714 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2470 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 2715 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2471 } else { 2716 } else {
@@ -2473,6 +2718,7 @@ void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2473 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B; 2718 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2474 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 2719 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2475 } 2720 }
2721
2476} 2722}
2477 2723
2478void rtl8723be_bt_reg_init(struct ieee80211_hw *hw) 2724void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
@@ -2493,6 +2739,7 @@ void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2493 2739
2494 if (rtlpriv->cfg->ops->get_btc_status()) 2740 if (rtlpriv->cfg->ops->get_btc_status())
2495 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 2741 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2742
2496} 2743}
2497 2744
2498void rtl8723be_suspend(struct ieee80211_hw *hw) 2745void rtl8723be_suspend(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/hw.h b/drivers/net/wireless/rtlwifi/rtl8723be/hw.h
index 64c7551af6b7..eae863d08de8 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/hw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/hw.h
@@ -59,4 +59,5 @@ void rtl8723be_bt_reg_init(struct ieee80211_hw *hw);
59void rtl8723be_bt_hw_init(struct ieee80211_hw *hw); 59void rtl8723be_bt_hw_init(struct ieee80211_hw *hw);
60void rtl8723be_suspend(struct ieee80211_hw *hw); 60void rtl8723be_suspend(struct ieee80211_hw *hw);
61void rtl8723be_resume(struct ieee80211_hw *hw); 61void rtl8723be_resume(struct ieee80211_hw *hw);
62
62#endif 63#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/led.c b/drivers/net/wireless/rtlwifi/rtl8723be/led.c
index cb931a38dc48..4196efb723a2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/led.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/led.c
@@ -42,7 +42,7 @@ void rtl8723be_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
42 struct rtl_priv *rtlpriv = rtl_priv(hw); 42 struct rtl_priv *rtlpriv = rtl_priv(hw);
43 43
44 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, 44 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
45 "LedAddr:%X ledpin =%d\n", REG_LEDCFG2, pled->ledpin); 45 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
46 46
47 switch (pled->ledpin) { 47 switch (pled->ledpin) {
48 case LED_PIN_GPIO0: 48 case LED_PIN_GPIO0:
@@ -71,7 +71,7 @@ void rtl8723be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
71 u8 ledcfg; 71 u8 ledcfg;
72 72
73 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, 73 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
74 "LedAddr:%X ledpin =%d\n", REG_LEDCFG2, pled->ledpin); 74 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
75 75
76 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2); 76 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
77 77
@@ -100,7 +100,7 @@ void rtl8723be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
100 break; 100 break;
101 default: 101 default:
102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
103 "switch case not processed\n"); 103 "switch case not process\n");
104 break; 104 break;
105 } 105 }
106 pled->ledon = false; 106 pled->ledon = false;
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/phy.c b/drivers/net/wireless/rtlwifi/rtl8723be/phy.c
index 1575ef9ece9f..20dcc25c506c 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/phy.c
@@ -26,224 +26,28 @@
26#include "../wifi.h" 26#include "../wifi.h"
27#include "../pci.h" 27#include "../pci.h"
28#include "../ps.h" 28#include "../ps.h"
29#include "../core.h"
30#include "reg.h" 29#include "reg.h"
31#include "def.h" 30#include "def.h"
32#include "phy.h" 31#include "phy.h"
33#include "../rtl8723com/phy_common.h" 32#include "../rtl8723com/phy_common.h"
34#include "rf.h" 33#include "rf.h"
35#include "dm.h" 34#include "dm.h"
35#include "../rtl8723com/dm_common.h"
36#include "table.h" 36#include "table.h"
37#include "trx.h" 37#include "trx.h"
38 38
39static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw); 39static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw);
40static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
41static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
42 u8 configtype);
40static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 43static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
41 u8 configtype); 44 u8 configtype);
42static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw, 45static bool _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
43 u8 channel, u8 *stage, 46 u8 channel, u8 *stage,
44 u8 *step, u32 *delay); 47 u8 *step, u32 *delay);
45static bool _rtl8723be_check_condition(struct ieee80211_hw *hw,
46 const u32 condition)
47{
48 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
49 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
50 u32 _board = rtlefuse->board_type; /*need efuse define*/
51 u32 _interface = rtlhal->interface;
52 u32 _platform = 0x08;/*SupportPlatform */
53 u32 cond = condition;
54
55 if (condition == 0xCDCDCDCD)
56 return true;
57
58 cond = condition & 0xFF;
59 if ((_board & cond) == 0 && cond != 0x1F)
60 return false;
61
62 cond = condition & 0xFF00;
63 cond = cond >> 8;
64 if ((_interface & cond) == 0 && cond != 0x07)
65 return false;
66
67 cond = condition & 0xFF0000;
68 cond = cond >> 16;
69 if ((_platform & cond) == 0 && cond != 0x0F)
70 return false;
71 return true;
72}
73
74static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
75{
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 u32 i;
78 u32 arraylength;
79 u32 *ptrarray;
80
81 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read rtl8723beMACPHY_Array\n");
82 arraylength = RTL8723BEMAC_1T_ARRAYLEN;
83 ptrarray = RTL8723BEMAC_1T_ARRAY;
84 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
85 "Img:RTL8723bEMAC_1T_ARRAY LEN %d\n", arraylength);
86 for (i = 0; i < arraylength; i = i + 2)
87 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
88 return true;
89}
90
91static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
92 u8 configtype)
93{
94 #define READ_NEXT_PAIR(v1, v2, i) \
95 do { \
96 i += 2; \
97 v1 = array_table[i];\
98 v2 = array_table[i+1]; \
99 } while (0)
100
101 int i;
102 u32 *array_table;
103 u16 arraylen;
104 struct rtl_priv *rtlpriv = rtl_priv(hw);
105 u32 v1 = 0, v2 = 0;
106
107 if (configtype == BASEBAND_CONFIG_PHY_REG) {
108 arraylen = RTL8723BEPHY_REG_1TARRAYLEN;
109 array_table = RTL8723BEPHY_REG_1TARRAY;
110
111 for (i = 0; i < arraylen; i = i + 2) {
112 v1 = array_table[i];
113 v2 = array_table[i+1];
114 if (v1 < 0xcdcdcdcd) {
115 rtl_bb_delay(hw, v1, v2);
116 } else {/*This line is the start line of branch.*/
117 if (!_rtl8723be_check_condition(hw, array_table[i])) {
118 /*Discard the following (offset, data) pairs*/
119 READ_NEXT_PAIR(v1, v2, i);
120 while (v2 != 0xDEAD &&
121 v2 != 0xCDEF &&
122 v2 != 0xCDCD &&
123 i < arraylen - 2) {
124 READ_NEXT_PAIR(v1, v2, i);
125 }
126 i -= 2; /* prevent from for-loop += 2*/
127 /* Configure matched pairs and
128 * skip to end of if-else.
129 */
130 } else {
131 READ_NEXT_PAIR(v1, v2, i);
132 while (v2 != 0xDEAD &&
133 v2 != 0xCDEF &&
134 v2 != 0xCDCD &&
135 i < arraylen - 2) {
136 rtl_bb_delay(hw,
137 v1, v2);
138 READ_NEXT_PAIR(v1, v2, i);
139 }
140 48
141 while (v2 != 0xDEAD && i < arraylen - 2) 49static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw);
142 READ_NEXT_PAIR(v1, v2, i); 50static void rtl8723be_phy_set_io(struct ieee80211_hw *hw);
143 }
144 }
145 }
146 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
147 arraylen = RTL8723BEAGCTAB_1TARRAYLEN;
148 array_table = RTL8723BEAGCTAB_1TARRAY;
149
150 for (i = 0; i < arraylen; i = i + 2) {
151 v1 = array_table[i];
152 v2 = array_table[i+1];
153 if (v1 < 0xCDCDCDCD) {
154 rtl_set_bbreg(hw, array_table[i],
155 MASKDWORD,
156 array_table[i + 1]);
157 udelay(1);
158 continue;
159 } else {/*This line is the start line of branch.*/
160 if (!_rtl8723be_check_condition(hw, array_table[i])) {
161 /* Discard the following
162 * (offset, data) pairs
163 */
164 READ_NEXT_PAIR(v1, v2, i);
165 while (v2 != 0xDEAD &&
166 v2 != 0xCDEF &&
167 v2 != 0xCDCD &&
168 i < arraylen - 2) {
169 READ_NEXT_PAIR(v1, v2, i);
170 }
171 i -= 2; /* prevent from for-loop += 2*/
172 /*Configure matched pairs and
173 *skip to end of if-else.
174 */
175 } else {
176 READ_NEXT_PAIR(v1, v2, i);
177 while (v2 != 0xDEAD &&
178 v2 != 0xCDEF &&
179 v2 != 0xCDCD &&
180 i < arraylen - 2) {
181 rtl_set_bbreg(hw, array_table[i],
182 MASKDWORD,
183 array_table[i + 1]);
184 udelay(1);
185 READ_NEXT_PAIR(v1, v2, i);
186 }
187
188 while (v2 != 0xDEAD && i < arraylen - 2)
189 READ_NEXT_PAIR(v1, v2, i);
190 }
191 }
192 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
193 "The agctab_array_table[0] is "
194 "%x Rtl818EEPHY_REGArray[1] is %x\n",
195 array_table[i], array_table[i + 1]);
196 }
197 }
198 return true;
199}
200
201static u8 _rtl8723be_get_rate_section_index(u32 regaddr)
202{
203 u8 index = 0;
204
205 switch (regaddr) {
206 case RTXAGC_A_RATE18_06:
207 case RTXAGC_B_RATE18_06:
208 index = 0;
209 break;
210 case RTXAGC_A_RATE54_24:
211 case RTXAGC_B_RATE54_24:
212 index = 1;
213 break;
214 case RTXAGC_A_CCK1_MCS32:
215 case RTXAGC_B_CCK1_55_MCS32:
216 index = 2;
217 break;
218 case RTXAGC_B_CCK11_A_CCK2_11:
219 index = 3;
220 break;
221 case RTXAGC_A_MCS03_MCS00:
222 case RTXAGC_B_MCS03_MCS00:
223 index = 4;
224 break;
225 case RTXAGC_A_MCS07_MCS04:
226 case RTXAGC_B_MCS07_MCS04:
227 index = 5;
228 break;
229 case RTXAGC_A_MCS11_MCS08:
230 case RTXAGC_B_MCS11_MCS08:
231 index = 6;
232 break;
233 case RTXAGC_A_MCS15_MCS12:
234 case RTXAGC_B_MCS15_MCS12:
235 index = 7;
236 break;
237 default:
238 regaddr &= 0xFFF;
239 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
240 index = (u8) ((regaddr - 0xC20) / 4);
241 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
242 index = (u8) ((regaddr - 0xE20) / 4);
243 break;
244 };
245 return index;
246}
247 51
248u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 52u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
249 u32 regaddr, u32 bitmask) 53 u32 regaddr, u32 bitmask)
@@ -265,9 +69,8 @@ u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
265 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 69 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
266 70
267 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 71 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
268 "regaddr(%#x), rfpath(%#x), " 72 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
269 "bitmask(%#x), original_value(%#x)\n", 73 regaddr, rfpath, bitmask, original_value);
270 regaddr, rfpath, bitmask, original_value);
271 74
272 return readback_value; 75 return readback_value;
273} 76}
@@ -300,6 +103,7 @@ void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path path,
300 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 103 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
301 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 104 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
302 regaddr, bitmask, data, path); 105 regaddr, bitmask, data, path);
106
303} 107}
304 108
305bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw) 109bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw)
@@ -316,7 +120,7 @@ bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw)
316 bool rtstatus = true; 120 bool rtstatus = true;
317 struct rtl_priv *rtlpriv = rtl_priv(hw); 121 struct rtl_priv *rtlpriv = rtl_priv(hw);
318 u16 regval; 122 u16 regval;
319 u8 reg_hwparafile = 1; 123 u8 b_reg_hwparafile = 1;
320 u32 tmp; 124 u32 tmp;
321 u8 crystalcap = rtlpriv->efuse.crystalcap; 125 u8 crystalcap = rtlpriv->efuse.crystalcap;
322 rtl8723_phy_init_bb_rf_reg_def(hw); 126 rtl8723_phy_init_bb_rf_reg_def(hw);
@@ -333,7 +137,7 @@ bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw)
333 137
334 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 138 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
335 139
336 if (reg_hwparafile == 1) 140 if (b_reg_hwparafile == 1)
337 rtstatus = _rtl8723be_phy_bb8723b_config_parafile(hw); 141 rtstatus = _rtl8723be_phy_bb8723b_config_parafile(hw);
338 142
339 crystalcap = crystalcap & 0x3F; 143 crystalcap = crystalcap & 0x3F;
@@ -348,18 +152,49 @@ bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw)
348 return rtl8723be_phy_rf6052_config(hw); 152 return rtl8723be_phy_rf6052_config(hw);
349} 153}
350 154
155static bool _rtl8723be_check_condition(struct ieee80211_hw *hw,
156 const u32 condition)
157{
158 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
159 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
160 u32 _board = rtlefuse->board_type; /*need efuse define*/
161 u32 _interface = rtlhal->interface;
162 u32 _platform = 0x08;/*SupportPlatform */
163 u32 cond = condition;
164
165 if (condition == 0xCDCDCDCD)
166 return true;
167
168 cond = condition & 0xFF;
169 if ((_board & cond) == 0 && cond != 0x1F)
170 return false;
171
172 cond = condition & 0xFF00;
173 cond = cond >> 8;
174 if ((_interface & cond) == 0 && cond != 0x07)
175 return false;
176
177 cond = condition & 0xFF0000;
178 cond = cond >> 16;
179 if ((_platform & cond) == 0 && cond != 0x0F)
180 return false;
181 return true;
182}
183
351static void _rtl8723be_config_rf_reg(struct ieee80211_hw *hw, u32 addr, 184static void _rtl8723be_config_rf_reg(struct ieee80211_hw *hw, u32 addr,
352 u32 data, enum radio_path rfpath, 185 u32 data, enum radio_path rfpath,
353 u32 regaddr) 186 u32 regaddr)
354{ 187{
355 if (addr == 0xfe || addr == 0xffe) { 188 if (addr == 0xfe || addr == 0xffe) {
189 /* In order not to disturb BT music
190 * when wifi init.(1ant NIC only)
191 */
356 mdelay(50); 192 mdelay(50);
357 } else { 193 } else {
358 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); 194 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
359 udelay(1); 195 udelay(1);
360 } 196 }
361} 197}
362
363static void _rtl8723be_config_rf_radio_a(struct ieee80211_hw *hw, 198static void _rtl8723be_config_rf_radio_a(struct ieee80211_hw *hw,
364 u32 addr, u32 data) 199 u32 addr, u32 data)
365{ 200{
@@ -368,12 +203,13 @@ static void _rtl8723be_config_rf_radio_a(struct ieee80211_hw *hw,
368 203
369 _rtl8723be_config_rf_reg(hw, addr, data, RF90_PATH_A, 204 _rtl8723be_config_rf_reg(hw, addr, data, RF90_PATH_A,
370 addr | maskforphyset); 205 addr | maskforphyset);
206
371} 207}
372 208
373static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) 209static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
374{ 210{
375 struct rtl_priv *rtlpriv = rtl_priv(hw); 211 struct rtl_priv *rtlpriv = rtl_priv(hw);
376 struct rtl_phy *rtlphy = &(rtlpriv->phy); 212 struct rtl_phy *rtlphy = &rtlpriv->phy;
377 213
378 u8 band, path, txnum, section; 214 u8 band, path, txnum, section;
379 215
@@ -383,16 +219,38 @@ static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
383 for (section = 0; 219 for (section = 0;
384 section < TX_PWR_BY_RATE_NUM_SECTION; 220 section < TX_PWR_BY_RATE_NUM_SECTION;
385 ++section) 221 ++section)
386 rtlphy->tx_power_by_rate_offset[band] 222 rtlphy->tx_power_by_rate_offset
387 [path][txnum][section] = 0; 223 [band][path][txnum][section] = 0;
224}
225
226static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw,
227 u32 addr, u32 data)
228{
229 if (addr == 0xfe) {
230 mdelay(50);
231 } else if (addr == 0xfd) {
232 mdelay(5);
233 } else if (addr == 0xfc) {
234 mdelay(1);
235 } else if (addr == 0xfb) {
236 udelay(50);
237 } else if (addr == 0xfa) {
238 udelay(5);
239 } else if (addr == 0xf9) {
240 udelay(1);
241 } else {
242 rtl_set_bbreg(hw, addr, MASKDWORD, data);
243 udelay(1);
244 }
388} 245}
389 246
390static void phy_set_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band, 247static void _rtl8723be_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
391 u8 path, u8 rate_section, 248 u8 band,
392 u8 txnum, u8 value) 249 u8 path, u8 rate_section,
250 u8 txnum, u8 value)
393{ 251{
394 struct rtl_priv *rtlpriv = rtl_priv(hw); 252 struct rtl_priv *rtlpriv = rtl_priv(hw);
395 struct rtl_phy *rtlphy = &(rtlpriv->phy); 253 struct rtl_phy *rtlphy = &rtlpriv->phy;
396 254
397 if (path > RF90_PATH_D) { 255 if (path > RF90_PATH_D) {
398 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 256 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
@@ -417,23 +275,24 @@ static void phy_set_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band,
417 break; 275 break;
418 default: 276 default:
419 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 277 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
420 "Invalid RateSection %d in Band 2.4G, Rf Path" 278 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
421 " %d, %dTx in PHY_SetTxPowerByRateBase()\n", 279 rate_section, path, txnum);
422 rate_section, path, txnum);
423 break; 280 break;
424 }; 281 };
425 } else { 282 } else {
426 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 283 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
427 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n", 284 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n",
428 band); 285 band);
429 } 286 }
287
430} 288}
431 289
432static u8 phy_get_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band, u8 path, 290static u8 _rtl8723be_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
433 u8 txnum, u8 rate_section) 291 u8 band, u8 path, u8 txnum,
292 u8 rate_section)
434{ 293{
435 struct rtl_priv *rtlpriv = rtl_priv(hw); 294 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct rtl_phy *rtlphy = &(rtlpriv->phy); 295 struct rtl_phy *rtlphy = &rtlpriv->phy;
437 u8 value = 0; 296 u8 value = 0;
438 if (path > RF90_PATH_D) { 297 if (path > RF90_PATH_D) {
439 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 298 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
@@ -458,15 +317,14 @@ static u8 phy_get_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band, u8 path,
458 break; 317 break;
459 default: 318 default:
460 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 319 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
461 "Invalid RateSection %d in Band 2.4G, Rf Path" 320 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
462 " %d, %dTx in PHY_GetTxPowerByRateBase()\n", 321 rate_section, path, txnum);
463 rate_section, path, txnum);
464 break; 322 break;
465 }; 323 };
466 } else { 324 } else {
467 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 325 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
468 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n", 326 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n",
469 band); 327 band);
470 } 328 }
471 329
472 return value; 330 return value;
@@ -475,45 +333,51 @@ static u8 phy_get_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band, u8 path,
475static void _rtl8723be_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) 333static void _rtl8723be_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
476{ 334{
477 struct rtl_priv *rtlpriv = rtl_priv(hw); 335 struct rtl_priv *rtlpriv = rtl_priv(hw);
478 struct rtl_phy *rtlphy = &(rtlpriv->phy); 336 struct rtl_phy *rtlphy = &rtlpriv->phy;
479 u16 raw_value = 0; 337 u16 rawvalue = 0;
480 u8 base = 0, path = 0; 338 u8 base = 0, path = 0;
481 339
482 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) { 340 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
483 if (path == RF90_PATH_A) { 341 if (path == RF90_PATH_A) {
484 raw_value = (u16) (rtlphy->tx_power_by_rate_offset 342 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
485 [BAND_ON_2_4G][path][RF_1TX][3] >> 24) & 0xFF; 343 [BAND_ON_2_4G][path][RF_1TX][3] >> 24) & 0xFF;
486 base = (raw_value >> 4) * 10 + (raw_value & 0xF); 344 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
487 phy_set_txpwr_by_rate_base(hw, BAND_ON_2_4G, path, CCK, 345 _rtl8723be_phy_set_txpower_by_rate_base(hw,
488 RF_1TX, base); 346 BAND_ON_2_4G, path, CCK, RF_1TX, base);
489 } else if (path == RF90_PATH_B) { 347 } else if (path == RF90_PATH_B) {
490 raw_value = (u16) (rtlphy->tx_power_by_rate_offset 348 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
491 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) & 0xFF; 349 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) & 0xFF;
492 base = (raw_value >> 4) * 10 + (raw_value & 0xF); 350 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
493 phy_set_txpwr_by_rate_base(hw, BAND_ON_2_4G, path, 351 _rtl8723be_phy_set_txpower_by_rate_base(hw,
494 CCK, RF_1TX, base); 352 BAND_ON_2_4G,
353 path, CCK,
354 RF_1TX, base);
495 } 355 }
496 raw_value = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 356 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
497 [path][RF_1TX][1] >> 24) & 0xFF; 357 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF;
498 base = (raw_value >> 4) * 10 + (raw_value & 0xF); 358 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
499 phy_set_txpwr_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, 359 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
500 base); 360 path, OFDM, RF_1TX,
501 361 base);
502 raw_value = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 362
503 [path][RF_1TX][5] >> 24) & 0xFF; 363 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
504 base = (raw_value >> 4) * 10 + (raw_value & 0xF); 364 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF;
505 phy_set_txpwr_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, 365 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
506 RF_1TX, base); 366 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
507 367 path, HT_MCS0_MCS7,
508 raw_value = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 368 RF_1TX, base);
509 [path][RF_2TX][7] >> 24) & 0xFF; 369
510 base = (raw_value >> 4) * 10 + (raw_value & 0xF); 370 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
511 phy_set_txpwr_by_rate_base(hw, BAND_ON_2_4G, path, 371 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF;
512 HT_MCS8_MCS15, RF_2TX, base); 372 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
373 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
374 path, HT_MCS8_MCS15,
375 RF_2TX, base);
513 } 376 }
514} 377}
515 378
516static void phy_conv_dbm_to_rel(u32 *data, u8 start, u8 end, u8 base_val) 379static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
380 u8 end, u8 base_val)
517{ 381{
518 char i = 0; 382 char i = 0;
519 u8 temp_value = 0; 383 u8 temp_value = 0;
@@ -522,15 +386,15 @@ static void phy_conv_dbm_to_rel(u32 *data, u8 start, u8 end, u8 base_val)
522 for (i = 3; i >= 0; --i) { 386 for (i = 3; i >= 0; --i) {
523 if (i >= start && i <= end) { 387 if (i >= start && i <= end) {
524 /* Get the exact value */ 388 /* Get the exact value */
525 temp_value = (u8) (*data >> (i * 8)) & 0xF; 389 temp_value = (u8)(*data >> (i * 8)) & 0xF;
526 temp_value += ((u8) ((*data >> (i*8 + 4)) & 0xF)) * 10; 390 temp_value += ((u8)((*data >> (i*8 + 4)) & 0xF)) * 10;
527 391
528 /* Change the value to a relative value */ 392 /* Change the value to a relative value */
529 temp_value = (temp_value > base_val) ? 393 temp_value = (temp_value > base_val) ?
530 temp_value - base_val : 394 temp_value - base_val :
531 base_val - temp_value; 395 base_val - temp_value;
532 } else { 396 } else {
533 temp_value = (u8) (*data >> (i * 8)) & 0xFF; 397 temp_value = (u8)(*data >> (i * 8)) & 0xFF;
534 } 398 }
535 temp_data <<= 8; 399 temp_data <<= 8;
536 temp_data |= temp_value; 400 temp_data |= temp_value;
@@ -538,56 +402,65 @@ static void phy_conv_dbm_to_rel(u32 *data, u8 start, u8 end, u8 base_val)
538 *data = temp_data; 402 *data = temp_data;
539} 403}
540 404
541static void conv_dbm_to_rel(struct ieee80211_hw *hw) 405static void _rtl8723be_phy_convert_txpower_dbm_to_relative_value(
406 struct ieee80211_hw *hw)
542{ 407{
543 struct rtl_priv *rtlpriv = rtl_priv(hw); 408 struct rtl_priv *rtlpriv = rtl_priv(hw);
544 struct rtl_phy *rtlphy = &(rtlpriv->phy); 409 struct rtl_phy *rtlphy = &rtlpriv->phy;
545 u8 base = 0, rfpath = RF90_PATH_A; 410 u8 base = 0, rfpath = RF90_PATH_A;
546 411
547 base = phy_get_txpwr_by_rate_base(hw, BAND_ON_2_4G, rfpath, 412 base = _rtl8723be_phy_get_txpower_by_rate_base(hw,
548 RF_1TX, CCK); 413 BAND_ON_2_4G, rfpath, RF_1TX, CCK);
549 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 414 _phy_convert_txpower_dbm_to_relative_value(
550 [rfpath][RF_1TX][2]), 1, 1, base); 415 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][2],
551 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 416 1, 1, base);
552 [rfpath][RF_1TX][3]), 1, 3, base); 417 _phy_convert_txpower_dbm_to_relative_value(
553 418 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][3],
554 base = phy_get_txpwr_by_rate_base(hw, BAND_ON_2_4G, rfpath, 419 1, 3, base);
555 RF_1TX, OFDM); 420
556 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 421 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath,
557 [rfpath][RF_1TX][0]), 0, 3, base); 422 RF_1TX, OFDM);
558 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 423 _phy_convert_txpower_dbm_to_relative_value(
559 [rfpath][RF_1TX][1]), 0, 3, base); 424 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0],
560 425 0, 3, base);
561 base = phy_get_txpwr_by_rate_base(hw, BAND_ON_2_4G, rfpath, 426 _phy_convert_txpower_dbm_to_relative_value(
562 RF_1TX, HT_MCS0_MCS7); 427 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][1],
563 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 428 0, 3, base);
564 [rfpath][RF_1TX][4]), 0, 3, base); 429
565 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 430 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G,
566 [rfpath][RF_1TX][5]), 0, 3, base); 431 rfpath, RF_1TX, HT_MCS0_MCS7);
567 432 _phy_convert_txpower_dbm_to_relative_value(
568 base = phy_get_txpwr_by_rate_base(hw, BAND_ON_2_4G, rfpath, 433 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][4],
569 RF_2TX, HT_MCS8_MCS15); 434 0, 3, base);
570 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 435 _phy_convert_txpower_dbm_to_relative_value(
571 [rfpath][RF_2TX][6]), 0, 3, base); 436 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][5],
572 437 0, 3, base);
573 phy_conv_dbm_to_rel(&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G] 438
574 [rfpath][RF_2TX][7]), 0, 3, base); 439 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G,
440 rfpath, RF_2TX,
441 HT_MCS8_MCS15);
442 _phy_convert_txpower_dbm_to_relative_value(
443 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][6],
444 0, 3, base);
445
446 _phy_convert_txpower_dbm_to_relative_value(
447 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][7],
448 0, 3, base);
575 449
576 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 450 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
577 "<=== conv_dbm_to_rel()\n"); 451 "<===_rtl8723be_phy_convert_txpower_dbm_to_relative_value()\n");
578} 452}
579 453
580static void _rtl8723be_phy_txpower_by_rate_configuration( 454static void phy_txpower_by_rate_config(struct ieee80211_hw *hw)
581 struct ieee80211_hw *hw)
582{ 455{
583 _rtl8723be_phy_store_txpower_by_rate_base(hw); 456 _rtl8723be_phy_store_txpower_by_rate_base(hw);
584 conv_dbm_to_rel(hw); 457 _rtl8723be_phy_convert_txpower_dbm_to_relative_value(hw);
585} 458}
586 459
587static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw) 460static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw)
588{ 461{
589 struct rtl_priv *rtlpriv = rtl_priv(hw); 462 struct rtl_priv *rtlpriv = rtl_priv(hw);
590 struct rtl_phy *rtlphy = &(rtlpriv->phy); 463 struct rtl_phy *rtlphy = &rtlpriv->phy;
591 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 464 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
592 bool rtstatus; 465 bool rtstatus;
593 466
@@ -603,7 +476,7 @@ static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw)
603 rtstatus = _rtl8723be_phy_config_bb_with_pgheaderfile(hw, 476 rtstatus = _rtl8723be_phy_config_bb_with_pgheaderfile(hw,
604 BASEBAND_CONFIG_PHY_REG); 477 BASEBAND_CONFIG_PHY_REG);
605 } 478 }
606 _rtl8723be_phy_txpower_by_rate_configuration(hw); 479 phy_txpower_by_rate_config(hw);
607 if (!rtstatus) { 480 if (!rtstatus) {
608 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!"); 481 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
609 return false; 482 return false;
@@ -614,39 +487,237 @@ static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw)
614 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n"); 487 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
615 return false; 488 return false;
616 } 489 }
617 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 490 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
618 RFPGA0_XA_HSSIPARAMETER2, 491 RFPGA0_XA_HSSIPARAMETER2,
619 0x200)); 492 0x200));
620 return true; 493 return true;
621} 494}
622 495
496static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
497{
498 struct rtl_priv *rtlpriv = rtl_priv(hw);
499 u32 i;
500 u32 arraylength;
501 u32 *ptrarray;
502
503 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read rtl8723beMACPHY_Array\n");
504 arraylength = RTL8723BEMAC_1T_ARRAYLEN;
505 ptrarray = RTL8723BEMAC_1T_ARRAY;
506 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
507 "Img:RTL8723bEMAC_1T_ARRAY LEN %d\n", arraylength);
508 for (i = 0; i < arraylength; i = i + 2)
509 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
510 return true;
511}
512
513static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
514 u8 configtype)
515{
516 #define READ_NEXT_PAIR(v1, v2, i) \
517 do { \
518 i += 2; \
519 v1 = array_table[i];\
520 v2 = array_table[i+1]; \
521 } while (0)
522
523 int i;
524 u32 *array_table;
525 u16 arraylen;
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527 u32 v1 = 0, v2 = 0;
528
529 if (configtype == BASEBAND_CONFIG_PHY_REG) {
530 arraylen = RTL8723BEPHY_REG_1TARRAYLEN;
531 array_table = RTL8723BEPHY_REG_1TARRAY;
532
533 for (i = 0; i < arraylen; i = i + 2) {
534 v1 = array_table[i];
535 v2 = array_table[i+1];
536 if (v1 < 0xcdcdcdcd) {
537 _rtl8723be_config_bb_reg(hw, v1, v2);
538 } else {/*This line is the start line of branch.*/
539 /* to protect READ_NEXT_PAIR not overrun */
540 if (i >= arraylen - 2)
541 break;
542
543 if (!_rtl8723be_check_condition(hw,
544 array_table[i])) {
545 /*Discard the following
546 *(offset, data) pairs
547 */
548 READ_NEXT_PAIR(v1, v2, i);
549 while (v2 != 0xDEAD &&
550 v2 != 0xCDEF &&
551 v2 != 0xCDCD &&
552 i < arraylen - 2) {
553 READ_NEXT_PAIR(v1, v2, i);
554 }
555 i -= 2; /* prevent from for-loop += 2*/
556 /*Configure matched pairs and
557 *skip to end of if-else.
558 */
559 } else {
560 READ_NEXT_PAIR(v1, v2, i);
561 while (v2 != 0xDEAD &&
562 v2 != 0xCDEF &&
563 v2 != 0xCDCD &&
564 i < arraylen - 2) {
565 _rtl8723be_config_bb_reg(hw,
566 v1, v2);
567 READ_NEXT_PAIR(v1, v2, i);
568 }
569
570 while (v2 != 0xDEAD && i < arraylen - 2)
571 READ_NEXT_PAIR(v1, v2, i);
572 }
573 }
574 }
575 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
576 arraylen = RTL8723BEAGCTAB_1TARRAYLEN;
577 array_table = RTL8723BEAGCTAB_1TARRAY;
578
579 for (i = 0; i < arraylen; i = i + 2) {
580 v1 = array_table[i];
581 v2 = array_table[i+1];
582 if (v1 < 0xCDCDCDCD) {
583 rtl_set_bbreg(hw, array_table[i],
584 MASKDWORD,
585 array_table[i + 1]);
586 udelay(1);
587 continue;
588 } else {/*This line is the start line of branch.*/
589 /* to protect READ_NEXT_PAIR not overrun */
590 if (i >= arraylen - 2)
591 break;
592
593 if (!_rtl8723be_check_condition(hw,
594 array_table[i])) {
595 /*Discard the following
596 *(offset, data) pairs
597 */
598 READ_NEXT_PAIR(v1, v2, i);
599 while (v2 != 0xDEAD &&
600 v2 != 0xCDEF &&
601 v2 != 0xCDCD &&
602 i < arraylen - 2) {
603 READ_NEXT_PAIR(v1, v2, i);
604 }
605 i -= 2; /* prevent from for-loop += 2*/
606 /*Configure matched pairs and
607 *skip to end of if-else.
608 */
609 } else {
610 READ_NEXT_PAIR(v1, v2, i);
611 while (v2 != 0xDEAD &&
612 v2 != 0xCDEF &&
613 v2 != 0xCDCD &&
614 i < arraylen - 2) {
615 rtl_set_bbreg(hw, array_table[i],
616 MASKDWORD,
617 array_table[i + 1]);
618 udelay(1);
619 READ_NEXT_PAIR(v1, v2, i);
620 }
621
622 while (v2 != 0xDEAD && i < arraylen - 2)
623 READ_NEXT_PAIR(v1, v2, i);
624 }
625 }
626 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
627 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
628 array_table[i], array_table[i + 1]);
629 }
630 }
631 return true;
632}
633
634static u8 _rtl8723be_get_rate_section_index(u32 regaddr)
635{
636 u8 index = 0;
637
638 switch (regaddr) {
639 case RTXAGC_A_RATE18_06:
640 index = 0;
641 break;
642 case RTXAGC_A_RATE54_24:
643 index = 1;
644 break;
645 case RTXAGC_A_CCK1_MCS32:
646 index = 2;
647 break;
648 case RTXAGC_B_CCK11_A_CCK2_11:
649 index = 3;
650 break;
651 case RTXAGC_A_MCS03_MCS00:
652 index = 4;
653 break;
654 case RTXAGC_A_MCS07_MCS04:
655 index = 5;
656 break;
657 case RTXAGC_A_MCS11_MCS08:
658 index = 6;
659 break;
660 case RTXAGC_A_MCS15_MCS12:
661 index = 7;
662 break;
663 case RTXAGC_B_RATE18_06:
664 index = 0;
665 break;
666 case RTXAGC_B_RATE54_24:
667 index = 1;
668 break;
669 case RTXAGC_B_CCK1_55_MCS32:
670 index = 2;
671 break;
672 case RTXAGC_B_MCS03_MCS00:
673 index = 4;
674 break;
675 case RTXAGC_B_MCS07_MCS04:
676 index = 5;
677 break;
678 case RTXAGC_B_MCS11_MCS08:
679 index = 6;
680 break;
681 case RTXAGC_B_MCS15_MCS12:
682 index = 7;
683 break;
684 default:
685 regaddr &= 0xFFF;
686 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
687 index = (u8)((regaddr - 0xC20) / 4);
688 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
689 index = (u8)((regaddr - 0xE20) / 4);
690 break;
691 };
692 return index;
693}
694
623static void _rtl8723be_store_tx_power_by_rate(struct ieee80211_hw *hw, 695static void _rtl8723be_store_tx_power_by_rate(struct ieee80211_hw *hw,
624 u32 band, u32 rfpath, 696 u32 band, u32 rfpath,
625 u32 txnum, u32 regaddr, 697 u32 txnum, u32 regaddr,
626 u32 bitmask, u32 data) 698 u32 bitmask, u32 data)
627{ 699{
628 struct rtl_priv *rtlpriv = rtl_priv(hw); 700 struct rtl_priv *rtlpriv = rtl_priv(hw);
629 struct rtl_phy *rtlphy = &(rtlpriv->phy); 701 struct rtl_phy *rtlphy = &rtlpriv->phy;
630 u8 rate_section = _rtl8723be_get_rate_section_index(regaddr); 702 u8 rate_section = _rtl8723be_get_rate_section_index(regaddr);
631 703
632 if (band != BAND_ON_2_4G && band != BAND_ON_5G) { 704 if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
633 RT_TRACE(rtlpriv, COMP_POWER, PHY_TXPWR, 705 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band);
634 "Invalid Band %d\n", band);
635 return; 706 return;
636 } 707 }
637 708 if (rfpath > MAX_RF_PATH - 1) {
638 if (rfpath > TX_PWR_BY_RATE_NUM_RF) { 709 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR,
639 RT_TRACE(rtlpriv, COMP_POWER, PHY_TXPWR,
640 "Invalid RfPath %d\n", rfpath); 710 "Invalid RfPath %d\n", rfpath);
641 return; 711 return;
642 } 712 }
643 if (txnum > TX_PWR_BY_RATE_NUM_RF) { 713 if (txnum > MAX_RF_PATH - 1) {
644 RT_TRACE(rtlpriv, COMP_POWER, PHY_TXPWR, 714 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum);
645 "Invalid TxNum %d\n", txnum);
646 return; 715 return;
647 } 716 }
717
648 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = 718 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] =
649 data; 719 data;
720
650} 721}
651 722
652static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 723static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
@@ -678,21 +749,6 @@ static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
678 _rtl8723be_store_tx_power_by_rate(hw, 749 _rtl8723be_store_tx_power_by_rate(hw,
679 v1, v2, v3, v4, v5, v6); 750 v1, v2, v3, v4, v5, v6);
680 continue; 751 continue;
681 } else {
682 /*don't need the hw_body*/
683 if (!_rtl8723be_check_condition(hw,
684 phy_regarray_table_pg[i])) {
685 i += 2; /* skip the pair of expression*/
686 v1 = phy_regarray_table_pg[i];
687 v2 = phy_regarray_table_pg[i+1];
688 v3 = phy_regarray_table_pg[i+2];
689 while (v2 != 0xDEAD) {
690 i += 3;
691 v1 = phy_regarray_table_pg[i];
692 v2 = phy_regarray_table_pg[i+1];
693 v3 = phy_regarray_table_pg[i+2];
694 }
695 }
696 } 752 }
697 } 753 }
698 } else { 754 } else {
@@ -733,22 +789,27 @@ bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
733 v2 = radioa_array_table[i+1]; 789 v2 = radioa_array_table[i+1];
734 if (v1 < 0xcdcdcdcd) { 790 if (v1 < 0xcdcdcdcd) {
735 _rtl8723be_config_rf_radio_a(hw, v1, v2); 791 _rtl8723be_config_rf_radio_a(hw, v1, v2);
736 } else { /*This line is the start line of branch.*/ 792 } else {/*This line is the start line of branch.*/
793 /* to protect READ_NEXT_PAIR not overrun */
794 if (i >= radioa_arraylen - 2)
795 break;
796
737 if (!_rtl8723be_check_condition(hw, 797 if (!_rtl8723be_check_condition(hw,
738 radioa_array_table[i])) { 798 radioa_array_table[i])) {
739 /* Discard the following 799 /*Discard the following
740 * (offset, data) pairs 800 *(offset, data) pairs
741 */ 801 */
742 READ_NEXT_RF_PAIR(v1, v2, i); 802 READ_NEXT_RF_PAIR(v1, v2, i);
743 while (v2 != 0xDEAD && 803 while (v2 != 0xDEAD &&
744 v2 != 0xCDEF && 804 v2 != 0xCDEF &&
745 v2 != 0xCDCD && 805 v2 != 0xCDCD &&
746 i < radioa_arraylen - 2) 806 i < radioa_arraylen - 2) {
747 READ_NEXT_RF_PAIR(v1, v2, i); 807 READ_NEXT_RF_PAIR(v1, v2, i);
808 }
748 i -= 2; /* prevent from for-loop += 2*/ 809 i -= 2; /* prevent from for-loop += 2*/
749 } else { 810 } else {
750 /* Configure matched pairs 811 /*Configure matched pairs
751 * and skip to end of if-else. 812 *and skip to end of if-else.
752 */ 813 */
753 READ_NEXT_RF_PAIR(v1, v2, i); 814 READ_NEXT_RF_PAIR(v1, v2, i);
754 while (v2 != 0xDEAD && 815 while (v2 != 0xDEAD &&
@@ -770,18 +831,12 @@ bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
770 831
771 if (rtlhal->oem_id == RT_CID_819X_HP) 832 if (rtlhal->oem_id == RT_CID_819X_HP)
772 _rtl8723be_config_rf_radio_a(hw, 0x52, 0x7E4BD); 833 _rtl8723be_config_rf_radio_a(hw, 0x52, 0x7E4BD);
773
774 break; 834 break;
775 case RF90_PATH_B: 835 case RF90_PATH_B:
776 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
777 "switch case not process\n");
778 break;
779 case RF90_PATH_C: 836 case RF90_PATH_C:
780 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
781 "switch case not process\n");
782 break; 837 break;
783 case RF90_PATH_D: 838 case RF90_PATH_D:
784 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 839 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
785 "switch case not process\n"); 840 "switch case not process\n");
786 break; 841 break;
787 } 842 }
@@ -791,26 +846,25 @@ bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
791void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 846void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
792{ 847{
793 struct rtl_priv *rtlpriv = rtl_priv(hw); 848 struct rtl_priv *rtlpriv = rtl_priv(hw);
794 struct rtl_phy *rtlphy = &(rtlpriv->phy); 849 struct rtl_phy *rtlphy = &rtlpriv->phy;
795 850
796 rtlphy->default_initialgain[0] = 851 rtlphy->default_initialgain[0] =
797 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 852 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
798 rtlphy->default_initialgain[1] = 853 rtlphy->default_initialgain[1] =
799 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 854 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
800 rtlphy->default_initialgain[2] = 855 rtlphy->default_initialgain[2] =
801 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 856 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
802 rtlphy->default_initialgain[3] = 857 rtlphy->default_initialgain[3] =
803 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 858 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
804 859
805 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 860 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
806 "Default initial gain (c50 = 0x%x, " 861 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
807 "c58 = 0x%x, c60 = 0x%x, c68 = 0x%x\n", 862 rtlphy->default_initialgain[0],
808 rtlphy->default_initialgain[0], 863 rtlphy->default_initialgain[1],
809 rtlphy->default_initialgain[1], 864 rtlphy->default_initialgain[2],
810 rtlphy->default_initialgain[2], 865 rtlphy->default_initialgain[3]);
811 rtlphy->default_initialgain[3]); 866
812 867 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
813 rtlphy->framesync = (u8) rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
814 MASKBYTE0); 868 MASKBYTE0);
815 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 869 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
816 MASKDWORD); 870 MASKDWORD);
@@ -823,7 +877,7 @@ void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
823void rtl8723be_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 877void rtl8723be_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
824{ 878{
825 struct rtl_priv *rtlpriv = rtl_priv(hw); 879 struct rtl_priv *rtlpriv = rtl_priv(hw);
826 struct rtl_phy *rtlphy = &(rtlpriv->phy); 880 struct rtl_phy *rtlphy = &rtlpriv->phy;
827 u8 txpwr_level; 881 u8 txpwr_level;
828 long txpwr_dbm; 882 long txpwr_dbm;
829 883
@@ -854,6 +908,7 @@ static u8 _rtl8723be_phy_get_ratesection_intxpower_byrate(enum radio_path path,
854 case DESC92C_RATE1M: 908 case DESC92C_RATE1M:
855 rate_section = 2; 909 rate_section = 2;
856 break; 910 break;
911
857 case DESC92C_RATE2M: 912 case DESC92C_RATE2M:
858 case DESC92C_RATE5_5M: 913 case DESC92C_RATE5_5M:
859 if (path == RF90_PATH_A) 914 if (path == RF90_PATH_A)
@@ -861,49 +916,58 @@ static u8 _rtl8723be_phy_get_ratesection_intxpower_byrate(enum radio_path path,
861 else if (path == RF90_PATH_B) 916 else if (path == RF90_PATH_B)
862 rate_section = 2; 917 rate_section = 2;
863 break; 918 break;
919
864 case DESC92C_RATE11M: 920 case DESC92C_RATE11M:
865 rate_section = 3; 921 rate_section = 3;
866 break; 922 break;
923
867 case DESC92C_RATE6M: 924 case DESC92C_RATE6M:
868 case DESC92C_RATE9M: 925 case DESC92C_RATE9M:
869 case DESC92C_RATE12M: 926 case DESC92C_RATE12M:
870 case DESC92C_RATE18M: 927 case DESC92C_RATE18M:
871 rate_section = 0; 928 rate_section = 0;
872 break; 929 break;
930
873 case DESC92C_RATE24M: 931 case DESC92C_RATE24M:
874 case DESC92C_RATE36M: 932 case DESC92C_RATE36M:
875 case DESC92C_RATE48M: 933 case DESC92C_RATE48M:
876 case DESC92C_RATE54M: 934 case DESC92C_RATE54M:
877 rate_section = 1; 935 rate_section = 1;
878 break; 936 break;
937
879 case DESC92C_RATEMCS0: 938 case DESC92C_RATEMCS0:
880 case DESC92C_RATEMCS1: 939 case DESC92C_RATEMCS1:
881 case DESC92C_RATEMCS2: 940 case DESC92C_RATEMCS2:
882 case DESC92C_RATEMCS3: 941 case DESC92C_RATEMCS3:
883 rate_section = 4; 942 rate_section = 4;
884 break; 943 break;
944
885 case DESC92C_RATEMCS4: 945 case DESC92C_RATEMCS4:
886 case DESC92C_RATEMCS5: 946 case DESC92C_RATEMCS5:
887 case DESC92C_RATEMCS6: 947 case DESC92C_RATEMCS6:
888 case DESC92C_RATEMCS7: 948 case DESC92C_RATEMCS7:
889 rate_section = 5; 949 rate_section = 5;
890 break; 950 break;
951
891 case DESC92C_RATEMCS8: 952 case DESC92C_RATEMCS8:
892 case DESC92C_RATEMCS9: 953 case DESC92C_RATEMCS9:
893 case DESC92C_RATEMCS10: 954 case DESC92C_RATEMCS10:
894 case DESC92C_RATEMCS11: 955 case DESC92C_RATEMCS11:
895 rate_section = 6; 956 rate_section = 6;
896 break; 957 break;
958
897 case DESC92C_RATEMCS12: 959 case DESC92C_RATEMCS12:
898 case DESC92C_RATEMCS13: 960 case DESC92C_RATEMCS13:
899 case DESC92C_RATEMCS14: 961 case DESC92C_RATEMCS14:
900 case DESC92C_RATEMCS15: 962 case DESC92C_RATEMCS15:
901 rate_section = 7; 963 rate_section = 7;
902 break; 964 break;
965
903 default: 966 default:
904 RT_ASSERT(true, "Rate_Section is Illegal\n"); 967 RT_ASSERT(true, "Rate_Section is Illegal\n");
905 break; 968 break;
906 } 969 }
970
907 return rate_section; 971 return rate_section;
908} 972}
909 973
@@ -912,7 +976,7 @@ static u8 _rtl8723be_get_txpower_by_rate(struct ieee80211_hw *hw,
912 enum radio_path rfpath, u8 rate) 976 enum radio_path rfpath, u8 rate)
913{ 977{
914 struct rtl_priv *rtlpriv = rtl_priv(hw); 978 struct rtl_priv *rtlpriv = rtl_priv(hw);
915 struct rtl_phy *rtlphy = &(rtlpriv->phy); 979 struct rtl_phy *rtlphy = &rtlpriv->phy;
916 u8 shift = 0, rate_section, tx_num; 980 u8 shift = 0, rate_section, tx_num;
917 char tx_pwr_diff = 0; 981 char tx_pwr_diff = 0;
918 982
@@ -988,7 +1052,7 @@ static u8 _rtl8723be_get_txpower_index(struct ieee80211_hw *hw, u8 path,
988 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1052 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
989 "Illegal channel!\n"); 1053 "Illegal channel!\n");
990 } 1054 }
991 if (RTL8723E_RX_HAL_IS_CCK_RATE(rate)) 1055 if (RX_HAL_IS_CCK_RATE(rate))
992 txpower = rtlefuse->txpwrlevel_cck[path][index]; 1056 txpower = rtlefuse->txpwrlevel_cck[path][index];
993 else if (DESC92C_RATE6M <= rate) 1057 else if (DESC92C_RATE6M <= rate)
994 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index]; 1058 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
@@ -997,7 +1061,7 @@ static u8 _rtl8723be_get_txpower_index(struct ieee80211_hw *hw, u8 path,
997 "invalid rate\n"); 1061 "invalid rate\n");
998 1062
999 if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M && 1063 if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M &&
1000 !RTL8723E_RX_HAL_IS_CCK_RATE(rate)) 1064 !RX_HAL_IS_CCK_RATE(rate))
1001 txpower += rtlefuse->txpwr_legacyhtdiff[0][TX_1S]; 1065 txpower += rtlefuse->txpwr_legacyhtdiff[0][TX_1S];
1002 1066
1003 if (bandwidth == HT_CHANNEL_WIDTH_20) { 1067 if (bandwidth == HT_CHANNEL_WIDTH_20) {
@@ -1011,6 +1075,7 @@ static u8 _rtl8723be_get_txpower_index(struct ieee80211_hw *hw, u8 path,
1011 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15) 1075 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1012 txpower += rtlefuse->txpwr_ht40diff[0][TX_2S]; 1076 txpower += rtlefuse->txpwr_ht40diff[0][TX_2S];
1013 } 1077 }
1078
1014 if (rtlefuse->eeprom_regulatory != 2) 1079 if (rtlefuse->eeprom_regulatory != 2)
1015 power_diff_byrate = _rtl8723be_get_txpower_by_rate(hw, 1080 power_diff_byrate = _rtl8723be_get_txpower_by_rate(hw,
1016 BAND_ON_2_4G, 1081 BAND_ON_2_4G,
@@ -1046,6 +1111,7 @@ static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw,
1046 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11, 1111 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1047 MASKBYTE3, power_index); 1112 MASKBYTE3, power_index);
1048 break; 1113 break;
1114
1049 case DESC92C_RATE6M: 1115 case DESC92C_RATE6M:
1050 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06, 1116 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06,
1051 MASKBYTE0, power_index); 1117 MASKBYTE0, power_index);
@@ -1062,6 +1128,7 @@ static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw,
1062 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06, 1128 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06,
1063 MASKBYTE3, power_index); 1129 MASKBYTE3, power_index);
1064 break; 1130 break;
1131
1065 case DESC92C_RATE24M: 1132 case DESC92C_RATE24M:
1066 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24, 1133 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24,
1067 MASKBYTE0, power_index); 1134 MASKBYTE0, power_index);
@@ -1078,6 +1145,7 @@ static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw,
1078 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24, 1145 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24,
1079 MASKBYTE3, power_index); 1146 MASKBYTE3, power_index);
1080 break; 1147 break;
1148
1081 case DESC92C_RATEMCS0: 1149 case DESC92C_RATEMCS0:
1082 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00, 1150 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00,
1083 MASKBYTE0, power_index); 1151 MASKBYTE0, power_index);
@@ -1094,6 +1162,7 @@ static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw,
1094 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00, 1162 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00,
1095 MASKBYTE3, power_index); 1163 MASKBYTE3, power_index);
1096 break; 1164 break;
1165
1097 case DESC92C_RATEMCS4: 1166 case DESC92C_RATEMCS4:
1098 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04, 1167 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
1099 MASKBYTE0, power_index); 1168 MASKBYTE0, power_index);
@@ -1110,6 +1179,7 @@ static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw,
1110 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04, 1179 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
1111 MASKBYTE3, power_index); 1180 MASKBYTE3, power_index);
1112 break; 1181 break;
1182
1113 case DESC92C_RATEMCS8: 1183 case DESC92C_RATEMCS8:
1114 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08, 1184 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08,
1115 MASKBYTE0, power_index); 1185 MASKBYTE0, power_index);
@@ -1126,9 +1196,9 @@ static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw,
1126 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08, 1196 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08,
1127 MASKBYTE3, power_index); 1197 MASKBYTE3, power_index);
1128 break; 1198 break;
1199
1129 default: 1200 default:
1130 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1201 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Rate!!\n");
1131 "Invalid Rate!!\n");
1132 break; 1202 break;
1133 } 1203 }
1134 } else { 1204 } else {
@@ -1192,10 +1262,11 @@ void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1192 1262
1193 if (!is_hal_stop(rtlhal)) { 1263 if (!is_hal_stop(rtlhal)) {
1194 switch (operation) { 1264 switch (operation) {
1195 case SCAN_OPT_BACKUP: 1265 case SCAN_OPT_BACKUP_BAND0:
1196 iotype = IO_CMD_PAUSE_DM_BY_SCAN; 1266 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1197 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, 1267 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1198 (u8 *)&iotype); 1268 (u8 *)&iotype);
1269
1199 break; 1270 break;
1200 case SCAN_OPT_RESTORE: 1271 case SCAN_OPT_RESTORE:
1201 iotype = IO_CMD_RESUME_DM_BY_SCAN; 1272 iotype = IO_CMD_RESUME_DM_BY_SCAN;
@@ -1214,15 +1285,15 @@ void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1214{ 1285{
1215 struct rtl_priv *rtlpriv = rtl_priv(hw); 1286 struct rtl_priv *rtlpriv = rtl_priv(hw);
1216 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1287 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1217 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1288 struct rtl_phy *rtlphy = &rtlpriv->phy;
1218 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1289 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1219 u8 reg_bw_opmode; 1290 u8 reg_bw_opmode;
1220 u8 reg_prsr_rsc; 1291 u8 reg_prsr_rsc;
1221 1292
1222 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 1293 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1223 "Switch to %s bandwidth\n", 1294 "Switch to %s bandwidth\n",
1224 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 1295 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1225 "20MHz" : "40MHz"); 1296 "20MHz" : "40MHz");
1226 1297
1227 if (is_hal_stop(rtlhal)) { 1298 if (is_hal_stop(rtlhal)) {
1228 rtlphy->set_bwmode_inprogress = false; 1299 rtlphy->set_bwmode_inprogress = false;
@@ -1254,13 +1325,17 @@ void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1254 case HT_CHANNEL_WIDTH_20: 1325 case HT_CHANNEL_WIDTH_20:
1255 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 1326 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1256 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 1327 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1328 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1257 break; 1329 break;
1258 case HT_CHANNEL_WIDTH_20_40: 1330 case HT_CHANNEL_WIDTH_20_40:
1259 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1331 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1260 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1332 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1333
1261 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 1334 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1262 (mac->cur_40_prime_sc >> 1)); 1335 (mac->cur_40_prime_sc >> 1));
1263 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 1336 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1337 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1338
1264 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1339 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1265 (mac->cur_40_prime_sc == 1340 (mac->cur_40_prime_sc ==
1266 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1341 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
@@ -1279,7 +1354,7 @@ void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw,
1279 enum nl80211_channel_type ch_type) 1354 enum nl80211_channel_type ch_type)
1280{ 1355{
1281 struct rtl_priv *rtlpriv = rtl_priv(hw); 1356 struct rtl_priv *rtlpriv = rtl_priv(hw);
1282 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1357 struct rtl_phy *rtlphy = &rtlpriv->phy;
1283 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1358 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1284 u8 tmp_bw = rtlphy->current_chan_bw; 1359 u8 tmp_bw = rtlphy->current_chan_bw;
1285 1360
@@ -1300,7 +1375,7 @@ void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1300{ 1375{
1301 struct rtl_priv *rtlpriv = rtl_priv(hw); 1376 struct rtl_priv *rtlpriv = rtl_priv(hw);
1302 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1377 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1303 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1378 struct rtl_phy *rtlphy = &rtlpriv->phy;
1304 u32 delay; 1379 u32 delay;
1305 1380
1306 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 1381 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
@@ -1310,11 +1385,11 @@ void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1310 do { 1385 do {
1311 if (!rtlphy->sw_chnl_inprogress) 1386 if (!rtlphy->sw_chnl_inprogress)
1312 break; 1387 break;
1313 if (!rtl8723be_phy_sw_chn_step_by_step(hw, 1388 if (!_rtl8723be_phy_sw_chnl_step_by_step(hw,
1314 rtlphy->current_channel, 1389 rtlphy->current_channel,
1315 &rtlphy->sw_chnl_stage, 1390 &rtlphy->sw_chnl_stage,
1316 &rtlphy->sw_chnl_step, 1391 &rtlphy->sw_chnl_step,
1317 &delay)) { 1392 &delay)) {
1318 if (delay > 0) 1393 if (delay > 0)
1319 mdelay(delay); 1394 mdelay(delay);
1320 else 1395 else
@@ -1330,7 +1405,7 @@ void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1330u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw) 1405u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw)
1331{ 1406{
1332 struct rtl_priv *rtlpriv = rtl_priv(hw); 1407 struct rtl_priv *rtlpriv = rtl_priv(hw);
1333 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1408 struct rtl_phy *rtlphy = &rtlpriv->phy;
1334 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1409 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1335 1410
1336 if (rtlphy->sw_chnl_inprogress) 1411 if (rtlphy->sw_chnl_inprogress)
@@ -1345,25 +1420,23 @@ u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw)
1345 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1420 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1346 rtl8723be_phy_sw_chnl_callback(hw); 1421 rtl8723be_phy_sw_chnl_callback(hw);
1347 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 1422 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1348 "sw_chnl_inprogress false schdule " 1423 "sw_chnl_inprogress false schdule workitem current channel %d\n",
1349 "workitem current channel %d\n", 1424 rtlphy->current_channel);
1350 rtlphy->current_channel);
1351 rtlphy->sw_chnl_inprogress = false; 1425 rtlphy->sw_chnl_inprogress = false;
1352 } else { 1426 } else {
1353 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 1427 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1354 "sw_chnl_inprogress false driver sleep or" 1428 "sw_chnl_inprogress false driver sleep or unload\n");
1355 " unload\n");
1356 rtlphy->sw_chnl_inprogress = false; 1429 rtlphy->sw_chnl_inprogress = false;
1357 } 1430 }
1358 return 1; 1431 return 1;
1359} 1432}
1360 1433
1361static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw, 1434static bool _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1362 u8 channel, u8 *stage, 1435 u8 channel, u8 *stage,
1363 u8 *step, u32 *delay) 1436 u8 *step, u32 *delay)
1364{ 1437{
1365 struct rtl_priv *rtlpriv = rtl_priv(hw); 1438 struct rtl_priv *rtlpriv = rtl_priv(hw);
1366 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1439 struct rtl_phy *rtlphy = &rtlpriv->phy;
1367 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 1440 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1368 u32 precommoncmdcnt; 1441 u32 precommoncmdcnt;
1369 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 1442 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
@@ -1381,10 +1454,13 @@ static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
1381 0, 0, 0); 1454 0, 0, 0);
1382 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 1455 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1383 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 1456 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1457
1384 postcommoncmdcnt = 0; 1458 postcommoncmdcnt = 0;
1459
1385 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 1460 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1386 MAX_POSTCMD_CNT, CMDID_END, 1461 MAX_POSTCMD_CNT, CMDID_END,
1387 0, 0, 0); 1462 0, 0, 0);
1463
1388 rfdependcmdcnt = 0; 1464 rfdependcmdcnt = 0;
1389 1465
1390 RT_ASSERT((channel >= 1 && channel <= 14), 1466 RT_ASSERT((channel >= 1 && channel <= 14),
@@ -1397,7 +1473,7 @@ static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
1397 1473
1398 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 1474 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1399 MAX_RFDEPENDCMD_CNT, 1475 MAX_RFDEPENDCMD_CNT,
1400 CMDID_END, 0, 0, 0); 1476 CMDID_END, 0, 0, 0);
1401 1477
1402 do { 1478 do {
1403 switch (*stage) { 1479 switch (*stage) {
@@ -1410,6 +1486,10 @@ static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
1410 case 2: 1486 case 2:
1411 currentcmd = &postcommoncmd[*step]; 1487 currentcmd = &postcommoncmd[*step];
1412 break; 1488 break;
1489 default:
1490 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1491 "Invalid 'stage' = %d, Check it!\n", *stage);
1492 return true;
1413 } 1493 }
1414 1494
1415 if (currentcmd->cmdid == CMDID_END) { 1495 if (currentcmd->cmdid == CMDID_END) {
@@ -1432,11 +1512,11 @@ static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
1432 break; 1512 break;
1433 case CMDID_WRITEPORT_USHORT: 1513 case CMDID_WRITEPORT_USHORT:
1434 rtl_write_word(rtlpriv, currentcmd->para1, 1514 rtl_write_word(rtlpriv, currentcmd->para1,
1435 (u16) currentcmd->para2); 1515 (u16)currentcmd->para2);
1436 break; 1516 break;
1437 case CMDID_WRITEPORT_UCHAR: 1517 case CMDID_WRITEPORT_UCHAR:
1438 rtl_write_byte(rtlpriv, currentcmd->para1, 1518 rtl_write_byte(rtlpriv, currentcmd->para1,
1439 (u8) currentcmd->para2); 1519 (u8)currentcmd->para2);
1440 break; 1520 break;
1441 case CMDID_RF_WRITEREG: 1521 case CMDID_RF_WRITEREG:
1442 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 1522 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
@@ -1451,7 +1531,7 @@ static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
1451 } 1531 }
1452 break; 1532 break;
1453 default: 1533 default:
1454 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1534 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1455 "switch case not process\n"); 1535 "switch case not process\n");
1456 break; 1536 break;
1457 } 1537 }
@@ -1464,54 +1544,515 @@ static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
1464 return false; 1544 return false;
1465} 1545}
1466 1546
1467static u8 _rtl8723be_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 1547static u8 _rtl8723be_phy_path_a_iqk(struct ieee80211_hw *hw)
1468{ 1548{
1469 u32 reg_eac, reg_e94, reg_e9c, reg_ea4; 1549 u32 reg_eac, reg_e94, reg_e9c, tmp;
1470 u8 result = 0x00; 1550 u8 result = 0x00;
1471 1551
1472 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); 1552 /* leave IQK mode */
1473 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); 1553 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1474 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); 1554 /* switch to path A */
1475 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); 1555 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
1476 1556 /* enable path A PA in TXIQK mode */
1477 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1557 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1478 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1558 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x20000);
1479 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1559 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0003f);
1560 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xc7f87);
1561
1562 /* 1. TX IQK */
1563 /* path-A IQK setting */
1564 /* IQK setting */
1565 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1566 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1567 /* path-A IQK setting */
1568 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1569 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1570 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1571 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1572
1573 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);
1574 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1575 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1576 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1577 /* LO calibration setting */
1578 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1579 /* enter IQK mode */
1580 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1581
1582 /* One shot, path A LOK & IQK */
1583 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1584 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1480 1585
1481 mdelay(IQK_DELAY_TIME); 1586 mdelay(IQK_DELAY_TIME);
1482 1587
1588 /* leave IQK mode */
1589 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1590
1591 /* Check failed */
1483 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1592 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1484 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1593 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1485 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1594 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1486 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1487 1595
1488 if (!(reg_eac & BIT(28)) && 1596 if (!(reg_eac & BIT(28)) &&
1489 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1597 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1490 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1598 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1491 result |= 0x01; 1599 result |= 0x01;
1600 else /* if Tx not OK, ignore Rx */
1601 return result;
1602
1603 /* Allen 20131125 */
1604 tmp = (reg_e9c & 0x03FF0000) >> 16;
1605 if ((tmp & 0x200) > 0)
1606 tmp = 0x400 - tmp;
1607
1608 if (!(reg_eac & BIT(28)) &&
1609 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1610 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1611 (tmp < 0xf))
1612 result |= 0x01;
1613 else /* if Tx not OK, ignore Rx */
1614 return result;
1615
1492 return result; 1616 return result;
1493} 1617}
1494 1618
1495static bool phy_similarity_cmp(struct ieee80211_hw *hw, long result[][8], 1619/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1496 u8 c1, u8 c2) 1620static u8 _rtl8723be_phy_path_a_rx_iqk(struct ieee80211_hw *hw)
1497{ 1621{
1498 u32 i, j, diff, simularity_bitmap, bound; 1622 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32tmp, tmp;
1499 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1623 u8 result = 0x00;
1624
1625 /* leave IQK mode */
1626 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1627
1628 /* switch to path A */
1629 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
1630
1631 /* 1 Get TXIMR setting */
1632 /* modify RXIQK mode table */
1633 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1634 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1635 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1636 /* LNA2 off, PA on for Dcut */
1637 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7fb7);
1638 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1639
1640 /* IQK setting */
1641 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1642 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1643
1644 /* path-A IQK setting */
1645 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1646 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1647 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1648 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1649
1650 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);
1651 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1652 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1653 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1654
1655 /* LO calibration setting */
1656 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1657
1658 /* enter IQK mode */
1659 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1660
1661 /* One shot, path A LOK & IQK */
1662 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1663 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1664
1665 mdelay(IQK_DELAY_TIME);
1666
1667 /* leave IQK mode */
1668 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1669
1670 /* Check failed */
1671 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1672 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1673 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1674
1675 if (!(reg_eac & BIT(28)) &&
1676 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1677 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1678 result |= 0x01;
1679 else /* if Tx not OK, ignore Rx */
1680 return result;
1681
1682 /* Allen 20131125 */
1683 tmp = (reg_e9c & 0x03FF0000) >> 16;
1684 if ((tmp & 0x200) > 0)
1685 tmp = 0x400 - tmp;
1686
1687 if (!(reg_eac & BIT(28)) &&
1688 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1689 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1690 (tmp < 0xf))
1691 result |= 0x01;
1692 else /* if Tx not OK, ignore Rx */
1693 return result;
1694
1695 u32tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) |
1696 ((reg_e9c & 0x3FF0000) >> 16);
1697 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);
1698
1699 /* 1 RX IQK */
1700 /* modify RXIQK mode table */
1701 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1702 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1703 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1704 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1705 /* LAN2 on, PA off for Dcut */
1706 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77);
1707
1708 /* PA, PAD setting */
1709 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0xf80);
1710 rtl_set_rfreg(hw, RF90_PATH_A, 0x55, RFREG_OFFSET_MASK, 0x4021f);
1711
1712 /* IQK setting */
1713 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1714
1715 /* path-A IQK setting */
1716 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1717 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1718 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1719 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1720
1721 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1722 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);
1723 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1724 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1725
1726 /* LO calibration setting */
1727 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
1728
1729 /* enter IQK mode */
1730 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1731
1732 /* One shot, path A LOK & IQK */
1733 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1734 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1735
1736 mdelay(IQK_DELAY_TIME);
1737
1738 /* leave IQK mode */
1739 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1740
1741 /* Check failed */
1742 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1743 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1744
1745 /* leave IQK mode */
1746 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1747 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x780);
1748
1749 /* Allen 20131125 */
1750 tmp = (reg_eac & 0x03FF0000) >> 16;
1751 if ((tmp & 0x200) > 0)
1752 tmp = 0x400 - tmp;
1753 /* if Tx is OK, check whether Rx is OK */
1754 if (!(reg_eac & BIT(27)) &&
1755 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1756 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1757 result |= 0x02;
1758 else if (!(reg_eac & BIT(27)) &&
1759 (((reg_ea4 & 0x03FF0000) >> 16) < 0x110) &&
1760 (((reg_ea4 & 0x03FF0000) >> 16) > 0xf0) &&
1761 (tmp < 0xf))
1762 result |= 0x02;
1763
1764 return result;
1765}
1766
1767static u8 _rtl8723be_phy_path_b_iqk(struct ieee80211_hw *hw)
1768{
1769 u32 reg_eac, reg_e94, reg_e9c, tmp;
1770 u8 result = 0x00;
1771
1772 /* leave IQK mode */
1773 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1774 /* switch to path B */
1775 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
1776
1777 /* enable path B PA in TXIQK mode */
1778 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020);
1779 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x40fc1);
1780
1781 /* 1 Tx IQK */
1782 /* IQK setting */
1783 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1784 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1785 /* path-A IQK setting */
1786 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1787 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1788 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1789 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1790
1791 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);
1792 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1793 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1794 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1795
1796 /* LO calibration setting */
1797 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1798
1799 /* enter IQK mode */
1800 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1801
1802 /* One shot, path B LOK & IQK */
1803 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1804 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1805
1806 mdelay(IQK_DELAY_TIME);
1807
1808 /* leave IQK mode */
1809 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1810
1811 /* Check failed */
1812 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1813 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1814 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1815
1816 if (!(reg_eac & BIT(28)) &&
1817 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1818 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1819 result |= 0x01;
1820 else
1821 return result;
1822
1823 /* Allen 20131125 */
1824 tmp = (reg_e9c & 0x03FF0000) >> 16;
1825 if ((tmp & 0x200) > 0)
1826 tmp = 0x400 - tmp;
1827
1828 if (!(reg_eac & BIT(28)) &&
1829 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1830 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1831 (tmp < 0xf))
1832 result |= 0x01;
1833 else
1834 return result;
1835
1836 return result;
1837}
1838
1839/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1840static u8 _rtl8723be_phy_path_b_rx_iqk(struct ieee80211_hw *hw)
1841{
1842 u32 reg_e94, reg_e9c, reg_ea4, reg_eac, u32tmp, tmp;
1843 u8 result = 0x00;
1844
1845 /* leave IQK mode */
1846 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1847 /* switch to path B */
1848 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
1849
1850 /* 1 Get TXIMR setting */
1851 /* modify RXIQK mode table */
1852 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1853 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1854 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1855 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ff7);
1856
1857 /* open PA S1 & SMIXER */
1858 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020);
1859 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fed);
1860
1861 /* IQK setting */
1862 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1863 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1864
1865 /* path-B IQK setting */
1866 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1867 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1868 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1869 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1870
1871 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);
1872 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1873 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1874 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1875
1876 /* LO calibration setting */
1877 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1878 /* enter IQK mode */
1879 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1880
1881 /* One shot, path B TXIQK @ RXIQK */
1882 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1883 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1884
1885 mdelay(IQK_DELAY_TIME);
1886
1887 /* leave IQK mode */
1888 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1889 /* Check failed */
1890 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1891 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1892 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1893
1894 if (!(reg_eac & BIT(28)) &&
1895 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1896 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1897 result |= 0x01;
1898 else /* if Tx not OK, ignore Rx */
1899 return result;
1500 1900
1501 u8 final_candidate[2] = { 0xFF, 0xFF }; 1901 /* Allen 20131125 */
1502 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version); 1902 tmp = (reg_e9c & 0x03FF0000) >> 16;
1903 if ((tmp & 0x200) > 0)
1904 tmp = 0x400 - tmp;
1503 1905
1504 if (is2t) 1906 if (!(reg_eac & BIT(28)) &&
1505 bound = 8; 1907 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1908 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1909 (tmp < 0xf))
1910 result |= 0x01;
1911 else
1912 return result;
1913
1914 u32tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) |
1915 ((reg_e9c & 0x3FF0000) >> 16);
1916 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);
1917
1918 /* 1 RX IQK */
1919
1920 /* <20121009, Kordan> RF Mode = 3 */
1921 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1922 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1923 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1924 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1925 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77);
1926 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x0);
1927
1928 /* open PA S1 & close SMIXER */
1929 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020);
1930 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fbd);
1931
1932 /* IQK setting */
1933 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1934
1935 /* path-B IQK setting */
1936 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1937 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1938 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1939 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1940
1941 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1942 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);
1943 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1944 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1945
1946 /* LO calibration setting */
1947 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
1948 /* enter IQK mode */
1949 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1950
1951 /* One shot, path B LOK & IQK */
1952 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1953 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1954
1955 mdelay(IQK_DELAY_TIME);
1956
1957 /* leave IQK mode */
1958 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1959 /* Check failed */
1960 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1961 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1962
1963 /* Allen 20131125 */
1964 tmp = (reg_eac & 0x03FF0000) >> 16;
1965 if ((tmp & 0x200) > 0)
1966 tmp = 0x400 - tmp;
1967
1968 /* if Tx is OK, check whether Rx is OK */
1969 if (!(reg_eac & BIT(27)) &&
1970 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1971 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1972 result |= 0x02;
1973 else if (!(reg_eac & BIT(27)) &&
1974 (((reg_ea4 & 0x03FF0000) >> 16) < 0x110) &&
1975 (((reg_ea4 & 0x03FF0000) >> 16) > 0xf0) &&
1976 (tmp < 0xf))
1977 result |= 0x02;
1506 else 1978 else
1507 bound = 4; 1979 return result;
1980
1981 return result;
1982}
1983
1984static void _rtl8723be_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1985 bool b_iqk_ok,
1986 long result[][8],
1987 u8 final_candidate,
1988 bool btxonly)
1989{
1990 u32 oldval_1, x, tx1_a, reg;
1991 long y, tx1_c;
1992
1993 if (final_candidate == 0xFF) {
1994 return;
1995 } else if (b_iqk_ok) {
1996 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1997 MASKDWORD) >> 22) & 0x3FF;
1998 x = result[final_candidate][4];
1999 if ((x & 0x00000200) != 0)
2000 x = x | 0xFFFFFC00;
2001 tx1_a = (x * oldval_1) >> 8;
2002 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2003 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
2004 ((x * oldval_1 >> 7) & 0x1));
2005 y = result[final_candidate][5];
2006 if ((y & 0x00000200) != 0)
2007 y = y | 0xFFFFFC00;
2008 tx1_c = (y * oldval_1) >> 8;
2009 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2010 ((tx1_c & 0x3C0) >> 6));
2011 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2012 (tx1_c & 0x3F));
2013 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
2014 ((y * oldval_1 >> 7) & 0x1));
2015 if (btxonly)
2016 return;
2017 reg = result[final_candidate][6];
2018 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2019 reg = result[final_candidate][7] & 0x3F;
2020 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2021 reg = (result[final_candidate][7] >> 6) & 0xF;
2022 /* rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); */
2023 }
2024}
2025
2026static bool _rtl8723be_phy_simularity_compare(struct ieee80211_hw *hw,
2027 long result[][8], u8 c1, u8 c2)
2028{
2029 u32 i, j, diff, simularity_bitmap, bound = 0;
2030
2031 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2032 bool bresult = true; /* is2t = true*/
2033 s32 tmp1 = 0, tmp2 = 0;
2034
2035 bound = 8;
1508 2036
1509 simularity_bitmap = 0; 2037 simularity_bitmap = 0;
1510 2038
1511 for (i = 0; i < bound; i++) { 2039 for (i = 0; i < bound; i++) {
1512 diff = (result[c1][i] > result[c2][i]) ? 2040 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
1513 (result[c1][i] - result[c2][i]) : 2041 if ((result[c1][i] & 0x00000200) != 0)
1514 (result[c2][i] - result[c1][i]); 2042 tmp1 = result[c1][i] | 0xFFFFFC00;
2043 else
2044 tmp1 = result[c1][i];
2045
2046 if ((result[c2][i] & 0x00000200) != 0)
2047 tmp2 = result[c2][i] | 0xFFFFFC00;
2048 else
2049 tmp2 = result[c2][i];
2050 } else {
2051 tmp1 = result[c1][i];
2052 tmp2 = result[c2][i];
2053 }
2054
2055 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1515 2056
1516 if (diff > MAX_TOLERANCE) { 2057 if (diff > MAX_TOLERANCE) {
1517 if ((i == 2 || i == 6) && !simularity_bitmap) { 2058 if ((i == 2 || i == 6) && !simularity_bitmap) {
@@ -1521,9 +2062,8 @@ static bool phy_similarity_cmp(struct ieee80211_hw *hw, long result[][8],
1521 final_candidate[(i / 4)] = c1; 2062 final_candidate[(i / 4)] = c1;
1522 else 2063 else
1523 simularity_bitmap |= (1 << i); 2064 simularity_bitmap |= (1 << i);
1524 } else { 2065 } else
1525 simularity_bitmap |= (1 << i); 2066 simularity_bitmap |= (1 << i);
1526 }
1527 } 2067 }
1528 } 2068 }
1529 2069
@@ -1537,15 +2077,23 @@ static bool phy_similarity_cmp(struct ieee80211_hw *hw, long result[][8],
1537 } 2077 }
1538 } 2078 }
1539 return bresult; 2079 return bresult;
1540 } else if (!(simularity_bitmap & 0x0F)) {
1541 for (i = 0; i < 4; i++)
1542 result[3][i] = result[c1][i];
1543 return false;
1544 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1545 for (i = 4; i < 8; i++)
1546 result[3][i] = result[c1][i];
1547 return false;
1548 } else { 2080 } else {
2081 if (!(simularity_bitmap & 0x03)) { /* path A TX OK */
2082 for (i = 0; i < 2; i++)
2083 result[3][i] = result[c1][i];
2084 }
2085 if (!(simularity_bitmap & 0x0c)) { /* path A RX OK */
2086 for (i = 2; i < 4; i++)
2087 result[3][i] = result[c1][i];
2088 }
2089 if (!(simularity_bitmap & 0x30)) { /* path B TX OK */
2090 for (i = 4; i < 6; i++)
2091 result[3][i] = result[c1][i];
2092 }
2093 if (!(simularity_bitmap & 0xc0)) { /* path B RX OK */
2094 for (i = 6; i < 8; i++)
2095 result[3][i] = result[c1][i];
2096 }
1549 return false; 2097 return false;
1550 } 2098 }
1551} 2099}
@@ -1554,9 +2102,9 @@ static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
1554 long result[][8], u8 t, bool is2t) 2102 long result[][8], u8 t, bool is2t)
1555{ 2103{
1556 struct rtl_priv *rtlpriv = rtl_priv(hw); 2104 struct rtl_priv *rtlpriv = rtl_priv(hw);
1557 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2105 struct rtl_phy *rtlphy = &rtlpriv->phy;
1558 u32 i; 2106 u32 i;
1559 u8 patha_ok; 2107 u8 patha_ok, pathb_ok;
1560 u32 adda_reg[IQK_ADDA_REG_NUM] = { 2108 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1561 0x85c, 0xe6c, 0xe70, 0xe74, 2109 0x85c, 0xe6c, 0xe70, 0xe74,
1562 0xe78, 0xe7c, 0xe80, 0xe84, 2110 0xe78, 0xe7c, 0xe80, 0xe84,
@@ -1571,10 +2119,12 @@ static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
1571 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR, 2119 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
1572 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, 2120 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
1573 0x870, 0x860, 2121 0x870, 0x860,
1574 0x864, 0x800 2122 0x864, 0xa04
1575 }; 2123 };
1576 const u32 retrycount = 2; 2124 const u32 retrycount = 2;
1577 u32 path_sel_bb, path_sel_rf; 2125
2126 u32 path_sel_bb;/* path_sel_rf */
2127
1578 u8 tmp_reg_c50, tmp_reg_c58; 2128 u8 tmp_reg_c50, tmp_reg_c58;
1579 2129
1580 tmp_reg_c50 = rtl_get_bbreg(hw, 0xc50, MASKBYTE0); 2130 tmp_reg_c50 = rtl_get_bbreg(hw, 0xc50, MASKBYTE0);
@@ -1591,62 +2141,97 @@ static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
1591 } 2141 }
1592 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t); 2142 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t);
1593 if (t == 0) { 2143 if (t == 0) {
1594 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 2144 rtlphy->rfpi_enable = (u8)rtl_get_bbreg(hw,
1595 RFPGA0_XA_HSSIPARAMETER1, 2145 RFPGA0_XA_HSSIPARAMETER1,
1596 BIT(8)); 2146 BIT(8));
1597 } 2147 }
1598 if (!rtlphy->rfpi_enable)
1599 rtl8723_phy_pi_mode_switch(hw, true);
1600 2148
1601 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); 2149 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);
1602 path_sel_rf = rtl_get_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff);
1603 2150
2151 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg,
2152 rtlphy->iqk_mac_backup);
1604 /*BB Setting*/ 2153 /*BB Setting*/
1605 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); 2154 rtl_set_bbreg(hw, 0xa04, 0x0f000000, 0xf);
1606 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); 2155 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1607 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); 2156 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1608 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); 2157 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1609 2158
1610 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); 2159 /* path A TX IQK */
1611 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01);
1612 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00);
1613 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00);
1614
1615 if (is2t)
1616 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASKDWORD, 0x10000);
1617 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg,
1618 rtlphy->iqk_mac_backup);
1619 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1620
1621 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1622 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1623 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800);
1624 for (i = 0; i < retrycount; i++) { 2160 for (i = 0; i < retrycount; i++) {
1625 patha_ok = _rtl8723be_phy_path_a_iqk(hw, is2t); 2161 patha_ok = _rtl8723be_phy_path_a_iqk(hw);
1626 if (patha_ok == 0x01) { 2162 if (patha_ok == 0x01) {
1627 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2163 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1628 "Path A Tx IQK Success!!\n"); 2164 "Path A Tx IQK Success!!\n");
1629 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 2165 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1630 0x3FF0000) >> 16; 2166 0x3FF0000) >> 16;
1631 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 2167 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1632 0x3FF0000) >> 16; 2168 0x3FF0000) >> 16;
1633 break; 2169 break;
2170 } else {
2171 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2172 "Path A Tx IQK Fail!!\n");
1634 } 2173 }
1635 } 2174 }
1636 2175 /* path A RX IQK */
1637 if (0 == patha_ok) 2176 for (i = 0; i < retrycount; i++) {
2177 patha_ok = _rtl8723be_phy_path_a_rx_iqk(hw);
2178 if (patha_ok == 0x03) {
2179 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2180 "Path A Rx IQK Success!!\n");
2181 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2182 0x3FF0000) >> 16;
2183 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2184 0x3FF0000) >> 16;
2185 break;
2186 }
1638 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2187 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1639 "Path A IQK Success!!\n"); 2188 "Path A Rx IQK Fail!!\n");
2189 }
2190
2191 if (0x00 == patha_ok)
2192 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Path A IQK Fail!!\n");
2193
1640 if (is2t) { 2194 if (is2t) {
1641 rtl8723_phy_path_a_standby(hw); 2195 /* path B TX IQK */
1642 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t); 2196 for (i = 0; i < retrycount; i++) {
2197 pathb_ok = _rtl8723be_phy_path_b_iqk(hw);
2198 if (pathb_ok == 0x01) {
2199 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2200 "Path B Tx IQK Success!!\n");
2201 result[t][4] = (rtl_get_bbreg(hw, 0xe94,
2202 MASKDWORD) &
2203 0x3FF0000) >> 16;
2204 result[t][5] = (rtl_get_bbreg(hw, 0xe9c,
2205 MASKDWORD) &
2206 0x3FF0000) >> 16;
2207 break;
2208 }
2209 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2210 "Path B Tx IQK Fail!!\n");
2211 }
2212 /* path B RX IQK */
2213 for (i = 0; i < retrycount; i++) {
2214 pathb_ok = _rtl8723be_phy_path_b_rx_iqk(hw);
2215 if (pathb_ok == 0x03) {
2216 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2217 "Path B Rx IQK Success!!\n");
2218 result[t][6] = (rtl_get_bbreg(hw, 0xea4,
2219 MASKDWORD) &
2220 0x3FF0000) >> 16;
2221 result[t][7] = (rtl_get_bbreg(hw, 0xeac,
2222 MASKDWORD) &
2223 0x3FF0000) >> 16;
2224 break;
2225 }
2226 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2227 "Path B Rx IQK Fail!!\n");
2228 }
1643 } 2229 }
1644 2230
1645 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 2231 /* Back to BB mode, load original value */
2232 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);
1646 2233
1647 if (t != 0) { 2234 if (t != 0) {
1648 if (!rtlphy->rfpi_enable)
1649 rtl8723_phy_pi_mode_switch(hw, false);
1650 rtl8723_phy_reload_adda_registers(hw, adda_reg, 2235 rtl8723_phy_reload_adda_registers(hw, adda_reg,
1651 rtlphy->adda_backup, 16); 2236 rtlphy->adda_backup, 16);
1652 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg, 2237 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg,
@@ -1656,7 +2241,7 @@ static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
1656 IQK_BB_REG_NUM); 2241 IQK_BB_REG_NUM);
1657 2242
1658 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); 2243 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
1659 rtl_set_rfreg(hw, RF90_PATH_B, 0xb0, 0xfffff, path_sel_rf); 2244 /*rtl_set_rfreg(hw, RF90_PATH_B, 0xb0, 0xfffff, path_sel_rf);*/
1660 2245
1661 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); 2246 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
1662 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_reg_c50); 2247 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_reg_c50);
@@ -1670,11 +2255,33 @@ static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
1670 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "8723be IQK Finish!!\n"); 2255 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "8723be IQK Finish!!\n");
1671} 2256}
1672 2257
2258static u8 _get_right_chnl_place_for_iqk(u8 chnl)
2259{
2260 u8 channel_all[TARGET_CHNL_NUM_2G_5G] = {
2261 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2262 13, 14, 36, 38, 40, 42, 44, 46,
2263 48, 50, 52, 54, 56, 58, 60, 62, 64,
2264 100, 102, 104, 106, 108, 110,
2265 112, 114, 116, 118, 120, 122,
2266 124, 126, 128, 130, 132, 134, 136,
2267 138, 140, 149, 151, 153, 155, 157,
2268 159, 161, 163, 165};
2269 u8 place = chnl;
2270
2271 if (chnl > 14) {
2272 for (place = 14; place < sizeof(channel_all); place++) {
2273 if (channel_all[place] == chnl)
2274 return place - 13;
2275 }
2276 }
2277 return 0;
2278}
2279
1673static void _rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2280static void _rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1674{ 2281{
1675 struct rtl_priv *rtlpriv = rtl_priv(hw);
1676 u8 tmpreg; 2282 u8 tmpreg;
1677 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 2283 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
2284 struct rtl_priv *rtlpriv = rtl_priv(hw);
1678 2285
1679 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 2286 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1680 2287
@@ -1702,7 +2309,10 @@ static void _rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1702 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdfbe0); 2309 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdfbe0);
1703 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, 0x8c0a); 2310 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, 0x8c0a);
1704 2311
1705 mdelay(100); 2312 /* In order not to disturb BT music when wifi init.(1ant NIC only) */
2313 /*mdelay(100);*/
2314 /* In order not to disturb BT music when wifi init.(1ant NIC only) */
2315 mdelay(50);
1706 2316
1707 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdffe0); 2317 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdffe0);
1708 2318
@@ -1716,68 +2326,34 @@ static void _rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1716 } else { 2326 } else {
1717 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2327 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1718 } 2328 }
1719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 2329RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
2330
1720} 2331}
1721 2332
1722static void _rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, 2333static void _rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1723 bool bmain, bool is2t) 2334 bool bmain, bool is2t)
1724{ 2335{
1725 struct rtl_priv *rtlpriv = rtl_priv(hw); 2336 struct rtl_priv *rtlpriv = rtl_priv(hw);
1726 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1727 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1728 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 2337 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1729 2338
1730 if (is_hal_stop(rtlhal)) { 2339 if (bmain) /* left antenna */
1731 u8 u1btmp; 2340 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1);
1732 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0); 2341 else
1733 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7)); 2342 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2);
1734 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1735 }
1736 if (is2t) {
1737 if (bmain)
1738 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1739 BIT(5) | BIT(6), 0x1);
1740 else
1741 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1742 BIT(5) | BIT(6), 0x2);
1743 } else {
1744 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
1745 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
1746
1747 /* We use the RF definition of MAIN and AUX,
1748 * left antenna and right antenna repectively.
1749 * Default output at AUX.
1750 */
1751 if (bmain) {
1752 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1753 BIT(14) | BIT(13) | BIT(12), 0);
1754 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1755 BIT(5) | BIT(4) | BIT(3), 0);
1756 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1757 rtl_set_bbreg(hw, CONFIG_RAM64X16, BIT(31), 0);
1758 } else {
1759 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1760 BIT(14) | BIT(13) | BIT(12), 1);
1761 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1762 BIT(5) | BIT(4) | BIT(3), 1);
1763 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1764 rtl_set_bbreg(hw, CONFIG_RAM64X16, BIT(31), 1);
1765 }
1766 }
1767} 2343}
1768 2344
1769#undef IQK_ADDA_REG_NUM 2345#undef IQK_ADDA_REG_NUM
1770#undef IQK_DELAY_TIME 2346#undef IQK_DELAY_TIME
1771 2347/* IQK is merge from Merge Temp */
1772void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery) 2348void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1773{ 2349{
1774 struct rtl_priv *rtlpriv = rtl_priv(hw); 2350 struct rtl_priv *rtlpriv = rtl_priv(hw);
1775 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2351 struct rtl_phy *rtlphy = &rtlpriv->phy;
1776 long result[4][8]; 2352 long result[4][8];
1777 u8 i, final_candidate; 2353 u8 i, final_candidate, idx;
1778 bool patha_ok, pathb_ok; 2354 bool b_patha_ok, b_pathb_ok;
1779 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, 2355 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4;
1780 reg_ecc, reg_tmp = 0; 2356 long reg_ecc, reg_tmp = 0;
1781 bool is12simular, is13simular, is23simular; 2357 bool is12simular, is13simular, is23simular;
1782 u32 iqk_bb_reg[9] = { 2358 u32 iqk_bb_reg[9] = {
1783 ROFDM0_XARXIQIMBALANCE, 2359 ROFDM0_XARXIQIMBALANCE,
@@ -1790,12 +2366,23 @@ void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1790 ROFDM0_XDTXAFE, 2366 ROFDM0_XDTXAFE,
1791 ROFDM0_RXIQEXTANTA 2367 ROFDM0_RXIQEXTANTA
1792 }; 2368 };
2369 u32 path_sel_bb = 0; /* path_sel_rf = 0 */
1793 2370
1794 if (recovery) { 2371 if (rtlphy->lck_inprogress)
2372 return;
2373
2374 spin_lock(&rtlpriv->locks.iqk_lock);
2375 rtlphy->lck_inprogress = true;
2376 spin_unlock(&rtlpriv->locks.iqk_lock);
2377
2378 if (b_recovery) {
1795 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg, 2379 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg,
1796 rtlphy->iqk_bb_backup, 9); 2380 rtlphy->iqk_bb_backup, 9);
1797 return; 2381 return;
1798 } 2382 }
2383 /* Save RF Path */
2384 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);
2385 /* path_sel_rf = rtl_get_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff); */
1799 2386
1800 for (i = 0; i < 8; i++) { 2387 for (i = 0; i < 8; i++) {
1801 result[0][i] = 0; 2388 result[0][i] = 0;
@@ -1804,30 +2391,33 @@ void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1804 result[3][i] = 0; 2391 result[3][i] = 0;
1805 } 2392 }
1806 final_candidate = 0xff; 2393 final_candidate = 0xff;
1807 patha_ok = false; 2394 b_patha_ok = false;
1808 pathb_ok = false; 2395 b_pathb_ok = false;
1809 is12simular = false; 2396 is12simular = false;
1810 is23simular = false; 2397 is23simular = false;
1811 is13simular = false; 2398 is13simular = false;
1812 for (i = 0; i < 3; i++) { 2399 for (i = 0; i < 3; i++) {
1813 if (get_rf_type(rtlphy) == RF_2T2R) 2400 _rtl8723be_phy_iq_calibrate(hw, result, i, true);
1814 _rtl8723be_phy_iq_calibrate(hw, result, i, true);
1815 else
1816 _rtl8723be_phy_iq_calibrate(hw, result, i, false);
1817 if (i == 1) { 2401 if (i == 1) {
1818 is12simular = phy_similarity_cmp(hw, result, 0, 1); 2402 is12simular = _rtl8723be_phy_simularity_compare(hw,
2403 result,
2404 0, 1);
1819 if (is12simular) { 2405 if (is12simular) {
1820 final_candidate = 0; 2406 final_candidate = 0;
1821 break; 2407 break;
1822 } 2408 }
1823 } 2409 }
1824 if (i == 2) { 2410 if (i == 2) {
1825 is13simular = phy_similarity_cmp(hw, result, 0, 2); 2411 is13simular = _rtl8723be_phy_simularity_compare(hw,
2412 result,
2413 0, 2);
1826 if (is13simular) { 2414 if (is13simular) {
1827 final_candidate = 0; 2415 final_candidate = 0;
1828 break; 2416 break;
1829 } 2417 }
1830 is23simular = phy_similarity_cmp(hw, result, 1, 2); 2418 is23simular = _rtl8723be_phy_simularity_compare(hw,
2419 result,
2420 1, 2);
1831 if (is23simular) { 2421 if (is23simular) {
1832 final_candidate = 1; 2422 final_candidate = 1;
1833 } else { 2423 } else {
@@ -1864,32 +2454,48 @@ void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1864 rtlphy->reg_ebc = reg_ebc; 2454 rtlphy->reg_ebc = reg_ebc;
1865 reg_ec4 = result[final_candidate][6]; 2455 reg_ec4 = result[final_candidate][6];
1866 reg_ecc = result[final_candidate][7]; 2456 reg_ecc = result[final_candidate][7];
1867 patha_ok = true; 2457 b_patha_ok = true;
1868 pathb_ok = true; 2458 b_pathb_ok = true;
1869 } else { 2459 } else {
1870 rtlphy->reg_e94 = 0x100; 2460 rtlphy->reg_e94 = 0x100;
1871 rtlphy->reg_eb4 = 0x100; 2461 rtlphy->reg_eb4 = 0x100;
1872 rtlphy->reg_e9c = 0x0; 2462 rtlphy->reg_e9c = 0x0;
1873 rtlphy->reg_ebc = 0x0; 2463 rtlphy->reg_ebc = 0x0;
1874 } 2464 }
1875 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ 2465 if (reg_e94 != 0)
1876 rtl8723_phy_path_a_fill_iqk_matrix(hw, patha_ok, result, 2466 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1877 final_candidate, 2467 final_candidate,
1878 (reg_ea4 == 0)); 2468 (reg_ea4 == 0));
1879 if (final_candidate != 0xFF) { 2469 if (reg_eb4 != 0)
2470 _rtl8723be_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result,
2471 final_candidate,
2472 (reg_ec4 == 0));
2473
2474 idx = _get_right_chnl_place_for_iqk(rtlphy->current_channel);
2475
2476 if (final_candidate < 4) {
1880 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2477 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
1881 rtlphy->iqk_matrix[0].value[0][i] = 2478 rtlphy->iqk_matrix[idx].value[0][i] =
1882 result[final_candidate][i]; 2479 result[final_candidate][i];
1883 rtlphy->iqk_matrix[0].iqk_done = true; 2480 rtlphy->iqk_matrix[idx].iqk_done = true;
2481
1884 } 2482 }
1885 rtl8723_save_adda_registers(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 9); 2483 rtl8723_save_adda_registers(hw, iqk_bb_reg,
2484 rtlphy->iqk_bb_backup, 9);
2485
2486 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
2487 /* rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff, path_sel_rf); */
2488
2489 spin_lock(&rtlpriv->locks.iqk_lock);
2490 rtlphy->lck_inprogress = false;
2491 spin_unlock(&rtlpriv->locks.iqk_lock);
1886} 2492}
1887 2493
1888void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw) 2494void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw)
1889{ 2495{
1890 struct rtl_priv *rtlpriv = rtl_priv(hw); 2496 struct rtl_priv *rtlpriv = rtl_priv(hw);
1891 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2497 struct rtl_phy *rtlphy = &rtlpriv->phy;
1892 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2498 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
1893 u32 timeout = 2000, timecount = 0; 2499 u32 timeout = 2000, timecount = 0;
1894 2500
1895 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2501 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
@@ -1898,68 +2504,25 @@ void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw)
1898 } 2504 }
1899 2505
1900 rtlphy->lck_inprogress = true; 2506 rtlphy->lck_inprogress = true;
1901 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 2507 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1902 "LCK:Start!!! currentband %x delay %d ms\n", 2508 "LCK:Start!!! currentband %x delay %d ms\n",
1903 rtlhal->current_bandtype, timecount); 2509 rtlhal->current_bandtype, timecount);
1904 2510
1905 _rtl8723be_phy_lc_calibrate(hw, false); 2511 _rtl8723be_phy_lc_calibrate(hw, false);
1906 2512
1907 rtlphy->lck_inprogress = false; 2513 rtlphy->lck_inprogress = false;
1908} 2514}
1909 2515
1910void rtl23b_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
1911{
1912 struct rtl_priv *rtlpriv = rtl_priv(hw);
1913 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1914
1915 if (rtlphy->apk_done)
1916 return;
1917
1918 return;
1919}
1920
1921void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 2516void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1922{ 2517{
1923 _rtl8723be_phy_set_rfpath_switch(hw, bmain, false); 2518 _rtl8723be_phy_set_rfpath_switch(hw, bmain, true);
1924}
1925
1926static void rtl8723be_phy_set_io(struct ieee80211_hw *hw)
1927{
1928 struct rtl_priv *rtlpriv = rtl_priv(hw);
1929 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1930
1931 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1932 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1933 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1934 switch (rtlphy->current_io_type) {
1935 case IO_CMD_RESUME_DM_BY_SCAN:
1936 rtlpriv->dm_digtable.cur_igvalue =
1937 rtlphy->initgain_backup.xaagccore1;
1938 /*rtl92c_dm_write_dig(hw);*/
1939 rtl8723be_phy_set_txpower_level(hw, rtlphy->current_channel);
1940 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
1941 break;
1942 case IO_CMD_PAUSE_DM_BY_SCAN:
1943 rtlphy->initgain_backup.xaagccore1 =
1944 rtlpriv->dm_digtable.cur_igvalue;
1945 rtlpriv->dm_digtable.cur_igvalue = 0x17;
1946 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
1947 break;
1948 default:
1949 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1950 "switch case not process\n");
1951 break;
1952 }
1953 rtlphy->set_io_inprogress = false;
1954 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1955 "(%#x)\n", rtlphy->current_io_type);
1956} 2519}
1957 2520
1958bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 2521bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1959{ 2522{
1960 struct rtl_priv *rtlpriv = rtl_priv(hw); 2523 struct rtl_priv *rtlpriv = rtl_priv(hw);
1961 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2524 struct rtl_phy *rtlphy = &rtlpriv->phy;
1962 bool postprocessing = false; 2525 bool b_postprocessing = false;
1963 2526
1964 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2527 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1965 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 2528 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
@@ -1969,20 +2532,20 @@ bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1969 case IO_CMD_RESUME_DM_BY_SCAN: 2532 case IO_CMD_RESUME_DM_BY_SCAN:
1970 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2533 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1971 "[IO CMD] Resume DM after scan.\n"); 2534 "[IO CMD] Resume DM after scan.\n");
1972 postprocessing = true; 2535 b_postprocessing = true;
1973 break; 2536 break;
1974 case IO_CMD_PAUSE_DM_BY_SCAN: 2537 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1975 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2538 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1976 "[IO CMD] Pause DM before scan.\n"); 2539 "[IO CMD] Pause DM before scan.\n");
1977 postprocessing = true; 2540 b_postprocessing = true;
1978 break; 2541 break;
1979 default: 2542 default:
1980 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2543 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1981 "switch case not process\n"); 2544 "switch case not process\n");
1982 break; 2545 break;
1983 } 2546 }
1984 } while (false); 2547 } while (false);
1985 if (postprocessing && !rtlphy->set_io_inprogress) { 2548 if (b_postprocessing && !rtlphy->set_io_inprogress) {
1986 rtlphy->set_io_inprogress = true; 2549 rtlphy->set_io_inprogress = true;
1987 rtlphy->current_io_type = iotype; 2550 rtlphy->current_io_type = iotype;
1988 } else { 2551 } else {
@@ -1993,6 +2556,37 @@ bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1993 return true; 2556 return true;
1994} 2557}
1995 2558
2559static void rtl8723be_phy_set_io(struct ieee80211_hw *hw)
2560{
2561 struct rtl_priv *rtlpriv = rtl_priv(hw);
2562 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
2563 struct rtl_phy *rtlphy = &rtlpriv->phy;
2564
2565 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2566 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2567 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2568 switch (rtlphy->current_io_type) {
2569 case IO_CMD_RESUME_DM_BY_SCAN:
2570 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2571 /*rtl92c_dm_write_dig(hw);*/
2572 rtl8723be_phy_set_txpower_level(hw, rtlphy->current_channel);
2573 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
2574 break;
2575 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2576 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
2577 dm_digtable->cur_igvalue = 0x17;
2578 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
2579 break;
2580 default:
2581 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2582 "switch case not process\n");
2583 break;
2584 }
2585 rtlphy->set_io_inprogress = false;
2586 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2587 "(%#x)\n", rtlphy->current_io_type);
2588}
2589
1996static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw) 2590static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw)
1997{ 2591{
1998 struct rtl_priv *rtlpriv = rtl_priv(hw); 2592 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -2028,15 +2622,15 @@ static bool _rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
2028 switch (rfpwr_state) { 2622 switch (rfpwr_state) {
2029 case ERFON: 2623 case ERFON:
2030 if ((ppsc->rfpwr_state == ERFOFF) && 2624 if ((ppsc->rfpwr_state == ERFOFF) &&
2031 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2625 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2032 bool rtstatus; 2626 bool rtstatus;
2033 u32 initialize_count = 0; 2627 u32 initializecount = 0;
2034 do { 2628 do {
2035 initialize_count++; 2629 initializecount++;
2036 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2630 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2037 "IPS Set eRf nic enable\n"); 2631 "IPS Set eRf nic enable\n");
2038 rtstatus = rtl_ps_enable_nic(hw); 2632 rtstatus = rtl_ps_enable_nic(hw);
2039 } while (!rtstatus && (initialize_count < 10)); 2633 } while (!rtstatus && (initializecount < 10));
2040 RT_CLEAR_PS_LEVEL(ppsc, 2634 RT_CLEAR_PS_LEVEL(ppsc,
2041 RT_RF_OFF_LEVL_HALT_NIC); 2635 RT_RF_OFF_LEVL_HALT_NIC);
2042 } else { 2636 } else {
@@ -2051,28 +2645,33 @@ static bool _rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
2051 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); 2645 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
2052 else 2646 else
2053 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); 2647 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
2648
2054 break; 2649 break;
2650
2055 case ERFOFF: 2651 case ERFOFF:
2056 for (queue_id = 0, i = 0; 2652 for (queue_id = 0, i = 0;
2057 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2653 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2058 ring = &pcipriv->dev.tx_ring[queue_id]; 2654 ring = &pcipriv->dev.tx_ring[queue_id];
2059 if (skb_queue_len(&ring->queue) == 0) { 2655 /* Don't check BEACON Q.
2656 * BEACON Q is always not empty,
2657 * because '_rtl8723be_cmd_send_packet'
2658 */
2659 if (queue_id == BEACON_QUEUE ||
2660 skb_queue_len(&ring->queue) == 0) {
2060 queue_id++; 2661 queue_id++;
2061 continue; 2662 continue;
2062 } else { 2663 } else {
2063 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2664 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2064 "eRf Off/Sleep: %d times " 2665 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2065 "TcbBusyQueue[%d] =%d before " 2666 (i + 1), queue_id,
2066 "doze!\n", (i + 1), queue_id, 2667 skb_queue_len(&ring->queue));
2067 skb_queue_len(&ring->queue));
2068 2668
2069 udelay(10); 2669 udelay(10);
2070 i++; 2670 i++;
2071 } 2671 }
2072 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2672 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2073 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2673 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2074 "\n ERFSLEEP: %d times " 2674 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2075 "TcbBusyQueue[%d] = %d !\n",
2076 MAX_DOZE_WAITING_TIMES_9x, 2675 MAX_DOZE_WAITING_TIMES_9x,
2077 queue_id, 2676 queue_id,
2078 skb_queue_len(&ring->queue)); 2677 skb_queue_len(&ring->queue));
@@ -2095,6 +2694,7 @@ static bool _rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
2095 } 2694 }
2096 } 2695 }
2097 break; 2696 break;
2697
2098 case ERFSLEEP: 2698 case ERFSLEEP:
2099 if (ppsc->rfpwr_state == ERFOFF) 2699 if (ppsc->rfpwr_state == ERFOFF)
2100 break; 2700 break;
@@ -2106,21 +2706,19 @@ static bool _rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
2106 continue; 2706 continue;
2107 } else { 2707 } else {
2108 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2708 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2109 "eRf Off/Sleep: %d times " 2709 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2110 "TcbBusyQueue[%d] =%d before " 2710 (i + 1), queue_id,
2111 "doze!\n", (i + 1), queue_id, 2711 skb_queue_len(&ring->queue));
2112 skb_queue_len(&ring->queue));
2113 2712
2114 udelay(10); 2713 udelay(10);
2115 i++; 2714 i++;
2116 } 2715 }
2117 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2716 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2118 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2717 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2119 "\n ERFSLEEP: %d times " 2718 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2120 "TcbBusyQueue[%d] = %d !\n", 2719 MAX_DOZE_WAITING_TIMES_9x,
2121 MAX_DOZE_WAITING_TIMES_9x, 2720 queue_id,
2122 queue_id, 2721 skb_queue_len(&ring->queue));
2123 skb_queue_len(&ring->queue));
2124 break; 2722 break;
2125 } 2723 }
2126 } 2724 }
@@ -2131,8 +2729,9 @@ static bool _rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
2131 ppsc->last_sleep_jiffies = jiffies; 2729 ppsc->last_sleep_jiffies = jiffies;
2132 _rtl8723be_phy_set_rf_sleep(hw); 2730 _rtl8723be_phy_set_rf_sleep(hw);
2133 break; 2731 break;
2732
2134 default: 2733 default:
2135 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2734 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2136 "switch case not process\n"); 2735 "switch case not process\n");
2137 bresult = false; 2736 bresult = false;
2138 break; 2737 break;
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/phy.h b/drivers/net/wireless/rtlwifi/rtl8723be/phy.h
index 444ef95bb6af..6339738a0e33 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/phy.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/phy.h
@@ -26,22 +26,28 @@
26#ifndef __RTL8723BE_PHY_H__ 26#ifndef __RTL8723BE_PHY_H__
27#define __RTL8723BE_PHY_H__ 27#define __RTL8723BE_PHY_H__
28 28
29/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/ 29/* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence
30 * will be wrong.
31 */
30#define MAX_TX_COUNT 4 32#define MAX_TX_COUNT 4
31#define TX_1S 0 33#define TX_1S 0
32#define TX_2S 1 34#define TX_2S 1
35#define TX_3S 2
36#define TX_4S 3
33 37
34#define MAX_POWER_INDEX 0x3F 38#define MAX_POWER_INDEX 0x3F
35 39
36#define MAX_PRECMD_CNT 16 40#define MAX_PRECMD_CNT 16
37#define MAX_RFDEPENDCMD_CNT 16 41#define MAX_RFDEPENDCMD_CNT 16
38#define MAX_POSTCMD_CNT 16 42#define MAX_POSTCMD_CNT 16
39 43
40#define MAX_DOZE_WAITING_TIMES_9x 64 44#define MAX_DOZE_WAITING_TIMES_9x 64
41 45
42#define RT_CANNOT_IO(hw) false 46#define RT_CANNOT_IO(hw) false
43#define HIGHPOWER_RADIOA_ARRAYLEN 22 47#define HIGHPOWER_RADIOA_ARRAYLEN 22
44 48
49#define TARGET_CHNL_NUM_2G_5G 59
50
45#define IQK_ADDA_REG_NUM 16 51#define IQK_ADDA_REG_NUM 16
46#define IQK_BB_REG_NUM 9 52#define IQK_BB_REG_NUM 9
47#define MAX_TOLERANCE 5 53#define MAX_TOLERANCE 5
@@ -83,104 +89,19 @@
83 89
84#define RTL92C_MAX_PATH_NUM 2 90#define RTL92C_MAX_PATH_NUM 2
85 91
86enum hw90_block_e {
87 HW90_BLOCK_MAC = 0,
88 HW90_BLOCK_PHY0 = 1,
89 HW90_BLOCK_PHY1 = 2,
90 HW90_BLOCK_RF = 3,
91 HW90_BLOCK_MAXIMUM = 4,
92};
93
94enum baseband_config_type { 92enum baseband_config_type {
95 BASEBAND_CONFIG_PHY_REG = 0, 93 BASEBAND_CONFIG_PHY_REG = 0,
96 BASEBAND_CONFIG_AGC_TAB = 1, 94 BASEBAND_CONFIG_AGC_TAB = 1,
97}; 95};
98 96
99enum ra_offset_area { 97enum ant_div_type {
100 RA_OFFSET_LEGACY_OFDM1, 98 NO_ANTDIV = 0xFF,
101 RA_OFFSET_LEGACY_OFDM2, 99 CG_TRX_HW_ANTDIV = 0x01,
102 RA_OFFSET_HT_OFDM1, 100 CGCS_RX_HW_ANTDIV = 0x02,
103 RA_OFFSET_HT_OFDM2,
104 RA_OFFSET_HT_OFDM3,
105 RA_OFFSET_HT_OFDM4,
106 RA_OFFSET_HT_CCK,
107};
108
109enum antenna_path {
110 ANTENNA_NONE,
111 ANTENNA_D,
112 ANTENNA_C,
113 ANTENNA_CD,
114 ANTENNA_B,
115 ANTENNA_BD,
116 ANTENNA_BC,
117 ANTENNA_BCD,
118 ANTENNA_A,
119 ANTENNA_AD,
120 ANTENNA_AC,
121 ANTENNA_ACD,
122 ANTENNA_AB,
123 ANTENNA_ABD,
124 ANTENNA_ABC,
125 ANTENNA_ABCD
126};
127
128struct r_antenna_select_ofdm {
129 u32 r_tx_antenna:4;
130 u32 r_ant_l:4;
131 u32 r_ant_non_ht:4;
132 u32 r_ant_ht1:4;
133 u32 r_ant_ht2:4;
134 u32 r_ant_ht_s1:4;
135 u32 r_ant_non_ht_s1:4;
136 u32 ofdm_txsc:2;
137 u32 reserved:2;
138};
139
140struct r_antenna_select_cck {
141 u8 r_cckrx_enable_2:2;
142 u8 r_cckrx_enable:2;
143 u8 r_ccktx_enable:4;
144};
145
146
147struct efuse_contents {
148 u8 mac_addr[ETH_ALEN];
149 u8 cck_tx_power_idx[6];
150 u8 ht40_1s_tx_power_idx[6];
151 u8 ht40_2s_tx_power_idx_diff[3];
152 u8 ht20_tx_power_idx_diff[3];
153 u8 ofdm_tx_power_idx_diff[3];
154 u8 ht40_max_power_offset[3];
155 u8 ht20_max_power_offset[3];
156 u8 channel_plan;
157 u8 thermal_meter;
158 u8 rf_option[5];
159 u8 version;
160 u8 oem_id;
161 u8 regulatory;
162};
163
164struct tx_power_struct {
165 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
166 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
167 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
168 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
169 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
170 u8 legacy_ht_txpowerdiff;
171 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
172 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
173 u8 pwrgroup_cnt;
174 u32 mcs_original_offset[4][16];
175};
176
177enum _ANT_DIV_TYPE {
178 NO_ANTDIV = 0xFF,
179 CG_TRX_HW_ANTDIV = 0x01,
180 CGCS_RX_HW_ANTDIV = 0x02,
181 FIXED_HW_ANTDIV = 0x03, 101 FIXED_HW_ANTDIV = 0x03,
182 CG_TRX_SMART_ANTDIV = 0x04, 102 CG_TRX_SMART_ANTDIV = 0x04,
183 CGCS_RX_SW_ANTDIV = 0x05, 103 CGCS_RX_SW_ANTDIV = 0x05,
104
184}; 105};
185 106
186u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, 107u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw,
@@ -206,7 +127,6 @@ void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw);
206u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw); 127u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw);
207void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, 128void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
208 bool b_recovery); 129 bool b_recovery);
209void rtl23b_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
210void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw); 130void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw);
211void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 131void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
212bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 132bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h
index a62f43ed8d32..0fee5e0e55c2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h
@@ -26,7 +26,9 @@
26#ifndef __RTL8723BE_PWRSEQ_H__ 26#ifndef __RTL8723BE_PWRSEQ_H__
27#define __RTL8723BE_PWRSEQ_H__ 27#define __RTL8723BE_PWRSEQ_H__
28 28
29/* Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd 29#include "../pwrseqcmd.h"
30/**
31 * Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
30 * There are 6 HW Power States: 32 * There are 6 HW Power States:
31 * 0: POFF--Power Off 33 * 0: POFF--Power Off
32 * 1: PDN--Power Down 34 * 1: PDN--Power Down
@@ -35,7 +37,7 @@
35 * 4: LPS--Low Power State 37 * 4: LPS--Low Power State
36 * 5: SUS--Suspend 38 * 5: SUS--Suspend
37 * 39 *
38 * The transition from different states are defined below 40 * The transision from different states are defined below
39 * TRANS_CARDEMU_TO_ACT 41 * TRANS_CARDEMU_TO_ACT
40 * TRANS_ACT_TO_CARDEMU 42 * TRANS_ACT_TO_CARDEMU
41 * TRANS_CARDEMU_TO_SUS 43 * TRANS_CARDEMU_TO_SUS
@@ -57,203 +59,320 @@
57#define RTL8723B_TRANS_END_STEPS 1 59#define RTL8723B_TRANS_END_STEPS 1
58 60
59#define RTL8723B_TRANS_CARDEMU_TO_ACT \ 61#define RTL8723B_TRANS_CARDEMU_TO_ACT \
62 /* format */ \
63 /* comments here */ \
64 /* {offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value}, */\
65 /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
60 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 66 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
61 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 67 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
62 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
69 /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
63 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 70 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
64 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 71 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
65 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 72 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
73 /*Delay 1ms*/ \
66 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 74 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
67 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 75 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
68 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \ 76 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \
77 /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
69 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 78 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
70 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 79 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \ 80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
81 /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
72 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 82 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \ 83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
84 /* Disable USB suspend */ \
74 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 85 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
75 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \ 86 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
87 /* wait till 0x04[17] = 1 power ready*/ \
76 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 88 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
77 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
90 /* Enable USB suspend */ \
78 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 91 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \ 92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
93 /* release WLON reset 0x04[16]=1*/ \
80 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 94 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
81 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
96 /* disable HWPDN 0x04[15]=0*/ \
82 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 97 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ 98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
99 /* disable WL suspend*/ \
84 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 100 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \ 101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
102 /* polling until return 0*/ \
86 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 103 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
87 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 104 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
88 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 105 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \ 106 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
107 /* Enable WL control XTAL setting*/ \
90 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 108 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
91 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \ 109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
110 /*Enable falling edge triggering interrupt*/ \
92 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 111 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
113 /*Enable GPIO9 interrupt mode*/ \
94 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 114 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
116 /*Enable GPIO9 input mode*/ \
96 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 117 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
119 /*Enable HSISR GPIO[C:0] interrupt*/ \
98 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 120 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
122 /*Enable HSISR GPIO9 interrupt*/ \
100 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 123 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 124 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
125 /*For GPIO9 internal pull high setting by test chip*/ \
102 {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 126 {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \ 127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
128 /*For GPIO9 internal pull high setting*/ \
104 {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 129 {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, 130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
106 131
107#define RTL8723B_TRANS_ACT_TO_CARDEMU \ 132#define RTL8723B_TRANS_ACT_TO_CARDEMU \
133 /* format */ \
134 /* comments here */ \
135 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
136 /*0x1F[7:0] = 0 turn off RF*/ \
108 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 137 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \ 138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
139 /*0x4C[24] = 0x4F[0] = 0, */ \
140 /*switch DPDT_SEL_P output from register 0x65[2] */ \
110 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 141 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
111 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 142 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
143 /*Enable rising edge triggering interrupt*/ \
112 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 144 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
113 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 145 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
146 /*0x04[9] = 1 turn off MAC by HW state machine*/ \
114 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 147 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
149 /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
116 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 150 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
117 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \ 151 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
152 /* Enable BT control XTAL setting*/ \
118 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 153 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
119 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \ 154 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
155 /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
120 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 156 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
121 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ 157 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
122 PWR_CMD_WRITE, BIT(5), BIT(5)}, \ 158 PWR_CMD_WRITE, BIT(5), BIT(5)}, \
159 /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
123 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 160 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
124 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ 161 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
125 PWR_CMD_WRITE, BIT(0), 0}, 162 PWR_CMD_WRITE, BIT(0), 0},
126 163
127#define RTL8723B_TRANS_CARDEMU_TO_SUS \ 164#define RTL8723B_TRANS_CARDEMU_TO_SUS \
165 /* format */ \
166 /* comments here */ \
167 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
168 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
128 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 169 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
129 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \ 170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
171 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
130 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 172 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
131 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ 173 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
132 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ 174 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
175 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
133 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 176 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
134 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
178 /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
135 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 179 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
136 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \ 180 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
181 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
137 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 182 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\ 183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
184 /*Set SDIO suspend local register*/ \
139 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 185 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
140 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 186 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
187 /*wait power state to suspend*/ \
141 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 188 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
142 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, 189 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
143 190
144#define RTL8723B_TRANS_SUS_TO_CARDEMU \ 191#define RTL8723B_TRANS_SUS_TO_CARDEMU \
192 /* format */ \
193 /* comments here */ \
194 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
195 /*clear suspend enable and power down enable*/ \
145 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 196 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
146 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \ 197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
198 /*Set SDIO suspend local register*/ \
147 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 199 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
148 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
201 /*wait power state to suspend*/ \
149 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 202 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
150 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
204 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
151 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 205 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
207 /*0x04[12:11] = 2b'01enable WL suspend*/ \
153 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 208 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
154 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, 209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
155 210
156#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ 211#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \
212 /* format */ \
213 /* comments here */ \
214 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
215 /*0x07=0x20 , SOP option to disable BG/MB*/ \
157 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 216 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \ 217 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
218 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
159 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 219 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
160 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 220 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
161 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \ 221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
222 /*0x04[10] = 1, enable SW LPS*/ \
162 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 223 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
163 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \ 224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
225 /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
164 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 226 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
165 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \ 227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
228 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
166 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 229 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
167 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
231 /*Set SDIO suspend local register*/ \
168 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 232 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
169 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 233 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
234 /*wait power state to suspend*/ \
170 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 235 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
171 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, 236 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
172 237
173#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \ 238#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \
239 /* format */ \
240 /* comments here */ \
241 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
242 /*clear suspend enable and power down enable*/ \
174 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 243 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
175 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \ 244 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
245 /*Set SDIO suspend local register*/ \
176 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 246 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
177 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 247 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
248 /*wait power state to suspend*/ \
178 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 249 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
179 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 250 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
251 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
180 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 252 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
254 /*0x04[12:11] = 2b'01enable WL suspend*/ \
182 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 255 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \ 256 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
257 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
184 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 258 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
185 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
260 /*PCIe DMA start*/ \
186 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 261 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
187 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, 262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
188 263
189#define RTL8723B_TRANS_CARDEMU_TO_PDN \ 264#define RTL8723B_TRANS_CARDEMU_TO_PDN \
265 /* format */ \
266 /* comments here */ \
267 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
268 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
190 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 269 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
191 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 270 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
271 /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
192 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 272 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
193 PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, \ 273 PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, \
194 PWR_CMD_WRITE, 0xFF, 0x20}, \ 274 PWR_CMD_WRITE, 0xFF, 0x20}, \
275 /* 0x04[16] = 0*/ \
195 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 276 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
196 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
278 /* 0x04[15] = 1*/ \
197 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 279 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
198 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, 280 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
199 281
200#define RTL8723B_TRANS_PDN_TO_CARDEMU \ 282#define RTL8723B_TRANS_PDN_TO_CARDEMU \
283 /* format */ \
284 /* comments here */ \
285 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
286 /* 0x04[15] = 0*/ \
201 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 287 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, 288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
203 289
204#define RTL8723B_TRANS_ACT_TO_LPS \ 290#define RTL8723B_TRANS_ACT_TO_LPS \
291 /* format */ \
292 /* comments here */ \
293 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
294 /*PCIe DMA stop*/ \
205 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 295 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 296 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
297 /*Tx Pause*/ \
207 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 298 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
208 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 299 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
300 /*Should be zero if no packet is transmitting*/ \
209 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 301 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
210 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 302 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
303 /*Should be zero if no packet is transmitting*/ \
211 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 304 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
212 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 305 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
306 /*Should be zero if no packet is transmitting*/ \
213 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 307 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
214 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 308 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
309 /*Should be zero if no packet is transmitting*/ \
215 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 310 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
216 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 311 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
312 /*CCK and OFDM are disabled,and clock are gated*/ \
217 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 313 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 314 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
315 /*Delay 1us*/ \
219 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 316 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
220 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \ 317 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
318 /*Whole BB is reset*/ \
221 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 319 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
222 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 320 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
321 /*Reset MAC TRX*/ \
223 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 322 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \ 323 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
324 /*check if removed later*/ \
225 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 325 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
226 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 326 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
327 /*When driver enter Sus/ Disable, enable LOP for BT*/ \
227 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 328 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
228 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \ 329 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
330 /*Respond TxOK to scheduler*/ \
229 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 331 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, 332 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
231 333
232#define RTL8723B_TRANS_LPS_TO_ACT \ 334#define RTL8723B_TRANS_LPS_TO_ACT \
335 /* format */ \
336 /* comments here */ \
337 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
338 /*SDIO RPWM*/ \
233 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 339 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
234 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \ 340 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
341 /*USB RPWM*/ \
235 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 342 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
236 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \ 343 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
344 /*PCIe RPWM*/ \
237 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 345 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
238 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \ 346 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
347 /*Delay*/ \
239 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 348 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
240 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \ 349 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
350 /*. 0x08[4] = 0 switch TSF to 40M*/ \
241 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 351 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
242 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 352 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
353 /*Polling 0x109[7]=0 TSF in 40M*/ \
243 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 354 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
244 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \ 355 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
356 /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
245 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 357 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
246 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \ 358 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
359 /*. 0x101[1] = 1*/ \
247 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 360 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 361 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
362 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
249 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 363 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
250 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 364 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
365 /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
251 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 366 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
252 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ 367 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
368 /*. 0x522 = 0*/ \
253 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 369 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
254 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, 370 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
255 371
256#define RTL8723B_TRANS_END \ 372#define RTL8723B_TRANS_END \
373 /* format */ \
374 /* comments here */ \
375 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
257 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \ 376 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
258 PWR_CMD_END, 0, 0}, 377 PWR_CMD_END, 0, 0},
259 378
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/reg.h b/drivers/net/wireless/rtlwifi/rtl8723be/reg.h
index 3006849ed439..03581d2a5da0 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/reg.h
@@ -78,11 +78,11 @@
78#define REG_WOL_EVENT 0x0081 78#define REG_WOL_EVENT 0x0081
79#define REG_MCUTSTCFG 0x0084 79#define REG_MCUTSTCFG 0x0084
80 80
81
82#define REG_HIMR 0x00B0 81#define REG_HIMR 0x00B0
83#define REG_HISR 0x00B4 82#define REG_HISR 0x00B4
84#define REG_HIMRE 0x00B8 83#define REG_HIMRE 0x00B8
85#define REG_HISRE 0x00BC 84#define REG_HISRE 0x00BC
85#define REG_PMC_DBG_CTRL2 0x00CC
86 86
87#define REG_EFUSE_ACCESS 0x00CF 87#define REG_EFUSE_ACCESS 0x00CF
88 88
@@ -95,7 +95,8 @@
95#define REG_HPON_FSM 0x00EC 95#define REG_HPON_FSM 0x00EC
96#define REG_SYS_CFG 0x00F0 96#define REG_SYS_CFG 0x00F0
97#define REG_GPIO_OUTSTS 0x00F4 97#define REG_GPIO_OUTSTS 0x00F4
98#define REG_SYS_CFG1 0x00F0 98#define REG_MAC_PHY_CTRL_NORMAL 0x00F8
99#define REG_SYS_CFG1 0x00FC
99#define REG_ROM_VERSION 0x00FD 100#define REG_ROM_VERSION 0x00FD
100 101
101#define REG_CR 0x0100 102#define REG_CR 0x0100
@@ -170,8 +171,14 @@
170#define REG_BKQ_DESA 0x0338 171#define REG_BKQ_DESA 0x0338
171#define REG_RX_DESA 0x0340 172#define REG_RX_DESA 0x0340
172 173
173#define REG_DBI 0x0348 174#define REG_DBI_WDATA 0x0348
174#define REG_MDIO 0x0354 175#define REG_DBI_RDATA 0x034C
176#define REG_DBI_CTRL 0x0350
177#define REG_DBI_ADDR 0x0350
178#define REG_DBI_FLAG 0x0352
179#define REG_MDIO_WDATA 0x0354
180#define REG_MDIO_RDATA 0x0356
181#define REG_MDIO_CTL 0x0358
175#define REG_DBG_SEL 0x0360 182#define REG_DBG_SEL 0x0360
176#define REG_PCIE_HRPWM 0x0361 183#define REG_PCIE_HRPWM 0x0361
177#define REG_PCIE_HCPWM 0x0363 184#define REG_PCIE_HCPWM 0x0363
@@ -180,7 +187,6 @@
180#define REG_UART_TX_DESA 0x0370 187#define REG_UART_TX_DESA 0x0370
181#define REG_UART_RX_DESA 0x0378 188#define REG_UART_RX_DESA 0x0378
182 189
183
184#define REG_HDAQ_DESA_NODEF 0x0000 190#define REG_HDAQ_DESA_NODEF 0x0000
185#define REG_CMDQ_DESA_NODEF 0x0000 191#define REG_CMDQ_DESA_NODEF 0x0000
186 192
@@ -193,7 +199,6 @@
193#define REG_BCNQ_INFORMATION 0x0418 199#define REG_BCNQ_INFORMATION 0x0418
194#define REG_TXPKT_EMPTY 0x041A 200#define REG_TXPKT_EMPTY 0x041A
195 201
196
197#define REG_CPU_MGQ_INFORMATION 0x041C 202#define REG_CPU_MGQ_INFORMATION 0x041C
198#define REG_FWHW_TXQ_CTRL 0x0420 203#define REG_FWHW_TXQ_CTRL 0x0420
199#define REG_HWSEQ_CTRL 0x0423 204#define REG_HWSEQ_CTRL 0x0423
@@ -207,9 +212,7 @@
207#define REG_RARFRC 0x0438 212#define REG_RARFRC 0x0438
208#define REG_RRSR 0x0440 213#define REG_RRSR 0x0440
209#define REG_ARFR0 0x0444 214#define REG_ARFR0 0x0444
210#define REG_ARFR1 0x0448 215#define REG_ARFR1 0x044C
211#define REG_ARFR2 0x044C
212#define REG_ARFR3 0x0450
213#define REG_AMPDU_MAX_TIME 0x0456 216#define REG_AMPDU_MAX_TIME 0x0456
214#define REG_AGGLEN_LMT 0x0458 217#define REG_AGGLEN_LMT 0x0458
215#define REG_AMPDU_MIN_SPACE 0x045C 218#define REG_AMPDU_MIN_SPACE 0x045C
@@ -223,7 +226,10 @@
223#define REG_POWER_STAGE2 0x04B8 226#define REG_POWER_STAGE2 0x04B8
224#define REG_PKT_LIFE_TIME 0x04C0 227#define REG_PKT_LIFE_TIME 0x04C0
225#define REG_STBC_SETTING 0x04C4 228#define REG_STBC_SETTING 0x04C4
229#define REG_HT_SINGLE_AMPDU 0x04C7
230
226#define REG_PROT_MODE_CTRL 0x04C8 231#define REG_PROT_MODE_CTRL 0x04C8
232#define REG_MAX_AGGR_NUM 0x04CA
227#define REG_BAR_MODE_CTRL 0x04CC 233#define REG_BAR_MODE_CTRL 0x04CC
228#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 234#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
229#define REG_EARLY_MODE_CONTROL 0x04D0 235#define REG_EARLY_MODE_CONTROL 0x04D0
@@ -303,6 +309,7 @@
303#define REG_EIFS 0x0642 309#define REG_EIFS 0x0642
304 310
305#define REG_NAV_CTRL 0x0650 311#define REG_NAV_CTRL 0x0650
312#define REG_NAV_UPPER 0x0652
306#define REG_BACAMCMD 0x0654 313#define REG_BACAMCMD 0x0654
307#define REG_BACAMCONTENT 0x0658 314#define REG_BACAMCONTENT 0x0658
308#define REG_LBDLY 0x0660 315#define REG_LBDLY 0x0660
@@ -355,43 +362,43 @@
355#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 362#define REG_NORMAL_SIE_MAC_ADDR 0xFE70
356#define REG_NORMAL_SIE_STRING 0xFE80 363#define REG_NORMAL_SIE_STRING 0xFE80
357 364
358#define CR9346 REG_9346CR 365#define CR9346 REG_9346CR
359#define MSR (REG_CR + 2) 366#define MSR (REG_CR + 2)
360#define ISR REG_HISR 367#define ISR REG_HISR
361#define TSFR REG_TSFTR 368#define TSFR REG_TSFTR
362 369
363#define MACIDR0 REG_MACID 370#define MACIDR0 REG_MACID
364#define MACIDR4 (REG_MACID + 4) 371#define MACIDR4 (REG_MACID + 4)
365 372
366#define PBP REG_PBP 373#define PBP REG_PBP
367 374
368#define IDR0 MACIDR0 375#define IDR0 MACIDR0
369#define IDR4 MACIDR4 376#define IDR4 MACIDR4
370 377
371#define UNUSED_REGISTER 0x1BF 378#define UNUSED_REGISTER 0x1BF
372#define DCAM UNUSED_REGISTER 379#define DCAM UNUSED_REGISTER
373#define PSR UNUSED_REGISTER 380#define PSR UNUSED_REGISTER
374#define BBADDR UNUSED_REGISTER 381#define BBADDR UNUSED_REGISTER
375#define PHYDATAR UNUSED_REGISTER 382#define PHYDATAR UNUSED_REGISTER
376 383
377#define INVALID_BBRF_VALUE 0x12345678 384#define INVALID_BBRF_VALUE 0x12345678
378 385
379#define MAX_MSS_DENSITY_2T 0x13 386#define MAX_MSS_DENSITY_2T 0x13
380#define MAX_MSS_DENSITY_1T 0x0A 387#define MAX_MSS_DENSITY_1T 0x0A
381 388
382#define CMDEEPROM_EN BIT(5) 389#define CMDEEPROM_EN BIT(5)
383#define CMDEEPROM_SEL BIT(4) 390#define CMDEEPROM_SEL BIT(4)
384#define CMD9346CR_9356SEL BIT(4) 391#define CMD9346CR_9356SEL BIT(4)
385#define AUTOLOAD_EEPROM (CMDEEPROM_EN | CMDEEPROM_SEL) 392#define AUTOLOAD_EEPROM (CMDEEPROM_EN | CMDEEPROM_SEL)
386#define AUTOLOAD_EFUSE CMDEEPROM_EN 393#define AUTOLOAD_EFUSE CMDEEPROM_EN
387 394
388#define GPIOSEL_GPIO 0 395#define GPIOSEL_GPIO 0
389#define GPIOSEL_ENBT BIT(5) 396#define GPIOSEL_ENBT BIT(5)
390 397
391#define GPIO_IN REG_GPIO_PIN_CTRL 398#define GPIO_IN REG_GPIO_PIN_CTRL
392#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1) 399#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1)
393#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2) 400#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2)
394#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3) 401#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3)
395 402
396/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ 403/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
397#define HSIMR_GPIO12_0_INT_EN BIT(0) 404#define HSIMR_GPIO12_0_INT_EN BIT(0)
@@ -400,8 +407,7 @@
400#define HSIMR_PDN_INT_EN BIT(7) 407#define HSIMR_PDN_INT_EN BIT(7)
401#define HSIMR_GPIO9_INT_EN BIT(25) 408#define HSIMR_GPIO9_INT_EN BIT(25)
402 409
403/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 410/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
404
405#define HSISR_GPIO12_0_INT BIT(0) 411#define HSISR_GPIO12_0_INT BIT(0)
406#define HSISR_SPS_OCP_INT BIT(5) 412#define HSISR_SPS_OCP_INT BIT(5)
407#define HSISR_RON_INT_EN BIT(6) 413#define HSISR_RON_INT_EN BIT(6)
@@ -412,7 +418,6 @@
412#define MSR_ADHOC 0x01 418#define MSR_ADHOC 0x01
413#define MSR_INFRA 0x02 419#define MSR_INFRA 0x02
414#define MSR_AP 0x03 420#define MSR_AP 0x03
415#define MSR_MASK 0x03
416 421
417#define RRSR_RSC_OFFSET 21 422#define RRSR_RSC_OFFSET 21
418#define RRSR_SHORT_OFFSET 23 423#define RRSR_SHORT_OFFSET 23
@@ -542,7 +547,8 @@
542 547
543/********************************************* 548/*********************************************
544* 8723BE IMR/ISR bits 549* 8723BE IMR/ISR bits
545**********************************************/ 550*********************************************
551*/
546#define IMR_DISABLED 0x0 552#define IMR_DISABLED 0x0
547/* IMR DW0(0x0060-0063) Bit 0-31 */ 553/* IMR DW0(0x0060-0063) Bit 0-31 */
548#define IMR_TXCCK BIT(30) /* TXRPT interrupt when 554#define IMR_TXCCK BIT(30) /* TXRPT interrupt when
@@ -644,7 +650,7 @@
644#define RF_OPTION1 0x79 650#define RF_OPTION1 0x79
645#define RF_OPTION2 0x7A 651#define RF_OPTION2 0x7A
646#define RF_OPTION3 0x7B 652#define RF_OPTION3 0x7B
647#define RF_OPTION4 0xC3 653#define EEPROM_RF_BT_SETTING_8723B 0xC3
648 654
649#define EEPROM_DEFAULT_PID 0x1234 655#define EEPROM_DEFAULT_PID 0x1234
650#define EEPROM_DEFAULT_VID 0x5678 656#define EEPROM_DEFAULT_VID 0x5678
@@ -678,14 +684,11 @@
678#define EEPROM_CLK 0x06 684#define EEPROM_CLK 0x06
679#define EEPROM_TESTR 0x08 685#define EEPROM_TESTR 0x08
680 686
681
682#define EEPROM_TXPOWERCCK 0x10 687#define EEPROM_TXPOWERCCK 0x10
683#define EEPROM_TXPOWERHT40_1S 0x16 688#define EEPROM_TXPOWERHT40_1S 0x16
684#define EEPROM_TXPOWERHT20DIFF 0x1B 689#define EEPROM_TXPOWERHT20DIFF 0x1B
685#define EEPROM_TXPOWER_OFDMDIFF 0x1B 690#define EEPROM_TXPOWER_OFDMDIFF 0x1B
686 691
687
688
689#define EEPROM_TX_PWR_INX 0x10 692#define EEPROM_TX_PWR_INX 0x10
690 693
691#define EEPROM_CHANNELPLAN 0xB8 694#define EEPROM_CHANNELPLAN 0xB8
@@ -1198,7 +1201,7 @@
1198#define APP_MIC BIT(30) 1201#define APP_MIC BIT(30)
1199#define APP_FCS BIT(31) 1202#define APP_FCS BIT(31)
1200 1203
1201#define _MIN_SPACE(x) ((x) & 0x7) 1204#define _MIN_SPACE(x) ((x) & 0x7)
1202#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1205#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1203 1206
1204#define RXERR_TYPE_OFDM_PPDU 0 1207#define RXERR_TYPE_OFDM_PPDU 0
@@ -1216,105 +1219,105 @@
1216#define RXERR_TYPE_HT_MPDU_FAIL 12 1219#define RXERR_TYPE_HT_MPDU_FAIL 12
1217#define RXERR_TYPE_RX_FULL_DROP 15 1220#define RXERR_TYPE_RX_FULL_DROP 15
1218 1221
1219#define RXERR_COUNTER_MASK 0xFFFFF 1222#define RXERR_COUNTER_MASK 0xFFFFF
1220#define RXERR_RPT_RST BIT(27) 1223#define RXERR_RPT_RST BIT(27)
1221#define _RXERR_RPT_SEL(type) ((type) << 28) 1224#define _RXERR_RPT_SEL(type) ((type) << 28)
1222
1223#define SCR_TXUSEDK BIT(0)
1224#define SCR_RXUSEDK BIT(1)
1225#define SCR_TXENCENABLE BIT(2)
1226#define SCR_RXDECENABLE BIT(3)
1227#define SCR_SKBYA2 BIT(4)
1228#define SCR_NOSKMC BIT(5)
1229#define SCR_TXBCUSEDK BIT(6)
1230#define SCR_RXBCUSEDK BIT(7)
1231
1232#define XCLK_VLD BIT(0)
1233#define ACLK_VLD BIT(1)
1234#define UCLK_VLD BIT(2)
1235#define PCLK_VLD BIT(3)
1236#define PCIRSTB BIT(4)
1237#define V15_VLD BIT(5)
1238#define TRP_B15V_EN BIT(7)
1239#define SIC_IDLE BIT(8)
1240#define BD_MAC2 BIT(9)
1241#define BD_MAC1 BIT(10)
1242#define IC_MACPHY_MODE BIT(11)
1243#define BT_FUNC BIT(16)
1244#define VENDOR_ID BIT(19)
1245#define PAD_HWPD_IDN BIT(22)
1246#define TRP_VAUX_EN BIT(23)
1247#define TRP_BT_EN BIT(24)
1248#define BD_PKG_SEL BIT(25)
1249#define BD_HCI_SEL BIT(26)
1250#define TYPE_ID BIT(27)
1251
1252#define USB_IS_HIGH_SPEED 0
1253#define USB_IS_FULL_SPEED 1
1254#define USB_SPEED_MASK BIT(5)
1255
1256#define USB_NORMAL_SIE_EP_MASK 0xF
1257#define USB_NORMAL_SIE_EP_SHIFT 4
1258
1259#define USB_TEST_EP_MASK 0x30
1260#define USB_TEST_EP_SHIFT 4
1261
1262#define USB_AGG_EN BIT(3)
1263
1264#define MAC_ADDR_LEN 6
1265#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/
1266
1267#define POLLING_LLT_THRESHOLD 20
1268#define POLLING_READY_TIMEOUT_COUNT 3000
1269 1225
1270#define MAX_MSS_DENSITY_2T 0x13 1226#define SCR_TXUSEDK BIT(0)
1271#define MAX_MSS_DENSITY_1T 0x0A 1227#define SCR_RXUSEDK BIT(1)
1228#define SCR_TXENCENABLE BIT(2)
1229#define SCR_RXDECENABLE BIT(3)
1230#define SCR_SKBYA2 BIT(4)
1231#define SCR_NOSKMC BIT(5)
1232#define SCR_TXBCUSEDK BIT(6)
1233#define SCR_RXBCUSEDK BIT(7)
1234
1235#define XCLK_VLD BIT(0)
1236#define ACLK_VLD BIT(1)
1237#define UCLK_VLD BIT(2)
1238#define PCLK_VLD BIT(3)
1239#define PCIRSTB BIT(4)
1240#define V15_VLD BIT(5)
1241#define TRP_B15V_EN BIT(7)
1242#define SIC_IDLE BIT(8)
1243#define BD_MAC2 BIT(9)
1244#define BD_MAC1 BIT(10)
1245#define IC_MACPHY_MODE BIT(11)
1246#define BT_FUNC BIT(16)
1247#define VENDOR_ID BIT(19)
1248#define PAD_HWPD_IDN BIT(22)
1249#define TRP_VAUX_EN BIT(23)
1250#define TRP_BT_EN BIT(24)
1251#define BD_PKG_SEL BIT(25)
1252#define BD_HCI_SEL BIT(26)
1253#define TYPE_ID BIT(27)
1254
1255#define USB_IS_HIGH_SPEED 0
1256#define USB_IS_FULL_SPEED 1
1257#define USB_SPEED_MASK BIT(5)
1258
1259#define USB_NORMAL_SIE_EP_MASK 0xF
1260#define USB_NORMAL_SIE_EP_SHIFT 4
1261
1262#define USB_TEST_EP_MASK 0x30
1263#define USB_TEST_EP_SHIFT 4
1264
1265#define USB_AGG_EN BIT(3)
1266
1267#define MAC_ADDR_LEN 6
1268#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/
1269
1270#define POLLING_LLT_THRESHOLD 20
1271#define POLLING_READY_TIMEOUT_COUNT 3000
1272
1273#define MAX_MSS_DENSITY_2T 0x13
1274#define MAX_MSS_DENSITY_1T 0x0A
1272 1275
1273#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1276#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
1274#define EPROM_CMD_CONFIG 0x3 1277#define EPROM_CMD_CONFIG 0x3
1275#define EPROM_CMD_LOAD 1 1278#define EPROM_CMD_LOAD 1
1276 1279
1277#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1280#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1278 1281
1279#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1282#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1280 1283
1281#define RPMAC_RESET 0x100 1284#define RPMAC_RESET 0x100
1282#define RPMAC_TXSTART 0x104 1285#define RPMAC_TXSTART 0x104
1283#define RPMAC_TXLEGACYSIG 0x108 1286#define RPMAC_TXLEGACYSIG 0x108
1284#define RPMAC_TXHTSIG1 0x10c 1287#define RPMAC_TXHTSIG1 0x10c
1285#define RPMAC_TXHTSIG2 0x110 1288#define RPMAC_TXHTSIG2 0x110
1286#define RPMAC_PHYDEBUG 0x114 1289#define RPMAC_PHYDEBUG 0x114
1287#define RPMAC_TXPACKETNUM 0x118 1290#define RPMAC_TXPACKETNUM 0x118
1288#define RPMAC_TXIDLE 0x11c 1291#define RPMAC_TXIDLE 0x11c
1289#define RPMAC_TXMACHEADER0 0x120 1292#define RPMAC_TXMACHEADER0 0x120
1290#define RPMAC_TXMACHEADER1 0x124 1293#define RPMAC_TXMACHEADER1 0x124
1291#define RPMAC_TXMACHEADER2 0x128 1294#define RPMAC_TXMACHEADER2 0x128
1292#define RPMAC_TXMACHEADER3 0x12c 1295#define RPMAC_TXMACHEADER3 0x12c
1293#define RPMAC_TXMACHEADER4 0x130 1296#define RPMAC_TXMACHEADER4 0x130
1294#define RPMAC_TXMACHEADER5 0x134 1297#define RPMAC_TXMACHEADER5 0x134
1295#define RPMAC_TXDADATYPE 0x138 1298#define RPMAC_TXDADATYPE 0x138
1296#define RPMAC_TXRANDOMSEED 0x13c 1299#define RPMAC_TXRANDOMSEED 0x13c
1297#define RPMAC_CCKPLCPPREAMBLE 0x140 1300#define RPMAC_CCKPLCPPREAMBLE 0x140
1298#define RPMAC_CCKPLCPHEADER 0x144 1301#define RPMAC_CCKPLCPHEADER 0x144
1299#define RPMAC_CCKCRC16 0x148 1302#define RPMAC_CCKCRC16 0x148
1300#define RPMAC_OFDMRXCRC32OK 0x170 1303#define RPMAC_OFDMRXCRC32OK 0x170
1301#define RPMAC_OFDMRXCRC32ER 0x174 1304#define RPMAC_OFDMRXCRC32ER 0x174
1302#define RPMAC_OFDMRXPARITYER 0x178 1305#define RPMAC_OFDMRXPARITYER 0x178
1303#define RPMAC_OFDMRXCRC8ER 0x17c 1306#define RPMAC_OFDMRXCRC8ER 0x17c
1304#define RPMAC_CCKCRXRC16ER 0x180 1307#define RPMAC_CCKCRXRC16ER 0x180
1305#define RPMAC_CCKCRXRC32ER 0x184 1308#define RPMAC_CCKCRXRC32ER 0x184
1306#define RPMAC_CCKCRXRC32OK 0x188 1309#define RPMAC_CCKCRXRC32OK 0x188
1307#define RPMAC_TXSTATUS 0x18c 1310#define RPMAC_TXSTATUS 0x18c
1308 1311
1309#define RFPGA0_RFMOD 0x800 1312#define RFPGA0_RFMOD 0x800
1310 1313
1311#define RFPGA0_TXINFO 0x804 1314#define RFPGA0_TXINFO 0x804
1312#define RFPGA0_PSDFUNCTION 0x808 1315#define RFPGA0_PSDFUNCTION 0x808
1313 1316
1314#define RFPGA0_TXGAINSTAGE 0x80c 1317#define RFPGA0_TXGAINSTAGE 0x80c
1315 1318
1316#define RFPGA0_RFTIMING1 0x810 1319#define RFPGA0_RFTIMING1 0x810
1317#define RFPGA0_RFTIMING2 0x814 1320#define RFPGA0_RFTIMING2 0x814
1318 1321
1319#define RFPGA0_XA_HSSIPARAMETER1 0x820 1322#define RFPGA0_XA_HSSIPARAMETER1 0x820
1320#define RFPGA0_XA_HSSIPARAMETER2 0x824 1323#define RFPGA0_XA_HSSIPARAMETER2 0x824
@@ -1385,7 +1388,6 @@
1385#define RCCK0_FACOUNTERUPPER 0xa58 1388#define RCCK0_FACOUNTERUPPER 0xa58
1386#define RCCK0_CCA_CNT 0xa60 1389#define RCCK0_CCA_CNT 0xa60
1387 1390
1388
1389/* PageB(0xB00) */ 1391/* PageB(0xB00) */
1390#define RPDP_ANTA 0xb00 1392#define RPDP_ANTA 0xb00
1391#define RPDP_ANTA_4 0xb04 1393#define RPDP_ANTA_4 0xb04
@@ -1399,7 +1401,7 @@
1399#define RPDP_ANTA_24 0xb24 1401#define RPDP_ANTA_24 0xb24
1400 1402
1401#define RCONFIG_PMPD_ANTA 0xb28 1403#define RCONFIG_PMPD_ANTA 0xb28
1402#define CONFIG_RAM64X16 0xb2c 1404#define RCONFIG_ram64x16 0xb2c
1403 1405
1404#define RBNDA 0xb30 1406#define RBNDA 0xb30
1405#define RHSSIPAR 0xb34 1407#define RHSSIPAR 0xb34
@@ -1494,7 +1496,6 @@
1494#define ROFDM0_FRAMESYNC 0xcf0 1496#define ROFDM0_FRAMESYNC 0xcf0
1495#define ROFDM0_DFSREPORT 0xcf4 1497#define ROFDM0_DFSREPORT 0xcf4
1496 1498
1497
1498#define ROFDM1_LSTF 0xd00 1499#define ROFDM1_LSTF 0xd00
1499#define ROFDM1_TRXPATHENABLE 0xd04 1500#define ROFDM1_TRXPATHENABLE 0xd04
1500 1501
@@ -1593,144 +1594,144 @@
1593#define RSLEEP 0xee0 1594#define RSLEEP 0xee0
1594#define RPMPD_ANAEN 0xeec 1595#define RPMPD_ANAEN 0xeec
1595 1596
1596#define RZEBRA1_HSSIENABLE 0x0 1597#define RZEBRA1_HSSIENABLE 0x0
1597#define RZEBRA1_TRXENABLE1 0x1 1598#define RZEBRA1_TRXENABLE1 0x1
1598#define RZEBRA1_TRXENABLE2 0x2 1599#define RZEBRA1_TRXENABLE2 0x2
1599#define RZEBRA1_AGC 0x4 1600#define RZEBRA1_AGC 0x4
1600#define RZEBRA1_CHARGEPUMP 0x5 1601#define RZEBRA1_CHARGEPUMP 0x5
1601#define RZEBRA1_CHANNEL 0x7 1602#define RZEBRA1_CHANNEL 0x7
1602 1603
1603#define RZEBRA1_TXGAIN 0x8 1604#define RZEBRA1_TXGAIN 0x8
1604#define RZEBRA1_TXLPF 0x9 1605#define RZEBRA1_TXLPF 0x9
1605#define RZEBRA1_RXLPF 0xb 1606#define RZEBRA1_RXLPF 0xb
1606#define RZEBRA1_RXHPFCORNER 0xc 1607#define RZEBRA1_RXHPFCORNER 0xc
1607 1608
1608#define RGLOBALCTRL 0 1609#define RGLOBALCTRL 0
1609#define RRTL8256_TXLPF 19 1610#define RRTL8256_TXLPF 19
1610#define RRTL8256_RXLPF 11 1611#define RRTL8256_RXLPF 11
1611#define RRTL8258_TXLPF 0x11 1612#define RRTL8258_TXLPF 0x11
1612#define RRTL8258_RXLPF 0x13 1613#define RRTL8258_RXLPF 0x13
1613#define RRTL8258_RSSILPF 0xa 1614#define RRTL8258_RSSILPF 0xa
1614 1615
1615#define RF_AC 0x00 1616#define RF_AC 0x00
1616 1617
1617#define RF_IQADJ_G1 0x01 1618#define RF_IQADJ_G1 0x01
1618#define RF_IQADJ_G2 0x02 1619#define RF_IQADJ_G2 0x02
1619#define RF_POW_TRSW 0x05 1620#define RF_POW_TRSW 0x05
1620 1621
1621#define RF_GAIN_RX 0x06 1622#define RF_GAIN_RX 0x06
1622#define RF_GAIN_TX 0x07 1623#define RF_GAIN_TX 0x07
1623 1624
1624#define RF_TXM_IDAC 0x08 1625#define RF_TXM_IDAC 0x08
1625#define RF_BS_IQGEN 0x0F 1626#define RF_BS_IQGEN 0x0F
1626 1627
1627#define RF_MODE1 0x10 1628#define RF_MODE1 0x10
1628#define RF_MODE2 0x11 1629#define RF_MODE2 0x11
1629 1630
1630#define RF_RX_AGC_HP 0x12 1631#define RF_RX_AGC_HP 0x12
1631#define RF_TX_AGC 0x13 1632#define RF_TX_AGC 0x13
1632#define RF_BIAS 0x14 1633#define RF_BIAS 0x14
1633#define RF_IPA 0x15 1634#define RF_IPA 0x15
1634#define RF_POW_ABILITY 0x17 1635#define RF_POW_ABILITY 0x17
1635#define RF_MODE_AG 0x18 1636#define RF_MODE_AG 0x18
1636#define RRFCHANNEL 0x18 1637#define RRFCHANNEL 0x18
1637#define RF_CHNLBW 0x18 1638#define RF_CHNLBW 0x18
1638#define RF_TOP 0x19 1639#define RF_TOP 0x19
1639 1640
1640#define RF_RX_G1 0x1A 1641#define RF_RX_G1 0x1A
1641#define RF_RX_G2 0x1B 1642#define RF_RX_G2 0x1B
1642 1643
1643#define RF_RX_BB2 0x1C 1644#define RF_RX_BB2 0x1C
1644#define RF_RX_BB1 0x1D 1645#define RF_RX_BB1 0x1D
1645 1646
1646#define RF_RCK1 0x1E 1647#define RF_RCK1 0x1E
1647#define RF_RCK2 0x1F 1648#define RF_RCK2 0x1F
1648 1649
1649#define RF_TX_G1 0x20 1650#define RF_TX_G1 0x20
1650#define RF_TX_G2 0x21 1651#define RF_TX_G2 0x21
1651#define RF_TX_G3 0x22 1652#define RF_TX_G3 0x22
1652 1653
1653#define RF_TX_BB1 0x23 1654#define RF_TX_BB1 0x23
1654#define RF_T_METER 0x42 1655#define RF_T_METER 0x42
1655 1656
1656#define RF_SYN_G1 0x25 1657#define RF_SYN_G1 0x25
1657#define RF_SYN_G2 0x26 1658#define RF_SYN_G2 0x26
1658#define RF_SYN_G3 0x27 1659#define RF_SYN_G3 0x27
1659#define RF_SYN_G4 0x28 1660#define RF_SYN_G4 0x28
1660#define RF_SYN_G5 0x29 1661#define RF_SYN_G5 0x29
1661#define RF_SYN_G6 0x2A 1662#define RF_SYN_G6 0x2A
1662#define RF_SYN_G7 0x2B 1663#define RF_SYN_G7 0x2B
1663#define RF_SYN_G8 0x2C 1664#define RF_SYN_G8 0x2C
1664 1665
1665#define RF_RCK_OS 0x30 1666#define RF_RCK_OS 0x30
1666#define RF_TXPA_G1 0x31 1667#define RF_TXPA_G1 0x31
1667#define RF_TXPA_G2 0x32 1668#define RF_TXPA_G2 0x32
1668#define RF_TXPA_G3 0x33 1669#define RF_TXPA_G3 0x33
1669 1670
1670#define RF_TX_BIAS_A 0x35 1671#define RF_TX_BIAS_A 0x35
1671#define RF_TX_BIAS_D 0x36 1672#define RF_TX_BIAS_D 0x36
1672#define RF_LOBF_9 0x38 1673#define RF_LOBF_9 0x38
1673#define RF_RXRF_A3 0x3C 1674#define RF_RXRF_A3 0x3C
1674#define RF_TRSW 0x3F 1675#define RF_TRSW 0x3F
1675 1676
1676#define RF_TXRF_A2 0x41 1677#define RF_TXRF_A2 0x41
1677#define RF_TXPA_G4 0x46 1678#define RF_TXPA_G4 0x46
1678#define RF_TXPA_A4 0x4B 1679#define RF_TXPA_A4 0x4B
1679 1680
1680#define RF_WE_LUT 0xEF 1681#define RF_WE_LUT 0xEF
1681 1682
1682#define BBBRESETB 0x100 1683#define BBBRESETB 0x100
1683#define BGLOBALRESETB 0x200 1684#define BGLOBALRESETB 0x200
1684#define BOFDMTXSTART 0x4 1685#define BOFDMTXSTART 0x4
1685#define BCCKTXSTART 0x8 1686#define BCCKTXSTART 0x8
1686#define BCRC32DEBUG 0x100 1687#define BCRC32DEBUG 0x100
1687#define BPMACLOOPBACK 0x10 1688#define BPMACLOOPBACK 0x10
1688#define BTXLSIG 0xffffff 1689#define BTXLSIG 0xffffff
1689#define BOFDMTXRATE 0xf 1690#define BOFDMTXRATE 0xf
1690#define BOFDMTXRESERVED 0x10 1691#define BOFDMTXRESERVED 0x10
1691#define BOFDMTXLENGTH 0x1ffe0 1692#define BOFDMTXLENGTH 0x1ffe0
1692#define BOFDMTXPARITY 0x20000 1693#define BOFDMTXPARITY 0x20000
1693#define BTXHTSIG1 0xffffff 1694#define BTXHTSIG1 0xffffff
1694#define BTXHTMCSRATE 0x7f 1695#define BTXHTMCSRATE 0x7f
1695#define BTXHTBW 0x80 1696#define BTXHTBW 0x80
1696#define BTXHTLENGTH 0xffff00 1697#define BTXHTLENGTH 0xffff00
1697#define BTXHTSIG2 0xffffff 1698#define BTXHTSIG2 0xffffff
1698#define BTXHTSMOOTHING 0x1 1699#define BTXHTSMOOTHING 0x1
1699#define BTXHTSOUNDING 0x2 1700#define BTXHTSOUNDING 0x2
1700#define BTXHTRESERVED 0x4 1701#define BTXHTRESERVED 0x4
1701#define BTXHTAGGREATION 0x8 1702#define BTXHTAGGREATION 0x8
1702#define BTXHTSTBC 0x30 1703#define BTXHTSTBC 0x30
1703#define BTXHTADVANCECODING 0x40 1704#define BTXHTADVANCECODING 0x40
1704#define BTXHTSHORTGI 0x80 1705#define BTXHTSHORTGI 0x80
1705#define BTXHTNUMBERHT_LTF 0x300 1706#define BTXHTNUMBERHT_LTF 0x300
1706#define BTXHTCRC8 0x3fc00 1707#define BTXHTCRC8 0x3fc00
1707#define BCOUNTERRESET 0x10000 1708#define BCOUNTERRESET 0x10000
1708#define BNUMOFOFDMTX 0xffff 1709#define BNUMOFOFDMTX 0xffff
1709#define BNUMOFCCKTX 0xffff0000 1710#define BNUMOFCCKTX 0xffff0000
1710#define BTXIDLEINTERVAL 0xffff 1711#define BTXIDLEINTERVAL 0xffff
1711#define BOFDMSERVICE 0xffff0000 1712#define BOFDMSERVICE 0xffff0000
1712#define BTXMACHEADER 0xffffffff 1713#define BTXMACHEADER 0xffffffff
1713#define BTXDATAINIT 0xff 1714#define BTXDATAINIT 0xff
1714#define BTXHTMODE 0x100 1715#define BTXHTMODE 0x100
1715#define BTXDATATYPE 0x30000 1716#define BTXDATATYPE 0x30000
1716#define BTXRANDOMSEED 0xffffffff 1717#define BTXRANDOMSEED 0xffffffff
1717#define BCCKTXPREAMBLE 0x1 1718#define BCCKTXPREAMBLE 0x1
1718#define BCCKTXSFD 0xffff0000 1719#define BCCKTXSFD 0xffff0000
1719#define BCCKTXSIG 0xff 1720#define BCCKTXSIG 0xff
1720#define BCCKTXSERVICE 0xff00 1721#define BCCKTXSERVICE 0xff00
1721#define BCCKLENGTHEXT 0x8000 1722#define BCCKLENGTHEXT 0x8000
1722#define BCCKTXLENGHT 0xffff0000 1723#define BCCKTXLENGHT 0xffff0000
1723#define BCCKTXCRC16 0xffff 1724#define BCCKTXCRC16 0xffff
1724#define BCCKTXSTATUS 0x1 1725#define BCCKTXSTATUS 0x1
1725#define BOFDMTXSTATUS 0x2 1726#define BOFDMTXSTATUS 0x2
1726#define IS_BB_REG_OFFSET_92S(_offset) \ 1727#define IS_BB_REG_OFFSET_92S(_offset) \
1727 ((_offset >= 0x800) && (_offset <= 0xfff)) 1728 ((_offset >= 0x800) && (_offset <= 0xfff))
1728 1729
1729#define BRFMOD 0x1 1730#define BRFMOD 0x1
1730#define BJAPANMODE 0x2 1731#define BJAPANMODE 0x2
1731#define BCCKTXSC 0x30 1732#define BCCKTXSC 0x30
1732#define BCCKEN 0x1000000 1733#define BCCKEN 0x1000000
1733#define BOFDMEN 0x2000000 1734#define BOFDMEN 0x2000000
1734 1735
1735#define BOFDMRXADCPHASE 0x10000 1736#define BOFDMRXADCPHASE 0x10000
1736#define BOFDMTXDACPHASE 0x40000 1737#define BOFDMTXDACPHASE 0x40000
@@ -1824,13 +1825,13 @@
1824#define BDA6SWING 0x380000 1825#define BDA6SWING 0x380000
1825 1826
1826#define BADCLKPHASE 0x4000000 1827#define BADCLKPHASE 0x4000000
1827#define B80MCLKDELAY 0x18000000 1828#define B80MCLKDELAY 0x18000000
1828#define BAFEWATCHDOGENABLE 0x20000000 1829#define BAFEWATCHDOGENABLE 0x20000000
1829 1830
1830#define BXTALCAP01 0xc0000000 1831#define BXTALCAP01 0xc0000000
1831#define BXTALCAP23 0x3 1832#define BXTALCAP23 0x3
1832#define BXTALCAP92X 0x0f000000 1833#define BXTALCAP92X 0x0f000000
1833#define BXTALCAP 0x0f000000 1834#define BXTALCAP 0x0f000000
1834 1835
1835#define BINTDIFCLKENABLE 0x400 1836#define BINTDIFCLKENABLE 0x400
1836#define BEXTSIGCLKENABLE 0x800 1837#define BEXTSIGCLKENABLE 0x800
@@ -1857,7 +1858,7 @@
1857#define BCCKRX_AGC_FORMAT 0x200 1858#define BCCKRX_AGC_FORMAT 0x200
1858#define BPSDFFT_SAMPLE_POINT 0xc000 1859#define BPSDFFT_SAMPLE_POINT 0xc000
1859#define BPSD_AVERAGE_NUM 0x3000 1860#define BPSD_AVERAGE_NUM 0x3000
1860#define BIQPATH_CONTROL 0xc00 1861#define BIQPATH_CONTROL 0xc00
1861#define BPSD_FREQ 0x3ff 1862#define BPSD_FREQ 0x3ff
1862#define BPSD_ANTENNA_PATH 0x30 1863#define BPSD_ANTENNA_PATH 0x30
1863#define BPSD_IQ_SWITCH 0x40 1864#define BPSD_IQ_SWITCH 0x40
@@ -1957,300 +1958,316 @@
1957#define BCCK_DEFAULT_RXPATH 0xc000000 1958#define BCCK_DEFAULT_RXPATH 0xc000000
1958#define BCCK_OPTION_RXPATH 0x3000000 1959#define BCCK_OPTION_RXPATH 0x3000000
1959 1960
1960#define BNUM_OFSTF 0x3 1961#define BNUM_OFSTF 0x3
1961#define BSHIFT_L 0xc0 1962#define BSHIFT_L 0xc0
1962#define BGI_TH 0xc 1963#define BGI_TH 0xc
1963#define BRXPATH_A 0x1 1964#define BRXPATH_A 0x1
1964#define BRXPATH_B 0x2 1965#define BRXPATH_B 0x2
1965#define BRXPATH_C 0x4 1966#define BRXPATH_C 0x4
1966#define BRXPATH_D 0x8 1967#define BRXPATH_D 0x8
1967#define BTXPATH_A 0x1 1968#define BTXPATH_A 0x1
1968#define BTXPATH_B 0x2 1969#define BTXPATH_B 0x2
1969#define BTXPATH_C 0x4 1970#define BTXPATH_C 0x4
1970#define BTXPATH_D 0x8 1971#define BTXPATH_D 0x8
1971#define BTRSSI_FREQ 0x200 1972#define BTRSSI_FREQ 0x200
1972#define BADC_BACKOFF 0x3000 1973#define BADC_BACKOFF 0x3000
1973#define BDFIR_BACKOFF 0xc000 1974#define BDFIR_BACKOFF 0xc000
1974#define BTRSSI_LATCH_PHASE 0x10000 1975#define BTRSSI_LATCH_PHASE 0x10000
1975#define BRX_LDC_OFFSET 0xff 1976#define BRX_LDC_OFFSET 0xff
1976#define BRX_QDC_OFFSET 0xff00 1977#define BRX_QDC_OFFSET 0xff00
1977#define BRX_DFIR_MODE 0x1800000 1978#define BRX_DFIR_MODE 0x1800000
1978#define BRX_DCNF_TYPE 0xe000000 1979#define BRX_DCNF_TYPE 0xe000000
1979#define BRXIQIMB_A 0x3ff 1980#define BRXIQIMB_A 0x3ff
1980#define BRXIQIMB_B 0xfc00 1981#define BRXIQIMB_B 0xfc00
1981#define BRXIQIMB_C 0x3f0000 1982#define BRXIQIMB_C 0x3f0000
1982#define BRXIQIMB_D 0xffc00000 1983#define BRXIQIMB_D 0xffc00000
1983#define BDC_DC_NOTCH 0x60000 1984#define BDC_DC_NOTCH 0x60000
1984#define BRXNB_NOTCH 0x1f000000 1985#define BRXNB_NOTCH 0x1f000000
1985#define BPD_TH 0xf 1986#define BPD_TH 0xf
1986#define BPD_TH_OPT2 0xc000 1987#define BPD_TH_OPT2 0xc000
1987#define BPWED_TH 0x700 1988#define BPWED_TH 0x700
1988#define BIFMF_WIN_L 0x800 1989#define BIFMF_WIN_L 0x800
1989#define BPD_OPTION 0x1000 1990#define BPD_OPTION 0x1000
1990#define BMF_WIN_L 0xe000 1991#define BMF_WIN_L 0xe000
1991#define BBW_SEARCH_L 0x30000 1992#define BBW_SEARCH_L 0x30000
1992#define BWIN_ENH_L 0xc0000 1993#define BWIN_ENH_L 0xc0000
1993#define BBW_TH 0x700000 1994#define BBW_TH 0x700000
1994#define BED_TH2 0x3800000 1995#define BED_TH2 0x3800000
1995#define BBW_OPTION 0x4000000 1996#define BBW_OPTION 0x4000000
1996#define BRADIO_TH 0x18000000 1997#define BRADIO_TH 0x18000000
1997#define BWINDOW_L 0xe0000000 1998#define BWINDOW_L 0xe0000000
1998#define BSBD_OPTION 0x1 1999#define BSBD_OPTION 0x1
1999#define BFRAME_TH 0x1c 2000#define BFRAME_TH 0x1c
2000#define BFS_OPTION 0x60 2001#define BFS_OPTION 0x60
2001#define BDC_SLOPE_CHECK 0x80 2002#define BDC_SLOPE_CHECK 0x80
2002#define BFGUARD_COUNTER_DC_L 0xe00 2003#define BFGUARD_COUNTER_DC_L 0xe00
2003#define BFRAME_WEIGHT_SHORT 0x7000 2004#define BFRAME_WEIGHT_SHORT 0x7000
2004#define BSUB_TUNE 0xe00000 2005#define BSUB_TUNE 0xe00000
2005#define BFRAME_DC_LENGTH 0xe000000 2006#define BFRAME_DC_LENGTH 0xe000000
2006#define BSBD_START_OFFSET 0x30000000 2007#define BSBD_START_OFFSET 0x30000000
2007#define BFRAME_TH_2 0x7 2008#define BFRAME_TH_2 0x7
2008#define BFRAME_GI2_TH 0x38 2009#define BFRAME_GI2_TH 0x38
2009#define BGI2_SYNC_EN 0x40 2010#define BGI2_SYNC_EN 0x40
2010#define BSARCH_SHORT_EARLY 0x300 2011#define BSARCH_SHORT_EARLY 0x300
2011#define BSARCH_SHORT_LATE 0xc00 2012#define BSARCH_SHORT_LATE 0xc00
2012#define BSARCH_GI2_LATE 0x70000 2013#define BSARCH_GI2_LATE 0x70000
2013#define BCFOANTSUM 0x1 2014#define BCFOANTSUM 0x1
2014#define BCFOACC 0x2 2015#define BCFOACC 0x2
2015#define BCFOSTARTOFFSET 0xc 2016#define BCFOSTARTOFFSET 0xc
2016#define BCFOLOOPBACK 0x70 2017#define BCFOLOOPBACK 0x70
2017#define BCFOSUMWEIGHT 0x80 2018#define BCFOSUMWEIGHT 0x80
2018#define BDAGCENABLE 0x10000 2019#define BDAGCENABLE 0x10000
2019#define BTXIQIMB_A 0x3ff 2020#define BTXIQIMB_A 0x3ff
2020#define BTXIQIMB_b 0xfc00 2021#define BTXIQIMB_b 0xfc00
2021#define BTXIQIMB_C 0x3f0000 2022#define BTXIQIMB_C 0x3f0000
2022#define BTXIQIMB_D 0xffc00000 2023#define BTXIQIMB_D 0xffc00000
2023#define BTXIDCOFFSET 0xff 2024#define BTXIDCOFFSET 0xff
2024#define BTXIQDCOFFSET 0xff00 2025#define BTXIQDCOFFSET 0xff00
2025#define BTXDFIRMODE 0x10000 2026#define BTXDFIRMODE 0x10000
2026#define BTXPESUDO_NOISEON 0x4000000 2027#define BTXPESUDO_NOISEON 0x4000000
2027#define BTXPESUDO_NOISE_A 0xff 2028#define BTXPESUDO_NOISE_A 0xff
2028#define BTXPESUDO_NOISE_B 0xff00 2029#define BTXPESUDO_NOISE_B 0xff00
2029#define BTXPESUDO_NOISE_C 0xff0000 2030#define BTXPESUDO_NOISE_C 0xff0000
2030#define BTXPESUDO_NOISE_D 0xff000000 2031#define BTXPESUDO_NOISE_D 0xff000000
2031#define BCCA_DROPOPTION 0x20000 2032#define BCCA_DROPOPTION 0x20000
2032#define BCCA_DROPTHRES 0xfff00000 2033#define BCCA_DROPTHRES 0xfff00000
2033#define BEDCCA_H 0xf 2034#define BEDCCA_H 0xf
2034#define BEDCCA_L 0xf0 2035#define BEDCCA_L 0xf0
2035#define BLAMBDA_ED 0x300 2036#define BLAMBDA_ED 0x300
2036#define BRX_INITIALGAIN 0x7f 2037#define BRX_INITIALGAIN 0x7f
2037#define BRX_ANTDIV_EN 0x80 2038#define BRX_ANTDIV_EN 0x80
2038#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 2039#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
2039#define BRX_HIGHPOWER_FLOW 0x8000 2040#define BRX_HIGHPOWER_FLOW 0x8000
2040#define BRX_AGC_FREEZE_THRES 0xc0000 2041#define BRX_AGC_FREEZE_THRES 0xc0000
2041#define BRX_FREEZESTEP_AGC1 0x300000 2042#define BRX_FREEZESTEP_AGC1 0x300000
2042#define BRX_FREEZESTEP_AGC2 0xc00000 2043#define BRX_FREEZESTEP_AGC2 0xc00000
2043#define BRX_FREEZESTEP_AGC3 0x3000000 2044#define BRX_FREEZESTEP_AGC3 0x3000000
2044#define BRX_FREEZESTEP_AGC0 0xc000000 2045#define BRX_FREEZESTEP_AGC0 0xc000000
2045#define BRXRSSI_CMP_EN 0x10000000 2046#define BRXRSSI_CMP_EN 0x10000000
2046#define BRXQUICK_AGCEN 0x20000000 2047#define BRXQUICK_AGCEN 0x20000000
2047#define BRXAGC_FREEZE_THRES_MODE 0x40000000 2048#define BRXAGC_FREEZE_THRES_MODE 0x40000000
2048#define BRX_OVERFLOW_CHECKTYPE 0x80000000 2049#define BRX_OVERFLOW_CHECKTYPE 0x80000000
2049#define BRX_AGCSHIFT 0x7f 2050#define BRX_AGCSHIFT 0x7f
2050#define BTRSW_TRI_ONLY 0x80 2051#define BTRSW_TRI_ONLY 0x80
2051#define BPOWER_THRES 0x300 2052#define BPOWER_THRES 0x300
2052#define BRXAGC_EN 0x1 2053#define BRXAGC_EN 0x1
2053#define BRXAGC_TOGETHER_EN 0x2 2054#define BRXAGC_TOGETHER_EN 0x2
2054#define BRXAGC_MIN 0x4 2055#define BRXAGC_MIN 0x4
2055#define BRXHP_INI 0x7 2056#define BRXHP_INI 0x7
2056#define BRXHP_TRLNA 0x70 2057#define BRXHP_TRLNA 0x70
2057#define BRXHP_RSSI 0x700 2058#define BRXHP_RSSI 0x700
2058#define BRXHP_BBP1 0x7000 2059#define BRXHP_BBP1 0x7000
2059#define BRXHP_BBP2 0x70000 2060#define BRXHP_BBP2 0x70000
2060#define BRXHP_BBP3 0x700000 2061#define BRXHP_BBP3 0x700000
2061#define BRSSI_H 0x7f0000 2062#define BRSSI_H 0x7f0000
2062#define BRSSI_GEN 0x7f000000 2063#define BRSSI_GEN 0x7f000000
2063#define BRXSETTLE_TRSW 0x7 2064#define BRXSETTLE_TRSW 0x7
2064#define BRXSETTLE_LNA 0x38 2065#define BRXSETTLE_LNA 0x38
2065#define BRXSETTLE_RSSI 0x1c0 2066#define BRXSETTLE_RSSI 0x1c0
2066#define BRXSETTLE_BBP 0xe00 2067#define BRXSETTLE_BBP 0xe00
2067#define BRXSETTLE_RXHP 0x7000 2068#define BRXSETTLE_RXHP 0x7000
2068#define BRXSETTLE_ANTSW_RSSI 0x38000 2069#define BRXSETTLE_ANTSW_RSSI 0x38000
2069#define BRXSETTLE_ANTSW 0xc0000 2070#define BRXSETTLE_ANTSW 0xc0000
2070#define BRXPROCESS_TIME_DAGC 0x300000 2071#define BRXPROCESS_TIME_DAGC 0x300000
2071#define BRXSETTLE_HSSI 0x400000 2072#define BRXSETTLE_HSSI 0x400000
2072#define BRXPROCESS_TIME_BBPPW 0x800000 2073#define BRXPROCESS_TIME_BBPPW 0x800000
2073#define BRXANTENNA_POWER_SHIFT 0x3000000 2074#define BRXANTENNA_POWER_SHIFT 0x3000000
2074#define BRSSI_TABLE_SELECT 0xc000000 2075#define BRSSI_TABLE_SELECT 0xc000000
2075#define BRXHP_FINAL 0x7000000 2076#define BRXHP_FINAL 0x7000000
2076#define BRXHPSETTLE_BBP 0x7 2077#define BRXHPSETTLE_BBP 0x7
2077#define BRXHTSETTLE_HSSI 0x8 2078#define BRXHTSETTLE_HSSI 0x8
2078#define BRXHTSETTLE_RXHP 0x70 2079#define BRXHTSETTLE_RXHP 0x70
2079#define BRXHTSETTLE_BBPPW 0x80 2080#define BRXHTSETTLE_BBPPW 0x80
2080#define BRXHTSETTLE_IDLE 0x300 2081#define BRXHTSETTLE_IDLE 0x300
2081#define BRXHTSETTLE_RESERVED 0x1c00 2082#define BRXHTSETTLE_RESERVED 0x1c00
2082#define BRXHT_RXHP_EN 0x8000 2083#define BRXHT_RXHP_EN 0x8000
2083#define BRXAGC_FREEZE_THRES 0x30000 2084#define BRXAGC_FREEZE_THRES 0x30000
2084#define BRXAGC_TOGETHEREN 0x40000 2085#define BRXAGC_TOGETHEREN 0x40000
2085#define BRXHTAGC_MIN 0x80000 2086#define BRXHTAGC_MIN 0x80000
2086#define BRXHTAGC_EN 0x100000 2087#define BRXHTAGC_EN 0x100000
2087#define BRXHTDAGC_EN 0x200000 2088#define BRXHTDAGC_EN 0x200000
2088#define BRXHT_RXHP_BBP 0x1c00000 2089#define BRXHT_RXHP_BBP 0x1c00000
2089#define BRXHT_RXHP_FINAL 0xe0000000 2090#define BRXHT_RXHP_FINAL 0xe0000000
2090#define BRXPW_RADIO_TH 0x3 2091#define BRXPW_RADIO_TH 0x3
2091#define BRXPW_RADIO_EN 0x4 2092#define BRXPW_RADIO_EN 0x4
2092#define BRXMF_HOLD 0x3800 2093#define BRXMF_HOLD 0x3800
2093#define BRXPD_DELAY_TH1 0x38 2094#define BRXPD_DELAY_TH1 0x38
2094#define BRXPD_DELAY_TH2 0x1c0 2095#define BRXPD_DELAY_TH2 0x1c0
2095#define BRXPD_DC_COUNT_MAX 0x600 2096#define BRXPD_DC_COUNT_MAX 0x600
2096#define BRXPD_DELAY_TH 0x8000 2097#define BRXPD_DELAY_TH 0x8000
2097#define BRXPROCESS_DELAY 0xf0000 2098#define BRXPROCESS_DELAY 0xf0000
2098#define BRXSEARCHRANGE_GI2_EARLY 0x700000 2099#define BRXSEARCHRANGE_GI2_EARLY 0x700000
2099#define BRXFRAME_FUARD_COUNTER_L 0x3800000 2100#define BRXFRAME_FUARD_COUNTER_L 0x3800000
2100#define BRXSGI_GUARD_L 0xc000000 2101#define BRXSGI_GUARD_L 0xc000000
2101#define BRXSGI_SEARCH_L 0x30000000 2102#define BRXSGI_SEARCH_L 0x30000000
2102#define BRXSGI_TH 0xc0000000 2103#define BRXSGI_TH 0xc0000000
2103#define BDFSCNT0 0xff 2104#define BDFSCNT0 0xff
2104#define BDFSCNT1 0xff00 2105#define BDFSCNT1 0xff00
2105#define BDFSFLAG 0xf0000 2106#define BDFSFLAG 0xf0000
2106#define BMF_WEIGHT_SUM 0x300000 2107#define BMF_WEIGHT_SUM 0x300000
2107#define BMINIDX_TH 0x7f000000 2108#define BMINIDX_TH 0x7f000000
2108#define BDAFORMAT 0x40000 2109#define BDAFORMAT 0x40000
2109#define BTXCH_EMU_ENABLE 0x01000000 2110#define BTXCH_EMU_ENABLE 0x01000000
2110#define BTRSW_ISOLATION_A 0x7f 2111#define BTRSW_ISOLATION_A 0x7f
2111#define BTRSW_ISOLATION_B 0x7f00 2112#define BTRSW_ISOLATION_B 0x7f00
2112#define BTRSW_ISOLATION_C 0x7f0000 2113#define BTRSW_ISOLATION_C 0x7f0000
2113#define BTRSW_ISOLATION_D 0x7f000000 2114#define BTRSW_ISOLATION_D 0x7f000000
2114#define BEXT_LNA_GAIN 0x7c00 2115#define BEXT_LNA_GAIN 0x7c00
2115 2116
2116#define BSTBC_EN 0x4 2117#define BSTBC_EN 0x4
2117#define BANTENNA_MAPPING 0x10 2118#define BANTENNA_MAPPING 0x10
2118#define BNSS 0x20 2119#define BNSS 0x20
2119#define BCFO_ANTSUM_ID 0x200 2120#define BCFO_ANTSUM_ID 0x200
2120#define BPHY_COUNTER_RESET 0x8000000 2121#define BPHY_COUNTER_RESET 0x8000000
2121#define BCFO_REPORT_GET 0x4000000 2122#define BCFO_REPORT_GET 0x4000000
2122#define BOFDM_CONTINUE_TX 0x10000000 2123#define BOFDM_CONTINUE_TX 0x10000000
2123#define BOFDM_SINGLE_CARRIER 0x20000000 2124#define BOFDM_SINGLE_CARRIER 0x20000000
2124#define BOFDM_SINGLE_TONE 0x40000000 2125#define BOFDM_SINGLE_TONE 0x40000000
2125#define BHT_DETECT 0x100 2126#define BHT_DETECT 0x100
2126#define BCFOEN 0x10000 2127#define BCFOEN 0x10000
2127#define BCFOVALUE 0xfff00000 2128#define BCFOVALUE 0xfff00000
2128#define BSIGTONE_RE 0x3f 2129#define BSIGTONE_RE 0x3f
2129#define BSIGTONE_IM 0x7f00 2130#define BSIGTONE_IM 0x7f00
2130#define BCOUNTER_CCA 0xffff 2131#define BCOUNTER_CCA 0xffff
2131#define BCOUNTER_PARITYFAIL 0xffff0000 2132#define BCOUNTER_PARITYFAIL 0xffff0000
2132#define BCOUNTER_RATEILLEGAL 0xffff 2133#define BCOUNTER_RATEILLEGAL 0xffff
2133#define BCOUNTER_CRC8FAIL 0xffff0000 2134#define BCOUNTER_CRC8FAIL 0xffff0000
2134#define BCOUNTER_MCSNOSUPPORT 0xffff 2135#define BCOUNTER_MCSNOSUPPORT 0xffff
2135#define BCOUNTER_FASTSYNC 0xffff 2136#define BCOUNTER_FASTSYNC 0xffff
2136#define BSHORTCFO 0xfff 2137#define BSHORTCFO 0xfff
2137#define BSHORTCFOT_LENGTH 12 2138#define BSHORTCFOT_LENGTH 12
2138#define BSHORTCFOF_LENGTH 11 2139#define BSHORTCFOF_LENGTH 11
2139#define BLONGCFO 0x7ff 2140#define BLONGCFO 0x7ff
2140#define BLONGCFOT_LENGTH 11 2141#define BLONGCFOT_LENGTH 11
2141#define BLONGCFOF_LENGTH 11 2142#define BLONGCFOF_LENGTH 11
2142#define BTAILCFO 0x1fff 2143#define BTAILCFO 0x1fff
2143#define BTAILCFOT_LENGTH 13 2144#define BTAILCFOT_LENGTH 13
2144#define BTAILCFOF_LENGTH 12 2145#define BTAILCFOF_LENGTH 12
2145#define BNOISE_EN_PWDB 0xffff 2146#define BNOISE_EN_PWDB 0xffff
2146#define BCC_POWER_DB 0xffff0000 2147#define BCC_POWER_DB 0xffff0000
2147#define BMOISE_PWDB 0xffff 2148#define BMOISE_PWDB 0xffff
2148#define BPOWERMEAST_LENGTH 10 2149#define BPOWERMEAST_LENGTH 10
2149#define BPOWERMEASF_LENGTH 3 2150#define BPOWERMEASF_LENGTH 3
2150#define BRX_HT_BW 0x1 2151#define BRX_HT_BW 0x1
2151#define BRXSC 0x6 2152#define BRXSC 0x6
2152#define BRX_HT 0x8 2153#define BRX_HT 0x8
2153#define BNB_INTF_DET_ON 0x1 2154#define BNB_INTF_DET_ON 0x1
2154#define BINTF_WIN_LEN_CFG 0x30 2155#define BINTF_WIN_LEN_CFG 0x30
2155#define BNB_INTF_TH_CFG 0x1c0 2156#define BNB_INTF_TH_CFG 0x1c0
2156#define BRFGAIN 0x3f 2157#define BRFGAIN 0x3f
2157#define BTABLESEL 0x40 2158#define BTABLESEL 0x40
2158#define BTRSW 0x80 2159#define BTRSW 0x80
2159#define BRXSNR_A 0xff 2160#define BRXSNR_A 0xff
2160#define BRXSNR_B 0xff00 2161#define BRXSNR_B 0xff00
2161#define BRXSNR_C 0xff0000 2162#define BRXSNR_C 0xff0000
2162#define BRXSNR_D 0xff000000 2163#define BRXSNR_D 0xff000000
2163#define BSNR_EVMT_LENGTH 8 2164#define BSNR_EVMT_LENGTH 8
2164#define BSNR_EVMF_LENGTH 1 2165#define BSNR_EVMF_LENGTH 1
2165#define BCSI1ST 0xff 2166#define BCSI1ST 0xff
2166#define BCSI2ND 0xff00 2167#define BCSI2ND 0xff00
2167#define BRXEVM1ST 0xff0000 2168#define BRXEVM1ST 0xff0000
2168#define BRXEVM2ND 0xff000000 2169#define BRXEVM2ND 0xff000000
2169#define BSIGEVM 0xff 2170#define BSIGEVM 0xff
2170#define BPWDB 0xff00 2171#define BPWDB 0xff00
2171#define BSGIEN 0x10000 2172#define BSGIEN 0x10000
2172 2173
2173#define BSFACTOR_QMA1 0xf 2174#define BSFACTOR_QMA1 0xf
2174#define BSFACTOR_QMA2 0xf0 2175#define BSFACTOR_QMA2 0xf0
2175#define BSFACTOR_QMA3 0xf00 2176#define BSFACTOR_QMA3 0xf00
2176#define BSFACTOR_QMA4 0xf000 2177#define BSFACTOR_QMA4 0xf000
2177#define BSFACTOR_QMA5 0xf0000 2178#define BSFACTOR_QMA5 0xf0000
2178#define BSFACTOR_QMA6 0xf0000 2179#define BSFACTOR_QMA6 0xf0000
2179#define BSFACTOR_QMA7 0xf00000 2180#define BSFACTOR_QMA7 0xf00000
2180#define BSFACTOR_QMA8 0xf000000 2181#define BSFACTOR_QMA8 0xf000000
2181#define BSFACTOR_QMA9 0xf0000000 2182#define BSFACTOR_QMA9 0xf0000000
2182#define BCSI_SCHEME 0x100000 2183#define BCSI_SCHEME 0x100000
2183 2184
2184#define BNOISE_LVL_TOP_SET 0x3 2185#define BNOISE_LVL_TOP_SET 0x3
2185#define BCHSMOOTH 0x4 2186#define BCHSMOOTH 0x4
2186#define BCHSMOOTH_CFG1 0x38 2187#define BCHSMOOTH_CFG1 0x38
2187#define BCHSMOOTH_CFG2 0x1c0 2188#define BCHSMOOTH_CFG2 0x1c0
2188#define BCHSMOOTH_CFG3 0xe00 2189#define BCHSMOOTH_CFG3 0xe00
2189#define BCHSMOOTH_CFG4 0x7000 2190#define BCHSMOOTH_CFG4 0x7000
2190#define BMRCMODE 0x800000 2191#define BMRCMODE 0x800000
2191#define BTHEVMCFG 0x7000000 2192#define BTHEVMCFG 0x7000000
2192 2193
2193#define BLOOP_FIT_TYPE 0x1 2194#define BLOOP_FIT_TYPE 0x1
2194#define BUPD_CFO 0x40 2195#define BUPD_CFO 0x40
2195#define BUPD_CFO_OFFDATA 0x80 2196#define BUPD_CFO_OFFDATA 0x80
2196#define BADV_UPD_CFO 0x100 2197#define BADV_UPD_CFO 0x100
2197#define BADV_TIME_CTRL 0x800 2198#define BADV_TIME_CTRL 0x800
2198#define BUPD_CLKO 0x1000 2199#define BUPD_CLKO 0x1000
2199#define BFC 0x6000 2200#define BFC 0x6000
2200#define BTRACKING_MODE 0x8000 2201#define BTRACKING_MODE 0x8000
2201#define BPHCMP_ENABLE 0x10000 2202#define BPHCMP_ENABLE 0x10000
2202#define BUPD_CLKO_LTF 0x20000 2203#define BUPD_CLKO_LTF 0x20000
2203#define BCOM_CH_CFO 0x40000 2204#define BCOM_CH_CFO 0x40000
2204#define BCSI_ESTI_MODE 0x80000 2205#define BCSI_ESTI_MODE 0x80000
2205#define BADV_UPD_EQZ 0x100000 2206#define BADV_UPD_EQZ 0x100000
2206#define BUCHCFG 0x7000000 2207#define BUCHCFG 0x7000000
2207#define BUPDEQZ 0x8000000 2208#define BUPDEQZ 0x8000000
2208 2209
2209#define BRX_PESUDO_NOISE_ON 0x20000000 2210#define BRX_PESUDO_NOISE_ON 0x20000000
2210#define BRX_PESUDO_NOISE_A 0xff 2211#define BRX_PESUDO_NOISE_A 0xff
2211#define BRX_PESUDO_NOISE_B 0xff00 2212#define BRX_PESUDO_NOISE_B 0xff00
2212#define BRX_PESUDO_NOISE_C 0xff0000 2213#define BRX_PESUDO_NOISE_C 0xff0000
2213#define BRX_PESUDO_NOISE_D 0xff000000 2214#define BRX_PESUDO_NOISE_D 0xff000000
2214#define BRX_PESUDO_NOISESTATE_A 0xffff 2215#define BRX_PESUDO_NOISESTATE_A 0xffff
2215#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2216#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2216#define BRX_PESUDO_NOISESTATE_C 0xffff 2217#define BRX_PESUDO_NOISESTATE_C 0xffff
2217#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2218#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2218 2219
2219#define BZEBRA1_HSSIENABLE 0x8 2220#define BZEBRA1_HSSIENABLE 0x8
2220#define BZEBRA1_TRXCONTROL 0xc00 2221#define BZEBRA1_TRXCONTROL 0xc00
2221#define BZEBRA1_TRXGAINSETTING 0x07f 2222#define BZEBRA1_TRXGAINSETTING 0x07f
2222#define BZEBRA1_RXCOUNTER 0xc00 2223#define BZEBRA1_RXCOUNTER 0xc00
2223#define BZEBRA1_TXCHANGEPUMP 0x38 2224#define BZEBRA1_TXCHANGEPUMP 0x38
2224#define BZEBRA1_RXCHANGEPUMP 0x7 2225#define BZEBRA1_RXCHANGEPUMP 0x7
2225#define BZEBRA1_CHANNEL_NUM 0xf80 2226#define BZEBRA1_CHANNEL_NUM 0xf80
2226#define BZEBRA1_TXLPFBW 0x400 2227#define BZEBRA1_TXLPFBW 0x400
2227#define BZEBRA1_RXLPFBW 0x600 2228#define BZEBRA1_RXLPFBW 0x600
2228 2229
2229#define BRTL8256REG_MODE_CTRL1 0x100 2230#define BRTL8256REG_MODE_CTRL1 0x100
2230#define BRTL8256REG_MODE_CTRL0 0x40 2231#define BRTL8256REG_MODE_CTRL0 0x40
2231#define BRTL8256REG_TXLPFBW 0x18 2232#define BRTL8256REG_TXLPFBW 0x18
2232#define BRTL8256REG_RXLPFBW 0x600 2233#define BRTL8256REG_RXLPFBW 0x600
2233 2234
2234#define BRTL8258_TXLPFBW 0xc 2235#define BRTL8258_TXLPFBW 0xc
2235#define BRTL8258_RXLPFBW 0xc00 2236#define BRTL8258_RXLPFBW 0xc00
2236#define BRTL8258_RSSILPFBW 0xc0 2237#define BRTL8258_RSSILPFBW 0xc0
2237 2238
2238#define BBYTE0 0x1 2239#define BBYTE0 0x1
2239#define BBYTE1 0x2 2240#define BBYTE1 0x2
2240#define BBYTE2 0x4 2241#define BBYTE2 0x4
2241#define BBYTE3 0x8 2242#define BBYTE3 0x8
2242#define BWORD0 0x3 2243#define BWORD0 0x3
2243#define BWORD1 0xc 2244#define BWORD1 0xc
2244#define BWORD 0xf 2245#define BWORD 0xf
2245 2246
2246#define BENABLE 0x1 2247#define MASKBYTE0 0xff
2247#define BDISABLE 0x0 2248#define MASKBYTE1 0xff00
2248 2249#define MASKBYTE2 0xff0000
2249#define LEFT_ANTENNA 0x0 2250#define MASKBYTE3 0xff000000
2250#define RIGHT_ANTENNA 0x1 2251#define MASKHWORD 0xffff0000
2251 2252#define MASKLWORD 0x0000ffff
2252#define TCHECK_TXSTATUS 500 2253#define MASKDWORD 0xffffffff
2253#define TUPDATE_RXCOUNTER 100 2254#define MASK12BITS 0xfff
2255#define MASKH4BITS 0xf0000000
2256#define MASKOFDM_D 0xffc00000
2257#define MASKCCK 0x3f3f3f3f
2258
2259#define MASK4BITS 0x0f
2260#define MASK20BITS 0xfffff
2261#define RFREG_OFFSET_MASK 0xfffff
2262
2263#define BENABLE 0x1
2264#define BDISABLE 0x0
2265
2266#define LEFT_ANTENNA 0x0
2267#define RIGHT_ANTENNA 0x1
2268
2269#define TCHECK_TXSTATUS 500
2270#define TUPDATE_RXCOUNTER 100
2254 2271
2255#define REG_UN_used_register 0x01bf 2272#define REG_UN_used_register 0x01bf
2256 2273
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/rf.c b/drivers/net/wireless/rtlwifi/rtl8723be/rf.c
index 486294930a7b..5ed4492d3c80 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/rf.c
@@ -51,7 +51,7 @@ void rtl8723be_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
51 rtlphy->rfreg_chnlval[0]); 51 rtlphy->rfreg_chnlval[0]);
52 break; 52 break;
53 default: 53 default:
54 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 54 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
55 "unknown bandwidth: %#X\n", bandwidth); 55 "unknown bandwidth: %#X\n", bandwidth);
56 break; 56 break;
57 } 57 }
@@ -93,18 +93,20 @@ void rtl8723be_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
93 (ppowerlevel[idx1] << 16) | 93 (ppowerlevel[idx1] << 16) |
94 (ppowerlevel[idx1] << 24); 94 (ppowerlevel[idx1] << 24);
95 } 95 }
96
96 if (rtlefuse->eeprom_regulatory == 0) { 97 if (rtlefuse->eeprom_regulatory == 0) {
97 tmpval = 98 tmpval =
98 (rtlphy->mcs_offset[0][6]) + 99 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
99 (rtlphy->mcs_offset[0][7] << 8); 100 (rtlphy->mcs_txpwrlevel_origoffset[0][7] << 8);
100 tx_agc[RF90_PATH_A] += tmpval; 101 tx_agc[RF90_PATH_A] += tmpval;
101 102
102 tmpval = (rtlphy->mcs_offset[0][14]) + 103 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
103 (rtlphy->mcs_offset[0][15] << 104 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
104 24); 105 24);
105 tx_agc[RF90_PATH_B] += tmpval; 106 tx_agc[RF90_PATH_B] += tmpval;
106 } 107 }
107 } 108 }
109
108 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { 110 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
109 ptr = (u8 *)(&(tx_agc[idx1])); 111 ptr = (u8 *)(&(tx_agc[idx1]));
110 for (idx2 = 0; idx2 < 4; idx2++) { 112 for (idx2 = 0; idx2 < 4; idx2++) {
@@ -124,30 +126,32 @@ void rtl8723be_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
124 tmpval = tx_agc[RF90_PATH_A] & 0xff; 126 tmpval = tx_agc[RF90_PATH_A] & 0xff;
125 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); 127 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
126 128
127 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 129 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
128 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 130 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
129 RTXAGC_A_CCK1_MCS32); 131 RTXAGC_A_CCK1_MCS32);
130 132
131 tmpval = tx_agc[RF90_PATH_A] >> 8; 133 tmpval = tx_agc[RF90_PATH_A] >> 8;
132 134
135 /*tmpval = tmpval & 0xff00ffff;*/
136
133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); 137 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
134 138
135 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
136 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 140 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
137 RTXAGC_B_CCK11_A_CCK2_11); 141 RTXAGC_B_CCK11_A_CCK2_11);
138 142
139 tmpval = tx_agc[RF90_PATH_B] >> 24; 143 tmpval = tx_agc[RF90_PATH_B] >> 24;
140 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); 144 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
141 145
142 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 146 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
143 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 147 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
144 RTXAGC_B_CCK11_A_CCK2_11); 148 RTXAGC_B_CCK11_A_CCK2_11);
145 149
146 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; 150 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
147 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); 151 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
148 152
149 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 153 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
150 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 154 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
151 RTXAGC_B_CCK1_55_MCS32); 155 RTXAGC_B_CCK1_55_MCS32);
152} 156}
153 157
@@ -169,8 +173,8 @@ static void rtl8723be_phy_get_power_base(struct ieee80211_hw *hw,
169 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | 173 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
170 (powerbase0 << 8) | powerbase0; 174 (powerbase0 << 8) | powerbase0;
171 *(ofdmbase + i) = powerbase0; 175 *(ofdmbase + i) = powerbase0;
172 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 176 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
173 " [OFDM power base index rf(%c) = 0x%x]\n", 177 " [OFDM power base index rf(%c) = 0x%x]\n",
174 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)); 178 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
175 } 179 }
176 180
@@ -179,27 +183,30 @@ static void rtl8723be_phy_get_power_base(struct ieee80211_hw *hw,
179 powerlevel[i] = ppowerlevel_bw20[i]; 183 powerlevel[i] = ppowerlevel_bw20[i];
180 else 184 else
181 powerlevel[i] = ppowerlevel_bw40[i]; 185 powerlevel[i] = ppowerlevel_bw40[i];
186
182 powerbase1 = powerlevel[i]; 187 powerbase1 = powerlevel[i];
183 powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) | 188 powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
184 (powerbase1 << 8) | powerbase1; 189 (powerbase1 << 8) | powerbase1;
185 190
186 *(mcsbase + i) = powerbase1; 191 *(mcsbase + i) = powerbase1;
187 192
188 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 193 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
189 " [MCS power base index rf(%c) = 0x%x]\n", 194 " [MCS power base index rf(%c) = 0x%x]\n",
190 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)); 195 ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
191 } 196 }
192} 197}
193 198
194static void txpwr_by_regulatory(struct ieee80211_hw *hw, u8 channel, u8 index, 199static void _rtl8723be_get_txpower_writeval_by_regulatory(
195 u32 *powerbase0, u32 *powerbase1, 200 struct ieee80211_hw *hw,
196 u32 *p_outwriteval) 201 u8 channel, u8 index,
202 u32 *powerbase0,
203 u32 *powerbase1,
204 u32 *p_outwriteval)
197{ 205{
198 struct rtl_priv *rtlpriv = rtl_priv(hw); 206 struct rtl_priv *rtlpriv = rtl_priv(hw);
199 struct rtl_phy *rtlphy = &(rtlpriv->phy); 207 struct rtl_phy *rtlphy = &(rtlpriv->phy);
200 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 208 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
201 u8 i, chnlgroup = 0, pwr_diff_limit[4]; 209 u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
202 u8 pwr_diff = 0, customer_pwr_diff;
203 u32 writeval, customer_limit, rf; 210 u32 writeval, customer_limit, rf;
204 211
205 for (rf = 0; rf < 2; rf++) { 212 for (rf = 0; rf < 2; rf++) {
@@ -208,13 +215,13 @@ static void txpwr_by_regulatory(struct ieee80211_hw *hw, u8 channel, u8 index,
208 chnlgroup = 0; 215 chnlgroup = 0;
209 216
210 writeval = 217 writeval =
211 rtlphy->mcs_offset[chnlgroup][index + (rf ? 8 : 0)] 218 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
219 (rf ? 8 : 0)]
212 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); 220 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
213 221
214 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 222 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
215 "RTK better performance, " 223 "RTK better performance, writeval(%c) = 0x%x\n",
216 "writeval(%c) = 0x%x\n", 224 ((rf == 0) ? 'A' : 'B'), writeval);
217 ((rf == 0) ? 'A' : 'B'), writeval);
218 break; 225 break;
219 case 1: 226 case 1:
220 if (rtlphy->pwrgroup_cnt == 1) { 227 if (rtlphy->pwrgroup_cnt == 1) {
@@ -233,43 +240,41 @@ static void txpwr_by_regulatory(struct ieee80211_hw *hw, u8 channel, u8 index,
233 else if (channel == 14) 240 else if (channel == 14)
234 chnlgroup = 5; 241 chnlgroup = 5;
235 } 242 }
236 writeval = rtlphy->mcs_offset[chnlgroup] 243
244 writeval =
245 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
237 [index + (rf ? 8 : 0)] + ((index < 2) ? 246 [index + (rf ? 8 : 0)] + ((index < 2) ?
238 powerbase0[rf] : 247 powerbase0[rf] :
239 powerbase1[rf]); 248 powerbase1[rf]);
240 249
241 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 250 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
242 "Realtek regulatory, 20MHz, " 251 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
243 "writeval(%c) = 0x%x\n", 252 ((rf == 0) ? 'A' : 'B'), writeval);
244 ((rf == 0) ? 'A' : 'B'), writeval);
245 253
246 break; 254 break;
247 case 2: 255 case 2:
248 writeval = 256 writeval =
249 ((index < 2) ? powerbase0[rf] : powerbase1[rf]); 257 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
250 258
251 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 259 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
252 "Better regulatory, " 260 "Better regulatory, writeval(%c) = 0x%x\n",
253 "writeval(%c) = 0x%x\n", 261 ((rf == 0) ? 'A' : 'B'), writeval);
254 ((rf == 0) ? 'A' : 'B'), writeval);
255 break; 262 break;
256 case 3: 263 case 3:
257 chnlgroup = 0; 264 chnlgroup = 0;
258 265
259 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 266 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
260 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 267 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
261 "customer's limit, 40MHz " 268 "customer's limit, 40MHz rf(%c) = 0x%x\n",
262 "rf(%c) = 0x%x\n", 269 ((rf == 0) ? 'A' : 'B'),
263 ((rf == 0) ? 'A' : 'B'), 270 rtlefuse->pwrgroup_ht40
264 rtlefuse->pwrgroup_ht40[rf] 271 [rf][channel - 1]);
265 [channel-1]);
266 } else { 272 } else {
267 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 273 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
268 "customer's limit, 20MHz " 274 "customer's limit, 20MHz rf(%c) = 0x%x\n",
269 "rf(%c) = 0x%x\n", 275 ((rf == 0) ? 'A' : 'B'),
270 ((rf == 0) ? 'A' : 'B'), 276 rtlefuse->pwrgroup_ht20
271 rtlefuse->pwrgroup_ht20[rf] 277 [rf][channel - 1]);
272 [channel-1]);
273 } 278 }
274 279
275 if (index < 2) 280 if (index < 2)
@@ -294,9 +299,9 @@ static void txpwr_by_regulatory(struct ieee80211_hw *hw, u8 channel, u8 index,
294 299
295 for (i = 0; i < 4; i++) { 300 for (i = 0; i < 4; i++) {
296 pwr_diff_limit[i] = 301 pwr_diff_limit[i] =
297 (u8)((rtlphy->mcs_offset 302 (u8)((rtlphy->mcs_txpwrlevel_origoffset
298 [chnlgroup][index + (rf ? 8 : 0)] & 303 [chnlgroup][index + (rf ? 8 : 0)] &
299 (0x7f << (i * 8))) >> (i * 8)); 304 (0x7f << (i * 8))) >> (i * 8));
300 305
301 if (pwr_diff_limit[i] > pwr_diff) 306 if (pwr_diff_limit[i] > pwr_diff)
302 pwr_diff_limit[i] = pwr_diff; 307 pwr_diff_limit[i] = pwr_diff;
@@ -307,29 +312,28 @@ static void txpwr_by_regulatory(struct ieee80211_hw *hw, u8 channel, u8 index,
307 (pwr_diff_limit[1] << 8) | 312 (pwr_diff_limit[1] << 8) |
308 (pwr_diff_limit[0]); 313 (pwr_diff_limit[0]);
309 314
310 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 315 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
311 "Customer's limit rf(%c) = 0x%x\n", 316 "Customer's limit rf(%c) = 0x%x\n",
312 ((rf == 0) ? 'A' : 'B'), customer_limit); 317 ((rf == 0) ? 'A' : 'B'), customer_limit);
313 318
314 writeval = customer_limit + ((index < 2) ? 319 writeval = customer_limit + ((index < 2) ?
315 powerbase0[rf] : 320 powerbase0[rf] :
316 powerbase1[rf]); 321 powerbase1[rf]);
317 322
318 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 323 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
319 "Customer, writeval rf(%c)= 0x%x\n", 324 "Customer, writeval rf(%c)= 0x%x\n",
320 ((rf == 0) ? 'A' : 'B'), writeval); 325 ((rf == 0) ? 'A' : 'B'), writeval);
321 break; 326 break;
322 default: 327 default:
323 chnlgroup = 0; 328 chnlgroup = 0;
324 writeval = 329 writeval =
325 rtlphy->mcs_offset[chnlgroup] 330 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
326 [index + (rf ? 8 : 0)] 331 [index + (rf ? 8 : 0)]
327 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); 332 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
328 333
329 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 334 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
330 "RTK better performance, writeval " 335 "RTK better performance, writeval rf(%c) = 0x%x\n",
331 "rf(%c) = 0x%x\n", 336 ((rf == 0) ? 'A' : 'B'), writeval);
332 ((rf == 0) ? 'A' : 'B'), writeval);
333 break; 337 break;
334 } 338 }
335 339
@@ -343,7 +347,7 @@ static void txpwr_by_regulatory(struct ieee80211_hw *hw, u8 channel, u8 index,
343} 347}
344 348
345static void _rtl8723be_write_ofdm_power_reg(struct ieee80211_hw *hw, 349static void _rtl8723be_write_ofdm_power_reg(struct ieee80211_hw *hw,
346 u8 index, u32 *value) 350 u8 index, u32 *pvalue)
347{ 351{
348 struct rtl_priv *rtlpriv = rtl_priv(hw); 352 struct rtl_priv *rtlpriv = rtl_priv(hw);
349 u16 regoffset_a[6] = { 353 u16 regoffset_a[6] = {
@@ -361,9 +365,9 @@ static void _rtl8723be_write_ofdm_power_reg(struct ieee80211_hw *hw,
361 u16 regoffset; 365 u16 regoffset;
362 366
363 for (rf = 0; rf < 2; rf++) { 367 for (rf = 0; rf < 2; rf++) {
364 writeval = value[rf]; 368 writeval = pvalue[rf];
365 for (i = 0; i < 4; i++) { 369 for (i = 0; i < 4; i++) {
366 pwr_val[i] = (u8) ((writeval & (0x7f << 370 pwr_val[i] = (u8)((writeval & (0x7f <<
367 (i * 8))) >> (i * 8)); 371 (i * 8))) >> (i * 8));
368 372
369 if (pwr_val[i] > RF6052_MAX_TX_PWR) 373 if (pwr_val[i] > RF6052_MAX_TX_PWR)
@@ -378,8 +382,8 @@ static void _rtl8723be_write_ofdm_power_reg(struct ieee80211_hw *hw,
378 regoffset = regoffset_b[index]; 382 regoffset = regoffset_b[index];
379 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); 383 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
380 384
381 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 385 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
382 "Set 0x%x = %08x\n", regoffset, writeval); 386 "Set 0x%x = %08x\n", regoffset, writeval);
383 } 387 }
384} 388}
385 389
@@ -400,8 +404,11 @@ void rtl8723be_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
400 rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value); 404 rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
401 405
402 for (index = 0; index < 6; index++) { 406 for (index = 0; index < 6; index++) {
403 txpwr_by_regulatory(hw, channel, index, &powerbase0[0], 407 _rtl8723be_get_txpower_writeval_by_regulatory(hw,
404 &powerbase1[0], &writeval[0]); 408 channel, index,
409 &powerbase0[0],
410 &powerbase1[0],
411 &writeval[0]);
405 if (direction == 1) { 412 if (direction == 1) {
406 writeval[0] += pwrtrac_value; 413 writeval[0] += pwrtrac_value;
407 writeval[1] += pwrtrac_value; 414 writeval[1] += pwrtrac_value;
@@ -424,16 +431,17 @@ bool rtl8723be_phy_rf6052_config(struct ieee80211_hw *hw)
424 rtlphy->num_total_rfpath = 2; 431 rtlphy->num_total_rfpath = 2;
425 432
426 return _rtl8723be_phy_rf6052_config_parafile(hw); 433 return _rtl8723be_phy_rf6052_config_parafile(hw);
434
427} 435}
428 436
429static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw) 437static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
430{ 438{
431 struct rtl_priv *rtlpriv = rtl_priv(hw); 439 struct rtl_priv *rtlpriv = rtl_priv(hw);
432 struct rtl_phy *rtlphy = &(rtlpriv->phy); 440 struct rtl_phy *rtlphy = &(rtlpriv->phy);
433 struct bb_reg_def *pphyreg;
434 u32 u4_regvalue = 0; 441 u32 u4_regvalue = 0;
435 u8 rfpath; 442 u8 rfpath;
436 bool rtstatus = true; 443 bool rtstatus = true;
444 struct bb_reg_def *pphyreg;
437 445
438 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { 446 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
439 pphyreg = &rtlphy->phyreg_def[rfpath]; 447 pphyreg = &rtlphy->phyreg_def[rfpath];
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/sw.c b/drivers/net/wireless/rtlwifi/rtl8723be/sw.c
index 8b4a5f3e8e82..223eb42992bd 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/sw.c
@@ -31,6 +31,7 @@
31#include "phy.h" 31#include "phy.h"
32#include "../rtl8723com/phy_common.h" 32#include "../rtl8723com/phy_common.h"
33#include "dm.h" 33#include "dm.h"
34#include "../rtl8723com/dm_common.h"
34#include "hw.h" 35#include "hw.h"
35#include "fw.h" 36#include "fw.h"
36#include "../rtl8723com/fw_common.h" 37#include "../rtl8723com/fw_common.h"
@@ -101,6 +102,8 @@ int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
101 rtlpriv->dm.thermalvalue = 0; 102 rtlpriv->dm.thermalvalue = 0;
102 rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25); 103 rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
103 104
105 rtlpriv->phy.lck_inprogress = false;
106
104 mac->ht_enable = true; 107 mac->ht_enable = true;
105 108
106 /* compatible 5G band 88ce just 2.4G band & smsp */ 109 /* compatible 5G band 88ce just 2.4G band & smsp */
@@ -137,12 +140,19 @@ int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
137 140
138 rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0); 141 rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
139 142
143 rtlpci->sys_irq_mask = (u32)(HSIMR_PDN_INT_EN |
144 HSIMR_RON_INT_EN |
145 0);
146
140 /* for debug level */ 147 /* for debug level */
141 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 148 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
142 /* for LPS & IPS */ 149 /* for LPS & IPS */
143 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 150 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
144 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 151 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
145 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 152 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
153 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
154 if (rtlpriv->cfg->mod_params->disable_watchdog)
155 pr_info("watchdog disabled\n");
146 rtlpriv->psc.reg_fwctrl_lps = 3; 156 rtlpriv->psc.reg_fwctrl_lps = 3;
147 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 157 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
148 /* for ASPM, you can close aspm through 158 /* for ASPM, you can close aspm through
@@ -157,6 +167,11 @@ int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
157 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 167 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
158 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 168 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
159 169
170 /*low power: Disable 32k */
171 rtlpriv->psc.low_power_enable = false;
172
173 rtlpriv->rtlhal.earlymode_enable = false;
174
160 /* for firmware buf */ 175 /* for firmware buf */
161 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 176 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
162 if (!rtlpriv->rtlhal.pfirmware) { 177 if (!rtlpriv->rtlhal.pfirmware) {
@@ -182,8 +197,6 @@ void rtl8723be_deinit_sw_vars(struct ieee80211_hw *hw)
182{ 197{
183 struct rtl_priv *rtlpriv = rtl_priv(hw); 198 struct rtl_priv *rtlpriv = rtl_priv(hw);
184 199
185 if (rtlpriv->cfg->ops->get_btc_status())
186 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
187 if (rtlpriv->rtlhal.pfirmware) { 200 if (rtlpriv->rtlhal.pfirmware) {
188 vfree(rtlpriv->rtlhal.pfirmware); 201 vfree(rtlpriv->rtlhal.pfirmware);
189 rtlpriv->rtlhal.pfirmware = NULL; 202 rtlpriv->rtlhal.pfirmware = NULL;
@@ -245,6 +258,7 @@ static struct rtl_hal_ops rtl8723be_hal_ops = {
245 .set_rfreg = rtl8723be_phy_set_rf_reg, 258 .set_rfreg = rtl8723be_phy_set_rf_reg,
246 .fill_h2c_cmd = rtl8723be_fill_h2c_cmd, 259 .fill_h2c_cmd = rtl8723be_fill_h2c_cmd,
247 .get_btc_status = rtl8723be_get_btc_status, 260 .get_btc_status = rtl8723be_get_btc_status,
261 .rx_command_packet = rtl8723be_rx_command_packet,
248 .is_fw_header = is_fw_header, 262 .is_fw_header = is_fw_header,
249}; 263};
250 264
@@ -253,8 +267,6 @@ static struct rtl_mod_params rtl8723be_mod_params = {
253 .inactiveps = true, 267 .inactiveps = true,
254 .swctrl_lps = false, 268 .swctrl_lps = false,
255 .fwctrl_lps = true, 269 .fwctrl_lps = true,
256 .msi_support = false,
257 .debug = DBG_EMERG,
258}; 270};
259 271
260static struct rtl_hal_cfg rtl8723be_hal_cfg = { 272static struct rtl_hal_cfg rtl8723be_hal_cfg = {
@@ -272,6 +284,9 @@ static struct rtl_hal_cfg rtl8723be_hal_cfg = {
272 .maps[MAC_RCR_ACRC32] = ACRC32, 284 .maps[MAC_RCR_ACRC32] = ACRC32,
273 .maps[MAC_RCR_ACF] = ACF, 285 .maps[MAC_RCR_ACF] = ACF,
274 .maps[MAC_RCR_AAP] = AAP, 286 .maps[MAC_RCR_AAP] = AAP,
287 .maps[MAC_HIMR] = REG_HIMR,
288 .maps[MAC_HIMRE] = REG_HIMRE,
289 .maps[MAC_HSISR] = REG_HSISR,
275 290
276 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS, 291 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
277 292
@@ -305,6 +320,7 @@ static struct rtl_hal_cfg rtl8723be_hal_cfg = {
305 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 320 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
306 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 321 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
307 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 322 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
323/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
308 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 324 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
309 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 325 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
310 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 326 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
@@ -312,6 +328,8 @@ static struct rtl_hal_cfg rtl8723be_hal_cfg = {
312 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 328 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
313 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 329 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
314 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 330 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
331/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
332/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
315 333
316 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 334 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
317 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 335 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
@@ -329,6 +347,7 @@ static struct rtl_hal_cfg rtl8723be_hal_cfg = {
329 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 347 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
330 .maps[RTL_IMR_VODOK] = IMR_VODOK, 348 .maps[RTL_IMR_VODOK] = IMR_VODOK,
331 .maps[RTL_IMR_ROK] = IMR_ROK, 349 .maps[RTL_IMR_ROK] = IMR_ROK,
350 .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
332 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER), 351 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
333 352
334 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M, 353 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
@@ -348,12 +367,12 @@ static struct rtl_hal_cfg rtl8723be_hal_cfg = {
348 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15, 367 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
349}; 368};
350 369
351static const struct pci_device_id rtl8723be_pci_id[] = { 370static struct pci_device_id rtl8723be_pci_ids[] = {
352 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb723, rtl8723be_hal_cfg)}, 371 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xB723, rtl8723be_hal_cfg)},
353 {}, 372 {},
354}; 373};
355 374
356MODULE_DEVICE_TABLE(pci, rtl8723be_pci_id); 375MODULE_DEVICE_TABLE(pci, rtl8723be_pci_ids);
357 376
358MODULE_AUTHOR("PageHe <page_he@realsil.com.cn>"); 377MODULE_AUTHOR("PageHe <page_he@realsil.com.cn>");
359MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 378MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
@@ -366,21 +385,22 @@ module_param_named(debug, rtl8723be_mod_params.debug, int, 0444);
366module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444); 385module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444);
367module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444); 386module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444);
368module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444); 387module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444);
369module_param_named(msi, rtl8723be_mod_params.msi_support, bool, 0444); 388module_param_named(disable_watchdog, rtl8723be_mod_params.disable_watchdog,
389 bool, 0444);
370MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n"); 390MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
371MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n"); 391MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
372MODULE_PARM_DESC(fwlps, "using linked fw control power save (default 1 is open)\n"); 392MODULE_PARM_DESC(fwlps, "using linked fw control power save (default 1 is open)\n");
373MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n"); 393MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
374MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 394MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
395MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
375 396
376static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 397static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
377 398
378static struct pci_driver rtl8723be_driver = { 399static struct pci_driver rtl8723be_driver = {
379 .name = KBUILD_MODNAME, 400 .name = KBUILD_MODNAME,
380 .id_table = rtl8723be_pci_id, 401 .id_table = rtl8723be_pci_ids,
381 .probe = rtl_pci_probe, 402 .probe = rtl_pci_probe,
382 .remove = rtl_pci_disconnect, 403 .remove = rtl_pci_disconnect,
383
384 .driver.pm = &rtlwifi_pm_ops, 404 .driver.pm = &rtlwifi_pm_ops,
385}; 405};
386 406
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/table.c b/drivers/net/wireless/rtlwifi/rtl8723be/table.c
index 4b283cde042e..a180761e8810 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/table.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/table.c
@@ -27,200 +27,201 @@
27 27
28#include "table.h" 28#include "table.h"
29u32 RTL8723BEPHY_REG_1TARRAY[] = { 29u32 RTL8723BEPHY_REG_1TARRAY[] = {
30 0x800, 0x80040000, 30 0x800, 0x80040000,
31 0x804, 0x00000003, 31 0x804, 0x00000003,
32 0x808, 0x0000FC00, 32 0x808, 0x0000FC00,
33 0x80C, 0x0000000A, 33 0x80C, 0x0000000A,
34 0x810, 0x10001331, 34 0x810, 0x10001331,
35 0x814, 0x020C3D10, 35 0x814, 0x020C3D10,
36 0x818, 0x02200385, 36 0x818, 0x02200385,
37 0x81C, 0x00000000, 37 0x81C, 0x00000000,
38 0x820, 0x01000100, 38 0x820, 0x01000100,
39 0x824, 0x00390204, 39 0x824, 0x00390204,
40 0x828, 0x00000000, 40 0x828, 0x00000000,
41 0x82C, 0x00000000, 41 0x82C, 0x00000000,
42 0x830, 0x00000000, 42 0x830, 0x00000000,
43 0x834, 0x00000000, 43 0x834, 0x00000000,
44 0x838, 0x00000000, 44 0x838, 0x00000000,
45 0x83C, 0x00000000, 45 0x83C, 0x00000000,
46 0x840, 0x00010000, 46 0x840, 0x00010000,
47 0x844, 0x00000000, 47 0x844, 0x00000000,
48 0x848, 0x00000000, 48 0x848, 0x00000000,
49 0x84C, 0x00000000, 49 0x84C, 0x00000000,
50 0x850, 0x00000000, 50 0x850, 0x00000000,
51 0x854, 0x00000000, 51 0x854, 0x00000000,
52 0x858, 0x569A11A9, 52 0x858, 0x569A11A9,
53 0x85C, 0x01000014, 53 0x85C, 0x01000014,
54 0x860, 0x66F60110, 54 0x860, 0x66F60110,
55 0x864, 0x061F0649, 55 0x864, 0x061F0649,
56 0x868, 0x00000000, 56 0x868, 0x00000000,
57 0x86C, 0x27272700, 57 0x86C, 0x27272700,
58 0x870, 0x07000760, 58 0x870, 0x07000760,
59 0x874, 0x25004000, 59 0x874, 0x25004000,
60 0x878, 0x00000808, 60 0x878, 0x00000808,
61 0x87C, 0x00000000, 61 0x87C, 0x00000000,
62 0x880, 0xB0000C1C, 62 0x880, 0xB0000C1C,
63 0x884, 0x00000001, 63 0x884, 0x00000001,
64 0x888, 0x00000000, 64 0x888, 0x00000000,
65 0x88C, 0xCCC000C0, 65 0x88C, 0xCCC000C0,
66 0x890, 0x00000800, 66 0x890, 0x00000800,
67 0x894, 0xFFFFFFFE, 67 0x894, 0xFFFFFFFE,
68 0x898, 0x40302010, 68 0x898, 0x40302010,
69 0x89C, 0x00706050, 69 0x89C, 0x00706050,
70 0x900, 0x00000000, 70 0x900, 0x00000000,
71 0x904, 0x00000023, 71 0x904, 0x00000023,
72 0x908, 0x00000000, 72 0x908, 0x00000000,
73 0x90C, 0x81121111, 73 0x90C, 0x81121111,
74 0x910, 0x00000002, 74 0x910, 0x00000002,
75 0x914, 0x00000201, 75 0x914, 0x00000201,
76 0x948, 0x00000000, 76 0x948, 0x00000280,
77 0xA00, 0x00D047C8, 77 0xA00, 0x00D047C8,
78 0xA04, 0x80FF000C, 78 0xA04, 0x80FF000C,
79 0xA08, 0x8C838300, 79 0xA08, 0x8C838300,
80 0xA0C, 0x2E7F120F, 80 0xA0C, 0x2E7F120F,
81 0xA10, 0x9500BB78, 81 0xA10, 0x9500BB78,
82 0xA14, 0x1114D028, 82 0xA14, 0x1114D028,
83 0xA18, 0x00881117, 83 0xA18, 0x00881117,
84 0xA1C, 0x89140F00, 84 0xA1C, 0x89140F00,
85 0xA20, 0x1A1B0000, 85 0xA20, 0x1A1B0000,
86 0xA24, 0x090E1317, 86 0xA24, 0x090E1317,
87 0xA28, 0x00000204, 87 0xA28, 0x00000204,
88 0xA2C, 0x00D30000, 88 0xA2C, 0x00D30000,
89 0xA70, 0x101FBF00, 89 0xA70, 0x101FBF00,
90 0xA74, 0x00000007, 90 0xA74, 0x00000007,
91 0xA78, 0x00000900, 91 0xA78, 0x00000900,
92 0xA7C, 0x225B0606, 92 0xA7C, 0x225B0606,
93 0xA80, 0x21806490, 93 0xA80, 0x21806490,
94 0xB2C, 0x00000000, 94 0xB2C, 0x00000000,
95 0xC00, 0x48071D40, 95 0xC00, 0x48071D40,
96 0xC04, 0x03A05611, 96 0xC04, 0x03A05611,
97 0xC08, 0x000000E4, 97 0xC08, 0x000000E4,
98 0xC0C, 0x6C6C6C6C, 98 0xC0C, 0x6C6C6C6C,
99 0xC10, 0x08800000, 99 0xC10, 0x08800000,
100 0xC14, 0x40000100, 100 0xC14, 0x40000100,
101 0xC18, 0x08800000, 101 0xC18, 0x08800000,
102 0xC1C, 0x40000100, 102 0xC1C, 0x40000100,
103 0xC20, 0x00000000, 103 0xC20, 0x00000000,
104 0xC24, 0x00000000, 104 0xC24, 0x00000000,
105 0xC28, 0x00000000, 105 0xC28, 0x00000000,
106 0xC2C, 0x00000000, 106 0xC2C, 0x00000000,
107 0xC30, 0x69E9AC44, 107 0xC30, 0x69E9AC44,
108 0xC34, 0x469652AF, 108 0xC34, 0x469652AF,
109 0xC38, 0x49795994, 109 0xC38, 0x49795994,
110 0xC3C, 0x0A97971C, 110 0xC3C, 0x0A97971C,
111 0xC40, 0x1F7C403F, 111 0xC40, 0x1F7C403F,
112 0xC44, 0x000100B7, 112 0xC44, 0x000100B7,
113 0xC48, 0xEC020107, 113 0xC48, 0xEC020107,
114 0xC4C, 0x007F037F, 114 0xC4C, 0x007F037F,
115 0xC50, 0x69553420, 115 0xC50, 0x69553420,
116 0xC54, 0x43BC0094, 116 0xC54, 0x43BC0094,
117 0xC58, 0x00023169, 117 0xC58, 0x00023169,
118 0xC5C, 0x00250492, 118 0xC5C, 0x00250492,
119 0xC60, 0x00000000, 119 0xC60, 0x00000000,
120 0xC64, 0x7112848B, 120 0xC64, 0x7112848B,
121 0xC68, 0x47C00BFF, 121 0xC68, 0x47C00BFF,
122 0xC6C, 0x00000036, 122 0xC6C, 0x00000036,
123 0xC70, 0x2C7F000D, 123 0xC70, 0x2C7F000D,
124 0xC74, 0x020610DB, 124 0xC74, 0x020610DB,
125 0xC78, 0x0000001F, 125 0xC78, 0x0000001F,
126 0xC7C, 0x00B91612, 126 0xC7C, 0x00B91612,
127 0xC80, 0x390000E4, 127 0xC80, 0x390000E4,
128 0xC84, 0x20F60000, 128 0xC84, 0x20F60000,
129 0xC88, 0x40000100, 129 0xC88, 0x40000100,
130 0xC8C, 0x20200000, 130 0xC8C, 0x20200000,
131 0xC90, 0x00020E1A, 131 0xC90, 0x00020E1A,
132 0xC94, 0x00000000, 132 0xC94, 0x00000000,
133 0xC98, 0x00020E1A, 133 0xC98, 0x00020E1A,
134 0xC9C, 0x00007F7F, 134 0xC9C, 0x00007F7F,
135 0xCA0, 0x00000000, 135 0xCA0, 0x00000000,
136 0xCA4, 0x000300A0, 136 0xCA4, 0x000300A0,
137 0xCA8, 0x00000000, 137 0xCA8, 0x00000000,
138 0xCAC, 0x00000000, 138 0xCAC, 0x00000000,
139 0xCB0, 0x00000000, 139 0xCB0, 0x00000000,
140 0xCB4, 0x00000000, 140 0xCB4, 0x00000000,
141 0xCB8, 0x00000000, 141 0xCB8, 0x00000000,
142 0xCBC, 0x28000000, 142 0xCBC, 0x28000000,
143 0xCC0, 0x00000000, 143 0xCC0, 0x00000000,
144 0xCC4, 0x00000000, 144 0xCC4, 0x00000000,
145 0xCC8, 0x00000000, 145 0xCC8, 0x00000000,
146 0xCCC, 0x00000000, 146 0xCCC, 0x00000000,
147 0xCD0, 0x00000000, 147 0xCD0, 0x00000000,
148 0xCD4, 0x00000000, 148 0xCD4, 0x00000000,
149 0xCD8, 0x64B22427, 149 0xCD8, 0x64B22427,
150 0xCDC, 0x00766932, 150 0xCDC, 0x00766932,
151 0xCE0, 0x00222222, 151 0xCE0, 0x00222222,
152 0xCE4, 0x00000000, 152 0xCE4, 0x00000000,
153 0xCE8, 0x37644302, 153 0xCE8, 0x37644302,
154 0xCEC, 0x2F97D40C, 154 0xCEC, 0x2F97D40C,
155 0xD00, 0x00000740, 155 0xD00, 0x00000740,
156 0xD04, 0x40020401, 156 0xD04, 0x40020401,
157 0xD08, 0x0000907F, 157 0xD08, 0x0000907F,
158 0xD0C, 0x20010201, 158 0xD0C, 0x20010201,
159 0xD10, 0xA0633333, 159 0xD10, 0xA0633333,
160 0xD14, 0x3333BC53, 160 0xD14, 0x3333BC53,
161 0xD18, 0x7A8F5B6F, 161 0xD18, 0x7A8F5B6F,
162 0xD2C, 0xCC979975, 162 0xD2C, 0xCC979975,
163 0xD30, 0x00000000, 163 0xD30, 0x00000000,
164 0xD34, 0x80608000, 164 0xD34, 0x80608000,
165 0xD38, 0x00000000, 165 0xD38, 0x00000000,
166 0xD3C, 0x00127353, 166 0xD3C, 0x00127353,
167 0xD40, 0x00000000, 167 0xD40, 0x00000000,
168 0xD44, 0x00000000, 168 0xD44, 0x00000000,
169 0xD48, 0x00000000, 169 0xD48, 0x00000000,
170 0xD4C, 0x00000000, 170 0xD4C, 0x00000000,
171 0xD50, 0x6437140A, 171 0xD50, 0x6437140A,
172 0xD54, 0x00000000, 172 0xD54, 0x00000000,
173 0xD58, 0x00000282, 173 0xD58, 0x00000282,
174 0xD5C, 0x30032064, 174 0xD5C, 0x30032064,
175 0xD60, 0x4653DE68, 175 0xD60, 0x4653DE68,
176 0xD64, 0x04518A3C, 176 0xD64, 0x04518A3C,
177 0xD68, 0x00002101, 177 0xD68, 0x00002101,
178 0xD6C, 0x2A201C16, 178 0xD6C, 0x2A201C16,
179 0xD70, 0x1812362E, 179 0xD70, 0x1812362E,
180 0xD74, 0x322C2220, 180 0xD74, 0x322C2220,
181 0xD78, 0x000E3C24, 181 0xD78, 0x000E3C24,
182 0xE00, 0x2D2D2D2D, 182 0xE00, 0x2D2D2D2D,
183 0xE04, 0x2D2D2D2D, 183 0xE04, 0x2D2D2D2D,
184 0xE08, 0x0390272D, 184 0xE08, 0x0390272D,
185 0xE10, 0x2D2D2D2D, 185 0xE10, 0x2D2D2D2D,
186 0xE14, 0x2D2D2D2D, 186 0xE14, 0x2D2D2D2D,
187 0xE18, 0x2D2D2D2D, 187 0xE18, 0x2D2D2D2D,
188 0xE1C, 0x2D2D2D2D, 188 0xE1C, 0x2D2D2D2D,
189 0xE28, 0x00000000, 189 0xE28, 0x00000000,
190 0xE30, 0x1000DC1F, 190 0xE30, 0x1000DC1F,
191 0xE34, 0x10008C1F, 191 0xE34, 0x10008C1F,
192 0xE38, 0x02140102, 192 0xE38, 0x02140102,
193 0xE3C, 0x681604C2, 193 0xE3C, 0x681604C2,
194 0xE40, 0x01007C00, 194 0xE40, 0x01007C00,
195 0xE44, 0x01004800, 195 0xE44, 0x01004800,
196 0xE48, 0xFB000000, 196 0xE48, 0xFB000000,
197 0xE4C, 0x000028D1, 197 0xE4C, 0x000028D1,
198 0xE50, 0x1000DC1F, 198 0xE50, 0x1000DC1F,
199 0xE54, 0x10008C1F, 199 0xE54, 0x10008C1F,
200 0xE58, 0x02140102, 200 0xE58, 0x02140102,
201 0xE5C, 0x28160D05, 201 0xE5C, 0x28160D05,
202 0xE60, 0x00000008, 202 0xE60, 0x00000008,
203 0xE68, 0x001B2556, 203 0xE68, 0x001B2556,
204 0xE6C, 0x00C00096, 204 0xE6C, 0x00C00096,
205 0xE70, 0x00C00096, 205 0xE70, 0x00C00096,
206 0xE74, 0x01000056, 206 0xE74, 0x01000056,
207 0xE78, 0x01000014, 207 0xE78, 0x01000014,
208 0xE7C, 0x01000056, 208 0xE7C, 0x01000056,
209 0xE80, 0x01000014, 209 0xE80, 0x01000014,
210 0xE84, 0x00C00096, 210 0xE84, 0x00C00096,
211 0xE88, 0x01000056, 211 0xE88, 0x01000056,
212 0xE8C, 0x00C00096, 212 0xE8C, 0x00C00096,
213 0xED0, 0x00C00096, 213 0xED0, 0x00C00096,
214 0xED4, 0x00C00096, 214 0xED4, 0x00C00096,
215 0xED8, 0x00C00096, 215 0xED8, 0x00C00096,
216 0xEDC, 0x000000D6, 216 0xEDC, 0x000000D6,
217 0xEE0, 0x000000D6, 217 0xEE0, 0x000000D6,
218 0xEEC, 0x01C00016, 218 0xEEC, 0x01C00016,
219 0xF14, 0x00000003, 219 0xF14, 0x00000003,
220 0xF4C, 0x00000000, 220 0xF4C, 0x00000000,
221 0xF00, 0x00000300, 221 0xF00, 0x00000300,
222 0x820, 0x01000100, 222 0x820, 0x01000100,
223 0x800, 0x83040000, 223 0x800, 0x83040000,
224
224}; 225};
225 226
226u32 RTL8723BEPHY_REG_ARRAY_PG[] = { 227u32 RTL8723BEPHY_REG_ARRAY_PG[] = {
@@ -233,340 +234,344 @@ u32 RTL8723BEPHY_REG_ARRAY_PG[] = {
233}; 234};
234 235
235u32 RTL8723BE_RADIOA_1TARRAY[] = { 236u32 RTL8723BE_RADIOA_1TARRAY[] = {
236 0x000, 0x00010000, 237 0x000, 0x00010000,
237 0x0B0, 0x000DFFE0, 238 0x0B0, 0x000DFFE0,
238 0x0FE, 0x00000000, 239 0x0FE, 0x00000000,
239 0x0FE, 0x00000000, 240 0x0FE, 0x00000000,
240 0x0FE, 0x00000000, 241 0x0FE, 0x00000000,
241 0x0B1, 0x00000018, 242 0x0B1, 0x00000018,
242 0x0FE, 0x00000000, 243 0x0FE, 0x00000000,
243 0x0FE, 0x00000000, 244 0x0FE, 0x00000000,
244 0x0FE, 0x00000000, 245 0x0FE, 0x00000000,
245 0x0B2, 0x00084C00, 246 0x0B2, 0x00084C00,
246 0x0B5, 0x0000D2CC, 247 0x0B5, 0x0000D2CC,
247 0x0B6, 0x000925AA, 248 0x0B6, 0x000925AA,
248 0x0B7, 0x00000010, 249 0x0B7, 0x00000010,
249 0x0B8, 0x0000907F, 250 0x0B8, 0x0000907F,
250 0x05C, 0x00000002, 251 0x05C, 0x00000002,
251 0x07C, 0x00000002, 252 0x07C, 0x00000002,
252 0x07E, 0x00000005, 253 0x07E, 0x00000005,
253 0x08B, 0x0006FC00, 254 0x08B, 0x0006FC00,
254 0x0B0, 0x000FF9F0, 255 0x0B0, 0x000FF9F0,
255 0x01C, 0x000739D2, 256 0x01C, 0x000739D2,
256 0x01E, 0x00000000, 257 0x01E, 0x00000000,
257 0x0DF, 0x00000780, 258 0x0DF, 0x00000780,
258 0x050, 0x00067435, 259 0x050, 0x00067435,
259 0x051, 0x0006B04E, 260 0x051, 0x0006B04E,
260 0x052, 0x000007D2, 261 0x052, 0x000007D2,
261 0x053, 0x00000000, 262 0x053, 0x00000000,
262 0x054, 0x00050400, 263 0x054, 0x00050400,
263 0x055, 0x0004026E, 264 0x055, 0x0004026E,
264 0x0DD, 0x0000004C, 265 0x0DD, 0x0000004C,
265 0x070, 0x00067435, 266 0x070, 0x00067435,
266 0x071, 0x0006B04E, 267 0x071, 0x0006B04E,
267 0x072, 0x000007D2, 268 0x072, 0x000007D2,
268 0x073, 0x00000000, 269 0x073, 0x00000000,
269 0x074, 0x00050400, 270 0x074, 0x00050400,
270 0x075, 0x0004026E, 271 0x075, 0x0004026E,
271 0x0EF, 0x00000100, 272 0x0EF, 0x00000100,
272 0x034, 0x0000ADD7, 273 0x034, 0x0000ADD7,
273 0x035, 0x00005C00, 274 0x035, 0x00005C00,
274 0x034, 0x00009DD4, 275 0x034, 0x00009DD4,
275 0x035, 0x00005000, 276 0x035, 0x00005000,
276 0x034, 0x00008DD1, 277 0x034, 0x00008DD1,
277 0x035, 0x00004400, 278 0x035, 0x00004400,
278 0x034, 0x00007DCE, 279 0x034, 0x00007DCE,
279 0x035, 0x00003800, 280 0x035, 0x00003800,
280 0x034, 0x00006CD1, 281 0x034, 0x00006CD1,
281 0x035, 0x00004400, 282 0x035, 0x00004400,
282 0x034, 0x00005CCE, 283 0x034, 0x00005CCE,
283 0x035, 0x00003800, 284 0x035, 0x00003800,
284 0x034, 0x000048CE, 285 0x034, 0x000048CE,
285 0x035, 0x00004400, 286 0x035, 0x00004400,
286 0x034, 0x000034CE, 287 0x034, 0x000034CE,
287 0x035, 0x00003800, 288 0x035, 0x00003800,
288 0x034, 0x00002451, 289 0x034, 0x00002451,
289 0x035, 0x00004400, 290 0x035, 0x00004400,
290 0x034, 0x0000144E, 291 0x034, 0x0000144E,
291 0x035, 0x00003800, 292 0x035, 0x00003800,
292 0x034, 0x00000051, 293 0x034, 0x00000051,
293 0x035, 0x00004400, 294 0x035, 0x00004400,
294 0x0EF, 0x00000000, 295 0x0EF, 0x00000000,
295 0x0EF, 0x00000100, 296 0x0EF, 0x00000100,
296 0x0ED, 0x00000010, 297 0x0ED, 0x00000010,
297 0x044, 0x0000ADD7, 298 0x044, 0x0000ADD7,
298 0x044, 0x00009DD4, 299 0x044, 0x00009DD4,
299 0x044, 0x00008DD1, 300 0x044, 0x00008DD1,
300 0x044, 0x00007DCE, 301 0x044, 0x00007DCE,
301 0x044, 0x00006CC1, 302 0x044, 0x00006CC1,
302 0x044, 0x00005CCE, 303 0x044, 0x00005CCE,
303 0x044, 0x000044D1, 304 0x044, 0x000044D1,
304 0x044, 0x000034CE, 305 0x044, 0x000034CE,
305 0x044, 0x00002451, 306 0x044, 0x00002451,
306 0x044, 0x0000144E, 307 0x044, 0x0000144E,
307 0x044, 0x00000051, 308 0x044, 0x00000051,
308 0x0EF, 0x00000000, 309 0x0EF, 0x00000000,
309 0x0ED, 0x00000000, 310 0x0ED, 0x00000000,
310 0x0EF, 0x00002000, 311 0x0EF, 0x00002000,
311 0x03B, 0x000380EF, 312 0x03B, 0x000380EF,
312 0x03B, 0x000302FE, 313 0x03B, 0x000302FE,
313 0x03B, 0x00028CE6, 314 0x03B, 0x00028CE6,
314 0x03B, 0x000200BC, 315 0x03B, 0x000200BC,
315 0x03B, 0x000188A5, 316 0x03B, 0x000188A5,
316 0x03B, 0x00010FBC, 317 0x03B, 0x00010FBC,
317 0x03B, 0x00008F71, 318 0x03B, 0x00008F71,
318 0x03B, 0x00000900, 319 0x03B, 0x00000900,
319 0x0EF, 0x00000000, 320 0x0EF, 0x00000000,
320 0x0ED, 0x00000001, 321 0x0ED, 0x00000001,
321 0x040, 0x000380EF, 322 0x040, 0x000380EF,
322 0x040, 0x000302FE, 323 0x040, 0x000302FE,
323 0x040, 0x00028CE6, 324 0x040, 0x00028CE6,
324 0x040, 0x000200BC, 325 0x040, 0x000200BC,
325 0x040, 0x000188A5, 326 0x040, 0x000188A5,
326 0x040, 0x00010FBC, 327 0x040, 0x00010FBC,
327 0x040, 0x00008F71, 328 0x040, 0x00008F71,
328 0x040, 0x00000900, 329 0x040, 0x00000900,
329 0x0ED, 0x00000000, 330 0x0ED, 0x00000000,
330 0x082, 0x00080000, 331 0x082, 0x00080000,
331 0x083, 0x00008000, 332 0x083, 0x00008000,
332 0x084, 0x00048D80, 333 0x084, 0x00048D80,
333 0x085, 0x00068000, 334 0x085, 0x00068000,
334 0x0A2, 0x00080000, 335 0x0A2, 0x00080000,
335 0x0A3, 0x00008000, 336 0x0A3, 0x00008000,
336 0x0A4, 0x00048D80, 337 0x0A4, 0x00048D80,
337 0x0A5, 0x00068000, 338 0x0A5, 0x00068000,
338 0x000, 0x00033D80, 339 0x000, 0x00033D80,
340
339}; 341};
340 342
341u32 RTL8723BEMAC_1T_ARRAY[] = { 343u32 RTL8723BEMAC_1T_ARRAY[] = {
342 0x02F, 0x00000030, 344 0x02F, 0x00000030,
343 0x035, 0x00000000, 345 0x035, 0x00000000,
344 0x428, 0x0000000A, 346 0x067, 0x00000020,
345 0x429, 0x00000010, 347 0x428, 0x0000000A,
346 0x430, 0x00000000, 348 0x429, 0x00000010,
347 0x431, 0x00000000, 349 0x430, 0x00000000,
348 0x432, 0x00000000, 350 0x431, 0x00000000,
349 0x433, 0x00000001, 351 0x432, 0x00000000,
350 0x434, 0x00000004, 352 0x433, 0x00000001,
351 0x435, 0x00000005, 353 0x434, 0x00000004,
352 0x436, 0x00000007, 354 0x435, 0x00000005,
353 0x437, 0x00000008, 355 0x436, 0x00000007,
354 0x43C, 0x00000004, 356 0x437, 0x00000008,
355 0x43D, 0x00000005, 357 0x43C, 0x00000004,
356 0x43E, 0x00000007, 358 0x43D, 0x00000005,
357 0x43F, 0x00000008, 359 0x43E, 0x00000007,
358 0x440, 0x0000005D, 360 0x43F, 0x00000008,
359 0x441, 0x00000001, 361 0x440, 0x0000005D,
360 0x442, 0x00000000, 362 0x441, 0x00000001,
361 0x444, 0x00000010, 363 0x442, 0x00000000,
362 0x445, 0x00000000, 364 0x444, 0x00000010,
363 0x446, 0x00000000, 365 0x445, 0x00000000,
364 0x447, 0x00000000, 366 0x446, 0x00000000,
365 0x448, 0x00000000, 367 0x447, 0x00000000,
366 0x449, 0x000000F0, 368 0x448, 0x00000000,
367 0x44A, 0x0000000F, 369 0x449, 0x000000F0,
368 0x44B, 0x0000003E, 370 0x44A, 0x0000000F,
369 0x44C, 0x00000010, 371 0x44B, 0x0000003E,
370 0x44D, 0x00000000, 372 0x44C, 0x00000010,
371 0x44E, 0x00000000, 373 0x44D, 0x00000000,
372 0x44F, 0x00000000, 374 0x44E, 0x00000000,
373 0x450, 0x00000000, 375 0x44F, 0x00000000,
374 0x451, 0x000000F0, 376 0x450, 0x00000000,
375 0x452, 0x0000000F, 377 0x451, 0x000000F0,
376 0x453, 0x00000000, 378 0x452, 0x0000000F,
377 0x456, 0x0000005E, 379 0x453, 0x00000000,
378 0x460, 0x00000066, 380 0x456, 0x0000005E,
379 0x461, 0x00000066, 381 0x460, 0x00000066,
380 0x4C8, 0x000000FF, 382 0x461, 0x00000066,
381 0x4C9, 0x00000008, 383 0x4C8, 0x000000FF,
382 0x4CC, 0x000000FF, 384 0x4C9, 0x00000008,
383 0x4CD, 0x000000FF, 385 0x4CC, 0x000000FF,
384 0x4CE, 0x00000001, 386 0x4CD, 0x000000FF,
385 0x500, 0x00000026, 387 0x4CE, 0x00000001,
386 0x501, 0x000000A2, 388 0x500, 0x00000026,
387 0x502, 0x0000002F, 389 0x501, 0x000000A2,
388 0x503, 0x00000000, 390 0x502, 0x0000002F,
389 0x504, 0x00000028, 391 0x503, 0x00000000,
390 0x505, 0x000000A3, 392 0x504, 0x00000028,
391 0x506, 0x0000005E, 393 0x505, 0x000000A3,
392 0x507, 0x00000000, 394 0x506, 0x0000005E,
393 0x508, 0x0000002B, 395 0x507, 0x00000000,
394 0x509, 0x000000A4, 396 0x508, 0x0000002B,
395 0x50A, 0x0000005E, 397 0x509, 0x000000A4,
396 0x50B, 0x00000000, 398 0x50A, 0x0000005E,
397 0x50C, 0x0000004F, 399 0x50B, 0x00000000,
398 0x50D, 0x000000A4, 400 0x50C, 0x0000004F,
399 0x50E, 0x00000000, 401 0x50D, 0x000000A4,
400 0x50F, 0x00000000, 402 0x50E, 0x00000000,
401 0x512, 0x0000001C, 403 0x50F, 0x00000000,
402 0x514, 0x0000000A, 404 0x512, 0x0000001C,
403 0x516, 0x0000000A, 405 0x514, 0x0000000A,
404 0x525, 0x0000004F, 406 0x516, 0x0000000A,
405 0x550, 0x00000010, 407 0x525, 0x0000004F,
406 0x551, 0x00000010, 408 0x550, 0x00000010,
407 0x559, 0x00000002, 409 0x551, 0x00000010,
408 0x55C, 0x00000050, 410 0x559, 0x00000002,
409 0x55D, 0x000000FF, 411 0x55C, 0x00000050,
410 0x605, 0x00000030, 412 0x55D, 0x000000FF,
411 0x608, 0x0000000E, 413 0x605, 0x00000030,
412 0x609, 0x0000002A, 414 0x608, 0x0000000E,
413 0x620, 0x000000FF, 415 0x609, 0x0000002A,
414 0x621, 0x000000FF, 416 0x620, 0x000000FF,
415 0x622, 0x000000FF, 417 0x621, 0x000000FF,
416 0x623, 0x000000FF, 418 0x622, 0x000000FF,
417 0x624, 0x000000FF, 419 0x623, 0x000000FF,
418 0x625, 0x000000FF, 420 0x624, 0x000000FF,
419 0x626, 0x000000FF, 421 0x625, 0x000000FF,
420 0x627, 0x000000FF, 422 0x626, 0x000000FF,
421 0x638, 0x00000050, 423 0x627, 0x000000FF,
422 0x63C, 0x0000000A, 424 0x638, 0x00000050,
423 0x63D, 0x0000000A, 425 0x63C, 0x0000000A,
424 0x63E, 0x0000000E, 426 0x63D, 0x0000000A,
425 0x63F, 0x0000000E, 427 0x63E, 0x0000000E,
426 0x640, 0x00000040, 428 0x63F, 0x0000000E,
427 0x642, 0x00000040, 429 0x640, 0x00000040,
428 0x643, 0x00000000, 430 0x642, 0x00000040,
429 0x652, 0x000000C8, 431 0x643, 0x00000000,
430 0x66E, 0x00000005, 432 0x652, 0x000000C8,
431 0x700, 0x00000021, 433 0x66E, 0x00000005,
432 0x701, 0x00000043, 434 0x700, 0x00000021,
433 0x702, 0x00000065, 435 0x701, 0x00000043,
434 0x703, 0x00000087, 436 0x702, 0x00000065,
435 0x708, 0x00000021, 437 0x703, 0x00000087,
436 0x709, 0x00000043, 438 0x708, 0x00000021,
437 0x70A, 0x00000065, 439 0x709, 0x00000043,
438 0x70B, 0x00000087, 440 0x70A, 0x00000065,
441 0x70B, 0x00000087,
442
439}; 443};
440 444
441u32 RTL8723BEAGCTAB_1TARRAY[] = { 445u32 RTL8723BEAGCTAB_1TARRAY[] = {
442 0xC78, 0xFD000001, 446 0xC78, 0xFD000001,
443 0xC78, 0xFC010001, 447 0xC78, 0xFC010001,
444 0xC78, 0xFB020001, 448 0xC78, 0xFB020001,
445 0xC78, 0xFA030001, 449 0xC78, 0xFA030001,
446 0xC78, 0xF9040001, 450 0xC78, 0xF9040001,
447 0xC78, 0xF8050001, 451 0xC78, 0xF8050001,
448 0xC78, 0xF7060001, 452 0xC78, 0xF7060001,
449 0xC78, 0xF6070001, 453 0xC78, 0xF6070001,
450 0xC78, 0xF5080001, 454 0xC78, 0xF5080001,
451 0xC78, 0xF4090001, 455 0xC78, 0xF4090001,
452 0xC78, 0xF30A0001, 456 0xC78, 0xF30A0001,
453 0xC78, 0xF20B0001, 457 0xC78, 0xF20B0001,
454 0xC78, 0xF10C0001, 458 0xC78, 0xF10C0001,
455 0xC78, 0xF00D0001, 459 0xC78, 0xF00D0001,
456 0xC78, 0xEF0E0001, 460 0xC78, 0xEF0E0001,
457 0xC78, 0xEE0F0001, 461 0xC78, 0xEE0F0001,
458 0xC78, 0xED100001, 462 0xC78, 0xED100001,
459 0xC78, 0xEC110001, 463 0xC78, 0xEC110001,
460 0xC78, 0xEB120001, 464 0xC78, 0xEB120001,
461 0xC78, 0xEA130001, 465 0xC78, 0xEA130001,
462 0xC78, 0xE9140001, 466 0xC78, 0xE9140001,
463 0xC78, 0xE8150001, 467 0xC78, 0xE8150001,
464 0xC78, 0xE7160001, 468 0xC78, 0xE7160001,
465 0xC78, 0xAA170001, 469 0xC78, 0xAA170001,
466 0xC78, 0xA9180001, 470 0xC78, 0xA9180001,
467 0xC78, 0xA8190001, 471 0xC78, 0xA8190001,
468 0xC78, 0xA71A0001, 472 0xC78, 0xA71A0001,
469 0xC78, 0xA61B0001, 473 0xC78, 0xA61B0001,
470 0xC78, 0xA51C0001, 474 0xC78, 0xA51C0001,
471 0xC78, 0xA41D0001, 475 0xC78, 0xA41D0001,
472 0xC78, 0xA31E0001, 476 0xC78, 0xA31E0001,
473 0xC78, 0x671F0001, 477 0xC78, 0x671F0001,
474 0xC78, 0x66200001, 478 0xC78, 0x66200001,
475 0xC78, 0x65210001, 479 0xC78, 0x65210001,
476 0xC78, 0x64220001, 480 0xC78, 0x64220001,
477 0xC78, 0x63230001, 481 0xC78, 0x63230001,
478 0xC78, 0x62240001, 482 0xC78, 0x62240001,
479 0xC78, 0x61250001, 483 0xC78, 0x61250001,
480 0xC78, 0x47260001, 484 0xC78, 0x47260001,
481 0xC78, 0x46270001, 485 0xC78, 0x46270001,
482 0xC78, 0x45280001, 486 0xC78, 0x45280001,
483 0xC78, 0x44290001, 487 0xC78, 0x44290001,
484 0xC78, 0x432A0001, 488 0xC78, 0x432A0001,
485 0xC78, 0x422B0001, 489 0xC78, 0x422B0001,
486 0xC78, 0x292C0001, 490 0xC78, 0x292C0001,
487 0xC78, 0x282D0001, 491 0xC78, 0x282D0001,
488 0xC78, 0x272E0001, 492 0xC78, 0x272E0001,
489 0xC78, 0x262F0001, 493 0xC78, 0x262F0001,
490 0xC78, 0x25300001, 494 0xC78, 0x25300001,
491 0xC78, 0x24310001, 495 0xC78, 0x24310001,
492 0xC78, 0x09320001, 496 0xC78, 0x09320001,
493 0xC78, 0x08330001, 497 0xC78, 0x08330001,
494 0xC78, 0x07340001, 498 0xC78, 0x07340001,
495 0xC78, 0x06350001, 499 0xC78, 0x06350001,
496 0xC78, 0x05360001, 500 0xC78, 0x05360001,
497 0xC78, 0x04370001, 501 0xC78, 0x04370001,
498 0xC78, 0x03380001, 502 0xC78, 0x03380001,
499 0xC78, 0x02390001, 503 0xC78, 0x02390001,
500 0xC78, 0x013A0001, 504 0xC78, 0x013A0001,
501 0xC78, 0x003B0001, 505 0xC78, 0x003B0001,
502 0xC78, 0x003C0001, 506 0xC78, 0x003C0001,
503 0xC78, 0x003D0001, 507 0xC78, 0x003D0001,
504 0xC78, 0x003E0001, 508 0xC78, 0x003E0001,
505 0xC78, 0x003F0001, 509 0xC78, 0x003F0001,
506 0xC78, 0xFC400001, 510 0xC78, 0xFC400001,
507 0xC78, 0xFB410001, 511 0xC78, 0xFB410001,
508 0xC78, 0xFA420001, 512 0xC78, 0xFA420001,
509 0xC78, 0xF9430001, 513 0xC78, 0xF9430001,
510 0xC78, 0xF8440001, 514 0xC78, 0xF8440001,
511 0xC78, 0xF7450001, 515 0xC78, 0xF7450001,
512 0xC78, 0xF6460001, 516 0xC78, 0xF6460001,
513 0xC78, 0xF5470001, 517 0xC78, 0xF5470001,
514 0xC78, 0xF4480001, 518 0xC78, 0xF4480001,
515 0xC78, 0xF3490001, 519 0xC78, 0xF3490001,
516 0xC78, 0xF24A0001, 520 0xC78, 0xF24A0001,
517 0xC78, 0xF14B0001, 521 0xC78, 0xF14B0001,
518 0xC78, 0xF04C0001, 522 0xC78, 0xF04C0001,
519 0xC78, 0xEF4D0001, 523 0xC78, 0xEF4D0001,
520 0xC78, 0xEE4E0001, 524 0xC78, 0xEE4E0001,
521 0xC78, 0xED4F0001, 525 0xC78, 0xED4F0001,
522 0xC78, 0xEC500001, 526 0xC78, 0xEC500001,
523 0xC78, 0xEB510001, 527 0xC78, 0xEB510001,
524 0xC78, 0xEA520001, 528 0xC78, 0xEA520001,
525 0xC78, 0xE9530001, 529 0xC78, 0xE9530001,
526 0xC78, 0xE8540001, 530 0xC78, 0xE8540001,
527 0xC78, 0xE7550001, 531 0xC78, 0xE7550001,
528 0xC78, 0xE6560001, 532 0xC78, 0xE6560001,
529 0xC78, 0xE5570001, 533 0xC78, 0xE5570001,
530 0xC78, 0xAA580001, 534 0xC78, 0xAA580001,
531 0xC78, 0xA9590001, 535 0xC78, 0xA9590001,
532 0xC78, 0xA85A0001, 536 0xC78, 0xA85A0001,
533 0xC78, 0xA75B0001, 537 0xC78, 0xA75B0001,
534 0xC78, 0xA65C0001, 538 0xC78, 0xA65C0001,
535 0xC78, 0xA55D0001, 539 0xC78, 0xA55D0001,
536 0xC78, 0xA45E0001, 540 0xC78, 0xA45E0001,
537 0xC78, 0x675F0001, 541 0xC78, 0x675F0001,
538 0xC78, 0x66600001, 542 0xC78, 0x66600001,
539 0xC78, 0x65610001, 543 0xC78, 0x65610001,
540 0xC78, 0x64620001, 544 0xC78, 0x64620001,
541 0xC78, 0x63630001, 545 0xC78, 0x63630001,
542 0xC78, 0x62640001, 546 0xC78, 0x62640001,
543 0xC78, 0x61650001, 547 0xC78, 0x61650001,
544 0xC78, 0x47660001, 548 0xC78, 0x47660001,
545 0xC78, 0x46670001, 549 0xC78, 0x46670001,
546 0xC78, 0x45680001, 550 0xC78, 0x45680001,
547 0xC78, 0x44690001, 551 0xC78, 0x44690001,
548 0xC78, 0x436A0001, 552 0xC78, 0x436A0001,
549 0xC78, 0x426B0001, 553 0xC78, 0x426B0001,
550 0xC78, 0x296C0001, 554 0xC78, 0x296C0001,
551 0xC78, 0x286D0001, 555 0xC78, 0x286D0001,
552 0xC78, 0x276E0001, 556 0xC78, 0x276E0001,
553 0xC78, 0x266F0001, 557 0xC78, 0x266F0001,
554 0xC78, 0x25700001, 558 0xC78, 0x25700001,
555 0xC78, 0x24710001, 559 0xC78, 0x24710001,
556 0xC78, 0x09720001, 560 0xC78, 0x09720001,
557 0xC78, 0x08730001, 561 0xC78, 0x08730001,
558 0xC78, 0x07740001, 562 0xC78, 0x07740001,
559 0xC78, 0x06750001, 563 0xC78, 0x06750001,
560 0xC78, 0x05760001, 564 0xC78, 0x05760001,
561 0xC78, 0x04770001, 565 0xC78, 0x04770001,
562 0xC78, 0x03780001, 566 0xC78, 0x03780001,
563 0xC78, 0x02790001, 567 0xC78, 0x02790001,
564 0xC78, 0x017A0001, 568 0xC78, 0x017A0001,
565 0xC78, 0x007B0001, 569 0xC78, 0x007B0001,
566 0xC78, 0x007C0001, 570 0xC78, 0x007C0001,
567 0xC78, 0x007D0001, 571 0xC78, 0x007D0001,
568 0xC78, 0x007E0001, 572 0xC78, 0x007E0001,
569 0xC78, 0x007F0001, 573 0xC78, 0x007F0001,
570 0xC50, 0x69553422, 574 0xC50, 0x69553422,
571 0xC50, 0x69553420, 575 0xC50, 0x69553420,
576
572}; 577};
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/table.h b/drivers/net/wireless/rtlwifi/rtl8723be/table.h
index 932760a84827..dc17001632f7 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/table.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/table.h
@@ -35,7 +35,7 @@ extern u32 RTL8723BEPHY_REG_1TARRAY[];
35extern u32 RTL8723BEPHY_REG_ARRAY_PG[]; 35extern u32 RTL8723BEPHY_REG_ARRAY_PG[];
36#define RTL8723BE_RADIOA_1TARRAYLEN 206 36#define RTL8723BE_RADIOA_1TARRAYLEN 206
37extern u32 RTL8723BE_RADIOA_1TARRAY[]; 37extern u32 RTL8723BE_RADIOA_1TARRAY[];
38#define RTL8723BEMAC_1T_ARRAYLEN 194 38#define RTL8723BEMAC_1T_ARRAYLEN 196
39extern u32 RTL8723BEMAC_1T_ARRAY[]; 39extern u32 RTL8723BEMAC_1T_ARRAY[];
40#define RTL8723BEAGCTAB_1TARRAYLEN 260 40#define RTL8723BEAGCTAB_1TARRAYLEN 260
41extern u32 RTL8723BEAGCTAB_1TARRAY[]; 41extern u32 RTL8723BEAGCTAB_1TARRAY[];
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/trx.c b/drivers/net/wireless/rtlwifi/rtl8723be/trx.c
index 557b416246b0..9679cd207fad 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/trx.c
@@ -33,6 +33,7 @@
33#include "trx.h" 33#include "trx.h"
34#include "led.h" 34#include "led.h"
35#include "dm.h" 35#include "dm.h"
36#include "fw.h"
36 37
37static u8 _rtl8723be_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue) 38static u8 _rtl8723be_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
38{ 39{
@@ -207,196 +208,150 @@ static int _rtl8723be_rate_mapping(struct ieee80211_hw *hw,
207static void _rtl8723be_query_rxphystatus(struct ieee80211_hw *hw, 208static void _rtl8723be_query_rxphystatus(struct ieee80211_hw *hw,
208 struct rtl_stats *pstatus, u8 *pdesc, 209 struct rtl_stats *pstatus, u8 *pdesc,
209 struct rx_fwinfo_8723be *p_drvinfo, 210 struct rx_fwinfo_8723be *p_drvinfo,
210 bool packet_match_bssid, 211 bool bpacket_match_bssid,
211 bool packet_toself, 212 bool bpacket_toself,
212 bool packet_beacon) 213 bool packet_beacon)
213{ 214{
214 struct rtl_priv *rtlpriv = rtl_priv(hw); 215 struct rtl_priv *rtlpriv = rtl_priv(hw);
215 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
216 struct phy_sts_cck_8723e_t *cck_buf;
217 struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo; 216 struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
218 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
219 char rx_pwr_all = 0, rx_pwr[4]; 217 char rx_pwr_all = 0, rx_pwr[4];
220 u8 rf_rx_num = 0, evm, pwdb_all; 218 u8 rf_rx_num = 0, evm, pwdb_all, pwdb_all_bt = 0;
221 u8 i, max_spatial_stream; 219 u8 i, max_spatial_stream;
222 u32 rssi, total_rssi = 0; 220 u32 rssi, total_rssi = 0;
223 bool is_cck = pstatus->is_cck; 221 bool is_cck = pstatus->is_cck;
224 u8 lan_idx, vga_idx; 222 u8 lan_idx, vga_idx;
225 223
226 /* Record it for next packet processing */ 224 /* Record it for next packet processing */
227 pstatus->packet_matchbssid = packet_match_bssid; 225 pstatus->packet_matchbssid = bpacket_match_bssid;
228 pstatus->packet_toself = packet_toself; 226 pstatus->packet_toself = bpacket_toself;
229 pstatus->packet_beacon = packet_beacon; 227 pstatus->packet_beacon = packet_beacon;
230 pstatus->rx_mimo_sig_qual[0] = -1; 228 pstatus->rx_mimo_signalquality[0] = -1;
231 pstatus->rx_mimo_sig_qual[1] = -1; 229 pstatus->rx_mimo_signalquality[1] = -1;
232 230
233 if (is_cck) { 231 if (is_cck) {
234 u8 cck_highpwr; 232 u8 cck_highpwr;
235 u8 cck_agc_rpt; 233 u8 cck_agc_rpt;
236 /* CCK Driver info Structure is not the same as OFDM packet. */
237 cck_buf = (struct phy_sts_cck_8723e_t *)p_drvinfo;
238 cck_agc_rpt = cck_buf->cck_agc_rpt;
239 234
240 /* (1)Hardware does not provide RSSI for CCK 235 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;
241 * (2)PWDB, Average PWDB cacluated by 236
237 /* (1)Hardware does not provide RSSI for CCK */
238 /* (2)PWDB, Average PWDB cacluated by
242 * hardware (for rate adaptive) 239 * hardware (for rate adaptive)
243 */ 240 */
244 if (ppsc->rfpwr_state == ERFON) 241 cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
245 cck_highpwr = (u8) rtl_get_bbreg(hw, 242 BIT(9));
246 RFPGA0_XA_HSSIPARAMETER2,
247 BIT(9));
248 else
249 cck_highpwr = false;
250 243
251 lan_idx = ((cck_agc_rpt & 0xE0) >> 5); 244 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
252 vga_idx = (cck_agc_rpt & 0x1f); 245 vga_idx = (cck_agc_rpt & 0x1f);
246
253 switch (lan_idx) { 247 switch (lan_idx) {
254 case 7: 248 /* 46 53 73 95 201301231630 */
255 if (vga_idx <= 27)/*VGA_idx = 27~2*/ 249 /* 46 53 77 99 201301241630 */
256 rx_pwr_all = -100 + 2 * (27 - vga_idx); 250 case 6:
257 else 251 rx_pwr_all = -34 - (2 * vga_idx);
258 rx_pwr_all = -100;
259 break;
260 case 6:/*VGA_idx = 2~0*/
261 rx_pwr_all = -48 + 2 * (2 - vga_idx);
262 break;
263 case 5:/*VGA_idx = 7~5*/
264 rx_pwr_all = -42 + 2 * (7 - vga_idx);
265 break;
266 case 4:/*VGA_idx = 7~4*/
267 rx_pwr_all = -36 + 2 * (7 - vga_idx);
268 break; 252 break;
269 case 3:/*VGA_idx = 7~0*/ 253 case 4:
270 rx_pwr_all = -24 + 2 * (7 - vga_idx); 254 rx_pwr_all = -14 - (2 * vga_idx);
271 break;
272 case 2:
273 if (cck_highpwr)/*VGA_idx = 5~0*/
274 rx_pwr_all = -12 + 2 * (5 - vga_idx);
275 else
276 rx_pwr_all = -6 + 2 * (5 - vga_idx);
277 break; 255 break;
278 case 1: 256 case 1:
279 rx_pwr_all = 8 - 2 * vga_idx; 257 rx_pwr_all = 6 - (2 * vga_idx);
280 break; 258 break;
281 case 0: 259 case 0:
282 rx_pwr_all = 14 - 2 * vga_idx; 260 rx_pwr_all = 16 - (2 * vga_idx);
283 break; 261 break;
284 default: 262 default:
285 break; 263 break;
286 } 264 }
287 rx_pwr_all += 6; 265
288 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); 266 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
289 /* CCK gain is smaller than OFDM/MCS gain, */
290 /* so we add gain diff by experiences,
291 * the val is 6
292 */
293 pwdb_all += 6;
294 if (pwdb_all > 100) 267 if (pwdb_all > 100)
295 pwdb_all = 100; 268 pwdb_all = 100;
296 /* modify the offset to make the same gain index with OFDM. */
297 if (pwdb_all > 34 && pwdb_all <= 42)
298 pwdb_all -= 2;
299 else if (pwdb_all > 26 && pwdb_all <= 34)
300 pwdb_all -= 6;
301 else if (pwdb_all > 14 && pwdb_all <= 26)
302 pwdb_all -= 8;
303 else if (pwdb_all > 4 && pwdb_all <= 14)
304 pwdb_all -= 4;
305 if (!cck_highpwr) {
306 if (pwdb_all >= 80)
307 pwdb_all = ((pwdb_all - 80) << 1) +
308 ((pwdb_all - 80) >> 1) + 80;
309 else if ((pwdb_all <= 78) && (pwdb_all >= 20))
310 pwdb_all += 3;
311 if (pwdb_all > 100)
312 pwdb_all = 100;
313 }
314 269
315 pstatus->rx_pwdb_all = pwdb_all; 270 pstatus->rx_pwdb_all = pwdb_all;
271 pstatus->bt_rx_rssi_percentage = pwdb_all;
316 pstatus->recvsignalpower = rx_pwr_all; 272 pstatus->recvsignalpower = rx_pwr_all;
317 273
318 /* (3) Get Signal Quality (EVM) */ 274 /* (3) Get Signal Quality (EVM) */
319 if (packet_match_bssid) { 275 if (bpacket_match_bssid) {
320 u8 sq; 276 u8 sq, sq_rpt;
321
322 if (pstatus->rx_pwdb_all > 40) { 277 if (pstatus->rx_pwdb_all > 40) {
323 sq = 100; 278 sq = 100;
324 } else { 279 } else {
325 sq = cck_buf->sq_rpt; 280 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;
326 if (sq > 64) 281 if (sq_rpt > 64)
327 sq = 0; 282 sq = 0;
328 else if (sq < 20) 283 else if (sq_rpt < 20)
329 sq = 100; 284 sq = 100;
330 else 285 else
331 sq = ((64 - sq) * 100) / 44; 286 sq = ((64 - sq_rpt) * 100) / 44;
332 } 287 }
333
334 pstatus->signalquality = sq; 288 pstatus->signalquality = sq;
335 pstatus->rx_mimo_sig_qual[0] = sq; 289 pstatus->rx_mimo_signalquality[0] = sq;
336 pstatus->rx_mimo_sig_qual[1] = -1; 290 pstatus->rx_mimo_signalquality[1] = -1;
337 } 291 }
338 } else { 292 } else {
339 rtlpriv->dm.rfpath_rxenable[0] = true;
340 rtlpriv->dm.rfpath_rxenable[1] = true;
341
342 /* (1)Get RSSI for HT rate */ 293 /* (1)Get RSSI for HT rate */
343 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) { 294 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
344 /* we will judge RF RX path now. */ 295 /* we will judge RF RX path now. */
345 if (rtlpriv->dm.rfpath_rxenable[i]) 296 if (rtlpriv->dm.rfpath_rxenable[i])
346 rf_rx_num++; 297 rf_rx_num++;
347 298
348 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f)*2) - 110; 299 rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)
300 - 110;
349 301
302 pstatus->rx_pwr[i] = rx_pwr[i];
350 /* Translate DBM to percentage. */ 303 /* Translate DBM to percentage. */
351 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); 304 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
352 total_rssi += rssi; 305 total_rssi += rssi;
353 306
354 /* Get Rx snr value in DB */ 307 pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
355 rtlpriv->stats.rx_snr_db[i] =
356 (long)(p_drvinfo->rxsnr[i] / 2);
357
358 /* Record Signal Strength for next packet */
359 if (packet_match_bssid)
360 pstatus->rx_mimo_signalstrength[i] = (u8) rssi;
361 } 308 }
362 309
363 /* (2)PWDB, Avg cacluated by hardware (for rate adaptive) */ 310 /* (2)PWDB, Average PWDB cacluated by
364 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110; 311 * hardware (for rate adaptive)
312 */
313 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1) &
314 0x7f) - 110;
365 315
366 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); 316 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
317 pwdb_all_bt = pwdb_all;
367 pstatus->rx_pwdb_all = pwdb_all; 318 pstatus->rx_pwdb_all = pwdb_all;
319 pstatus->bt_rx_rssi_percentage = pwdb_all_bt;
368 pstatus->rxpower = rx_pwr_all; 320 pstatus->rxpower = rx_pwr_all;
369 pstatus->recvsignalpower = rx_pwr_all; 321 pstatus->recvsignalpower = rx_pwr_all;
370 322
371 /* (3)EVM of HT rate */ 323 /* (3)EVM of HT rate */
372 if (pstatus->is_ht && pstatus->rate >= DESC92C_RATEMCS8 && 324 if (pstatus->rate >= DESC92C_RATEMCS8 &&
373 pstatus->rate <= DESC92C_RATEMCS15) 325 pstatus->rate <= DESC92C_RATEMCS15)
374 max_spatial_stream = 2; 326 max_spatial_stream = 2;
375 else 327 else
376 max_spatial_stream = 1; 328 max_spatial_stream = 1;
377 329
378 for (i = 0; i < max_spatial_stream; i++) { 330 for (i = 0; i < max_spatial_stream; i++) {
379 evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]); 331 evm = rtl_evm_db_to_percentage(
332 p_phystrpt->stream_rxevm[i]);
380 333
381 if (packet_match_bssid) { 334 if (bpacket_match_bssid) {
382 /* Fill value in RFD, Get the first 335 /* Fill value in RFD, Get the first
383 * spatial stream only 336 * spatial stream only
384 */ 337 */
385 if (i == 0) 338 if (i == 0)
386 pstatus->signalquality = 339 pstatus->signalquality =
387 (u8) (evm & 0xff); 340 (u8)(evm & 0xff);
388 pstatus->rx_mimo_sig_qual[i] = 341 pstatus->rx_mimo_signalquality[i] =
389 (u8) (evm & 0xff); 342 (u8)(evm & 0xff);
390 } 343 }
391 } 344 }
392 if (packet_match_bssid) { 345
346 if (bpacket_match_bssid) {
393 for (i = RF90_PATH_A; i <= RF90_PATH_B; i++) 347 for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
394 rtl_priv(hw)->dm.cfo_tail[i] = 348 rtl_priv(hw)->dm.cfo_tail[i] =
395 (char)p_phystrpt->path_cfotail[i]; 349 (int)p_phystrpt->path_cfotail[i];
396 350
397 rtl_priv(hw)->dm.packet_count++;
398 if (rtl_priv(hw)->dm.packet_count == 0xffffffff) 351 if (rtl_priv(hw)->dm.packet_count == 0xffffffff)
399 rtl_priv(hw)->dm.packet_count = 0; 352 rtl_priv(hw)->dm.packet_count = 0;
353 else
354 rtl_priv(hw)->dm.packet_count++;
400 } 355 }
401 } 356 }
402 357
@@ -409,10 +364,6 @@ static void _rtl8723be_query_rxphystatus(struct ieee80211_hw *hw,
409 else if (rf_rx_num != 0) 364 else if (rf_rx_num != 0)
410 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw, 365 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
411 total_rssi /= rf_rx_num)); 366 total_rssi /= rf_rx_num));
412 /*HW antenna diversity*/
413 rtldm->fat_table.antsel_rx_keep_0 = p_phystrpt->ant_sel;
414 rtldm->fat_table.antsel_rx_keep_1 = p_phystrpt->ant_sel_b;
415 rtldm->fat_table.antsel_rx_keep_2 = p_phystrpt->antsel_rx_keep_2;
416} 367}
417 368
418static void _rtl8723be_translate_rx_signal_stuff(struct ieee80211_hw *hw, 369static void _rtl8723be_translate_rx_signal_stuff(struct ieee80211_hw *hw,
@@ -440,14 +391,14 @@ static void _rtl8723be_translate_rx_signal_stuff(struct ieee80211_hw *hw,
440 memcpy(pstatus->psaddr, psaddr, ETH_ALEN); 391 memcpy(pstatus->psaddr, psaddr, ETH_ALEN);
441 392
442 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) && 393 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
443 (!ether_addr_equal(mac->bssid, (fc & IEEE80211_FCTL_TODS) ? 394 (ether_addr_equal(mac->bssid, (fc & IEEE80211_FCTL_TODS) ?
444 hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ? 395 hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ?
445 hdr->addr2 : hdr->addr3)) && 396 hdr->addr2 : hdr->addr3)) &&
446 (!pstatus->hwerror) && 397 (!pstatus->hwerror) &&
447 (!pstatus->crc) && (!pstatus->icv)); 398 (!pstatus->crc) && (!pstatus->icv));
448 399
449 packet_toself = packet_matchbssid && 400 packet_toself = packet_matchbssid &&
450 (!ether_addr_equal(praddr, rtlefuse->dev_addr)); 401 (ether_addr_equal(praddr, rtlefuse->dev_addr));
451 402
452 /* YP: packet_beacon is not initialized, 403 /* YP: packet_beacon is not initialized,
453 * this assignment is neccesary, 404 * this assignment is neccesary,
@@ -531,30 +482,33 @@ bool rtl8723be_rx_query_desc(struct ieee80211_hw *hw,
531 struct ieee80211_hdr *hdr; 482 struct ieee80211_hdr *hdr;
532 483
533 u32 phystatus = GET_RX_DESC_PHYST(pdesc); 484 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
534 status->packet_report_type = (u8)GET_RX_STATUS_DESC_RPT_SEL(pdesc); 485
535 if (status->packet_report_type == TX_REPORT2) 486 status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
536 status->length = (u16) GET_RX_RPT2_DESC_PKT_LEN(pdesc); 487 status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
537 else
538 status->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
539 status->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
540 RX_DRV_INFO_SIZE_UNIT; 488 RX_DRV_INFO_SIZE_UNIT;
541 status->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03); 489 status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
542 status->icv = (u16) GET_RX_DESC_ICV(pdesc); 490 status->icv = (u16) GET_RX_DESC_ICV(pdesc);
543 status->crc = (u16) GET_RX_DESC_CRC32(pdesc); 491 status->crc = (u16) GET_RX_DESC_CRC32(pdesc);
544 status->hwerror = (status->crc | status->icv); 492 status->hwerror = (status->crc | status->icv);
545 status->decrypted = !GET_RX_DESC_SWDEC(pdesc); 493 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
546 status->rate = (u8) GET_RX_DESC_RXMCS(pdesc); 494 status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
547 status->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc); 495 status->shortpreamble = (u16)GET_RX_DESC_SPLCP(pdesc);
548 status->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1); 496 status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
549 status->isfirst_ampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1); 497 status->isfirst_ampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
550 if (status->packet_report_type == NORMAL_RX) 498 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
551 status->timestamp_low = GET_RX_DESC_TSFL(pdesc); 499 status->rx_is40Mhzpacket = (bool)GET_RX_DESC_BW(pdesc);
552 status->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc); 500 status->bandwidth = (u8)GET_RX_DESC_BW(pdesc);
501 status->macid = GET_RX_DESC_MACID(pdesc);
553 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc); 502 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
554 503
555 status->is_cck = RTL8723E_RX_HAL_IS_CCK_RATE(status->rate); 504 status->is_cck = RX_HAL_IS_CCK_RATE(status->rate);
505
506 if (GET_RX_STATUS_DESC_RPT_SEL(pdesc))
507 status->packet_report_type = C2H_PACKET;
508 else
509 status->packet_report_type = NORMAL_RX;
510
556 511
557 status->macid = GET_RX_DESC_MACID(pdesc);
558 if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc)) 512 if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
559 status->wake_match = BIT(2); 513 status->wake_match = BIT(2);
560 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc)) 514 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
@@ -565,12 +519,11 @@ bool rtl8723be_rx_query_desc(struct ieee80211_hw *hw,
565 status->wake_match = 0; 519 status->wake_match = 0;
566 if (status->wake_match) 520 if (status->wake_match)
567 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD, 521 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
568 "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n", 522 "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
569 status->wake_match); 523 status->wake_match);
570 rx_status->freq = hw->conf.chandef.chan->center_freq; 524 rx_status->freq = hw->conf.chandef.chan->center_freq;
571 rx_status->band = hw->conf.chandef.chan->band; 525 rx_status->band = hw->conf.chandef.chan->band;
572 526
573
574 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size + 527 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
575 status->rx_bufshift); 528 status->rx_bufshift);
576 529
@@ -596,22 +549,21 @@ bool rtl8723be_rx_query_desc(struct ieee80211_hw *hw,
596 if (status->decrypted) { 549 if (status->decrypted) {
597 if (!hdr) { 550 if (!hdr) {
598 WARN_ON_ONCE(true); 551 WARN_ON_ONCE(true);
599 pr_err("decrypted is true but hdr NULL in skb %p\n", 552 pr_err("decrypted is true but hdr NULL, from skb %p\n",
600 rtl_get_hdr(skb)); 553 rtl_get_hdr(skb));
601 return false; 554 return false;
602 } 555 }
603 556
604 if ((_ieee80211_is_robust_mgmt_frame(hdr)) && 557 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
605 (ieee80211_has_protected(hdr->frame_control))) 558 (ieee80211_has_protected(hdr->frame_control)))
606 rx_status->flag &= ~RX_FLAG_DECRYPTED;
607 else
608 rx_status->flag |= RX_FLAG_DECRYPTED; 559 rx_status->flag |= RX_FLAG_DECRYPTED;
560 else
561 rx_status->flag &= ~RX_FLAG_DECRYPTED;
609 } 562 }
610 563
611 /* rate_idx: index of data rate into band's 564 /* rate_idx: index of data rate into band's
612 * supported rates or MCS index if HT rates 565 * supported rates or MCS index if HT rates
613 * are use (RX_FLAG_HT) 566 * are use (RX_FLAG_HT)
614 * Notice: this is diff with windows define
615 */ 567 */
616 rx_status->rate_idx = _rtl8723be_rate_mapping(hw, status->is_ht, 568 rx_status->rate_idx = _rtl8723be_rate_mapping(hw, status->is_ht,
617 status->rate); 569 status->rate);
@@ -624,21 +576,19 @@ bool rtl8723be_rx_query_desc(struct ieee80211_hw *hw,
624 _rtl8723be_translate_rx_signal_stuff(hw, skb, status, 576 _rtl8723be_translate_rx_signal_stuff(hw, skb, status,
625 pdesc, p_drvinfo); 577 pdesc, p_drvinfo);
626 } 578 }
627
628 /*rx_status->qual = status->signal; */
629 rx_status->signal = status->recvsignalpower + 10; 579 rx_status->signal = status->recvsignalpower + 10;
630 if (status->packet_report_type == TX_REPORT2) { 580 if (status->packet_report_type == TX_REPORT2) {
631 status->macid_valid_entry[0] = 581 status->macid_valid_entry[0] =
632 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc); 582 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
633 status->macid_valid_entry[1] = 583 status->macid_valid_entry[1] =
634 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc); 584 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
635 } 585 }
636 return true; 586 return true;
637} 587}
638 588
639void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw, 589void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
640 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 590 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
641 u8 *pbd_desc_tx, struct ieee80211_tx_info *info, 591 u8 *txbd, struct ieee80211_tx_info *info,
642 struct ieee80211_sta *sta, struct sk_buff *skb, 592 struct ieee80211_sta *sta, struct sk_buff *skb,
643 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc) 593 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
644{ 594{
@@ -646,16 +596,16 @@ void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
646 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 596 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
647 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 597 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
648 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 598 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
649 u8 *pdesc = pdesc_tx; 599 u8 *pdesc = (u8 *)pdesc_tx;
650 u16 seq_number; 600 u16 seq_number;
651 __le16 fc = hdr->frame_control; 601 __le16 fc = hdr->frame_control;
652 unsigned int buf_len = 0; 602 unsigned int buf_len = 0;
653 unsigned int skb_len = skb->len; 603 unsigned int skb_len = skb->len;
654 u8 fw_qsel = _rtl8723be_map_hwqueue_to_fwqueue(skb, hw_queue); 604 u8 fw_qsel = _rtl8723be_map_hwqueue_to_fwqueue(skb, hw_queue);
655 bool firstseg = ((hdr->seq_ctrl & 605 bool firstseg = ((hdr->seq_ctrl &
656 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0); 606 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
657 bool lastseg = ((hdr->frame_control & 607 bool lastseg = ((hdr->frame_control &
658 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0); 608 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
659 dma_addr_t mapping; 609 dma_addr_t mapping;
660 u8 bw_40 = 0; 610 u8 bw_40 = 0;
661 u8 short_gi = 0; 611 u8 short_gi = 0;
@@ -736,7 +686,7 @@ void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
736 SET_TX_DESC_NAV_USE_HDR(pdesc, 1); 686 SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
737 687
738 if (bw_40) { 688 if (bw_40) {
739 if (ptcb_desc->packet_bw) { 689 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
740 SET_TX_DESC_DATA_BW(pdesc, 1); 690 SET_TX_DESC_DATA_BW(pdesc, 1);
741 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3); 691 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
742 } else { 692 } else {
@@ -776,9 +726,12 @@ void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
776 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F); 726 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
777 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF); 727 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
778 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ? 728 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
779 1 : 0); 729 1 : 0);
780 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0); 730 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
781 731
732 /* Set TxRate and RTSRate in TxDesc */
733 /* This prevent Tx initial rate of new-coming packets */
734 /* from being overwritten by retried packet rate.*/
782 if (ieee80211_is_data_qos(fc)) { 735 if (ieee80211_is_data_qos(fc)) {
783 if (mac->rdg_en) { 736 if (mac->rdg_en) {
784 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 737 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
@@ -793,9 +746,14 @@ void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
793 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0)); 746 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
794 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len); 747 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len);
795 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); 748 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
796 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index); 749 /* if (rtlpriv->dm.useramask) { */
797 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id); 750 if (1) {
798 751 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
752 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
753 } else {
754 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
755 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
756 }
799 if (!ieee80211_is_data_qos(fc)) { 757 if (!ieee80211_is_data_qos(fc)) {
800 SET_TX_DESC_HWSEQ_EN(pdesc, 1); 758 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
801 SET_TX_DESC_HWSEQ_SEL(pdesc, 0); 759 SET_TX_DESC_HWSEQ_SEL(pdesc, 0);
@@ -805,11 +763,12 @@ void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
805 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) { 763 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
806 SET_TX_DESC_BMC(pdesc, 1); 764 SET_TX_DESC_BMC(pdesc, 1);
807 } 765 }
766
808 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); 767 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
809} 768}
810 769
811void rtl8723be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, 770void rtl8723be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
812 bool b_firstseg, bool b_lastseg, 771 bool firstseg, bool lastseg,
813 struct sk_buff *skb) 772 struct sk_buff *skb)
814{ 773{
815 struct rtl_priv *rtlpriv = rtl_priv(hw); 774 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -849,16 +808,19 @@ void rtl8723be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
849 808
850 SET_TX_DESC_OWN(pdesc, 1); 809 SET_TX_DESC_OWN(pdesc, 1);
851 810
852 SET_TX_DESC_PKT_SIZE(pdesc, (u16)(skb->len)); 811 SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
853 812
854 SET_TX_DESC_FIRST_SEG(pdesc, 1); 813 SET_TX_DESC_FIRST_SEG(pdesc, 1);
855 SET_TX_DESC_LAST_SEG(pdesc, 1); 814 SET_TX_DESC_LAST_SEG(pdesc, 1);
856 815
857 SET_TX_DESC_USE_RATE(pdesc, 1); 816 SET_TX_DESC_USE_RATE(pdesc, 1);
817
818 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
819 "H2C Tx Cmd Content\n", pdesc, TX_DESC_SIZE);
858} 820}
859 821
860void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 822void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
861 u8 desc_name, u8 *val) 823 bool istx, u8 desc_name, u8 *val)
862{ 824{
863 if (istx) { 825 if (istx) {
864 switch (desc_name) { 826 switch (desc_name) {
@@ -870,7 +832,7 @@ void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
870 break; 832 break;
871 default: 833 default:
872 RT_ASSERT(false, "ERR txdesc :%d not process\n", 834 RT_ASSERT(false, "ERR txdesc :%d not process\n",
873 desc_name); 835 desc_name);
874 break; 836 break;
875 } 837 }
876 } else { 838 } else {
@@ -889,7 +851,7 @@ void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
889 break; 851 break;
890 default: 852 default:
891 RT_ASSERT(false, "ERR rxdesc :%d not process\n", 853 RT_ASSERT(false, "ERR rxdesc :%d not process\n",
892 desc_name); 854 desc_name);
893 break; 855 break;
894 } 856 }
895 } 857 }
@@ -909,7 +871,7 @@ u32 rtl8723be_get_desc(u8 *pdesc, bool istx, u8 desc_name)
909 break; 871 break;
910 default: 872 default:
911 RT_ASSERT(false, "ERR txdesc :%d not process\n", 873 RT_ASSERT(false, "ERR txdesc :%d not process\n",
912 desc_name); 874 desc_name);
913 break; 875 break;
914 } 876 }
915 } else { 877 } else {
@@ -920,6 +882,9 @@ u32 rtl8723be_get_desc(u8 *pdesc, bool istx, u8 desc_name)
920 case HW_DESC_RXPKT_LEN: 882 case HW_DESC_RXPKT_LEN:
921 ret = GET_RX_DESC_PKT_LEN(pdesc); 883 ret = GET_RX_DESC_PKT_LEN(pdesc);
922 break; 884 break;
885 case HW_DESC_RXBUFF_ADDR:
886 ret = GET_RX_DESC_BUFF_ADDR(pdesc);
887 break;
923 default: 888 default:
924 RT_ASSERT(false, "ERR rxdesc :%d not process\n", 889 RT_ASSERT(false, "ERR rxdesc :%d not process\n",
925 desc_name); 890 desc_name);
@@ -935,16 +900,15 @@ bool rtl8723be_is_tx_desc_closed(struct ieee80211_hw *hw,
935 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 900 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
936 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 901 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
937 u8 *entry = (u8 *)(&ring->desc[ring->idx]); 902 u8 *entry = (u8 *)(&ring->desc[ring->idx]);
938 u8 own = (u8) rtl8723be_get_desc(entry, true, HW_DESC_OWN); 903 u8 own = (u8)rtl8723be_get_desc(entry, true, HW_DESC_OWN);
939 904
940 /*beacon packet will only use the first 905 /*beacon packet will only use the first
941 *descriptor by default, and the own may not 906 *descriptor defautly,and the own may not
942 *be cleared by the hardware 907 *be cleared by the hardware
943 */ 908 */
944 if (own) 909 if (own)
945 return false; 910 return false;
946 else 911 return true;
947 return true;
948} 912}
949 913
950void rtl8723be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue) 914void rtl8723be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
@@ -957,3 +921,28 @@ void rtl8723be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
957 BIT(0) << (hw_queue)); 921 BIT(0) << (hw_queue));
958 } 922 }
959} 923}
924
925u32 rtl8723be_rx_command_packet(struct ieee80211_hw *hw,
926 struct rtl_stats status,
927 struct sk_buff *skb)
928{
929 u32 result = 0;
930 struct rtl_priv *rtlpriv = rtl_priv(hw);
931
932 switch (status.packet_report_type) {
933 case NORMAL_RX:
934 result = 0;
935 break;
936 case C2H_PACKET:
937 rtl8723be_c2h_packet_handler(hw, skb->data,
938 (u8)skb->len);
939 result = 1;
940 break;
941 default:
942 RT_TRACE(rtlpriv, COMP_RECV, DBG_TRACE,
943 "No this packet type!!\n");
944 break;
945 }
946
947 return result;
948}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/trx.h b/drivers/net/wireless/rtlwifi/rtl8723be/trx.h
index 102f33dcc988..45949ac4854c 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/trx.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/trx.h
@@ -415,21 +415,25 @@ struct phy_status_rpt {
415} __packed; 415} __packed;
416 416
417struct rx_fwinfo_8723be { 417struct rx_fwinfo_8723be {
418 u8 gain_trsw[4]; 418 u8 gain_trsw[2];
419 u16 chl_num:10;
420 u16 sub_chnl:4;
421 u16 r_rfmod:2;
419 u8 pwdb_all; 422 u8 pwdb_all;
420 u8 cfosho[4]; 423 u8 cfosho[4];
421 u8 cfotail[4]; 424 u8 cfotail[4];
422 char rxevm[2]; 425 char rxevm[2];
423 char rxsnr[4]; 426 char rxsnr[2];
427 u8 pcts_msk_rpt[2];
424 u8 pdsnr[2]; 428 u8 pdsnr[2];
425 u8 csi_current[2]; 429 u8 csi_current[2];
426 u8 csi_target[2]; 430 u8 rx_gain_c;
431 u8 rx_gain_d;
427 u8 sigevm; 432 u8 sigevm;
428 u8 max_ex_pwr; 433 u8 resvd_0;
429 u8 ex_intf_flag:1; 434 u8 antidx_anta:3;
430 u8 sgi_en:1; 435 u8 antidx_antb:3;
431 u8 rxsc:2; 436 u8 resvd_1:2;
432 u8 reserve:4;
433} __packed; 437} __packed;
434 438
435struct tx_desc_8723be { 439struct tx_desc_8723be {
@@ -597,21 +601,25 @@ struct rx_desc_8723be {
597} __packed; 601} __packed;
598 602
599void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw, 603void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
600 struct ieee80211_hdr *hdr, u8 *pdesc, 604 struct ieee80211_hdr *hdr,
601 u8 *pbd_desc_tx, struct ieee80211_tx_info *info, 605 u8 *pdesc_tx, u8 *txbd,
606 struct ieee80211_tx_info *info,
602 struct ieee80211_sta *sta, struct sk_buff *skb, 607 struct ieee80211_sta *sta, struct sk_buff *skb,
603 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc); 608 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
604bool rtl8723be_rx_query_desc(struct ieee80211_hw *hw, 609bool rtl8723be_rx_query_desc(struct ieee80211_hw *hw,
605 struct rtl_stats *status, 610 struct rtl_stats *status,
606 struct ieee80211_rx_status *rx_status, 611 struct ieee80211_rx_status *rx_status,
607 u8 *pdesc, struct sk_buff *skb); 612 u8 *pdesc, struct sk_buff *skb);
608void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 613void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
609 u8 desc_name, u8 *val); 614 bool istx, u8 desc_name, u8 *val);
610u32 rtl8723be_get_desc(u8 *pdesc, bool istx, u8 desc_name); 615u32 rtl8723be_get_desc(u8 *pdesc, bool istx, u8 desc_name);
611bool rtl8723be_is_tx_desc_closed(struct ieee80211_hw *hw, 616bool rtl8723be_is_tx_desc_closed(struct ieee80211_hw *hw,
612 u8 hw_queue, u16 index); 617 u8 hw_queue, u16 index);
613void rtl8723be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); 618void rtl8723be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
614void rtl8723be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, 619void rtl8723be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
615 bool b_firstseg, bool b_lastseg, 620 bool firstseg, bool lastseg,
616 struct sk_buff *skb); 621 struct sk_buff *skb);
622u32 rtl8723be_rx_command_packet(struct ieee80211_hw *hw,
623 struct rtl_stats status,
624 struct sk_buff *skb);
617#endif 625#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c
index 6f35506a8fd2..dd698e7e9ace 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c
@@ -267,7 +267,7 @@ int rtl8723_download_fw(struct ieee80211_hw *hw,
267 pfwdata = rtlhal->pfirmware; 267 pfwdata = rtlhal->pfirmware;
268 fwsize = rtlhal->fwsize; 268 fwsize = rtlhal->fwsize;
269 269
270 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) 270 if (!is_8723be)
271 max_page = 6; 271 max_page = 6;
272 else 272 else
273 max_page = 8; 273 max_page = 8;
@@ -275,10 +275,10 @@ int rtl8723_download_fw(struct ieee80211_hw *hw,
275 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, 275 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
276 "Firmware Version(%d), Signature(%#x), Size(%d)\n", 276 "Firmware Version(%d), Signature(%#x), Size(%d)\n",
277 pfwheader->version, pfwheader->signature, 277 pfwheader->version, pfwheader->signature,
278 (int)sizeof(struct rtl92c_firmware_header)); 278 (int)sizeof(struct rtl8723e_firmware_header));
279 279
280 pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header); 280 pfwdata = pfwdata + sizeof(struct rtl8723e_firmware_header);
281 fwsize = fwsize - sizeof(struct rtl92c_firmware_header); 281 fwsize = fwsize - sizeof(struct rtl8723e_firmware_header);
282 } 282 }
283 283
284 if (rtl_read_byte(rtlpriv, REG_MCUFWDL)&BIT(7)) { 284 if (rtl_read_byte(rtlpriv, REG_MCUFWDL)&BIT(7)) {
diff --git a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h
index f9bab10d4726..3ebafc80972f 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h
@@ -30,7 +30,8 @@
30#define REG_MCUFWDL 0x0080 30#define REG_MCUFWDL 0x0080
31#define FW_8192C_START_ADDRESS 0x1000 31#define FW_8192C_START_ADDRESS 0x1000
32#define FW_8192C_PAGE_SIZE 4096 32#define FW_8192C_PAGE_SIZE 4096
33#define FW_8723A_POLLING_TIMEOUT_COUNT 6000 33#define FW_8723A_POLLING_TIMEOUT_COUNT 1000
34#define FW_8723B_POLLING_TIMEOUT_COUNT 6000
34#define FW_8192C_POLLING_DELAY 5 35#define FW_8192C_POLLING_DELAY 5
35 36
36#define MCUFWDL_RDY BIT(1) 37#define MCUFWDL_RDY BIT(1)
@@ -99,25 +100,6 @@ enum rtl8723be_cmd {
99 MAX_8723BE_H2CCMD 100 MAX_8723BE_H2CCMD
100}; 101};
101 102
102struct rtl92c_firmware_header {
103 u16 signature;
104 u8 category;
105 u8 function;
106 u16 version;
107 u8 subversion;
108 u8 rsvd1;
109 u8 month;
110 u8 date;
111 u8 hour;
112 u8 minute;
113 u16 ramcodesize;
114 u16 rsvd2;
115 u32 svnindex;
116 u32 rsvd3;
117 u32 rsvd4;
118 u32 rsvd5;
119};
120
121void rtl8723ae_firmware_selfreset(struct ieee80211_hw *hw); 103void rtl8723ae_firmware_selfreset(struct ieee80211_hw *hw);
122void rtl8723be_firmware_selfreset(struct ieee80211_hw *hw); 104void rtl8723be_firmware_selfreset(struct ieee80211_hw *hw);
123void rtl8723_enable_fw_download(struct ieee80211_hw *hw, bool enable); 105void rtl8723_enable_fw_download(struct ieee80211_hw *hw, bool enable);
diff --git a/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c b/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c
index 56aff32b9c56..75cbd1509b52 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c
@@ -96,7 +96,7 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
96 u8 rfpi_enable = 0; 96 u8 rfpi_enable = 0;
97 u32 retvalue; 97 u32 retvalue;
98 98
99 offset &= 0x3f; 99 offset &= 0xff;
100 newoffset = offset; 100 newoffset = offset;
101 if (RT_CANNOT_IO(hw)) { 101 if (RT_CANNOT_IO(hw)) {
102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n"); 102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
@@ -150,7 +150,7 @@ void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
150 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n"); 150 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
151 return; 151 return;
152 } 152 }
153 offset &= 0x3f; 153 offset &= 0xff;
154 newoffset = offset; 154 newoffset = offset;
155 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 155 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
156 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 156 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
@@ -390,14 +390,21 @@ EXPORT_SYMBOL_GPL(rtl8723_phy_reload_mac_registers);
390void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg, 390void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
391 bool is_patha_on, bool is2t) 391 bool is_patha_on, bool is2t)
392{ 392{
393 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
393 u32 pathon; 394 u32 pathon;
394 u32 i; 395 u32 i;
395 396
396 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; 397 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
397 if (!is2t) { 398 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
398 pathon = 0x0bdb25a0; 399 if (!is2t) {
399 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); 400 pathon = 0x0bdb25a0;
401 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
402 } else {
403 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
404 }
400 } else { 405 } else {
406 /* rtl8723be */
407 pathon = 0x01c00014;
401 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); 408 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
402 } 409 }
403 410
diff --git a/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
index 58bbaf432b0e..310d3163dc5b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8821ae/hw.c
@@ -48,7 +48,9 @@ static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
48 struct rtl_priv *rtlpriv = rtl_priv(hw); 48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
51 unsigned long flags;
51 52
53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
52 while (skb_queue_len(&ring->queue)) { 54 while (skb_queue_len(&ring->queue)) {
53 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 55 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
54 struct sk_buff *skb = __skb_dequeue(&ring->queue); 56 struct sk_buff *skb = __skb_dequeue(&ring->queue);
@@ -60,6 +62,7 @@ static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
60 kfree_skb(skb); 62 kfree_skb(skb);
61 ring->idx = (ring->idx + 1) % ring->entries; 63 ring->idx = (ring->idx + 1) % ring->entries;
62 } 64 }
65 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
63} 66}
64 67
65static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 68static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index e34b8eaa9ba7..92874b1a8aa6 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -330,13 +330,7 @@ enum hardware_type {
330#define IS_HARDWARE_TYPE_8723(rtlhal) \ 330#define IS_HARDWARE_TYPE_8723(rtlhal) \
331(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) 331(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
332 332
333#define RX_HAL_IS_CCK_RATE(_pdesc)\ 333#define RX_HAL_IS_CCK_RATE(rxmcs) \
334 (_pdesc->rxmcs == DESC92_RATE1M || \
335 _pdesc->rxmcs == DESC92_RATE2M || \
336 _pdesc->rxmcs == DESC92_RATE5_5M || \
337 _pdesc->rxmcs == DESC92_RATE11M)
338
339#define RTL8723E_RX_HAL_IS_CCK_RATE(rxmcs) \
340 ((rxmcs) == DESC92_RATE1M || \ 334 ((rxmcs) == DESC92_RATE1M || \
341 (rxmcs) == DESC92_RATE2M || \ 335 (rxmcs) == DESC92_RATE2M || \
342 (rxmcs) == DESC92_RATE5_5M || \ 336 (rxmcs) == DESC92_RATE5_5M || \
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 23:28:13 -0400