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authorYaniv Rosner <yanivr@broadcom.com>2011-01-17 23:33:36 -0500
committerDavid S. Miller <davem@davemloft.net>2011-01-18 19:10:38 -0500
commit5c99274b0177cd614455c277b1a4d4410d9cb702 (patch)
treeab857db34f7375c19e6e7d97af13534fe0b6d224
parent1f48353a3ce7297f5150b47e21df5ec212876e5d (diff)
bnx2x: Fix BCM8073/BCM8727 microcode loading
Improve microcode loading verification before proceeding to next stage Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c73
1 files changed, 43 insertions, 30 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 36a88448b245..500258d38cf1 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -3870,11 +3870,14 @@ static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3870 pause_result); 3870 pause_result);
3871 } 3871 }
3872} 3872}
3873 3873static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3874static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3875 struct bnx2x_phy *phy, 3874 struct bnx2x_phy *phy,
3876 u8 port) 3875 u8 port)
3877{ 3876{
3877 u32 count = 0;
3878 u16 fw_ver1, fw_msgout;
3879 u8 rc = 0;
3880
3878 /* Boot port from external ROM */ 3881 /* Boot port from external ROM */
3879 /* EDC grst */ 3882 /* EDC grst */
3880 bnx2x_cl45_write(bp, phy, 3883 bnx2x_cl45_write(bp, phy,
@@ -3904,14 +3907,45 @@ static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3904 MDIO_PMA_REG_GEN_CTRL, 3907 MDIO_PMA_REG_GEN_CTRL,
3905 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 3908 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3906 3909
3907 /* wait for 120ms for code download via SPI port */ 3910 /* Delay 100ms per the PHY specifications */
3908 msleep(120); 3911 msleep(100);
3912
3913 /* 8073 sometimes taking longer to download */
3914 do {
3915 count++;
3916 if (count > 300) {
3917 DP(NETIF_MSG_LINK,
3918 "bnx2x_8073_8727_external_rom_boot port %x:"
3919 "Download failed. fw version = 0x%x\n",
3920 port, fw_ver1);
3921 rc = -EINVAL;
3922 break;
3923 }
3924
3925 bnx2x_cl45_read(bp, phy,
3926 MDIO_PMA_DEVAD,
3927 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3928 bnx2x_cl45_read(bp, phy,
3929 MDIO_PMA_DEVAD,
3930 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3931
3932 msleep(1);
3933 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3934 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
3909 3936
3910 /* Clear ser_boot_ctl bit */ 3937 /* Clear ser_boot_ctl bit */
3911 bnx2x_cl45_write(bp, phy, 3938 bnx2x_cl45_write(bp, phy,
3912 MDIO_PMA_DEVAD, 3939 MDIO_PMA_DEVAD,
3913 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 3940 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3914 bnx2x_save_bcm_spirom_ver(bp, phy, port); 3941 bnx2x_save_bcm_spirom_ver(bp, phy, port);
3942
3943 DP(NETIF_MSG_LINK,
3944 "bnx2x_8073_8727_external_rom_boot port %x:"
3945 "Download complete. fw version = 0x%x\n",
3946 port, fw_ver1);
3947
3948 return rc;
3915} 3949}
3916 3950
3917static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp, 3951static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
@@ -7721,7 +7755,6 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7721 7755
7722 /* PART2 - Download firmware to both phys */ 7756 /* PART2 - Download firmware to both phys */
7723 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 7757 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7724 u16 fw_ver1;
7725 if (CHIP_IS_E2(bp)) 7758 if (CHIP_IS_E2(bp))
7726 port_of_path = 0; 7759 port_of_path = 0;
7727 else 7760 else
@@ -7729,19 +7762,9 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7729 7762
7730 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 7763 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7731 phy_blk[port]->addr); 7764 phy_blk[port]->addr);
7732 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 7765 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7733 port_of_path); 7766 port_of_path))
7734
7735 bnx2x_cl45_read(bp, phy_blk[port],
7736 MDIO_PMA_DEVAD,
7737 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7738 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7739 DP(NETIF_MSG_LINK,
7740 "bnx2x_8073_common_init_phy port %x:"
7741 "Download failed. fw version = 0x%x\n",
7742 port, fw_ver1);
7743 return -EINVAL; 7767 return -EINVAL;
7744 }
7745 7768
7746 /* Only set bit 10 = 1 (Tx power down) */ 7769 /* Only set bit 10 = 1 (Tx power down) */
7747 bnx2x_cl45_read(bp, phy_blk[port], 7770 bnx2x_cl45_read(bp, phy_blk[port],
@@ -7906,27 +7929,17 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7906 } 7929 }
7907 /* PART2 - Download firmware to both phys */ 7930 /* PART2 - Download firmware to both phys */
7908 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 7931 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7909 u16 fw_ver1;
7910 if (CHIP_IS_E2(bp)) 7932 if (CHIP_IS_E2(bp))
7911 port_of_path = 0; 7933 port_of_path = 0;
7912 else 7934 else
7913 port_of_path = port; 7935 port_of_path = port;
7914 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 7936 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7915 phy_blk[port]->addr); 7937 phy_blk[port]->addr);
7916 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 7938 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7917 port_of_path); 7939 port_of_path))
7918 bnx2x_cl45_read(bp, phy_blk[port],
7919 MDIO_PMA_DEVAD,
7920 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7921 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7922 DP(NETIF_MSG_LINK,
7923 "bnx2x_8727_common_init_phy port %x:"
7924 "Download failed. fw version = 0x%x\n",
7925 port, fw_ver1);
7926 return -EINVAL; 7940 return -EINVAL;
7927 }
7928 }
7929 7941
7942 }
7930 return 0; 7943 return 0;
7931} 7944}
7932 7945