Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm

Pull ARM fixes from Russell King.

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
  ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
  ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
  ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
  ARM: 7611/1: VIC: fix bug in VIC irqdomain code
  ARM: 7610/1: versatile: bump IRQ numbers
  ARM: 7609/1: disable errata work-arounds which access secure registers
  ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier

7 files changed, 40 insertions, 22 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab864d9545dd..67874b82a4ed 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1229,6 +1229,7 @@ config ARM_ERRATA_430973
 config ARM_ERRATA_458693
         bool "ARM errata: Processor deadlock when a false hazard is created"
         depends on CPU_V7
+        depends on !ARCH_MULTIPLATFORM
         help
           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
           erratum. For very specific sequences of memory operations, it is
@@ -1242,6 +1243,7 @@ config ARM_ERRATA_458693
 config ARM_ERRATA_460075
         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
         depends on CPU_V7
+        depends on !ARCH_MULTIPLATFORM
         help
           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
           erratum. Any asynchronous access to the L2 cache may encounter a
@@ -1254,6 +1256,7 @@ config ARM_ERRATA_460075
 config ARM_ERRATA_742230
         bool "ARM errata: DMB operation may be faulty"
         depends on CPU_V7 && SMP
+        depends on !ARCH_MULTIPLATFORM
         help
           This option enables the workaround for the 742230 Cortex-A9
           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
@@ -1266,6 +1269,7 @@ config ARM_ERRATA_742230
 config ARM_ERRATA_742231
         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
         depends on CPU_V7 && SMP
+        depends on !ARCH_MULTIPLATFORM
         help
           This option enables the workaround for the 742231 Cortex-A9
           (r2p0..r2p2) erratum. Under certain conditions, specific to the
@@ -1316,6 +1320,7 @@ config PL310_ERRATA_727915
 config ARM_ERRATA_743622
         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
         depends on CPU_V7
+        depends on !ARCH_MULTIPLATFORM
         help
           This option enables the workaround for the 743622 Cortex-A9
           (r2p*) erratum. Under very rare conditions, a faulty
@@ -1329,6 +1334,7 @@ config ARM_ERRATA_743622
 config ARM_ERRATA_751472
         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
         depends on CPU_V7
+        depends on !ARCH_MULTIPLATFORM
         help
           This option enables the workaround for the 751472 Cortex-A9 (prior
           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index e4df17ca90c7..8f324b99416e 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -206,6 +206,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
                                 struct device_node *node)
 {
         struct vic_device *v;
+        int i;
 
         if (vic_id >= ARRAY_SIZE(vic_devices)) {
                 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
@@ -220,6 +221,10 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
         vic_id++;
         v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
                                           &vic_irqdomain_ops, v);
+        /* create an IRQ mapping for each valid IRQ */
+        for (i = 0; i < fls(valid_sources); i++)
+                if (valid_sources & (1 << i))
+                        irq_create_mapping(v->domain, i);
 }
 
 static void vic_ack_irq(struct irq_data *d)
@@ -416,9 +421,9 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
                 return -EIO;
 
         /*
-         * Passing -1 as first IRQ makes the simple domain allocate descriptors
+         * Passing 0 as first IRQ makes the simple domain allocate descriptors
          */
-        __vic_init(regs, -1, ~0, ~0, node);
+        __vic_init(regs, 0, ~0, ~0, node);
 
         return 0;
 }
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 1ad0d76de8c7..3e628fd7a674 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -841,8 +841,6 @@ config SOC_IMX6Q
         select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
-        select ARM_ERRATA_743622
-        select ARM_ERRATA_751472
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_ERRATA_775420
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h
index bf44c61bd1f6..0fd771ca617b 100644
--- a/arch/arm/mach-versatile/include/mach/irqs.h
+++ b/arch/arm/mach-versatile/include/mach/irqs.h
@@ -25,7 +25,7 @@
  *  IRQ interrupts definitions are the same as the INT definitions
  *  held within platform.h
  */
-#define IRQ_VIC_START           0
+#define IRQ_VIC_START           32
 #define IRQ_WDOGINT             (IRQ_VIC_START + INT_WDOGINT)
 #define IRQ_SOFTINT             (IRQ_VIC_START + INT_SOFTINT)
 #define IRQ_COMMRx              (IRQ_VIC_START + INT_COMMRx)
@@ -100,7 +100,7 @@
 /*
  * Secondary interrupt controller
  */
-#define IRQ_SIC_START           32
+#define IRQ_SIC_START           64
 #define IRQ_SIC_MMCI0B          (IRQ_SIC_START + SIC_INT_MMCI0B)
 #define IRQ_SIC_MMCI1B          (IRQ_SIC_START + SIC_INT_MMCI1B)
 #define IRQ_SIC_KMI0            (IRQ_SIC_START + SIC_INT_KMI0)
@@ -120,7 +120,7 @@
 #define IRQ_SIC_PCI1            (IRQ_SIC_START + SIC_INT_PCI1)
 #define IRQ_SIC_PCI2            (IRQ_SIC_START + SIC_INT_PCI2)
 #define IRQ_SIC_PCI3            (IRQ_SIC_START + SIC_INT_PCI3)
-#define IRQ_SIC_END             63
+#define IRQ_SIC_END             95
 
 #define IRQ_GPIO0_START         (IRQ_SIC_END + 1)
 #define IRQ_GPIO0_END           (IRQ_GPIO0_START + 31)
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 99e63f5f99d1..52d315b792c8 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -42,7 +42,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         bool "Enable A5 and A9 only errata work-arounds"
         default y
         select ARM_ERRATA_720789
-        select ARM_ERRATA_751472
         select PL310_ERRATA_753970 if CACHE_PL310
         help
           Provides common dependencies for Versatile Express platforms
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 6911b8b2745c..c2f37390308a 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -352,7 +352,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                 /* Unmapped register. */
                 sync_reg_offset = L2X0_DUMMY_REG;
 #endif
-                outer_cache.set_debug = pl310_set_debug;
+                if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
+                        outer_cache.set_debug = pl310_set_debug;
                 break;
         case L2X0_CACHE_ID_PART_L210:
                 ways = (aux >> 13) & 0xf;
@@ -459,8 +460,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end,
         unsigned long flags;
 
         raw_spin_lock_irqsave(&l2x0_lock, flags);
-        writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
-        writel(end, l2x0_base + offset);
+        writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+        writel_relaxed(end, l2x0_base + offset);
         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 
         cache_sync();
@@ -505,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
 
 static void aurora_flush_range(unsigned long start, unsigned long end)
 {
-        if (!l2_wt_override) {
-                start &= ~(CACHE_LINE_SIZE - 1);
-                end = ALIGN(end, CACHE_LINE_SIZE);
-                while (start != end) {
-                        unsigned long range_end = calc_range_end(start, end);
+        start &= ~(CACHE_LINE_SIZE - 1);
+        end = ALIGN(end, CACHE_LINE_SIZE);
+        while (start != end) {
+                unsigned long range_end = calc_range_end(start, end);
+                /*
+                 * If L2 is forced to WT, the L2 will always be clean and we
+                 * just need to invalidate.
+                 */
+                if (l2_wt_override)
                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
-                                        AURORA_FLUSH_RANGE_REG);
-                        start = range_end;
-                }
+                                                        AURORA_INVAL_RANGE_REG);
+                else
+                        aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+                                                        AURORA_FLUSH_RANGE_REG);
+                start = range_end;
         }
 }
 
@@ -668,8 +675,9 @@ static void pl310_resume(void)
 static void aurora_resume(void)
 {
         if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-                writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
-                writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+                writel_relaxed(l2x0_saved_regs.aux_ctrl,
+                                l2x0_base + L2X0_AUX_CTRL);
+                writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
         }
 }
 
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 350f6a74992b..3a3c015f8d5c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -169,6 +169,7 @@ __v7_ca15mp_setup:
         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
         mcreq   p15, 0, r0, c1, c0, 1
 #endif
+        b       __v7_setup
 
 __v7_pj4b_setup:
 #ifdef CONFIG_CPU_PJ4B
@@ -245,7 +246,8 @@ __v7_setup:
         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
         teq     r0, r10
         bne     2f
-#ifdef CONFIG_ARM_ERRATA_430973
+#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
+
         teq     r5, #0x00100000                 @ only present in r1p*
         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
         orreq   r10, r10, #(1 << 6)             @ set IBE to 1