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authorAlex Deucher <alexdeucher@gmail.com>2011-05-20 12:35:22 -0400
committerDave Airlie <airlied@redhat.com>2011-05-23 18:59:33 -0400
commit5bfa487955016dc99f83195921f74287743f0033 (patch)
treec86a182869c84bdf6236e050d1af11bc76a39ffb
parentac89af1e1010640db072416c786f97391b85790f (diff)
drm/radeon/kms: properly set num banks for fusion asics
Needed by userspace for 2D tiled buffer alignment Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 864e853cc0ec..34cd5a878088 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1933,8 +1933,12 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1933 rdev->config.evergreen.tile_config |= (3 << 0); 1933 rdev->config.evergreen.tile_config |= (3 << 0);
1934 break; 1934 break;
1935 } 1935 }
1936 rdev->config.evergreen.tile_config |= 1936 /* num banks is 8 on all fusion asics */
1937 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 1937 if (rdev->flags & RADEON_IS_IGP)
1938 rdev->config.evergreen.tile_config |= 8 << 4;
1939 else
1940 rdev->config.evergreen.tile_config |=
1941 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1938 rdev->config.evergreen.tile_config |= 1942 rdev->config.evergreen.tile_config |=
1939 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; 1943 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1940 rdev->config.evergreen.tile_config |= 1944 rdev->config.evergreen.tile_config |=