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authorBen Hutchings <bhutchings@solarflare.com>2009-08-26 04:17:19 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-26 20:38:54 -0400
commit5afaa753d681c437419e3dd9b532c2712dd1d2ea (patch)
treecaf3dc892f20ae1ce7603df97fefdb739d100892
parent771046d7b1def64c00a5a47ca48526cbbacd7fe3 (diff)
sfc: QT2025C: Use hard reset only
At probe time, falcon_reset_hw() performs a hard reset of the PHY along with Falcon. There is no need to perform a soft reset later, and any access to standard MDIO registers before the PHY firmware has booted can interrupt the boot process, making the port unusable. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/sfc/xfp_phy.c19
1 files changed, 10 insertions, 9 deletions
diff --git a/drivers/net/sfc/xfp_phy.c b/drivers/net/sfc/xfp_phy.c
index bb2e6afd0829..e6b3d5eaddba 100644
--- a/drivers/net/sfc/xfp_phy.c
+++ b/drivers/net/sfc/xfp_phy.c
@@ -97,23 +97,24 @@ static int qt2025c_wait_reset(struct efx_nic *efx)
97 return 0; 97 return 0;
98} 98}
99 99
100/* Reset the PHYXS MMD. This is documented (for the Quake PHYs) as doing
101 * a complete soft reset.
102 */
103static int xfp_reset_phy(struct efx_nic *efx) 100static int xfp_reset_phy(struct efx_nic *efx)
104{ 101{
105 int rc; 102 int rc;
106 103
107 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
108 XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
109 XFP_RESET_WAIT);
110 if (rc < 0)
111 goto fail;
112
113 if (efx->phy_type == PHY_TYPE_QT2025C) { 104 if (efx->phy_type == PHY_TYPE_QT2025C) {
105 /* Wait for the reset triggered by falcon_reset_hw()
106 * to complete */
114 rc = qt2025c_wait_reset(efx); 107 rc = qt2025c_wait_reset(efx);
115 if (rc < 0) 108 if (rc < 0)
116 goto fail; 109 goto fail;
110 } else {
111 /* Reset the PHYXS MMD. This is documented as doing
112 * a complete soft reset. */
113 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
114 XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
115 XFP_RESET_WAIT);
116 if (rc < 0)
117 goto fail;
117 } 118 }
118 119
119 /* Wait 250ms for the PHY to complete bootup */ 120 /* Wait 250ms for the PHY to complete bootup */