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authorDavid S. Miller <davem@davemloft.net>2011-05-04 16:54:50 -0400
committerDavid S. Miller <davem@davemloft.net>2011-05-04 16:54:50 -0400
commit5a412ad7f4c95bb5b756aa12b52646e857e7c75d (patch)
treecff969a08da663077938e41bdeaa43855e00d4d9
parent301102cc832f9f3e24c5748705f152eaa7c307f6 (diff)
parent6716344c521bb585c1b89987c918d4b83b81adbe (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/jkirsher/net-next-2.6
-rw-r--r--drivers/net/e100.c2
-rw-r--r--drivers/net/igb/e1000_82575.c8
-rw-r--r--drivers/net/igbvf/ethtool.c6
-rw-r--r--drivers/net/ixgb/ixgb.h3
-rw-r--r--drivers/net/ixgb/ixgb_ethtool.c46
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c1
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c38
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c440
-rw-r--r--drivers/net/ixgbe/ixgbe_common.h8
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c115
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c7
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c10
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h7
-rw-r--r--drivers/net/ixgbe/ixgbe_x540.c69
14 files changed, 559 insertions, 201 deletions
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index c810cda3bf1f..29f812dc1098 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -1512,7 +1512,7 @@ static int e100_phy_init(struct nic *nic)
1512 1512
1513static int e100_hw_init(struct nic *nic) 1513static int e100_hw_init(struct nic *nic)
1514{ 1514{
1515 int err; 1515 int err = 0;
1516 1516
1517 e100_hw_reset(nic); 1517 e100_hw_reset(nic);
1518 1518
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index 0cd41c49bc17..0f563c8c5ffc 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -244,6 +244,14 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
244 */ 244 */
245 size += NVM_WORD_SIZE_BASE_SHIFT; 245 size += NVM_WORD_SIZE_BASE_SHIFT;
246 246
247 /*
248 * Check for invalid size
249 */
250 if ((hw->mac.type == e1000_82576) && (size > 15)) {
251 printk("igb: The NVM size is not valid, "
252 "defaulting to 32K.\n");
253 size = 15;
254 }
247 nvm->word_size = 1 << size; 255 nvm->word_size = 1 << size;
248 if (nvm->word_size == (1 << 15)) 256 if (nvm->word_size == (1 << 15))
249 nvm->page_size = 128; 257 nvm->page_size = 128;
diff --git a/drivers/net/igbvf/ethtool.c b/drivers/net/igbvf/ethtool.c
index 112ae15b2d49..b0b14d63dfbf 100644
--- a/drivers/net/igbvf/ethtool.c
+++ b/drivers/net/igbvf/ethtool.c
@@ -391,11 +391,6 @@ static int igbvf_set_wol(struct net_device *netdev,
391 return -EOPNOTSUPP; 391 return -EOPNOTSUPP;
392} 392}
393 393
394static int igbvf_phys_id(struct net_device *netdev, u32 data)
395{
396 return 0;
397}
398
399static int igbvf_get_coalesce(struct net_device *netdev, 394static int igbvf_get_coalesce(struct net_device *netdev,
400 struct ethtool_coalesce *ec) 395 struct ethtool_coalesce *ec)
401{ 396{
@@ -527,7 +522,6 @@ static const struct ethtool_ops igbvf_ethtool_ops = {
527 .self_test = igbvf_diag_test, 522 .self_test = igbvf_diag_test,
528 .get_sset_count = igbvf_get_sset_count, 523 .get_sset_count = igbvf_get_sset_count,
529 .get_strings = igbvf_get_strings, 524 .get_strings = igbvf_get_strings,
530 .phys_id = igbvf_phys_id,
531 .get_ethtool_stats = igbvf_get_ethtool_stats, 525 .get_ethtool_stats = igbvf_get_ethtool_stats,
532 .get_coalesce = igbvf_get_coalesce, 526 .get_coalesce = igbvf_get_coalesce,
533 .set_coalesce = igbvf_set_coalesce, 527 .set_coalesce = igbvf_set_coalesce,
diff --git a/drivers/net/ixgb/ixgb.h b/drivers/net/ixgb/ixgb.h
index 8f3df044e81e..49e8408f05fc 100644
--- a/drivers/net/ixgb/ixgb.h
+++ b/drivers/net/ixgb/ixgb.h
@@ -157,9 +157,6 @@ struct ixgb_adapter {
157 u16 link_duplex; 157 u16 link_duplex;
158 struct work_struct tx_timeout_task; 158 struct work_struct tx_timeout_task;
159 159
160 struct timer_list blink_timer;
161 unsigned long led_status;
162
163 /* TX */ 160 /* TX */
164 struct ixgb_desc_ring tx_ring ____cacheline_aligned_in_smp; 161 struct ixgb_desc_ring tx_ring ____cacheline_aligned_in_smp;
165 unsigned int restart_queue; 162 unsigned int restart_queue;
diff --git a/drivers/net/ixgb/ixgb_ethtool.c b/drivers/net/ixgb/ixgb_ethtool.c
index 5f224c387e0c..6da890b9534c 100644
--- a/drivers/net/ixgb/ixgb_ethtool.c
+++ b/drivers/net/ixgb/ixgb_ethtool.c
@@ -611,45 +611,23 @@ err_setup_rx:
611 return err; 611 return err;
612} 612}
613 613
614/* toggle LED 4 times per second = 2 "blinks" per second */
615#define IXGB_ID_INTERVAL (HZ/4)
616
617/* bit defines for adapter->led_status */
618#define IXGB_LED_ON 0
619
620static void
621ixgb_led_blink_callback(unsigned long data)
622{
623 struct ixgb_adapter *adapter = (struct ixgb_adapter *)data;
624
625 if (test_and_change_bit(IXGB_LED_ON, &adapter->led_status))
626 ixgb_led_off(&adapter->hw);
627 else
628 ixgb_led_on(&adapter->hw);
629
630 mod_timer(&adapter->blink_timer, jiffies + IXGB_ID_INTERVAL);
631}
632
633static int 614static int
634ixgb_phys_id(struct net_device *netdev, u32 data) 615ixgb_set_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
635{ 616{
636 struct ixgb_adapter *adapter = netdev_priv(netdev); 617 struct ixgb_adapter *adapter = netdev_priv(netdev);
637 618
638 if (!data) 619 switch (state) {
639 data = INT_MAX; 620 case ETHTOOL_ID_ACTIVE:
640 621 return 2;
641 if (!adapter->blink_timer.function) {
642 init_timer(&adapter->blink_timer);
643 adapter->blink_timer.function = ixgb_led_blink_callback;
644 adapter->blink_timer.data = (unsigned long)adapter;
645 }
646 622
647 mod_timer(&adapter->blink_timer, jiffies); 623 case ETHTOOL_ID_ON:
624 ixgb_led_on(&adapter->hw);
625 break;
648 626
649 msleep_interruptible(data * 1000); 627 case ETHTOOL_ID_OFF:
650 del_timer_sync(&adapter->blink_timer); 628 case ETHTOOL_ID_INACTIVE:
651 ixgb_led_off(&adapter->hw); 629 ixgb_led_off(&adapter->hw);
652 clear_bit(IXGB_LED_ON, &adapter->led_status); 630 }
653 631
654 return 0; 632 return 0;
655} 633}
@@ -767,7 +745,7 @@ static const struct ethtool_ops ixgb_ethtool_ops = {
767 .set_msglevel = ixgb_set_msglevel, 745 .set_msglevel = ixgb_set_msglevel,
768 .set_tso = ixgb_set_tso, 746 .set_tso = ixgb_set_tso,
769 .get_strings = ixgb_get_strings, 747 .get_strings = ixgb_get_strings,
770 .phys_id = ixgb_phys_id, 748 .set_phys_id = ixgb_set_phys_id,
771 .get_sset_count = ixgb_get_sset_count, 749 .get_sset_count = ixgb_get_sset_count,
772 .get_ethtool_stats = ixgb_get_ethtool_stats, 750 .get_ethtool_stats = ixgb_get_ethtool_stats,
773 .get_flags = ethtool_op_get_flags, 751 .get_flags = ethtool_op_get_flags,
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 7a64f50435cf..8179e5060a18 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -1281,6 +1281,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
1281static struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1281static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1282 .init_params = &ixgbe_init_eeprom_params_generic, 1282 .init_params = &ixgbe_init_eeprom_params_generic,
1283 .read = &ixgbe_read_eerd_generic, 1283 .read = &ixgbe_read_eerd_generic,
1284 .read_buffer = &ixgbe_read_eerd_buffer_generic,
1284 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 1285 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
1285 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1286 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1286 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1287 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index d1cda36507f8..dba5ca6e35c4 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -110,7 +110,6 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
110 110
111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 &data_offset); 112 &data_offset);
113
114 if (ret_val != 0) 113 if (ret_val != 0)
115 goto setup_sfp_out; 114 goto setup_sfp_out;
116 115
@@ -130,7 +129,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
130 } 129 }
131 130
132 /* Release the semaphore */ 131 /* Release the semaphore */
133 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
134 /* 133 /*
135 * Delay obtaining semaphore again to allow FW access, 134 * Delay obtaining semaphore again to allow FW access,
136 * semaphore_delay is in ms usleep_range needs us. 135 * semaphore_delay is in ms usleep_range needs us.
@@ -2065,6 +2064,39 @@ out:
2065} 2064}
2066 2065
2067/** 2066/**
2067 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2068 * fastest available method
2069 *
2070 * @hw: pointer to hardware structure
2071 * @offset: offset of word in EEPROM to read
2072 * @words: number of words
2073 * @data: word(s) read from the EEPROM
2074 *
2075 * Retrieves 16 bit word(s) read from EEPROM
2076 **/
2077static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2078 u16 words, u16 *data)
2079{
2080 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2081 s32 ret_val = IXGBE_ERR_CONFIG;
2082
2083 /*
2084 * If EEPROM is detected and can be addressed using 14 bits,
2085 * use EERD otherwise use bit bang
2086 */
2087 if ((eeprom->type == ixgbe_eeprom_spi) &&
2088 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2089 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2090 data);
2091 else
2092 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2093 words,
2094 data);
2095
2096 return ret_val;
2097}
2098
2099/**
2068 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2100 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2069 * fastest available method 2101 * fastest available method
2070 * 2102 *
@@ -2140,7 +2172,9 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2140static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2172static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2141 .init_params = &ixgbe_init_eeprom_params_generic, 2173 .init_params = &ixgbe_init_eeprom_params_generic,
2142 .read = &ixgbe_read_eeprom_82599, 2174 .read = &ixgbe_read_eeprom_82599,
2175 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2143 .write = &ixgbe_write_eeprom_generic, 2176 .write = &ixgbe_write_eeprom_generic,
2177 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2144 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2178 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2145 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2179 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2146 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2180 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index cb2e8e18dd39..c4730cd39b22 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -55,6 +55,12 @@ static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num); 56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
58static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
61 u16 words, u16 *data);
62static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 u16 offset);
58 64
59/** 65/**
60 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 66 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
@@ -585,6 +591,8 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
585 /* Set default semaphore delay to 10ms which is a well 591 /* Set default semaphore delay to 10ms which is a well
586 * tested value */ 592 * tested value */
587 eeprom->semaphore_delay = 10; 593 eeprom->semaphore_delay = 10;
594 /* Clear EEPROM page size, it will be initialized as needed */
595 eeprom->word_page_size = 0;
588 596
589 /* 597 /*
590 * Check for EEPROM present first. 598 * Check for EEPROM present first.
@@ -617,26 +625,78 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
617} 625}
618 626
619/** 627/**
620 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 628 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
621 * @hw: pointer to hardware structure 629 * @hw: pointer to hardware structure
622 * @offset: offset within the EEPROM to be written to 630 * @offset: offset within the EEPROM to write
623 * @data: 16 bit word to be written to the EEPROM 631 * @words: number of words
632 * @data: 16 bit word(s) to write to EEPROM
624 * 633 *
625 * If ixgbe_eeprom_update_checksum is not called after this function, the 634 * Reads 16 bit word(s) from EEPROM through bit-bang method
626 * EEPROM will most likely contain an invalid checksum.
627 **/ 635 **/
628s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 636s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
637 u16 words, u16 *data)
629{ 638{
630 s32 status; 639 s32 status = 0;
631 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 640 u16 i, count;
632 641
633 hw->eeprom.ops.init_params(hw); 642 hw->eeprom.ops.init_params(hw);
634 643
635 if (offset >= hw->eeprom.word_size) { 644 if (words == 0) {
645 status = IXGBE_ERR_INVALID_ARGUMENT;
646 goto out;
647 }
648
649 if (offset + words > hw->eeprom.word_size) {
636 status = IXGBE_ERR_EEPROM; 650 status = IXGBE_ERR_EEPROM;
637 goto out; 651 goto out;
638 } 652 }
639 653
654 /*
655 * The EEPROM page size cannot be queried from the chip. We do lazy
656 * initialization. It is worth to do that when we write large buffer.
657 */
658 if ((hw->eeprom.word_page_size == 0) &&
659 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
660 ixgbe_detect_eeprom_page_size_generic(hw, offset);
661
662 /*
663 * We cannot hold synchronization semaphores for too long
664 * to avoid other entity starvation. However it is more efficient
665 * to read in bursts than synchronizing access for each word.
666 */
667 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
668 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
669 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
670 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
671 count, &data[i]);
672
673 if (status != 0)
674 break;
675 }
676
677out:
678 return status;
679}
680
681/**
682 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
683 * @hw: pointer to hardware structure
684 * @offset: offset within the EEPROM to be written to
685 * @words: number of word(s)
686 * @data: 16 bit word(s) to be written to the EEPROM
687 *
688 * If ixgbe_eeprom_update_checksum is not called after this function, the
689 * EEPROM will most likely contain an invalid checksum.
690 **/
691static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
692 u16 words, u16 *data)
693{
694 s32 status;
695 u16 word;
696 u16 page_size;
697 u16 i;
698 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
699
640 /* Prepare the EEPROM for writing */ 700 /* Prepare the EEPROM for writing */
641 status = ixgbe_acquire_eeprom(hw); 701 status = ixgbe_acquire_eeprom(hw);
642 702
@@ -648,62 +708,147 @@ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
648 } 708 }
649 709
650 if (status == 0) { 710 if (status == 0) {
651 ixgbe_standby_eeprom(hw); 711 for (i = 0; i < words; i++) {
712 ixgbe_standby_eeprom(hw);
652 713
653 /* Send the WRITE ENABLE command (8 bit opcode ) */ 714 /* Send the WRITE ENABLE command (8 bit opcode ) */
654 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 715 ixgbe_shift_out_eeprom_bits(hw,
655 IXGBE_EEPROM_OPCODE_BITS); 716 IXGBE_EEPROM_WREN_OPCODE_SPI,
717 IXGBE_EEPROM_OPCODE_BITS);
656 718
657 ixgbe_standby_eeprom(hw); 719 ixgbe_standby_eeprom(hw);
658 720
659 /* 721 /*
660 * Some SPI eeproms use the 8th address bit embedded in the 722 * Some SPI eeproms use the 8th address bit embedded
661 * opcode 723 * in the opcode
662 */ 724 */
663 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 725 if ((hw->eeprom.address_bits == 8) &&
664 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 726 ((offset + i) >= 128))
727 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
728
729 /* Send the Write command (8-bit opcode + addr) */
730 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
731 IXGBE_EEPROM_OPCODE_BITS);
732 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
733 hw->eeprom.address_bits);
734
735 page_size = hw->eeprom.word_page_size;
736
737 /* Send the data in burst via SPI*/
738 do {
739 word = data[i];
740 word = (word >> 8) | (word << 8);
741 ixgbe_shift_out_eeprom_bits(hw, word, 16);
742
743 if (page_size == 0)
744 break;
745
746 /* do not wrap around page */
747 if (((offset + i) & (page_size - 1)) ==
748 (page_size - 1))
749 break;
750 } while (++i < words);
751
752 ixgbe_standby_eeprom(hw);
753 usleep_range(10000, 20000);
754 }
755 /* Done with writing - release the EEPROM */
756 ixgbe_release_eeprom(hw);
757 }
665 758
666 /* Send the Write command (8-bit opcode + addr) */ 759 return status;
667 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 760}
668 IXGBE_EEPROM_OPCODE_BITS);
669 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
670 hw->eeprom.address_bits);
671 761
672 /* Send the data */ 762/**
673 data = (data >> 8) | (data << 8); 763 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
674 ixgbe_shift_out_eeprom_bits(hw, data, 16); 764 * @hw: pointer to hardware structure
675 ixgbe_standby_eeprom(hw); 765 * @offset: offset within the EEPROM to be written to
766 * @data: 16 bit word to be written to the EEPROM
767 *
768 * If ixgbe_eeprom_update_checksum is not called after this function, the
769 * EEPROM will most likely contain an invalid checksum.
770 **/
771s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
772{
773 s32 status;
676 774
677 /* Done with writing - release the EEPROM */ 775 hw->eeprom.ops.init_params(hw);
678 ixgbe_release_eeprom(hw); 776
777 if (offset >= hw->eeprom.word_size) {
778 status = IXGBE_ERR_EEPROM;
779 goto out;
679 } 780 }
680 781
782 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
783
681out: 784out:
682 return status; 785 return status;
683} 786}
684 787
685/** 788/**
686 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 789 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
687 * @hw: pointer to hardware structure 790 * @hw: pointer to hardware structure
688 * @offset: offset within the EEPROM to be read 791 * @offset: offset within the EEPROM to be read
689 * @data: read 16 bit value from EEPROM 792 * @words: number of word(s)
793 * @data: read 16 bit words(s) from EEPROM
690 * 794 *
691 * Reads 16 bit value from EEPROM through bit-bang method 795 * Reads 16 bit word(s) from EEPROM through bit-bang method
692 **/ 796 **/
693s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 797s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
694 u16 *data) 798 u16 words, u16 *data)
695{ 799{
696 s32 status; 800 s32 status = 0;
697 u16 word_in; 801 u16 i, count;
698 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
699 802
700 hw->eeprom.ops.init_params(hw); 803 hw->eeprom.ops.init_params(hw);
701 804
702 if (offset >= hw->eeprom.word_size) { 805 if (words == 0) {
806 status = IXGBE_ERR_INVALID_ARGUMENT;
807 goto out;
808 }
809
810 if (offset + words > hw->eeprom.word_size) {
703 status = IXGBE_ERR_EEPROM; 811 status = IXGBE_ERR_EEPROM;
704 goto out; 812 goto out;
705 } 813 }
706 814
815 /*
816 * We cannot hold synchronization semaphores for too long
817 * to avoid other entity starvation. However it is more efficient
818 * to read in bursts than synchronizing access for each word.
819 */
820 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
821 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
822 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
823
824 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
825 count, &data[i]);
826
827 if (status != 0)
828 break;
829 }
830
831out:
832 return status;
833}
834
835/**
836 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
837 * @hw: pointer to hardware structure
838 * @offset: offset within the EEPROM to be read
839 * @words: number of word(s)
840 * @data: read 16 bit word(s) from EEPROM
841 *
842 * Reads 16 bit word(s) from EEPROM through bit-bang method
843 **/
844static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
845 u16 words, u16 *data)
846{
847 s32 status;
848 u16 word_in;
849 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
850 u16 i;
851
707 /* Prepare the EEPROM for reading */ 852 /* Prepare the EEPROM for reading */
708 status = ixgbe_acquire_eeprom(hw); 853 status = ixgbe_acquire_eeprom(hw);
709 854
@@ -715,104 +860,208 @@ s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
715 } 860 }
716 861
717 if (status == 0) { 862 if (status == 0) {
718 ixgbe_standby_eeprom(hw); 863 for (i = 0; i < words; i++) {
864 ixgbe_standby_eeprom(hw);
865 /*
866 * Some SPI eeproms use the 8th address bit embedded
867 * in the opcode
868 */
869 if ((hw->eeprom.address_bits == 8) &&
870 ((offset + i) >= 128))
871 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
872
873 /* Send the READ command (opcode + addr) */
874 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
875 IXGBE_EEPROM_OPCODE_BITS);
876 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
877 hw->eeprom.address_bits);
878
879 /* Read the data. */
880 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
881 data[i] = (word_in >> 8) | (word_in << 8);
882 }
719 883
720 /* 884 /* End this read operation */
721 * Some SPI eeproms use the 8th address bit embedded in the 885 ixgbe_release_eeprom(hw);
722 * opcode 886 }
723 */
724 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
725 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
726 887
727 /* Send the READ command (opcode + addr) */ 888 return status;
728 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 889}
729 IXGBE_EEPROM_OPCODE_BITS);
730 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
731 hw->eeprom.address_bits);
732 890
733 /* Read the data. */ 891/**
734 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 892 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
735 *data = (word_in >> 8) | (word_in << 8); 893 * @hw: pointer to hardware structure
894 * @offset: offset within the EEPROM to be read
895 * @data: read 16 bit value from EEPROM
896 *
897 * Reads 16 bit value from EEPROM through bit-bang method
898 **/
899s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
900 u16 *data)
901{
902 s32 status;
736 903
737 /* End this read operation */ 904 hw->eeprom.ops.init_params(hw);
738 ixgbe_release_eeprom(hw); 905
906 if (offset >= hw->eeprom.word_size) {
907 status = IXGBE_ERR_EEPROM;
908 goto out;
739 } 909 }
740 910
911 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
912
741out: 913out:
742 return status; 914 return status;
743} 915}
744 916
745/** 917/**
746 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 918 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
747 * @hw: pointer to hardware structure 919 * @hw: pointer to hardware structure
748 * @offset: offset of word in the EEPROM to read 920 * @offset: offset of word in the EEPROM to read
749 * @data: word read from the EEPROM 921 * @words: number of word(s)
922 * @data: 16 bit word(s) from the EEPROM
750 * 923 *
751 * Reads a 16 bit word from the EEPROM using the EERD register. 924 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
752 **/ 925 **/
753s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 926s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
927 u16 words, u16 *data)
754{ 928{
755 u32 eerd; 929 u32 eerd;
756 s32 status; 930 s32 status = 0;
931 u32 i;
757 932
758 hw->eeprom.ops.init_params(hw); 933 hw->eeprom.ops.init_params(hw);
759 934
935 if (words == 0) {
936 status = IXGBE_ERR_INVALID_ARGUMENT;
937 goto out;
938 }
939
760 if (offset >= hw->eeprom.word_size) { 940 if (offset >= hw->eeprom.word_size) {
761 status = IXGBE_ERR_EEPROM; 941 status = IXGBE_ERR_EEPROM;
762 goto out; 942 goto out;
763 } 943 }
764 944
765 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) + 945 for (i = 0; i < words; i++) {
766 IXGBE_EEPROM_RW_REG_START; 946 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
947 IXGBE_EEPROM_RW_REG_START;
767 948
768 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 949 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
769 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 950 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
770 951
771 if (status == 0) 952 if (status == 0) {
772 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 953 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
773 IXGBE_EEPROM_RW_REG_DATA); 954 IXGBE_EEPROM_RW_REG_DATA);
774 else 955 } else {
775 hw_dbg(hw, "Eeprom read timed out\n"); 956 hw_dbg(hw, "Eeprom read timed out\n");
957 goto out;
958 }
959 }
960out:
961 return status;
962}
776 963
964/**
965 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
966 * @hw: pointer to hardware structure
967 * @offset: offset within the EEPROM to be used as a scratch pad
968 *
969 * Discover EEPROM page size by writing marching data at given offset.
970 * This function is called only when we are writing a new large buffer
971 * at given offset so the data would be overwritten anyway.
972 **/
973static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
974 u16 offset)
975{
976 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
977 s32 status = 0;
978 u16 i;
979
980 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
981 data[i] = i;
982
983 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
984 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
985 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
986 hw->eeprom.word_page_size = 0;
987 if (status != 0)
988 goto out;
989
990 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
991 if (status != 0)
992 goto out;
993
994 /*
995 * When writing in burst more than the actual page size
996 * EEPROM address wraps around current page.
997 */
998 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
999
1000 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1001 hw->eeprom.word_page_size);
777out: 1002out:
778 return status; 1003 return status;
779} 1004}
780 1005
781/** 1006/**
782 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1007 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1008 * @hw: pointer to hardware structure
1009 * @offset: offset of word in the EEPROM to read
1010 * @data: word read from the EEPROM
1011 *
1012 * Reads a 16 bit word from the EEPROM using the EERD register.
1013 **/
1014s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1015{
1016 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1017}
1018
1019/**
1020 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
783 * @hw: pointer to hardware structure 1021 * @hw: pointer to hardware structure
784 * @offset: offset of word in the EEPROM to write 1022 * @offset: offset of word in the EEPROM to write
785 * @data: word write to the EEPROM 1023 * @words: number of words
1024 * @data: word(s) write to the EEPROM
786 * 1025 *
787 * Write a 16 bit word to the EEPROM using the EEWR register. 1026 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
788 **/ 1027 **/
789s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1028s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1029 u16 words, u16 *data)
790{ 1030{
791 u32 eewr; 1031 u32 eewr;
792 s32 status; 1032 s32 status = 0;
1033 u16 i;
793 1034
794 hw->eeprom.ops.init_params(hw); 1035 hw->eeprom.ops.init_params(hw);
795 1036
1037 if (words == 0) {
1038 status = IXGBE_ERR_INVALID_ARGUMENT;
1039 goto out;
1040 }
1041
796 if (offset >= hw->eeprom.word_size) { 1042 if (offset >= hw->eeprom.word_size) {
797 status = IXGBE_ERR_EEPROM; 1043 status = IXGBE_ERR_EEPROM;
798 goto out; 1044 goto out;
799 } 1045 }
800 1046
801 eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1047 for (i = 0; i < words; i++) {
802 (data << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START; 1048 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1049 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1050 IXGBE_EEPROM_RW_REG_START;
803 1051
804 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1052 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
805 if (status != 0) { 1053 if (status != 0) {
806 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1054 hw_dbg(hw, "Eeprom write EEWR timed out\n");
807 goto out; 1055 goto out;
808 } 1056 }
809 1057
810 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1058 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
811 1059
812 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1060 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
813 if (status != 0) { 1061 if (status != 0) {
814 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1062 hw_dbg(hw, "Eeprom write EEWR timed out\n");
815 goto out; 1063 goto out;
1064 }
816 } 1065 }
817 1066
818out: 1067out:
@@ -820,6 +1069,19 @@ out:
820} 1069}
821 1070
822/** 1071/**
1072 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1073 * @hw: pointer to hardware structure
1074 * @offset: offset of word in the EEPROM to write
1075 * @data: word write to the EEPROM
1076 *
1077 * Write a 16 bit word to the EEPROM using the EEWR register.
1078 **/
1079s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1080{
1081 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1082}
1083
1084/**
823 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1085 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
824 * @hw: pointer to hardware structure 1086 * @hw: pointer to hardware structure
825 * @ee_reg: EEPROM flag for polling 1087 * @ee_reg: EEPROM flag for polling
diff --git a/drivers/net/ixgbe/ixgbe_common.h b/drivers/net/ixgbe/ixgbe_common.h
index e850adbb32a1..46be83cfb500 100644
--- a/drivers/net/ixgbe/ixgbe_common.h
+++ b/drivers/net/ixgbe/ixgbe_common.h
@@ -49,10 +49,18 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
49 49
50s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); 50s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
51s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 51s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
52s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
52s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); 54s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
55s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
53s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 57s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
58s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
54s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 60s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
55 u16 *data); 61 u16 *data);
62s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
63 u16 words, u16 *data);
56u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw); 64u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
57s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 65s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
58 u16 *checksum_val); 66 u16 *checksum_val);
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index bcba057b510f..f2efa3245352 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -847,11 +847,8 @@ static int ixgbe_get_eeprom(struct net_device *netdev,
847 if (!eeprom_buff) 847 if (!eeprom_buff)
848 return -ENOMEM; 848 return -ENOMEM;
849 849
850 for (i = 0; i < eeprom_len; i++) { 850 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
851 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i, 851 eeprom_buff);
852 &eeprom_buff[i])))
853 break;
854 }
855 852
856 /* Device's eeprom is always little-endian, word addressable */ 853 /* Device's eeprom is always little-endian, word addressable */
857 for (i = 0; i < eeprom_len; i++) 854 for (i = 0; i < eeprom_len; i++)
@@ -1236,46 +1233,62 @@ static const struct ixgbe_reg_test reg_test_82598[] = {
1236 { 0, 0, 0, 0 } 1233 { 0, 0, 0, 0 }
1237}; 1234};
1238 1235
1239static const u32 register_test_patterns[] = { 1236static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1240 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF 1237 u32 mask, u32 write)
1241}; 1238{
1242 1239 u32 pat, val, before;
1243#define REG_PATTERN_TEST(R, M, W) \ 1240 static const u32 test_pattern[] = {
1244{ \ 1241 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1245 u32 pat, val, before; \ 1242
1246 for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) { \ 1243 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1247 before = readl(adapter->hw.hw_addr + R); \ 1244 before = readl(adapter->hw.hw_addr + reg);
1248 writel((register_test_patterns[pat] & W), \ 1245 writel((test_pattern[pat] & write),
1249 (adapter->hw.hw_addr + R)); \ 1246 (adapter->hw.hw_addr + reg));
1250 val = readl(adapter->hw.hw_addr + R); \ 1247 val = readl(adapter->hw.hw_addr + reg);
1251 if (val != (register_test_patterns[pat] & W & M)) { \ 1248 if (val != (test_pattern[pat] & write & mask)) {
1252 e_err(drv, "pattern test reg %04X failed: got " \ 1249 e_err(drv, "pattern test reg %04X failed: got "
1253 "0x%08X expected 0x%08X\n", \ 1250 "0x%08X expected 0x%08X\n",
1254 R, val, (register_test_patterns[pat] & W & M)); \ 1251 reg, val, (test_pattern[pat] & write & mask));
1255 *data = R; \ 1252 *data = reg;
1256 writel(before, adapter->hw.hw_addr + R); \ 1253 writel(before, adapter->hw.hw_addr + reg);
1257 return 1; \ 1254 return 1;
1258 } \ 1255 }
1259 writel(before, adapter->hw.hw_addr + R); \ 1256 writel(before, adapter->hw.hw_addr + reg);
1260 } \ 1257 }
1258 return 0;
1261} 1259}
1262 1260
1263#define REG_SET_AND_CHECK(R, M, W) \ 1261static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1264{ \ 1262 u32 mask, u32 write)
1265 u32 val, before; \ 1263{
1266 before = readl(adapter->hw.hw_addr + R); \ 1264 u32 val, before;
1267 writel((W & M), (adapter->hw.hw_addr + R)); \ 1265 before = readl(adapter->hw.hw_addr + reg);
1268 val = readl(adapter->hw.hw_addr + R); \ 1266 writel((write & mask), (adapter->hw.hw_addr + reg));
1269 if ((W & M) != (val & M)) { \ 1267 val = readl(adapter->hw.hw_addr + reg);
1270 e_err(drv, "set/check reg %04X test failed: got 0x%08X " \ 1268 if ((write & mask) != (val & mask)) {
1271 "expected 0x%08X\n", R, (val & M), (W & M)); \ 1269 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1272 *data = R; \ 1270 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1273 writel(before, (adapter->hw.hw_addr + R)); \ 1271 *data = reg;
1274 return 1; \ 1272 writel(before, (adapter->hw.hw_addr + reg));
1275 } \ 1273 return 1;
1276 writel(before, (adapter->hw.hw_addr + R)); \ 1274 }
1275 writel(before, (adapter->hw.hw_addr + reg));
1276 return 0;
1277} 1277}
1278 1278
1279#define REG_PATTERN_TEST(reg, mask, write) \
1280 do { \
1281 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1282 return 1; \
1283 } while (0) \
1284
1285
1286#define REG_SET_AND_CHECK(reg, mask, write) \
1287 do { \
1288 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1289 return 1; \
1290 } while (0) \
1291
1279static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1292static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1280{ 1293{
1281 const struct ixgbe_reg_test *test; 1294 const struct ixgbe_reg_test *test;
@@ -1326,13 +1339,13 @@ static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1326 switch (test->test_type) { 1339 switch (test->test_type) {
1327 case PATTERN_TEST: 1340 case PATTERN_TEST:
1328 REG_PATTERN_TEST(test->reg + (i * 0x40), 1341 REG_PATTERN_TEST(test->reg + (i * 0x40),
1329 test->mask, 1342 test->mask,
1330 test->write); 1343 test->write);
1331 break; 1344 break;
1332 case SET_READ_TEST: 1345 case SET_READ_TEST:
1333 REG_SET_AND_CHECK(test->reg + (i * 0x40), 1346 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1334 test->mask, 1347 test->mask,
1335 test->write); 1348 test->write);
1336 break; 1349 break;
1337 case WRITE_NO_TEST: 1350 case WRITE_NO_TEST:
1338 writel(test->write, 1351 writel(test->write,
@@ -1341,18 +1354,18 @@ static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1341 break; 1354 break;
1342 case TABLE32_TEST: 1355 case TABLE32_TEST:
1343 REG_PATTERN_TEST(test->reg + (i * 4), 1356 REG_PATTERN_TEST(test->reg + (i * 4),
1344 test->mask, 1357 test->mask,
1345 test->write); 1358 test->write);
1346 break; 1359 break;
1347 case TABLE64_TEST_LO: 1360 case TABLE64_TEST_LO:
1348 REG_PATTERN_TEST(test->reg + (i * 8), 1361 REG_PATTERN_TEST(test->reg + (i * 8),
1349 test->mask, 1362 test->mask,
1350 test->write); 1363 test->write);
1351 break; 1364 break;
1352 case TABLE64_TEST_HI: 1365 case TABLE64_TEST_HI:
1353 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1366 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1354 test->mask, 1367 test->mask,
1355 test->write); 1368 test->write);
1356 break; 1369 break;
1357 } 1370 }
1358 } 1371 }
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 9160811c6d7d..eebb1921c660 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -3862,9 +3862,10 @@ static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3862 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3862 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3863 gpie |= IXGBE_SDP1_GPIEN; 3863 gpie |= IXGBE_SDP1_GPIEN;
3864 3864
3865 if (hw->mac.type == ixgbe_mac_82599EB) 3865 if (hw->mac.type == ixgbe_mac_82599EB) {
3866 gpie |= IXGBE_SDP1_GPIEN; 3866 gpie |= IXGBE_SDP1_GPIEN;
3867 gpie |= IXGBE_SDP2_GPIEN; 3867 gpie |= IXGBE_SDP2_GPIEN;
3868 }
3868 3869
3869 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 3870 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3870} 3871}
@@ -7468,8 +7469,8 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
7468 7469
7469 /* print bus type/speed/width info */ 7470 /* print bus type/speed/width info */
7470 e_dev_info("(PCI Express:%s:%s) %pM\n", 7471 e_dev_info("(PCI Express:%s:%s) %pM\n",
7471 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" : 7472 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7472 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" : 7473 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7473 "Unknown"), 7474 "Unknown"),
7474 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : 7475 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7475 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : 7476 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index edcaaebd72b2..735f686c3b36 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -1222,7 +1222,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1222 swfw_mask = IXGBE_GSSR_PHY0_SM; 1222 swfw_mask = IXGBE_GSSR_PHY0_SM;
1223 1223
1224 do { 1224 do {
1225 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { 1225 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1226 status = IXGBE_ERR_SWFW_SYNC; 1226 status = IXGBE_ERR_SWFW_SYNC;
1227 goto read_byte_out; 1227 goto read_byte_out;
1228 } 1228 }
@@ -1269,7 +1269,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1269 break; 1269 break;
1270 1270
1271fail: 1271fail:
1272 ixgbe_release_swfw_sync(hw, swfw_mask); 1272 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1273 msleep(100); 1273 msleep(100);
1274 ixgbe_i2c_bus_clear(hw); 1274 ixgbe_i2c_bus_clear(hw);
1275 retry++; 1275 retry++;
@@ -1280,7 +1280,7 @@ fail:
1280 1280
1281 } while (retry < max_retry); 1281 } while (retry < max_retry);
1282 1282
1283 ixgbe_release_swfw_sync(hw, swfw_mask); 1283 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1284 1284
1285read_byte_out: 1285read_byte_out:
1286 return status; 1286 return status;
@@ -1308,7 +1308,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1308 else 1308 else
1309 swfw_mask = IXGBE_GSSR_PHY0_SM; 1309 swfw_mask = IXGBE_GSSR_PHY0_SM;
1310 1310
1311 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { 1311 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1312 status = IXGBE_ERR_SWFW_SYNC; 1312 status = IXGBE_ERR_SWFW_SYNC;
1313 goto write_byte_out; 1313 goto write_byte_out;
1314 } 1314 }
@@ -1352,7 +1352,7 @@ fail:
1352 hw_dbg(hw, "I2C byte write error.\n"); 1352 hw_dbg(hw, "I2C byte write error.\n");
1353 } while (retry < max_retry); 1353 } while (retry < max_retry);
1354 1354
1355 ixgbe_release_swfw_sync(hw, swfw_mask); 1355 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1356 1356
1357write_byte_out: 1357write_byte_out:
1358 return status; 1358 return status;
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index fab9737c0d61..b1d523ca4d81 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1668,6 +1668,10 @@
1668 1668
1669#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 1669#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1670 1670
1671#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
1672#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
1673#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
1674
1671#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 1675#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1672#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1676#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1673#endif 1677#endif
@@ -2563,7 +2567,9 @@ typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2563struct ixgbe_eeprom_operations { 2567struct ixgbe_eeprom_operations {
2564 s32 (*init_params)(struct ixgbe_hw *); 2568 s32 (*init_params)(struct ixgbe_hw *);
2565 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 2569 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2570 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2566 s32 (*write)(struct ixgbe_hw *, u16, u16); 2571 s32 (*write)(struct ixgbe_hw *, u16, u16);
2572 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2567 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 2573 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2568 s32 (*update_checksum)(struct ixgbe_hw *); 2574 s32 (*update_checksum)(struct ixgbe_hw *);
2569 u16 (*calc_checksum)(struct ixgbe_hw *); 2575 u16 (*calc_checksum)(struct ixgbe_hw *);
@@ -2649,6 +2655,7 @@ struct ixgbe_eeprom_info {
2649 u32 semaphore_delay; 2655 u32 semaphore_delay;
2650 u16 word_size; 2656 u16 word_size;
2651 u16 address_bits; 2657 u16 address_bits;
2658 u16 word_page_size;
2652}; 2659};
2653 2660
2654#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 2661#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
diff --git a/drivers/net/ixgbe/ixgbe_x540.c b/drivers/net/ixgbe/ixgbe_x540.c
index 75c6465db893..4ed687be2fe3 100644
--- a/drivers/net/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ixgbe/ixgbe_x540.c
@@ -304,21 +304,49 @@ static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
304} 304}
305 305
306/** 306/**
307 * ixgbe_read_eerd_X540 - Read EEPROM word using EERD 307 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
308 * @hw: pointer to hardware structure 308 * @hw: pointer to hardware structure
309 * @offset: offset of word in the EEPROM to read 309 * @offset: offset of word in the EEPROM to read
310 * @data: word read from the EERPOM 310 * @data: word read from the EEPROM
311 *
312 * Reads a 16 bit word from the EEPROM using the EERD register.
311 **/ 313 **/
312static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 314static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
313{ 315{
314 s32 status; 316 s32 status = 0;
315 317
316 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) 318 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
319 0)
317 status = ixgbe_read_eerd_generic(hw, offset, data); 320 status = ixgbe_read_eerd_generic(hw, offset, data);
318 else 321 else
319 status = IXGBE_ERR_SWFW_SYNC; 322 status = IXGBE_ERR_SWFW_SYNC;
320 323
321 ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM); 324 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
325 return status;
326}
327
328/**
329 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
330 * @hw: pointer to hardware structure
331 * @offset: offset of word in the EEPROM to read
332 * @words: number of words
333 * @data: word(s) read from the EEPROM
334 *
335 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
336 **/
337static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
338 u16 offset, u16 words, u16 *data)
339{
340 s32 status = 0;
341
342 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
343 0)
344 status = ixgbe_read_eerd_buffer_generic(hw, offset,
345 words, data);
346 else
347 status = IXGBE_ERR_SWFW_SYNC;
348
349 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
322 return status; 350 return status;
323} 351}
324 352
@@ -344,6 +372,31 @@ static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
344} 372}
345 373
346/** 374/**
375 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
376 * @hw: pointer to hardware structure
377 * @offset: offset of word in the EEPROM to write
378 * @words: number of words
379 * @data: word(s) write to the EEPROM
380 *
381 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
382 **/
383static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
384 u16 offset, u16 words, u16 *data)
385{
386 s32 status = 0;
387
388 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
389 0)
390 status = ixgbe_write_eewr_buffer_generic(hw, offset,
391 words, data);
392 else
393 status = IXGBE_ERR_SWFW_SYNC;
394
395 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
396 return status;
397}
398
399/**
347 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 400 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
348 * 401 *
349 * This function does not use synchronization for EERD and EEWR. It can 402 * This function does not use synchronization for EERD and EEWR. It can
@@ -851,7 +904,9 @@ static struct ixgbe_mac_operations mac_ops_X540 = {
851static struct ixgbe_eeprom_operations eeprom_ops_X540 = { 904static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
852 .init_params = &ixgbe_init_eeprom_params_X540, 905 .init_params = &ixgbe_init_eeprom_params_X540,
853 .read = &ixgbe_read_eerd_X540, 906 .read = &ixgbe_read_eerd_X540,
907 .read_buffer = &ixgbe_read_eerd_buffer_X540,
854 .write = &ixgbe_write_eewr_X540, 908 .write = &ixgbe_write_eewr_X540,
909 .write_buffer = &ixgbe_write_eewr_buffer_X540,
855 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, 910 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
856 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, 911 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
857 .update_checksum = &ixgbe_update_eeprom_checksum_X540, 912 .update_checksum = &ixgbe_update_eeprom_checksum_X540,