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authorBen Skeggs <bskeggs@redhat.com>2013-11-26 00:39:15 -0500
committerBen Skeggs <bskeggs@redhat.com>2014-01-22 22:38:47 -0500
commit5905439224043465309e9989bfd9369efb9220ab (patch)
tree9b26fe2c42a6f8c119fa338cdd99bd327259f1a1
parent2daaf5b0e4fbed1fa9524881272c9a956a0aaf78 (diff)
drm/nve0/fb/gddr5: fix an assumption of sane memory controller layout
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c17
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
index 0fa983ffc4d4..cb03be38446a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
@@ -134,17 +134,20 @@ struct nve0_ram {
134 * GDDR5 134 * GDDR5
135 ******************************************************************************/ 135 ******************************************************************************/
136static void 136static void
137train(struct nve0_ramfuc *fuc, u32 magic) 137nve0_ram_train(struct nve0_ramfuc *fuc, u32 magic)
138{ 138{
139 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); 139 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
140 struct nouveau_fb *pfb = nouveau_fb(ram); 140 struct nouveau_fb *pfb = nouveau_fb(ram);
141 const int mc = nv_rd32(pfb, 0x02243c); 141 u32 part = nv_rd32(pfb, 0x022438), i;
142 int i; 142 u32 mask = nv_rd32(pfb, 0x022554);
143 u32 addr = 0x110974;
143 144
144 ram_mask(fuc, 0x10f910, 0xbc0e0000, magic); 145 ram_mask(fuc, 0x10f910, 0xbc0e0000, magic);
145 ram_mask(fuc, 0x10f914, 0xbc0e0000, magic); 146 ram_mask(fuc, 0x10f914, 0xbc0e0000, magic);
146 for (i = 0; i < mc; i++) { 147
147 const u32 addr = 0x110974 + (i * 0x1000); 148 for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {
149 if (mask & (1 << i))
150 continue;
148 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); 151 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
149 } 152 }
150} 153}
@@ -518,7 +521,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
518 521
519 if ((nv_ro08(bios, ramcfg + 0x08) & 0x10) && (ram->mode == 2) /*XXX*/) { 522 if ((nv_ro08(bios, ramcfg + 0x08) & 0x10) && (ram->mode == 2) /*XXX*/) {
520 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); 523 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
521 train(fuc, 0xa4010000); /*XXX*/ 524 nve0_ram_train(fuc, 0xa4010000); /*XXX*/
522 ram_nsec(fuc, 1000); 525 ram_nsec(fuc, 1000);
523 ram_wr32(fuc, 0x10f294, temp); 526 ram_wr32(fuc, 0x10f294, temp);
524 } 527 }
@@ -572,7 +575,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
572 } else { 575 } else {
573 data = 0xa40e0000; 576 data = 0xa40e0000;
574 } 577 }
575 train(fuc, data); 578 nve0_ram_train(fuc, data);
576 ram_nsec(fuc, 1000); 579 ram_nsec(fuc, 1000);
577 580
578 if (ram->mode == 2) { /*XXX*/ 581 if (ram->mode == 2) { /*XXX*/