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authorBjorn Helgaas <bhelgaas@google.com>2014-09-12 22:02:00 -0400
committerBjorn Helgaas <bhelgaas@google.com>2014-09-12 22:02:00 -0400
commit589fcc2307423d9c3856a4e2e72e1b57b6826f41 (patch)
treeeaefc0aecc778d34e3a1519e34712539dc7b33be
parent5e3d234456e25f664e0755c23689173588f4ca9b (diff)
PCI: Move pci_configure_slot() to drivers/pci/probe.c
Move pci_configure_slot() and related functions from drivers/pci/hotplug/pcihp_slot to drivers/pci/probe.c. This is to prepare for doing device configuration during the normal enumeration process instead of just after hot-add. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat
-rw-r--r--drivers/pci/hotplug/Makefile2
-rw-r--r--drivers/pci/hotplug/pcihp_slot.c176
-rw-r--r--drivers/pci/probe.c150
3 files changed, 151 insertions, 177 deletions
diff --git a/drivers/pci/hotplug/Makefile b/drivers/pci/hotplug/Makefile
index 3e6532b945c1..4a9aa08b08f1 100644
--- a/drivers/pci/hotplug/Makefile
+++ b/drivers/pci/hotplug/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_HOTPLUG_PCI_S390) += s390_pci_hpc.o
24 24
25obj-$(CONFIG_HOTPLUG_PCI_ACPI_IBM) += acpiphp_ibm.o 25obj-$(CONFIG_HOTPLUG_PCI_ACPI_IBM) += acpiphp_ibm.o
26 26
27pci_hotplug-objs := pci_hotplug_core.o pcihp_slot.o 27pci_hotplug-objs := pci_hotplug_core.o
28 28
29ifdef CONFIG_HOTPLUG_PCI_CPCI 29ifdef CONFIG_HOTPLUG_PCI_CPCI
30pci_hotplug-objs += cpci_hotplug_core.o \ 30pci_hotplug-objs += cpci_hotplug_core.o \
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c
deleted file mode 100644
index 3e36ec8d708a..000000000000
--- a/drivers/pci/hotplug/pcihp_slot.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/*
2 * Copyright (C) 1995,2001 Compaq Computer Corporation
3 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
4 * Copyright (C) 2001 IBM Corp.
5 * Copyright (C) 2003-2004 Intel Corporation
6 * (c) Copyright 2009 Hewlett-Packard Development Company, L.P.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/pci.h>
27#include <linux/export.h>
28#include <linux/pci_hotplug.h>
29
30static struct hpp_type0 pci_default_type0 = {
31 .revision = 1,
32 .cache_line_size = 8,
33 .latency_timer = 0x40,
34 .enable_serr = 0,
35 .enable_perr = 0,
36};
37
38static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
39{
40 u16 pci_cmd, pci_bctl;
41
42 if (!hpp) {
43 /*
44 * Perhaps we *should* use default settings for PCIe, but
45 * pciehp didn't, so we won't either.
46 */
47 if (pci_is_pcie(dev))
48 return;
49 hpp = &pci_default_type0;
50 }
51
52 if (hpp->revision > 1) {
53 dev_warn(&dev->dev,
54 "PCI settings rev %d not supported; using defaults\n",
55 hpp->revision);
56 hpp = &pci_default_type0;
57 }
58
59 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
60 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
61 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
62 if (hpp->enable_serr)
63 pci_cmd |= PCI_COMMAND_SERR;
64 else
65 pci_cmd &= ~PCI_COMMAND_SERR;
66 if (hpp->enable_perr)
67 pci_cmd |= PCI_COMMAND_PARITY;
68 else
69 pci_cmd &= ~PCI_COMMAND_PARITY;
70 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
71
72 /* Program bridge control value */
73 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
74 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
75 hpp->latency_timer);
76 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
77 if (hpp->enable_serr)
78 pci_bctl |= PCI_BRIDGE_CTL_SERR;
79 else
80 pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
81 if (hpp->enable_perr)
82 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
83 else
84 pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
85 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
86 }
87}
88
89static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
90{
91 if (hpp)
92 dev_warn(&dev->dev, "PCI-X settings not supported\n");
93}
94
95static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
96{
97 int pos;
98 u32 reg32;
99
100 if (!hpp)
101 return;
102
103 if (hpp->revision > 1) {
104 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
105 hpp->revision);
106 return;
107 }
108
109 /* Initialize Device Control Register */
110 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
111 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
112
113 /* Initialize Link Control Register */
114 if (dev->subordinate)
115 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
116 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
117
118 /* Find Advanced Error Reporting Enhanced Capability */
119 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
120 if (!pos)
121 return;
122
123 /* Initialize Uncorrectable Error Mask Register */
124 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
125 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
126 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
127
128 /* Initialize Uncorrectable Error Severity Register */
129 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
130 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
131 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
132
133 /* Initialize Correctable Error Mask Register */
134 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
135 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
136 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
137
138 /* Initialize Advanced Error Capabilities and Control Register */
139 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
140 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
141 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
142
143 /*
144 * FIXME: The following two registers are not supported yet.
145 *
146 * o Secondary Uncorrectable Error Severity Register
147 * o Secondary Uncorrectable Error Mask Register
148 */
149}
150
151void pci_configure_slot(struct pci_dev *dev)
152{
153 struct pci_dev *cdev;
154 struct hotplug_params hpp;
155
156 if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
157 (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
158 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
159 return;
160
161 pcie_bus_configure_settings(dev->bus);
162
163 memset(&hpp, 0, sizeof(hpp));
164 pci_get_hp_params(dev, &hpp);
165
166 program_hpp_type2(dev, hpp.t2);
167 program_hpp_type1(dev, hpp.t1);
168 program_hpp_type0(dev, hpp.t0);
169
170 if (dev->subordinate) {
171 list_for_each_entry(cdev, &dev->subordinate->devices,
172 bus_list)
173 pci_configure_slot(cdev);
174 }
175}
176EXPORT_SYMBOL_GPL(pci_configure_slot);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e3cf8a2e6292..6a198fc65999 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -6,6 +6,7 @@
6#include <linux/delay.h> 6#include <linux/delay.h>
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/pci.h> 8#include <linux/pci.h>
9#include <linux/pci_hotplug.h>
9#include <linux/slab.h> 10#include <linux/slab.h>
10#include <linux/module.h> 11#include <linux/module.h>
11#include <linux/cpumask.h> 12#include <linux/cpumask.h>
@@ -1236,6 +1237,155 @@ int pci_setup_device(struct pci_dev *dev)
1236 return 0; 1237 return 0;
1237} 1238}
1238 1239
1240static struct hpp_type0 pci_default_type0 = {
1241 .revision = 1,
1242 .cache_line_size = 8,
1243 .latency_timer = 0x40,
1244 .enable_serr = 0,
1245 .enable_perr = 0,
1246};
1247
1248static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1249{
1250 u16 pci_cmd, pci_bctl;
1251
1252 if (!hpp) {
1253 /*
1254 * Perhaps we *should* use default settings for PCIe, but
1255 * pciehp didn't, so we won't either.
1256 */
1257 if (pci_is_pcie(dev))
1258 return;
1259 hpp = &pci_default_type0;
1260 }
1261
1262 if (hpp->revision > 1) {
1263 dev_warn(&dev->dev,
1264 "PCI settings rev %d not supported; using defaults\n",
1265 hpp->revision);
1266 hpp = &pci_default_type0;
1267 }
1268
1269 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1270 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1271 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1272 if (hpp->enable_serr)
1273 pci_cmd |= PCI_COMMAND_SERR;
1274 else
1275 pci_cmd &= ~PCI_COMMAND_SERR;
1276 if (hpp->enable_perr)
1277 pci_cmd |= PCI_COMMAND_PARITY;
1278 else
1279 pci_cmd &= ~PCI_COMMAND_PARITY;
1280 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1281
1282 /* Program bridge control value */
1283 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1284 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1285 hpp->latency_timer);
1286 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1287 if (hpp->enable_serr)
1288 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1289 else
1290 pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
1291 if (hpp->enable_perr)
1292 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1293 else
1294 pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
1295 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1296 }
1297}
1298
1299static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1300{
1301 if (hpp)
1302 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1303}
1304
1305static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1306{
1307 int pos;
1308 u32 reg32;
1309
1310 if (!hpp)
1311 return;
1312
1313 if (hpp->revision > 1) {
1314 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1315 hpp->revision);
1316 return;
1317 }
1318
1319 /* Initialize Device Control Register */
1320 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1321 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1322
1323 /* Initialize Link Control Register */
1324 if (dev->subordinate)
1325 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1326 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1327
1328 /* Find Advanced Error Reporting Enhanced Capability */
1329 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1330 if (!pos)
1331 return;
1332
1333 /* Initialize Uncorrectable Error Mask Register */
1334 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1335 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1336 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1337
1338 /* Initialize Uncorrectable Error Severity Register */
1339 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1340 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1341 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1342
1343 /* Initialize Correctable Error Mask Register */
1344 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1345 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1346 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1347
1348 /* Initialize Advanced Error Capabilities and Control Register */
1349 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1350 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1351 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1352
1353 /*
1354 * FIXME: The following two registers are not supported yet.
1355 *
1356 * o Secondary Uncorrectable Error Severity Register
1357 * o Secondary Uncorrectable Error Mask Register
1358 */
1359}
1360
1361void pci_configure_slot(struct pci_dev *dev)
1362{
1363 struct pci_dev *cdev;
1364 struct hotplug_params hpp;
1365 int ret;
1366
1367 if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
1368 (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
1369 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
1370 return;
1371
1372 pcie_bus_configure_settings(dev->bus);
1373
1374 memset(&hpp, 0, sizeof(hpp));
1375 ret = pci_get_hp_params(dev, &hpp);
1376
1377 program_hpp_type2(dev, hpp.t2);
1378 program_hpp_type1(dev, hpp.t1);
1379 program_hpp_type0(dev, hpp.t0);
1380
1381 if (dev->subordinate) {
1382 list_for_each_entry(cdev, &dev->subordinate->devices,
1383 bus_list)
1384 pci_configure_slot(cdev);
1385 }
1386}
1387EXPORT_SYMBOL_GPL(pci_configure_slot);
1388
1239static void pci_release_capabilities(struct pci_dev *dev) 1389static void pci_release_capabilities(struct pci_dev *dev)
1240{ 1390{
1241 pci_vpd_release(dev); 1391 pci_vpd_release(dev);
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