ARM: tlb: don't bother with barriers for branch predictor maintenance

Branch predictor maintenance is only required when we are either
changing the kernel's view of memory (switching tables completely) or
dealing with ASID rollover.

Both of these use-cases require subsequent TLB invalidation, which has
the relevant barrier instructions to ensure completion and visibility
of the maintenance, so this patch removes the instruction barrier from
[local_]flush_bp_all.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 4 insertions, 3 deletions

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 3316264916e9..9b725d2bcb6b 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -527,6 +527,10 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr)
         }
 }
 
+/*
+ * Branch predictor maintenance is paired with full TLB invalidation, so
+ * there is no need for any barriers here.
+ */
 static inline void local_flush_bp_all(void)
 {
         const int zero = 0;
@@ -536,9 +540,6 @@ static inline void local_flush_bp_all(void)
                 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
         else if (tlb_flag(TLB_V6_BP))
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
-
-        if (tlb_flag(TLB_BARRIER))
-                isb();
 }
 
 #include <asm/cputype.h>