diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-02-05 05:42:54 -0500 |
---|---|---|
committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-02-08 05:47:03 -0500 |
commit | 58152a16901dfce8662f5ec7e16d06dfce6fd31e (patch) | |
tree | da04ba569b82d291be9d5b9a210f6eb3c67b0fa2 | |
parent | 69ddb488035068fce9a4ac4a63cffa91dfb3f37f (diff) |
arm/mx2/devices: use SoC-prefixed names where possible
There is only NFC_BASE_ADDR left which is defined differently for mx21
and mx27.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
-rw-r--r-- | arch/arm/mach-mx2/devices.c | 110 |
1 files changed, 55 insertions, 55 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index bed0fdb43bb8..9bf49da53072 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c | |||
@@ -116,9 +116,9 @@ DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); | |||
116 | */ | 116 | */ |
117 | static struct resource mxc_wdt_resources[] = { | 117 | static struct resource mxc_wdt_resources[] = { |
118 | { | 118 | { |
119 | .start = WDOG_BASE_ADDR, | 119 | .start = MX2x_WDOG_BASE_ADDR, |
120 | .end = WDOG_BASE_ADDR + 0x30, | 120 | .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, |
121 | .flags = IORESOURCE_MEM, | 121 | .flags = IORESOURCE_MEM, |
122 | }, | 122 | }, |
123 | }; | 123 | }; |
124 | 124 | ||
@@ -131,8 +131,8 @@ struct platform_device mxc_wdt = { | |||
131 | 131 | ||
132 | static struct resource mxc_w1_master_resources[] = { | 132 | static struct resource mxc_w1_master_resources[] = { |
133 | { | 133 | { |
134 | .start = OWIRE_BASE_ADDR, | 134 | .start = MX2x_OWIRE_BASE_ADDR, |
135 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | 135 | .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, |
136 | .flags = IORESOURCE_MEM, | 136 | .flags = IORESOURCE_MEM, |
137 | }, | 137 | }, |
138 | }; | 138 | }; |
@@ -146,13 +146,13 @@ struct platform_device mxc_w1_master_device = { | |||
146 | 146 | ||
147 | static struct resource mxc_nand_resources[] = { | 147 | static struct resource mxc_nand_resources[] = { |
148 | { | 148 | { |
149 | .start = NFC_BASE_ADDR, | 149 | .start = NFC_BASE_ADDR, |
150 | .end = NFC_BASE_ADDR + 0xfff, | 150 | .end = NFC_BASE_ADDR + SZ_4K - 1, |
151 | .flags = IORESOURCE_MEM, | 151 | .flags = IORESOURCE_MEM, |
152 | }, { | 152 | }, { |
153 | .start = MXC_INT_NANDFC, | 153 | .start = MX2x_INT_NANDFC, |
154 | .end = MXC_INT_NANDFC, | 154 | .end = MX2x_INT_NANDFC, |
155 | .flags = IORESOURCE_IRQ, | 155 | .flags = IORESOURCE_IRQ, |
156 | }, | 156 | }, |
157 | }; | 157 | }; |
158 | 158 | ||
@@ -171,12 +171,12 @@ struct platform_device mxc_nand_device = { | |||
171 | */ | 171 | */ |
172 | static struct resource mxc_fb[] = { | 172 | static struct resource mxc_fb[] = { |
173 | { | 173 | { |
174 | .start = LCDC_BASE_ADDR, | 174 | .start = MX2x_LCDC_BASE_ADDR, |
175 | .end = LCDC_BASE_ADDR + 0xFFF, | 175 | .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, |
176 | .flags = IORESOURCE_MEM, | 176 | .flags = IORESOURCE_MEM, |
177 | }, { | 177 | }, { |
178 | .start = MXC_INT_LCDC, | 178 | .start = MX2x_INT_LCDC, |
179 | .end = MXC_INT_LCDC, | 179 | .end = MX2x_INT_LCDC, |
180 | .flags = IORESOURCE_IRQ, | 180 | .flags = IORESOURCE_IRQ, |
181 | } | 181 | } |
182 | }; | 182 | }; |
@@ -195,13 +195,13 @@ struct platform_device mxc_fb_device = { | |||
195 | #ifdef CONFIG_MACH_MX27 | 195 | #ifdef CONFIG_MACH_MX27 |
196 | static struct resource mxc_fec_resources[] = { | 196 | static struct resource mxc_fec_resources[] = { |
197 | { | 197 | { |
198 | .start = FEC_BASE_ADDR, | 198 | .start = MX27_FEC_BASE_ADDR, |
199 | .end = FEC_BASE_ADDR + 0xfff, | 199 | .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, |
200 | .flags = IORESOURCE_MEM, | 200 | .flags = IORESOURCE_MEM, |
201 | }, { | 201 | }, { |
202 | .start = MXC_INT_FEC, | 202 | .start = MX27_INT_FEC, |
203 | .end = MXC_INT_FEC, | 203 | .end = MX27_INT_FEC, |
204 | .flags = IORESOURCE_IRQ, | 204 | .flags = IORESOURCE_IRQ, |
205 | }, | 205 | }, |
206 | }; | 206 | }; |
207 | 207 | ||
@@ -241,13 +241,13 @@ DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); | |||
241 | 241 | ||
242 | static struct resource mxc_pwm_resources[] = { | 242 | static struct resource mxc_pwm_resources[] = { |
243 | { | 243 | { |
244 | .start = PWM_BASE_ADDR, | 244 | .start = MX2x_PWM_BASE_ADDR, |
245 | .end = PWM_BASE_ADDR + 0x0fff, | 245 | .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, |
246 | .flags = IORESOURCE_MEM, | 246 | .flags = IORESOURCE_MEM, |
247 | }, { | 247 | }, { |
248 | .start = MXC_INT_PWM, | 248 | .start = MX2x_INT_PWM, |
249 | .end = MXC_INT_PWM, | 249 | .end = MX2x_INT_PWM, |
250 | .flags = IORESOURCE_IRQ, | 250 | .flags = IORESOURCE_IRQ, |
251 | } | 251 | } |
252 | }; | 252 | }; |
253 | 253 | ||
@@ -297,13 +297,13 @@ DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC | |||
297 | #ifdef CONFIG_MACH_MX27 | 297 | #ifdef CONFIG_MACH_MX27 |
298 | static struct resource otg_resources[] = { | 298 | static struct resource otg_resources[] = { |
299 | { | 299 | { |
300 | .start = OTG_BASE_ADDR, | 300 | .start = MX27_USBOTG_BASE_ADDR, |
301 | .end = OTG_BASE_ADDR + 0x1ff, | 301 | .end = MX27_USBOTG_BASE_ADDR + 0x1ff, |
302 | .flags = IORESOURCE_MEM, | 302 | .flags = IORESOURCE_MEM, |
303 | }, { | 303 | }, { |
304 | .start = MXC_INT_USB3, | 304 | .start = MX27_INT_USB3, |
305 | .end = MXC_INT_USB3, | 305 | .end = MX27_INT_USB3, |
306 | .flags = IORESOURCE_IRQ, | 306 | .flags = IORESOURCE_IRQ, |
307 | }, | 307 | }, |
308 | }; | 308 | }; |
309 | 309 | ||
@@ -311,14 +311,14 @@ static u64 otg_dmamask = 0xffffffffUL; | |||
311 | 311 | ||
312 | /* OTG gadget device */ | 312 | /* OTG gadget device */ |
313 | struct platform_device mxc_otg_udc_device = { | 313 | struct platform_device mxc_otg_udc_device = { |
314 | .name = "fsl-usb2-udc", | 314 | .name = "fsl-usb2-udc", |
315 | .id = -1, | 315 | .id = -1, |
316 | .dev = { | 316 | .dev = { |
317 | .dma_mask = &otg_dmamask, | 317 | .dma_mask = &otg_dmamask, |
318 | .coherent_dma_mask = 0xffffffffUL, | 318 | .coherent_dma_mask = 0xffffffffUL, |
319 | }, | 319 | }, |
320 | .resource = otg_resources, | 320 | .resource = otg_resources, |
321 | .num_resources = ARRAY_SIZE(otg_resources), | 321 | .num_resources = ARRAY_SIZE(otg_resources), |
322 | }; | 322 | }; |
323 | 323 | ||
324 | /* OTG host */ | 324 | /* OTG host */ |
@@ -339,12 +339,12 @@ static u64 usbh1_dmamask = 0xffffffffUL; | |||
339 | 339 | ||
340 | static struct resource mxc_usbh1_resources[] = { | 340 | static struct resource mxc_usbh1_resources[] = { |
341 | { | 341 | { |
342 | .start = OTG_BASE_ADDR + 0x200, | 342 | .start = MX27_USBOTG_BASE_ADDR + 0x200, |
343 | .end = OTG_BASE_ADDR + 0x3ff, | 343 | .end = MX27_USBOTG_BASE_ADDR + 0x3ff, |
344 | .flags = IORESOURCE_MEM, | 344 | .flags = IORESOURCE_MEM, |
345 | }, { | 345 | }, { |
346 | .start = MXC_INT_USB1, | 346 | .start = MX27_INT_USB1, |
347 | .end = MXC_INT_USB1, | 347 | .end = MX27_INT_USB1, |
348 | .flags = IORESOURCE_IRQ, | 348 | .flags = IORESOURCE_IRQ, |
349 | }, | 349 | }, |
350 | }; | 350 | }; |
@@ -365,12 +365,12 @@ static u64 usbh2_dmamask = 0xffffffffUL; | |||
365 | 365 | ||
366 | static struct resource mxc_usbh2_resources[] = { | 366 | static struct resource mxc_usbh2_resources[] = { |
367 | { | 367 | { |
368 | .start = OTG_BASE_ADDR + 0x400, | 368 | .start = MX27_USBOTG_BASE_ADDR + 0x400, |
369 | .end = OTG_BASE_ADDR + 0x5ff, | 369 | .end = MX27_USBOTG_BASE_ADDR + 0x5ff, |
370 | .flags = IORESOURCE_MEM, | 370 | .flags = IORESOURCE_MEM, |
371 | }, { | 371 | }, { |
372 | .start = MXC_INT_USB2, | 372 | .start = MX27_INT_USB2, |
373 | .end = MXC_INT_USB2, | 373 | .end = MX27_INT_USB2, |
374 | .flags = IORESOURCE_IRQ, | 374 | .flags = IORESOURCE_IRQ, |
375 | }, | 375 | }, |
376 | }; | 376 | }; |
@@ -426,28 +426,28 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); | |||
426 | static struct mxc_gpio_port imx_gpio_ports[] = { | 426 | static struct mxc_gpio_port imx_gpio_ports[] = { |
427 | { | 427 | { |
428 | .chip.label = "gpio-0", | 428 | .chip.label = "gpio-0", |
429 | .irq = MXC_INT_GPIO, | 429 | .irq = MX2x_INT_GPIO, |
430 | .base = IO_ADDRESS(GPIO_BASE_ADDR), | 430 | .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR), |
431 | .virtual_irq_start = MXC_GPIO_IRQ_START, | 431 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
432 | }, { | 432 | }, { |
433 | .chip.label = "gpio-1", | 433 | .chip.label = "gpio-1", |
434 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), | 434 | .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x100), |
435 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | 435 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
436 | }, { | 436 | }, { |
437 | .chip.label = "gpio-2", | 437 | .chip.label = "gpio-2", |
438 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), | 438 | .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x200), |
439 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | 439 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
440 | }, { | 440 | }, { |
441 | .chip.label = "gpio-3", | 441 | .chip.label = "gpio-3", |
442 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), | 442 | .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x300), |
443 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | 443 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, |
444 | }, { | 444 | }, { |
445 | .chip.label = "gpio-4", | 445 | .chip.label = "gpio-4", |
446 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), | 446 | .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x400), |
447 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, | 447 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, |
448 | }, { | 448 | }, { |
449 | .chip.label = "gpio-5", | 449 | .chip.label = "gpio-5", |
450 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), | 450 | .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x500), |
451 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, | 451 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |
452 | } | 452 | } |
453 | }; | 453 | }; |