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authorBen Skeggs <bskeggs@redhat.com>2013-05-13 23:09:28 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-06-30 23:50:41 -0400
commit57f0ec159b77df764a6948f8a612b0b825cd8350 (patch)
tree63fadeaf38daafb1559d2471c3f9f2102cdb7e5d
parenteb12f57be6f457d317562fda251214d1851134fc (diff)
drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c205
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc197
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h180
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc111
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h111
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c140
6 files changed, 344 insertions, 600 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index e0305bd8eedb..3be7b950eece 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1323,21 +1323,6 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
1323 nv_mthd(priv, 0x9097, 0x1450, 0x00300008); 1323 nv_mthd(priv, 0x9097, 0x1450, 0x00300008);
1324 nv_mthd(priv, 0x9097, 0x1454, 0x04000080); 1324 nv_mthd(priv, 0x9097, 0x1454, 0x04000080);
1325 nv_mthd(priv, 0x9097, 0x0214, 0x00000000); 1325 nv_mthd(priv, 0x9097, 0x0214, 0x00000000);
1326
1327 switch (nv_device(priv)->chipset) {
1328 case 0xc0:
1329 case 0xc3:
1330 case 0xc4:
1331 case 0xc1:
1332 case 0xc8:
1333 case 0xd9:
1334 case 0xd7:
1335 break;
1336 default:
1337 /* in trace, right after 0x90c0, not here */
1338 nv_mthd(priv, 0x9097, 0x3410, 0x80002006);
1339 break;
1340 }
1341} 1326}
1342 1327
1343static void 1328static void
@@ -1481,7 +1466,11 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1481 case 0xc4: 1466 case 0xc4:
1482 case 0xc1: 1467 case 0xc1:
1483 case 0xc8: 1468 case 0xc8:
1469 case 0xce:
1470 case 0xcf:
1471 break;
1484 default: 1472 default:
1473 BUG_ON(1);
1485 break; 1474 break;
1486 } 1475 }
1487 nv_wr32(priv, 0x404044, 0x00000000); 1476 nv_wr32(priv, 0x404044, 0x00000000);
@@ -1499,19 +1488,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1499 nv_wr32(priv, 0x4040c0, 0x00000000); 1488 nv_wr32(priv, 0x4040c0, 0x00000000);
1500 nv_wr32(priv, 0x4040c4, 0x00000000); 1489 nv_wr32(priv, 0x4040c4, 0x00000000);
1501 nv_wr32(priv, 0x4040c8, 0xf0000087); 1490 nv_wr32(priv, 0x4040c8, 0xf0000087);
1502 switch (nv_device(priv)->chipset) { 1491 nv_wr32(priv, 0x4040d0, 0x00000000);
1503 case 0xc0:
1504 case 0xc3:
1505 case 0xc4:
1506 case 0xc1:
1507 case 0xc8:
1508 case 0xd9:
1509 case 0xd7:
1510 nv_wr32(priv, 0x4040d0, 0x00000000);
1511 break;
1512 default:
1513 break;
1514 }
1515 nv_wr32(priv, 0x4040d4, 0x00000000); 1492 nv_wr32(priv, 0x4040d4, 0x00000000);
1516 nv_wr32(priv, 0x4040d8, 0x00000000); 1493 nv_wr32(priv, 0x4040d8, 0x00000000);
1517 nv_wr32(priv, 0x4040dc, 0x00000000); 1494 nv_wr32(priv, 0x4040dc, 0x00000000);
@@ -1536,9 +1513,13 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1536 case 0xc4: 1513 case 0xc4:
1537 case 0xc1: 1514 case 0xc1:
1538 case 0xc8: 1515 case 0xc8:
1539 default: 1516 case 0xce:
1517 case 0xcf:
1540 nv_wr32(priv, 0x404174, 0x00000000); 1518 nv_wr32(priv, 0x404174, 0x00000000);
1541 break; 1519 break;
1520 default:
1521 BUG_ON(1);
1522 break;
1542 } 1523 }
1543 nv_wr32(priv, 0x404178, 0x00000000); 1524 nv_wr32(priv, 0x404178, 0x00000000);
1544 nv_wr32(priv, 0x40417c, 0x00000000); 1525 nv_wr32(priv, 0x40417c, 0x00000000);
@@ -1681,11 +1662,15 @@ nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
1681 case 0xc3: 1662 case 0xc3:
1682 case 0xc4: 1663 case 0xc4:
1683 case 0xc8: 1664 case 0xc8:
1684 default: 1665 case 0xce:
1666 case 0xcf:
1685 nv_wr32(priv, 0x405800, 0x078000bf); 1667 nv_wr32(priv, 0x405800, 0x078000bf);
1686 nv_wr32(priv, 0x405830, 0x02180000); 1668 nv_wr32(priv, 0x405830, 0x02180000);
1687 nv_wr32(priv, 0x405834, 0x00000000); 1669 nv_wr32(priv, 0x405834, 0x00000000);
1688 break; 1670 break;
1671 default:
1672 BUG_ON(1);
1673 break;
1689 } 1674 }
1690 nv_wr32(priv, 0x405838, 0x00000000); 1675 nv_wr32(priv, 0x405838, 0x00000000);
1691 nv_wr32(priv, 0x405854, 0x00000000); 1676 nv_wr32(priv, 0x405854, 0x00000000);
@@ -1720,27 +1705,19 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
1720 case 0xd9: 1705 case 0xd9:
1721 case 0xd7: 1706 case 0xd7:
1722 nv_wr32(priv, 0x4064bc, 0x00000000); 1707 nv_wr32(priv, 0x4064bc, 0x00000000);
1723 break;
1724 case 0xc0:
1725 case 0xc3:
1726 case 0xc4:
1727 case 0xc1:
1728 case 0xc8:
1729 default:
1730 break;
1731 }
1732 switch (nv_device(priv)->chipset) {
1733 case 0xc1:
1734 case 0xd9:
1735 case 0xd7:
1736 nv_wr32(priv, 0x4064c0, 0x80140078); 1708 nv_wr32(priv, 0x4064c0, 0x80140078);
1737 nv_wr32(priv, 0x4064c4, 0x0086ffff); 1709 nv_wr32(priv, 0x4064c4, 0x0086ffff);
1738 break; 1710 break;
1739 case 0xc0: 1711 case 0xc0:
1740 case 0xc3: 1712 case 0xc3:
1741 case 0xc4: 1713 case 0xc4:
1714 case 0xc1:
1742 case 0xc8: 1715 case 0xc8:
1716 case 0xce:
1717 case 0xcf:
1718 break;
1743 default: 1719 default:
1720 BUG_ON(1);
1744 break; 1721 break;
1745 } 1722 }
1746} 1723}
@@ -1782,6 +1759,8 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
1782 case 0xc3: 1759 case 0xc3:
1783 case 0xc4: 1760 case 0xc4:
1784 case 0xc8: 1761 case 0xc8:
1762 case 0xce:
1763 case 0xcf:
1785 nv_wr32(priv, 0x408808, 0x0003e00d); 1764 nv_wr32(priv, 0x408808, 0x0003e00d);
1786 nv_wr32(priv, 0x408900, 0x3080b801); 1765 nv_wr32(priv, 0x408900, 0x3080b801);
1787 nv_wr32(priv, 0x408904, 0x02000001); 1766 nv_wr32(priv, 0x408904, 0x02000001);
@@ -1801,11 +1780,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
1801 nv_wr32(priv, 0x408908, 0x00c8102f); 1780 nv_wr32(priv, 0x408908, 0x00c8102f);
1802 break; 1781 break;
1803 default: 1782 default:
1804 nv_wr32(priv, 0x408808, 0x0003e00d); 1783 BUG_ON(1);
1805 nv_wr32(priv, 0x408900, 0x3080b801);
1806 nv_wr32(priv, 0x408904, 0x02000001);
1807 nv_wr32(priv, 0x408908, 0x00c80929);
1808 nv_wr32(priv, 0x40890c, 0x00000000);
1809 break; 1784 break;
1810 } 1785 }
1811 nv_wr32(priv, 0x408980, 0x0000011d); 1786 nv_wr32(priv, 0x408980, 0x0000011d);
@@ -1829,9 +1804,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1829 case 0xc4: 1804 case 0xc4:
1830 case 0xc1: 1805 case 0xc1:
1831 case 0xc8: 1806 case 0xc8:
1832 default: 1807 case 0xce:
1808 case 0xcf:
1833 nv_wr32(priv, 0x418408, 0x00000000); 1809 nv_wr32(priv, 0x418408, 0x00000000);
1834 break; 1810 break;
1811 default:
1812 BUG_ON(1);
1813 break;
1835 } 1814 }
1836 nv_wr32(priv, 0x41840c, 0x00001008); 1815 nv_wr32(priv, 0x41840c, 0x00001008);
1837 nv_wr32(priv, 0x418410, 0x0fff0fff); 1816 nv_wr32(priv, 0x418410, 0x0fff0fff);
@@ -1845,9 +1824,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1845 case 0xc4: 1824 case 0xc4:
1846 case 0xc1: 1825 case 0xc1:
1847 case 0xc8: 1826 case 0xc8:
1848 default: 1827 case 0xce:
1828 case 0xcf:
1849 nv_wr32(priv, 0x418414, 0x00200fff); 1829 nv_wr32(priv, 0x418414, 0x00200fff);
1850 break; 1830 break;
1831 default:
1832 BUG_ON(1);
1833 break;
1851 } 1834 }
1852 nv_wr32(priv, 0x418450, 0x00000000); 1835 nv_wr32(priv, 0x418450, 0x00000000);
1853 nv_wr32(priv, 0x418454, 0x00000000); 1836 nv_wr32(priv, 0x418454, 0x00000000);
@@ -1873,9 +1856,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1873 case 0xc4: 1856 case 0xc4:
1874 case 0xc1: 1857 case 0xc1:
1875 case 0xc8: 1858 case 0xc8:
1876 default: 1859 case 0xce:
1860 case 0xcf:
1877 nv_wr32(priv, 0x41870c, 0x07c80000); 1861 nv_wr32(priv, 0x41870c, 0x07c80000);
1878 break; 1862 break;
1863 default:
1864 BUG_ON(1);
1865 break;
1879 } 1866 }
1880 nv_wr32(priv, 0x418710, 0x00000000); 1867 nv_wr32(priv, 0x418710, 0x00000000);
1881 switch (nv_device(priv)->chipset) { 1868 switch (nv_device(priv)->chipset) {
@@ -1888,9 +1875,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1888 case 0xc4: 1875 case 0xc4:
1889 case 0xc1: 1876 case 0xc1:
1890 case 0xc8: 1877 case 0xc8:
1891 default: 1878 case 0xce:
1879 case 0xcf:
1892 nv_wr32(priv, 0x418800, 0x0006860a); 1880 nv_wr32(priv, 0x418800, 0x0006860a);
1893 break; 1881 break;
1882 default:
1883 BUG_ON(1);
1884 break;
1894 } 1885 }
1895 nv_wr32(priv, 0x418808, 0x00000000); 1886 nv_wr32(priv, 0x418808, 0x00000000);
1896 nv_wr32(priv, 0x41880c, 0x00000000); 1887 nv_wr32(priv, 0x41880c, 0x00000000);
@@ -1906,9 +1897,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1906 case 0xc3: 1897 case 0xc3:
1907 case 0xc4: 1898 case 0xc4:
1908 case 0xc8: 1899 case 0xc8:
1909 default: 1900 case 0xce:
1901 case 0xcf:
1910 nv_wr32(priv, 0x418830, 0x00000001); 1902 nv_wr32(priv, 0x418830, 0x00000001);
1911 break; 1903 break;
1904 default:
1905 BUG_ON(1);
1906 break;
1912 } 1907 }
1913 nv_wr32(priv, 0x4188d8, 0x00000008); 1908 nv_wr32(priv, 0x4188d8, 0x00000008);
1914 nv_wr32(priv, 0x4188e0, 0x01000000); 1909 nv_wr32(priv, 0x4188e0, 0x01000000);
@@ -1929,9 +1924,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1929 case 0xc3: 1924 case 0xc3:
1930 case 0xc4: 1925 case 0xc4:
1931 case 0xc8: 1926 case 0xc8:
1932 default: 1927 case 0xce:
1928 case 0xcf:
1933 nv_wr32(priv, 0x4188fc, 0x00100000); 1929 nv_wr32(priv, 0x4188fc, 0x00100000);
1934 break; 1930 break;
1931 default:
1932 BUG_ON(1);
1933 break;
1935 } 1934 }
1936 nv_wr32(priv, 0x41891c, 0x00ff00ff); 1935 nv_wr32(priv, 0x41891c, 0x00ff00ff);
1937 nv_wr32(priv, 0x418924, 0x00000000); 1936 nv_wr32(priv, 0x418924, 0x00000000);
@@ -1956,9 +1955,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1956 case 0xc4: 1955 case 0xc4:
1957 case 0xc1: 1956 case 0xc1:
1958 case 0xc8: 1957 case 0xc8:
1959 default: 1958 case 0xce:
1959 case 0xcf:
1960 nv_wr32(priv, 0x418b00, 0x00000000); 1960 nv_wr32(priv, 0x418b00, 0x00000000);
1961 break; 1961 break;
1962 default:
1963 BUG_ON(1);
1964 break;
1962 } 1965 }
1963 nv_wr32(priv, 0x418b08, 0x0a418820); 1966 nv_wr32(priv, 0x418b08, 0x0a418820);
1964 nv_wr32(priv, 0x418b0c, 0x062080e6); 1967 nv_wr32(priv, 0x418b0c, 0x062080e6);
@@ -1986,7 +1989,11 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1986 case 0xc3: 1989 case 0xc3:
1987 case 0xc4: 1990 case 0xc4:
1988 case 0xc8: 1991 case 0xc8:
1992 case 0xce:
1993 case 0xcf:
1994 break;
1989 default: 1995 default:
1996 BUG_ON(1);
1990 break; 1997 break;
1991 } 1998 }
1992 nv_wr32(priv, 0x418c80, 0x20200004); 1999 nv_wr32(priv, 0x418c80, 0x20200004);
@@ -2014,9 +2021,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2014 case 0xc3: 2021 case 0xc3:
2015 case 0xc4: 2022 case 0xc4:
2016 case 0xc8: 2023 case 0xc8:
2017 default: 2024 case 0xce:
2025 case 0xcf:
2018 nv_wr32(priv, 0x419864, 0x0000012a); 2026 nv_wr32(priv, 0x419864, 0x0000012a);
2019 break; 2027 break;
2028 default:
2029 BUG_ON(1);
2030 break;
2020 } 2031 }
2021 nv_wr32(priv, 0x419888, 0x00000000); 2032 nv_wr32(priv, 0x419888, 0x00000000);
2022 nv_wr32(priv, 0x419a00, 0x000001f0); 2033 nv_wr32(priv, 0x419a00, 0x000001f0);
@@ -2032,10 +2043,16 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2032 case 0xc4: 2043 case 0xc4:
2033 case 0xc1: 2044 case 0xc1:
2034 case 0xc8: 2045 case 0xc8:
2035 default: 2046 case 0xce:
2047 case 0xcf:
2048 case 0xd9:
2049 case 0xd7:
2036 nv_wr32(priv, 0x419a1c, 0x00000000); 2050 nv_wr32(priv, 0x419a1c, 0x00000000);
2037 nv_wr32(priv, 0x419a20, 0x00000800); 2051 nv_wr32(priv, 0x419a20, 0x00000800);
2038 break; 2052 break;
2053 default:
2054 BUG_ON(1);
2055 break;
2039 } 2056 }
2040 switch (nv_device(priv)->chipset) { 2057 switch (nv_device(priv)->chipset) {
2041 case 0xc0: 2058 case 0xc0:
@@ -2048,9 +2065,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2048 case 0xc3: 2065 case 0xc3:
2049 case 0xc4: 2066 case 0xc4:
2050 case 0xc1: 2067 case 0xc1:
2051 default: 2068 case 0xce:
2069 case 0xcf:
2052 nv_wr32(priv, 0x00419ac4, 0x0007f440); 2070 nv_wr32(priv, 0x00419ac4, 0x0007f440);
2053 break; 2071 break;
2072 default:
2073 BUG_ON(1);
2074 break;
2054 } 2075 }
2055 nv_wr32(priv, 0x419b00, 0x0a418820); 2076 nv_wr32(priv, 0x419b00, 0x0a418820);
2056 nv_wr32(priv, 0x419b04, 0x062080e6); 2077 nv_wr32(priv, 0x419b04, 0x062080e6);
@@ -2069,9 +2090,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2069 case 0xc3: 2090 case 0xc3:
2070 case 0xc4: 2091 case 0xc4:
2071 case 0xc8: 2092 case 0xc8:
2072 default: 2093 case 0xce:
2094 case 0xcf:
2073 nv_wr32(priv, 0x419be0, 0x00000001); 2095 nv_wr32(priv, 0x419be0, 0x00000001);
2074 break; 2096 break;
2097 default:
2098 BUG_ON(1);
2099 break;
2075 } 2100 }
2076 nv_wr32(priv, 0x419be4, 0x00000000); 2101 nv_wr32(priv, 0x419be4, 0x00000000);
2077 switch (nv_device(priv)->chipset) { 2102 switch (nv_device(priv)->chipset) {
@@ -2084,9 +2109,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2084 case 0xc4: 2109 case 0xc4:
2085 case 0xc1: 2110 case 0xc1:
2086 case 0xc8: 2111 case 0xc8:
2087 default: 2112 case 0xce:
2113 case 0xcf:
2088 nv_wr32(priv, 0x419c00, 0x00000002); 2114 nv_wr32(priv, 0x419c00, 0x00000002);
2089 break; 2115 break;
2116 default:
2117 BUG_ON(1);
2118 break;
2090 } 2119 }
2091 nv_wr32(priv, 0x419c04, 0x00000006); 2120 nv_wr32(priv, 0x419c04, 0x00000006);
2092 nv_wr32(priv, 0x419c08, 0x00000002); 2121 nv_wr32(priv, 0x419c08, 0x00000002);
@@ -2107,9 +2136,11 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2107 break; 2136 break;
2108 case 0xc0: 2137 case 0xc0:
2109 case 0xc8: 2138 case 0xc8:
2110 default:
2111 nv_wr32(priv, 0x419cb0, 0x00060048); 2139 nv_wr32(priv, 0x419cb0, 0x00060048);
2112 break; 2140 break;
2141 default:
2142 BUG_ON(1);
2143 break;
2113 } 2144 }
2114 nv_wr32(priv, 0x419ce8, 0x00000000); 2145 nv_wr32(priv, 0x419ce8, 0x00000000);
2115 nv_wr32(priv, 0x419cf4, 0x00000183); 2146 nv_wr32(priv, 0x419cf4, 0x00000183);
@@ -2123,9 +2154,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2123 case 0xc3: 2154 case 0xc3:
2124 case 0xc4: 2155 case 0xc4:
2125 case 0xc8: 2156 case 0xc8:
2126 default: 2157 case 0xce:
2158 case 0xcf:
2127 nv_wr32(priv, 0x419d20, 0x02180000); 2159 nv_wr32(priv, 0x419d20, 0x02180000);
2128 break; 2160 break;
2161 default:
2162 BUG_ON(1);
2163 break;
2129 } 2164 }
2130 nv_wr32(priv, 0x419d24, 0x00001fff); 2165 nv_wr32(priv, 0x419d24, 0x00001fff);
2131 switch (nv_device(priv)->chipset) { 2166 switch (nv_device(priv)->chipset) {
@@ -2138,7 +2173,11 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2138 case 0xc3: 2173 case 0xc3:
2139 case 0xc4: 2174 case 0xc4:
2140 case 0xc8: 2175 case 0xc8:
2176 case 0xce:
2177 case 0xcf:
2178 break;
2141 default: 2179 default:
2180 BUG_ON(1);
2142 break; 2181 break;
2143 } 2182 }
2144 nv_wr32(priv, 0x419e04, 0x00000000); 2183 nv_wr32(priv, 0x419e04, 0x00000000);
@@ -2177,9 +2216,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2177 case 0xc3: 2216 case 0xc3:
2178 case 0xc4: 2217 case 0xc4:
2179 case 0xc1: 2218 case 0xc1:
2180 default: 2219 case 0xce:
2220 case 0xcf:
2181 nv_wr32(priv, 0x419ee0, 0x00011110); 2221 nv_wr32(priv, 0x419ee0, 0x00011110);
2182 break; 2222 break;
2223 default:
2224 BUG_ON(1);
2225 break;
2183 } 2226 }
2184 switch (nv_device(priv)->chipset) { 2227 switch (nv_device(priv)->chipset) {
2185 case 0xc0: 2228 case 0xc0:
@@ -2190,6 +2233,8 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2190 case 0xc3: 2233 case 0xc3:
2191 case 0xc4: 2234 case 0xc4:
2192 case 0xc1: 2235 case 0xc1:
2236 case 0xce:
2237 case 0xcf:
2193 case 0xd9: 2238 case 0xd9:
2194 case 0xd7: 2239 case 0xd7:
2195 nv_wr32(priv, 0x419f30, 0x00000000); 2240 nv_wr32(priv, 0x419f30, 0x00000000);
@@ -2204,10 +2249,9 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2204 nv_wr32(priv, 0x419f54, 0x00000000); 2249 nv_wr32(priv, 0x419f54, 0x00000000);
2205 nv_wr32(priv, 0x419f58, 0x00000000); 2250 nv_wr32(priv, 0x419f58, 0x00000000);
2206 break; 2251 break;
2252 break;
2207 default: 2253 default:
2208 nv_wr32(priv, 0x419f50, 0x00000000); 2254 BUG_ON(1);
2209 nv_wr32(priv, 0x419f54, 0x00000000);
2210 nv_wr32(priv, 0x419f58, 0x00000000);
2211 break; 2255 break;
2212 } 2256 }
2213} 2257}
@@ -2277,7 +2321,13 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2277 } 2321 }
2278 } 2322 }
2279 break; 2323 break;
2280 default: 2324 break;
2325 case 0xc0:
2326 case 0xc3:
2327 case 0xc4:
2328 case 0xc8:
2329 case 0xce:
2330 case 0xcf:
2281 tmp = 0x02180000; 2331 tmp = 0x02180000;
2282 mmio_list(0x405830, tmp, 0, 0); 2332 mmio_list(0x405830, tmp, 0, 0);
2283 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 2333 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
@@ -2288,6 +2338,9 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2288 } 2338 }
2289 } 2339 }
2290 break; 2340 break;
2341 default:
2342 BUG_ON(1);
2343 break;
2291 } 2344 }
2292 2345
2293 for (tpc = 0, id = 0; tpc < 4; tpc++) { 2346 for (tpc = 0, id = 0; tpc < 4; tpc++) {
@@ -2530,7 +2583,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2530 case 0xc4: 2583 case 0xc4:
2531 case 0xc1: 2584 case 0xc1:
2532 case 0xc8: 2585 case 0xc8:
2586 case 0xce:
2587 case 0xcf:
2588 break;
2533 default: 2589 default:
2590 BUG_ON(1);
2534 break; 2591 break;
2535 } 2592 }
2536 nv_icmd(priv, 0x00000218, 0x0000c080); 2593 nv_icmd(priv, 0x00000218, 0x0000c080);
@@ -2552,8 +2609,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2552 case 0xc4: 2609 case 0xc4:
2553 case 0xc1: 2610 case 0xc1:
2554 case 0xc8: 2611 case 0xc8:
2612 case 0xce:
2613 case 0xcf:
2555 break; 2614 break;
2556 default: 2615 default:
2616 BUG_ON(1);
2557 break; 2617 break;
2558 } 2618 }
2559 nv_icmd(priv, 0x000000ad, 0x0000013e); 2619 nv_icmd(priv, 0x000000ad, 0x0000013e);
@@ -3128,7 +3188,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3128 case 0xc0: 3188 case 0xc0:
3129 case 0xc3: 3189 case 0xc3:
3130 case 0xc4: 3190 case 0xc4:
3191 case 0xce:
3192 case 0xcf:
3193 break;
3131 default: 3194 default:
3195 BUG_ON(1);
3132 break; 3196 break;
3133 } 3197 }
3134 nv_icmd(priv, 0x00000586, 0x00000040); 3198 nv_icmd(priv, 0x00000586, 0x00000040);
@@ -3241,7 +3305,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3241 case 0xc3: 3305 case 0xc3:
3242 case 0xc4: 3306 case 0xc4:
3243 case 0xc1: 3307 case 0xc1:
3308 case 0xce:
3309 case 0xcf:
3310 break;
3244 default: 3311 default:
3312 BUG_ON(1);
3245 break; 3313 break;
3246 } 3314 }
3247 nv_icmd(priv, 0x00000683, 0x00000006); 3315 nv_icmd(priv, 0x00000683, 0x00000006);
@@ -3392,6 +3460,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3392 case 0xc4: 3460 case 0xc4:
3393 case 0xc1: 3461 case 0xc1:
3394 case 0xc8: 3462 case 0xc8:
3463 case 0xce:
3464 case 0xcf:
3395 nv_mthd(priv, 0x902d, 0x3410, 0x00000000); 3465 nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
3396 break; 3466 break;
3397 case 0xd9: 3467 case 0xd9:
@@ -3399,6 +3469,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3399 nv_mthd(priv, 0x902d, 0x3410, 0x80002006); 3469 nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
3400 break; 3470 break;
3401 default: 3471 default:
3472 BUG_ON(1);
3402 break; 3473 break;
3403 } 3474 }
3404 3475
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index 4539e33174b7..61a6b43ece19 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -48,30 +48,30 @@ cmd_queue: queue_init
48// chipset descriptions 48// chipset descriptions
49chipsets: 49chipsets:
50.b8 0xc0 0 0 0 50.b8 0xc0 0 0 0
51.b16 #nnvc0_gpc_mmio_head 51.b16 #nvc0_gpc_mmio_head
52.b16 #nnvc0_gpc_mmio_tail 52.b16 #nvc0_gpc_mmio_tail
53.b16 #nnvc0_tpc_mmio_head 53.b16 #nvc0_tpc_mmio_head
54.b16 #nnvc0_tpc_mmio_tail 54.b16 #nvc0_tpc_mmio_tail
55.b8 0xc1 0 0 0 55.b8 0xc1 0 0 0
56.b16 #nnvc0_gpc_mmio_head 56.b16 #nvc0_gpc_mmio_head
57.b16 #nnvc1_gpc_mmio_tail 57.b16 #nvc1_gpc_mmio_tail
58.b16 #nnvc3_tpc_mmio_head 58.b16 #nvc0_tpc_mmio_head
59.b16 #nnvc1_tpc_mmio_tail 59.b16 #nvc1_tpc_mmio_tail
60.b8 0xc3 0 0 0 60.b8 0xc3 0 0 0
61.b16 #nnvc0_gpc_mmio_head 61.b16 #nvc0_gpc_mmio_head
62.b16 #nnvc0_gpc_mmio_tail 62.b16 #nvc0_gpc_mmio_tail
63.b16 #nnvc3_tpc_mmio_head 63.b16 #nvc0_tpc_mmio_head
64.b16 #nnvc3_tpc_mmio_tail 64.b16 #nvc3_tpc_mmio_tail
65.b8 0xc4 0 0 0 65.b8 0xc4 0 0 0
66.b16 #nnvc0_gpc_mmio_head 66.b16 #nvc0_gpc_mmio_head
67.b16 #nnvc0_gpc_mmio_tail 67.b16 #nvc0_gpc_mmio_tail
68.b16 #nnvc3_tpc_mmio_head 68.b16 #nvc0_tpc_mmio_head
69.b16 #nnvc3_tpc_mmio_tail 69.b16 #nvc3_tpc_mmio_tail
70.b8 0xc8 0 0 0 70.b8 0xc8 0 0 0
71.b16 #nnvc0_gpc_mmio_head 71.b16 #nvc0_gpc_mmio_head
72.b16 #nnvc0_gpc_mmio_tail 72.b16 #nvc0_gpc_mmio_tail
73.b16 #nnvc0_tpc_mmio_head 73.b16 #nvc0_tpc_mmio_head
74.b16 #nnvc0_tpc_mmio_tail 74.b16 #nvc0_tpc_mmio_tail
75.b8 0xce 0 0 0 75.b8 0xce 0 0 0
76.b16 #nvc0_gpc_mmio_head 76.b16 #nvc0_gpc_mmio_head
77.b16 #nvc0_gpc_mmio_tail 77.b16 #nvc0_gpc_mmio_tail
@@ -81,23 +81,26 @@ chipsets:
81.b16 #nvc0_gpc_mmio_head 81.b16 #nvc0_gpc_mmio_head
82.b16 #nvc0_gpc_mmio_tail 82.b16 #nvc0_gpc_mmio_tail
83.b16 #nvc0_tpc_mmio_head 83.b16 #nvc0_tpc_mmio_head
84.b16 #nvcf_tpc_mmio_tail 84.b16 #nvc3_tpc_mmio_tail
85.b8 0xd9 0 0 0 85.b8 0xd9 0 0 0
86.b16 #nvd9_gpc_mmio_head 86.b16 #nvd9_gpc_mmio_head
87.b16 #nvd9_gpc_mmio_tail 87.b16 #nvc1_gpc_mmio_tail
88.b16 #nvd9_tpc_mmio_head 88.b16 #nvc0_tpc_mmio_head
89.b16 #nvd9_tpc_mmio_tail 89.b16 #nvd9_tpc_mmio_tail
90.b8 0xd7 0 0 0 90.b8 0xd7 0 0 0
91.b16 #nvd9_gpc_mmio_head 91.b16 #nvd9_gpc_mmio_head
92.b16 #nvd9_gpc_mmio_tail 92.b16 #nvc1_gpc_mmio_tail
93.b16 #nvd9_tpc_mmio_head 93.b16 #nvc0_tpc_mmio_head
94.b16 #nvd9_tpc_mmio_tail 94.b16 #nvd9_tpc_mmio_tail
95.b8 0 0 0 0 95.b8 0 0 0 0
96 96
97// GPC mmio lists 97// GPC mmio lists
98nvc0_gpc_mmio_head: 98nvc0_gpc_mmio_head:
99mmctx_data(0x000408, 1)
100nvd9_gpc_mmio_head:
99mmctx_data(0x000380, 1) 101mmctx_data(0x000380, 1)
100mmctx_data(0x000400, 6) 102mmctx_data(0x000400, 2);
103mmctx_data(0x00040c, 3);
101mmctx_data(0x000450, 9) 104mmctx_data(0x000450, 9)
102mmctx_data(0x000600, 1) 105mmctx_data(0x000600, 1)
103mmctx_data(0x000684, 1) 106mmctx_data(0x000684, 1)
@@ -121,64 +124,8 @@ mmctx_data(0x000c8c, 1)
121mmctx_data(0x001000, 3) 124mmctx_data(0x001000, 3)
122mmctx_data(0x001014, 1) 125mmctx_data(0x001014, 1)
123nvc0_gpc_mmio_tail: 126nvc0_gpc_mmio_tail:
124
125nnvc0_gpc_mmio_head:
126mmctx_data(0x000380, 1)
127mmctx_data(0x000400, 6)
128mmctx_data(0x000450, 9)
129mmctx_data(0x000600, 1)
130mmctx_data(0x000684, 1)
131mmctx_data(0x000700, 5)
132mmctx_data(0x000800, 1)
133mmctx_data(0x000808, 3)
134mmctx_data(0x000828, 1)
135mmctx_data(0x000830, 1)
136mmctx_data(0x0008d8, 1)
137mmctx_data(0x0008e0, 1)
138mmctx_data(0x0008e8, 6)
139mmctx_data(0x00091c, 1)
140mmctx_data(0x000924, 3)
141mmctx_data(0x000b00, 1)
142mmctx_data(0x000b08, 6)
143mmctx_data(0x000bb8, 1)
144mmctx_data(0x000c08, 1)
145mmctx_data(0x000c10, 8)
146mmctx_data(0x000c80, 1)
147mmctx_data(0x000c8c, 1)
148mmctx_data(0x001000, 3)
149mmctx_data(0x001014, 1)
150nnvc0_gpc_mmio_tail:
151mmctx_data(0x000c6c, 1); 127mmctx_data(0x000c6c, 1);
152nnvc1_gpc_mmio_tail: 128nvc1_gpc_mmio_tail:
153
154nvd9_gpc_mmio_head:
155mmctx_data(0x000380, 1)
156mmctx_data(0x000400, 2)
157mmctx_data(0x00040c, 3)
158mmctx_data(0x000450, 9)
159mmctx_data(0x000600, 1)
160mmctx_data(0x000684, 1)
161mmctx_data(0x000700, 5)
162mmctx_data(0x000800, 1)
163mmctx_data(0x000808, 3)
164mmctx_data(0x000828, 1)
165mmctx_data(0x000830, 1)
166mmctx_data(0x0008d8, 1)
167mmctx_data(0x0008e0, 1)
168mmctx_data(0x0008e8, 6)
169mmctx_data(0x00091c, 1)
170mmctx_data(0x000924, 3)
171mmctx_data(0x000b00, 1)
172mmctx_data(0x000b08, 6)
173mmctx_data(0x000bb8, 1)
174mmctx_data(0x000c08, 1)
175mmctx_data(0x000c10, 8)
176mmctx_data(0x000c6c, 1)
177mmctx_data(0x000c80, 1)
178mmctx_data(0x000c8c, 1)
179mmctx_data(0x001000, 3)
180mmctx_data(0x001014, 1)
181nvd9_gpc_mmio_tail:
182 129
183// TPC mmio lists 130// TPC mmio lists
184nvc0_tpc_mmio_head: 131nvc0_tpc_mmio_head:
@@ -188,7 +135,6 @@ mmctx_data(0x000048, 1)
188mmctx_data(0x000064, 1) 135mmctx_data(0x000064, 1)
189mmctx_data(0x000088, 1) 136mmctx_data(0x000088, 1)
190mmctx_data(0x000200, 6) 137mmctx_data(0x000200, 6)
191mmctx_data(0x00021c, 2)
192mmctx_data(0x000300, 6) 138mmctx_data(0x000300, 6)
193mmctx_data(0x0003d0, 1) 139mmctx_data(0x0003d0, 1)
194mmctx_data(0x0003e0, 2) 140mmctx_data(0x0003e0, 2)
@@ -203,86 +149,15 @@ mmctx_data(0x000644, 20)
203mmctx_data(0x000698, 1) 149mmctx_data(0x000698, 1)
204mmctx_data(0x000750, 2) 150mmctx_data(0x000750, 2)
205nvc0_tpc_mmio_tail: 151nvc0_tpc_mmio_tail:
206mmctx_data(0x000758, 1)
207mmctx_data(0x0002c4, 1)
208mmctx_data(0x0006e0, 1)
209nvcf_tpc_mmio_tail:
210mmctx_data(0x0004bc, 1)
211nvc3_tpc_mmio_tail:
212
213nnvc0_tpc_mmio_head:
214mmctx_data(0x000018, 1)
215mmctx_data(0x00003c, 1)
216mmctx_data(0x000048, 1)
217mmctx_data(0x000064, 1)
218mmctx_data(0x000088, 1)
219mmctx_data(0x000200, 6)
220mmctx_data(0x000300, 6)
221mmctx_data(0x0003d0, 1)
222mmctx_data(0x0003e0, 2)
223mmctx_data(0x000400, 3)
224mmctx_data(0x000420, 1)
225mmctx_data(0x0004b0, 1)
226mmctx_data(0x0004e8, 1)
227mmctx_data(0x0004f4, 1)
228mmctx_data(0x000520, 2)
229mmctx_data(0x000604, 4)
230mmctx_data(0x000644, 20)
231mmctx_data(0x000698, 1)
232mmctx_data(0x000750, 2)
233nnvc0_tpc_mmio_tail:
234
235nnvc3_tpc_mmio_head:
236mmctx_data(0x000018, 1)
237mmctx_data(0x00003c, 1)
238mmctx_data(0x000048, 1)
239mmctx_data(0x000064, 1)
240mmctx_data(0x000088, 1)
241mmctx_data(0x000200, 6)
242mmctx_data(0x00021c, 2) 152mmctx_data(0x00021c, 2)
243mmctx_data(0x0002c4, 1) 153mmctx_data(0x0002c4, 1)
244mmctx_data(0x000300, 6) 154mmctx_data(0x000730, 8)
245mmctx_data(0x0003d0, 1) 155mmctx_data(0x000758, 1)
246mmctx_data(0x0003e0, 2) 156nvc3_tpc_mmio_tail:
247mmctx_data(0x000400, 3)
248mmctx_data(0x000420, 1)
249mmctx_data(0x0004b0, 1)
250mmctx_data(0x0004e8, 1)
251mmctx_data(0x0004f4, 1)
252mmctx_data(0x000520, 2)
253mmctx_data(0x000604, 4)
254mmctx_data(0x000644, 20)
255mmctx_data(0x000698, 1)
256mmctx_data(0x0006e0, 1)
257mmctx_data(0x000730, 11)
258nnvc3_tpc_mmio_tail:
259mmctx_data(0x000544, 1)
260nnvc1_tpc_mmio_tail:
261
262nvd9_tpc_mmio_head:
263mmctx_data(0x000018, 1)
264mmctx_data(0x00003c, 1)
265mmctx_data(0x000048, 1)
266mmctx_data(0x000064, 1)
267mmctx_data(0x000088, 1)
268mmctx_data(0x000200, 6)
269mmctx_data(0x00021c, 2)
270mmctx_data(0x0002c4, 1)
271mmctx_data(0x000300, 6)
272mmctx_data(0x0003d0, 1)
273mmctx_data(0x0003e0, 2)
274mmctx_data(0x000400, 3)
275mmctx_data(0x000420, 3)
276mmctx_data(0x0004b0, 1)
277mmctx_data(0x0004e8, 1)
278mmctx_data(0x0004f4, 1)
279mmctx_data(0x000520, 2)
280mmctx_data(0x000544, 1) 157mmctx_data(0x000544, 1)
281mmctx_data(0x000604, 4) 158nvc1_tpc_mmio_tail:
282mmctx_data(0x000644, 20) 159mmctx_data(0x000424, 2);
283mmctx_data(0x000698, 1) 160mmctx_data(0x0006e0, 1);
284mmctx_data(0x0006e0, 1)
285mmctx_data(0x000730, 11)
286nvd9_tpc_mmio_tail: 161nvd9_tpc_mmio_tail:
287 162
288.section #nvc0_grgpc_code 163.section #nvc0_grgpc_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
index bad9a16a9463..cafcc638042a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -34,88 +34,36 @@ uint32_t nvc0_grgpc_data[] = {
34 0x00000000, 34 0x00000000,
35/* 0x0064: chipsets */ 35/* 0x0064: chipsets */
36 0x000000c0, 36 0x000000c0,
37 0x01940134, 37 0x013c00d4,
38 0x02ac0260, 38 0x018c0140,
39 0x000000c1, 39 0x000000c1,
40 0x01980134, 40 0x014000d4,
41 0x030802ac, 41 0x01a00140,
42 0x000000c3, 42 0x000000c3,
43 0x01940134, 43 0x013c00d4,
44 0x030402ac, 44 0x019c0140,
45 0x000000c4, 45 0x000000c4,
46 0x01940134, 46 0x013c00d4,
47 0x030402ac, 47 0x019c0140,
48 0x000000c8, 48 0x000000c8,
49 0x01940134, 49 0x013c00d4,
50 0x02ac0260, 50 0x018c0140,
51 0x000000ce, 51 0x000000ce,
52 0x013400d4, 52 0x013c00d4,
53 0x02600200, 53 0x019c0140,
54 0x000000cf, 54 0x000000cf,
55 0x013400d4, 55 0x013c00d4,
56 0x025c0200, 56 0x019c0140,
57 0x000000d9, 57 0x000000d9,
58 0x02000198, 58 0x014000d8,
59 0x03640308, 59 0x01a80140,
60 0x000000d7, 60 0x000000d7,
61 0x02000198, 61 0x014000d8,
62 0x03640308, 62 0x01a80140,
63 0x00000000, 63 0x00000000,
64/* 0x00d4: nvc0_gpc_mmio_head */ 64/* 0x00d4: nvc0_gpc_mmio_head */
65 0x00000380, 65 0x00000408,
66 0x14000400, 66/* 0x00d8: nvd9_gpc_mmio_head */
67 0x20000450,
68 0x00000600,
69 0x00000684,
70 0x10000700,
71 0x00000800,
72 0x08000808,
73 0x00000828,
74 0x00000830,
75 0x000008d8,
76 0x000008e0,
77 0x140008e8,
78 0x0000091c,
79 0x08000924,
80 0x00000b00,
81 0x14000b08,
82 0x00000bb8,
83 0x00000c08,
84 0x1c000c10,
85 0x00000c80,
86 0x00000c8c,
87 0x08001000,
88 0x00001014,
89/* 0x0134: nvc0_gpc_mmio_tail */
90/* 0x0134: nnvc0_gpc_mmio_head */
91 0x00000380,
92 0x14000400,
93 0x20000450,
94 0x00000600,
95 0x00000684,
96 0x10000700,
97 0x00000800,
98 0x08000808,
99 0x00000828,
100 0x00000830,
101 0x000008d8,
102 0x000008e0,
103 0x140008e8,
104 0x0000091c,
105 0x08000924,
106 0x00000b00,
107 0x14000b08,
108 0x00000bb8,
109 0x00000c08,
110 0x1c000c10,
111 0x00000c80,
112 0x00000c8c,
113 0x08001000,
114 0x00001014,
115/* 0x0194: nnvc0_gpc_mmio_tail */
116 0x00000c6c,
117/* 0x0198: nnvc1_gpc_mmio_tail */
118/* 0x0198: nvd9_gpc_mmio_head */
119 0x00000380, 67 0x00000380,
120 0x04000400, 68 0x04000400,
121 0x0800040c, 69 0x0800040c,
@@ -137,41 +85,14 @@ uint32_t nvc0_grgpc_data[] = {
137 0x00000bb8, 85 0x00000bb8,
138 0x00000c08, 86 0x00000c08,
139 0x1c000c10, 87 0x1c000c10,
140 0x00000c6c,
141 0x00000c80, 88 0x00000c80,
142 0x00000c8c, 89 0x00000c8c,
143 0x08001000, 90 0x08001000,
144 0x00001014, 91 0x00001014,
145/* 0x0200: nvd9_gpc_mmio_tail */ 92/* 0x013c: nvc0_gpc_mmio_tail */
146/* 0x0200: nvc0_tpc_mmio_head */ 93 0x00000c6c,
147 0x00000018, 94/* 0x0140: nvc1_gpc_mmio_tail */
148 0x0000003c, 95/* 0x0140: nvc0_tpc_mmio_head */
149 0x00000048,
150 0x00000064,
151 0x00000088,
152 0x14000200,
153 0x0400021c,
154 0x14000300,
155 0x000003d0,
156 0x040003e0,
157 0x08000400,
158 0x00000420,
159 0x000004b0,
160 0x000004e8,
161 0x000004f4,
162 0x04000520,
163 0x0c000604,
164 0x4c000644,
165 0x00000698,
166 0x04000750,
167/* 0x0250: nvc0_tpc_mmio_tail */
168 0x00000758,
169 0x000002c4,
170 0x000006e0,
171/* 0x025c: nvcf_tpc_mmio_tail */
172 0x000004bc,
173/* 0x0260: nvc3_tpc_mmio_tail */
174/* 0x0260: nnvc0_tpc_mmio_head */
175 0x00000018, 96 0x00000018,
176 0x0000003c, 97 0x0000003c,
177 0x00000048, 98 0x00000048,
@@ -191,57 +112,16 @@ uint32_t nvc0_grgpc_data[] = {
191 0x4c000644, 112 0x4c000644,
192 0x00000698, 113 0x00000698,
193 0x04000750, 114 0x04000750,
194/* 0x02ac: nnvc0_tpc_mmio_tail */ 115/* 0x018c: nvc0_tpc_mmio_tail */
195/* 0x02ac: nnvc3_tpc_mmio_head */
196 0x00000018,
197 0x0000003c,
198 0x00000048,
199 0x00000064,
200 0x00000088,
201 0x14000200,
202 0x0400021c,
203 0x000002c4,
204 0x14000300,
205 0x000003d0,
206 0x040003e0,
207 0x08000400,
208 0x00000420,
209 0x000004b0,
210 0x000004e8,
211 0x000004f4,
212 0x04000520,
213 0x0c000604,
214 0x4c000644,
215 0x00000698,
216 0x000006e0,
217 0x28000730,
218/* 0x0304: nnvc3_tpc_mmio_tail */
219 0x00000544,
220/* 0x0308: nnvc1_tpc_mmio_tail */
221/* 0x0308: nvd9_tpc_mmio_head */
222 0x00000018,
223 0x0000003c,
224 0x00000048,
225 0x00000064,
226 0x00000088,
227 0x14000200,
228 0x0400021c, 116 0x0400021c,
229 0x000002c4, 117 0x000002c4,
230 0x14000300, 118 0x1c000730,
231 0x000003d0, 119 0x00000758,
232 0x040003e0, 120/* 0x019c: nvc3_tpc_mmio_tail */
233 0x08000400,
234 0x08000420,
235 0x000004b0,
236 0x000004e8,
237 0x000004f4,
238 0x04000520,
239 0x00000544, 121 0x00000544,
240 0x0c000604, 122/* 0x01a0: nvc1_tpc_mmio_tail */
241 0x4c000644, 123 0x04000424,
242 0x00000698,
243 0x000006e0, 124 0x000006e0,
244 0x28000730,
245}; 125};
246 126
247uint32_t nvc0_grgpc_code[] = { 127uint32_t nvc0_grgpc_code[] = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index 6eb5168a3811..9f174be6bc82 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -48,20 +48,20 @@ xfer_data: .b32 0
48.align 256 48.align 256
49chipsets: 49chipsets:
50.b8 0xc0 0 0 0 50.b8 0xc0 0 0 0
51.b16 #nnvc0_hub_mmio_head 51.b16 #nvc0_hub_mmio_head
52.b16 #nnvc0_hub_mmio_tail 52.b16 #nvc0_hub_mmio_tail
53.b8 0xc1 0 0 0 53.b8 0xc1 0 0 0
54.b16 #nnvc0_hub_mmio_head 54.b16 #nvc0_hub_mmio_head
55.b16 #nvc1_hub_mmio_tail 55.b16 #nvc1_hub_mmio_tail
56.b8 0xc3 0 0 0 56.b8 0xc3 0 0 0
57.b16 #nnvc0_hub_mmio_head 57.b16 #nvc0_hub_mmio_head
58.b16 #nnvc0_hub_mmio_tail 58.b16 #nvc0_hub_mmio_tail
59.b8 0xc4 0 0 0 59.b8 0xc4 0 0 0
60.b16 #nnvc0_hub_mmio_head 60.b16 #nvc0_hub_mmio_head
61.b16 #nnvc0_hub_mmio_tail 61.b16 #nvc0_hub_mmio_tail
62.b8 0xc8 0 0 0 62.b8 0xc8 0 0 0
63.b16 #nnvc0_hub_mmio_head 63.b16 #nvc0_hub_mmio_head
64.b16 #nnvc0_hub_mmio_tail 64.b16 #nvc0_hub_mmio_tail
65.b8 0xce 0 0 0 65.b8 0xce 0 0 0
66.b16 #nvc0_hub_mmio_head 66.b16 #nvc0_hub_mmio_head
67.b16 #nvc0_hub_mmio_tail 67.b16 #nvc0_hub_mmio_tail
@@ -77,91 +77,8 @@ chipsets:
77.b8 0 0 0 0 77.b8 0 0 0 0
78 78
79nvc0_hub_mmio_head: 79nvc0_hub_mmio_head:
80mmctx_data(0x17e91c, 2) 80mmctx_data(0x40402c, 1)
81mmctx_data(0x400204, 2) 81mmctx_data(0x404174, 1)
82mmctx_data(0x404004, 11)
83mmctx_data(0x404044, 1)
84mmctx_data(0x404094, 14)
85mmctx_data(0x4040d0, 7)
86mmctx_data(0x4040f8, 1)
87mmctx_data(0x404130, 3)
88mmctx_data(0x404150, 3)
89mmctx_data(0x404164, 2)
90mmctx_data(0x404174, 3)
91mmctx_data(0x404200, 8)
92mmctx_data(0x404404, 14)
93mmctx_data(0x404460, 4)
94mmctx_data(0x404480, 1)
95mmctx_data(0x404498, 1)
96mmctx_data(0x404604, 4)
97mmctx_data(0x404618, 32)
98mmctx_data(0x404698, 21)
99mmctx_data(0x4046f0, 2)
100mmctx_data(0x404700, 22)
101mmctx_data(0x405800, 1)
102mmctx_data(0x405830, 3)
103mmctx_data(0x405854, 1)
104mmctx_data(0x405870, 4)
105mmctx_data(0x405a00, 2)
106mmctx_data(0x405a18, 1)
107mmctx_data(0x406020, 1)
108mmctx_data(0x406028, 4)
109mmctx_data(0x4064a8, 2)
110mmctx_data(0x4064b4, 2)
111mmctx_data(0x407804, 1)
112mmctx_data(0x40780c, 6)
113mmctx_data(0x4078bc, 1)
114mmctx_data(0x408000, 7)
115mmctx_data(0x408064, 1)
116mmctx_data(0x408800, 3)
117mmctx_data(0x408900, 4)
118mmctx_data(0x408980, 1)
119nvc0_hub_mmio_tail:
120
121nnvc0_hub_mmio_head:
122mmctx_data(0x17e91c, 2)
123mmctx_data(0x400204, 2)
124mmctx_data(0x404004, 11)
125mmctx_data(0x404044, 1)
126mmctx_data(0x404094, 14)
127mmctx_data(0x4040d0, 7)
128mmctx_data(0x4040f8, 1)
129mmctx_data(0x404130, 3)
130mmctx_data(0x404150, 3)
131mmctx_data(0x404164, 2)
132mmctx_data(0x404174, 3)
133mmctx_data(0x404200, 8)
134mmctx_data(0x404404, 14)
135mmctx_data(0x404460, 4)
136mmctx_data(0x404480, 1)
137mmctx_data(0x404498, 1)
138mmctx_data(0x404604, 4)
139mmctx_data(0x404618, 32)
140mmctx_data(0x404698, 21)
141mmctx_data(0x4046f0, 2)
142mmctx_data(0x404700, 22)
143mmctx_data(0x405800, 1)
144mmctx_data(0x405830, 3)
145mmctx_data(0x405854, 1)
146mmctx_data(0x405870, 4)
147mmctx_data(0x405a00, 2)
148mmctx_data(0x405a18, 1)
149mmctx_data(0x406020, 1)
150mmctx_data(0x406028, 4)
151mmctx_data(0x4064a8, 2)
152mmctx_data(0x4064b4, 2)
153mmctx_data(0x407804, 1)
154mmctx_data(0x40780c, 6)
155mmctx_data(0x4078bc, 1)
156mmctx_data(0x408000, 7)
157mmctx_data(0x408064, 1)
158mmctx_data(0x408800, 3)
159mmctx_data(0x408900, 3)
160mmctx_data(0x408980, 1)
161nnvc0_hub_mmio_tail:
162mmctx_data(0x4064c0, 2)
163nvc1_hub_mmio_tail:
164
165nvd9_hub_mmio_head: 82nvd9_hub_mmio_head:
166mmctx_data(0x17e91c, 2) 83mmctx_data(0x17e91c, 2)
167mmctx_data(0x400204, 2) 84mmctx_data(0x400204, 2)
@@ -193,7 +110,7 @@ mmctx_data(0x405a18, 1)
193mmctx_data(0x406020, 1) 110mmctx_data(0x406020, 1)
194mmctx_data(0x406028, 4) 111mmctx_data(0x406028, 4)
195mmctx_data(0x4064a8, 2) 112mmctx_data(0x4064a8, 2)
196mmctx_data(0x4064b4, 5) 113mmctx_data(0x4064b4, 2)
197mmctx_data(0x407804, 1) 114mmctx_data(0x407804, 1)
198mmctx_data(0x40780c, 6) 115mmctx_data(0x40780c, 6)
199mmctx_data(0x4078bc, 1) 116mmctx_data(0x4078bc, 1)
@@ -202,6 +119,10 @@ mmctx_data(0x408064, 1)
202mmctx_data(0x408800, 3) 119mmctx_data(0x408800, 3)
203mmctx_data(0x408900, 3) 120mmctx_data(0x408900, 3)
204mmctx_data(0x408980, 1) 121mmctx_data(0x408980, 1)
122nvc0_hub_mmio_tail:
123mmctx_data(0x4064c0, 2)
124nvc1_hub_mmio_tail:
125mmctx_data(0x4064bc, 3)
205nvd9_hub_mmio_tail: 126nvd9_hub_mmio_tail:
206 127
207.section #nvc0_grhub_code 128.section #nvc0_grhub_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index 9d5517407dfb..0953c2db2d13 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -203,109 +203,28 @@ uint32_t nvc0_grhub_data[] = {
203 0x00000000, 203 0x00000000,
204/* 0x0300: chipsets */ 204/* 0x0300: chipsets */
205 0x000000c0, 205 0x000000c0,
206 0x048403e8, 206 0x03f0034c,
207 0x000000c1, 207 0x000000c1,
208 0x048803e8, 208 0x03f4034c,
209 0x000000c3, 209 0x000000c3,
210 0x048403e8, 210 0x03f0034c,
211 0x000000c4, 211 0x000000c4,
212 0x048403e8, 212 0x03f0034c,
213 0x000000c8, 213 0x000000c8,
214 0x048403e8, 214 0x03f0034c,
215 0x000000ce, 215 0x000000ce,
216 0x03e8034c, 216 0x03f0034c,
217 0x000000cf, 217 0x000000cf,
218 0x03e8034c, 218 0x03f0034c,
219 0x000000d9, 219 0x000000d9,
220 0x05240488, 220 0x03f80354,
221 0x000000d7, 221 0x000000d7,
222 0x05240488, 222 0x03f80354,
223 0x00000000, 223 0x00000000,
224/* 0x034c: nvc0_hub_mmio_head */ 224/* 0x034c: nvc0_hub_mmio_head */
225 0x0417e91c, 225 0x0040402c,
226 0x04400204, 226 0x00404174,
227 0x28404004, 227/* 0x0354: nvd9_hub_mmio_head */
228 0x00404044,
229 0x34404094,
230 0x184040d0,
231 0x004040f8,
232 0x08404130,
233 0x08404150,
234 0x04404164,
235 0x08404174,
236 0x1c404200,
237 0x34404404,
238 0x0c404460,
239 0x00404480,
240 0x00404498,
241 0x0c404604,
242 0x7c404618,
243 0x50404698,
244 0x044046f0,
245 0x54404700,
246 0x00405800,
247 0x08405830,
248 0x00405854,
249 0x0c405870,
250 0x04405a00,
251 0x00405a18,
252 0x00406020,
253 0x0c406028,
254 0x044064a8,
255 0x044064b4,
256 0x00407804,
257 0x1440780c,
258 0x004078bc,
259 0x18408000,
260 0x00408064,
261 0x08408800,
262 0x0c408900,
263 0x00408980,
264/* 0x03e8: nvc0_hub_mmio_tail */
265/* 0x03e8: nnvc0_hub_mmio_head */
266 0x0417e91c,
267 0x04400204,
268 0x28404004,
269 0x00404044,
270 0x34404094,
271 0x184040d0,
272 0x004040f8,
273 0x08404130,
274 0x08404150,
275 0x04404164,
276 0x08404174,
277 0x1c404200,
278 0x34404404,
279 0x0c404460,
280 0x00404480,
281 0x00404498,
282 0x0c404604,
283 0x7c404618,
284 0x50404698,
285 0x044046f0,
286 0x54404700,
287 0x00405800,
288 0x08405830,
289 0x00405854,
290 0x0c405870,
291 0x04405a00,
292 0x00405a18,
293 0x00406020,
294 0x0c406028,
295 0x044064a8,
296 0x044064b4,
297 0x00407804,
298 0x1440780c,
299 0x004078bc,
300 0x18408000,
301 0x00408064,
302 0x08408800,
303 0x08408900,
304 0x00408980,
305/* 0x0484: nnvc0_hub_mmio_tail */
306 0x044064c0,
307/* 0x0488: nvc1_hub_mmio_tail */
308/* 0x0488: nvd9_hub_mmio_head */
309 0x0417e91c, 228 0x0417e91c,
310 0x04400204, 229 0x04400204,
311 0x24404004, 230 0x24404004,
@@ -336,7 +255,7 @@ uint32_t nvc0_grhub_data[] = {
336 0x00406020, 255 0x00406020,
337 0x0c406028, 256 0x0c406028,
338 0x044064a8, 257 0x044064a8,
339 0x104064b4, 258 0x044064b4,
340 0x00407804, 259 0x00407804,
341 0x1440780c, 260 0x1440780c,
342 0x004078bc, 261 0x004078bc,
@@ -345,6 +264,10 @@ uint32_t nvc0_grhub_data[] = {
345 0x08408800, 264 0x08408800,
346 0x08408900, 265 0x08408900,
347 0x00408980, 266 0x00408980,
267/* 0x03f0: nvc0_hub_mmio_tail */
268 0x044064c0,
269/* 0x03f4: nvc1_hub_mmio_tail */
270 0x084064bc,
348}; 271};
349 272
350uint32_t nvc0_grhub_code[] = { 273uint32_t nvc0_grhub_code[] = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index f146ebc9c08d..d61c833be09f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -757,7 +757,11 @@ nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
757 case 0xc4: 757 case 0xc4:
758 case 0xc1: 758 case 0xc1:
759 case 0xc8: 759 case 0xc8:
760 case 0xce:
761 case 0xcf:
762 break;
760 default: 763 default:
764 BUG_ON(1);
761 break; 765 break;
762 } 766 }
763} 767}
@@ -771,13 +775,17 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
771 case 0xc3: 775 case 0xc3:
772 case 0xc4: 776 case 0xc4:
773 case 0xc1: 777 case 0xc1:
778 case 0xce:
779 case 0xcf:
774 case 0xd9: 780 case 0xd9:
775 case 0xd7: 781 case 0xd7:
776 nv_wr32(priv, 0x405900, 0x00002834); 782 nv_wr32(priv, 0x405900, 0x00002834);
777 break; 783 break;
778 case 0xc0: 784 case 0xc0:
779 case 0xc8: 785 case 0xc8:
786 break;
780 default: 787 default:
788 BUG_ON(1);
781 break; 789 break;
782 } 790 }
783 nv_wr32(priv, 0x405908, 0x00000000); 791 nv_wr32(priv, 0x405908, 0x00000000);
@@ -792,7 +800,11 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
792 case 0xc4: 800 case 0xc4:
793 case 0xc1: 801 case 0xc1:
794 case 0xc8: 802 case 0xc8:
803 case 0xce:
804 case 0xcf:
805 break;
795 default: 806 default:
807 BUG_ON(1);
796 break; 808 break;
797 } 809 }
798} 810}
@@ -816,7 +828,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
816 case 0xc4: 828 case 0xc4:
817 case 0xc1: 829 case 0xc1:
818 case 0xc8: 830 case 0xc8:
831 case 0xce:
832 case 0xcf:
833 break;
819 default: 834 default:
835 BUG_ON(1);
820 break; 836 break;
821 } 837 }
822 nv_wr32(priv, 0x4184a0, 0x00000000); 838 nv_wr32(priv, 0x4184a0, 0x00000000);
@@ -831,7 +847,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
831 case 0xc4: 847 case 0xc4:
832 case 0xc1: 848 case 0xc1:
833 case 0xc8: 849 case 0xc8:
850 case 0xce:
851 case 0xcf:
852 break;
834 default: 853 default:
854 BUG_ON(1);
835 break; 855 break;
836 } 856 }
837 nv_wr32(priv, 0x418604, 0x00000000); 857 nv_wr32(priv, 0x418604, 0x00000000);
@@ -846,9 +866,13 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
846 case 0xc3: 866 case 0xc3:
847 case 0xc4: 867 case 0xc4:
848 case 0xc8: 868 case 0xc8:
849 default: 869 case 0xce:
870 case 0xcf:
850 nv_wr32(priv, 0x418714, 0x80000000); 871 nv_wr32(priv, 0x418714, 0x80000000);
851 break; 872 break;
873 default:
874 BUG_ON(1);
875 break;
852 } 876 }
853 nv_wr32(priv, 0x418384, 0x00000000); 877 nv_wr32(priv, 0x418384, 0x00000000);
854 nv_wr32(priv, 0x418814, 0x00000000); 878 nv_wr32(priv, 0x418814, 0x00000000);
@@ -865,9 +889,13 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
865 case 0xc0: 889 case 0xc0:
866 case 0xc3: 890 case 0xc3:
867 case 0xc4: 891 case 0xc4:
868 default: 892 case 0xce:
893 case 0xcf:
869 nv_wr32(priv, 0x4188c8, 0x80000000); 894 nv_wr32(priv, 0x4188c8, 0x80000000);
870 break; 895 break;
896 default:
897 BUG_ON(1);
898 break;
871 } 899 }
872 nv_wr32(priv, 0x4188cc, 0x00000000); 900 nv_wr32(priv, 0x4188cc, 0x00000000);
873 nv_wr32(priv, 0x4188d0, 0x00010000); 901 nv_wr32(priv, 0x4188d0, 0x00010000);
@@ -891,7 +919,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
891 case 0xc4: 919 case 0xc4:
892 case 0xc1: 920 case 0xc1:
893 case 0xc8: 921 case 0xc8:
922 case 0xce:
923 case 0xcf:
924 break;
894 default: 925 default:
926 BUG_ON(1);
895 break; 927 break;
896 } 928 }
897 nv_wr32(priv, 0x418c88, 0x00000000); 929 nv_wr32(priv, 0x418c88, 0x00000000);
@@ -906,7 +938,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
906 case 0xc4: 938 case 0xc4:
907 case 0xc1: 939 case 0xc1:
908 case 0xc8: 940 case 0xc8:
941 case 0xce:
942 case 0xcf:
943 break;
909 default: 944 default:
945 BUG_ON(1);
910 break; 946 break;
911 } 947 }
912 nv_wr32(priv, 0x418d00, 0x00000000); 948 nv_wr32(priv, 0x418d00, 0x00000000);
@@ -922,7 +958,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
922 case 0xc4: 958 case 0xc4:
923 case 0xc1: 959 case 0xc1:
924 case 0xc8: 960 case 0xc8:
961 case 0xce:
962 case 0xcf:
963 break;
925 default: 964 default:
965 BUG_ON(1);
926 break; 966 break;
927 } 967 }
928 nv_wr32(priv, 0x418f08, 0x00000000); 968 nv_wr32(priv, 0x418f08, 0x00000000);
@@ -939,9 +979,13 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
939 case 0xc3: 979 case 0xc3:
940 case 0xc4: 980 case 0xc4:
941 case 0xc8: 981 case 0xc8:
942 default: 982 case 0xce:
983 case 0xcf:
943 nv_wr32(priv, 0x418e00, 0x00000050); 984 nv_wr32(priv, 0x418e00, 0x00000050);
944 break; 985 break;
986 default:
987 BUG_ON(1);
988 break;
945 } 989 }
946 nv_wr32(priv, 0x418e08, 0x00000000); 990 nv_wr32(priv, 0x418e08, 0x00000000);
947 switch (nv_device(priv)->chipset) { 991 switch (nv_device(priv)->chipset) {
@@ -955,7 +999,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
955 case 0xc4: 999 case 0xc4:
956 case 0xc1: 1000 case 0xc1:
957 case 0xc8: 1001 case 0xc8:
1002 case 0xce:
1003 case 0xcf:
1004 break;
958 default: 1005 default:
1006 BUG_ON(1);
959 break; 1007 break;
960 } 1008 }
961 nv_wr32(priv, 0x41900c, 0x00000000); 1009 nv_wr32(priv, 0x41900c, 0x00000000);
@@ -973,13 +1021,17 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
973 case 0xc3: 1021 case 0xc3:
974 case 0xc4: 1022 case 0xc4:
975 case 0xc1: 1023 case 0xc1:
1024 case 0xce:
1025 case 0xcf:
976 case 0xd9: 1026 case 0xd9:
977 case 0xd7: 1027 case 0xd7:
978 nv_wr32(priv, 0x419ac8, 0x00000000); 1028 nv_wr32(priv, 0x419ac8, 0x00000000);
979 break; 1029 break;
980 case 0xc0: 1030 case 0xc0:
981 case 0xc8: 1031 case 0xc8:
1032 break;
982 default: 1033 default:
1034 BUG_ON(1);
983 break; 1035 break;
984 } 1036 }
985 nv_wr32(priv, 0x419ab8, 0x000000e7); 1037 nv_wr32(priv, 0x419ab8, 0x000000e7);
@@ -996,9 +1048,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
996 case 0xc4: 1048 case 0xc4:
997 case 0xc1: 1049 case 0xc1:
998 case 0xc8: 1050 case 0xc8:
999 default: 1051 case 0xce:
1052 case 0xcf:
1000 nv_wr32(priv, 0x41980c, 0x00000000); 1053 nv_wr32(priv, 0x41980c, 0x00000000);
1001 break; 1054 break;
1055 default:
1056 BUG_ON(1);
1057 break;
1002 } 1058 }
1003 nv_wr32(priv, 0x419810, 0x00000000); 1059 nv_wr32(priv, 0x419810, 0x00000000);
1004 switch (nv_device(priv)->chipset) { 1060 switch (nv_device(priv)->chipset) {
@@ -1011,9 +1067,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1011 case 0xc3: 1067 case 0xc3:
1012 case 0xc4: 1068 case 0xc4:
1013 case 0xc8: 1069 case 0xc8:
1014 default: 1070 case 0xce:
1071 case 0xcf:
1015 nv_wr32(priv, 0x419814, 0x00000000); 1072 nv_wr32(priv, 0x419814, 0x00000000);
1016 break; 1073 break;
1074 default:
1075 BUG_ON(1);
1076 break;
1017 } 1077 }
1018 nv_wr32(priv, 0x419844, 0x00000000); 1078 nv_wr32(priv, 0x419844, 0x00000000);
1019 switch (nv_device(priv)->chipset) { 1079 switch (nv_device(priv)->chipset) {
@@ -1026,9 +1086,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1026 case 0xc4: 1086 case 0xc4:
1027 case 0xc1: 1087 case 0xc1:
1028 case 0xc8: 1088 case 0xc8:
1029 default: 1089 case 0xce:
1090 case 0xcf:
1030 nv_wr32(priv, 0x41984c, 0x00005bc5); 1091 nv_wr32(priv, 0x41984c, 0x00005bc5);
1031 break; 1092 break;
1093 default:
1094 BUG_ON(1);
1095 break;
1032 } 1096 }
1033 nv_wr32(priv, 0x419850, 0x00000000); 1097 nv_wr32(priv, 0x419850, 0x00000000);
1034 nv_wr32(priv, 0x419854, 0x00000000); 1098 nv_wr32(priv, 0x419854, 0x00000000);
@@ -1038,13 +1102,17 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1038 case 0xc3: 1102 case 0xc3:
1039 case 0xc4: 1103 case 0xc4:
1040 case 0xc1: 1104 case 0xc1:
1105 case 0xce:
1106 case 0xcf:
1041 case 0xd9: 1107 case 0xd9:
1042 case 0xd7: 1108 case 0xd7:
1043 nv_wr32(priv, 0x419880, 0x00000002); 1109 nv_wr32(priv, 0x419880, 0x00000002);
1044 break; 1110 break;
1045 case 0xc0: 1111 case 0xc0:
1046 case 0xc8: 1112 case 0xc8:
1113 break;
1047 default: 1114 default:
1115 BUG_ON(1);
1048 break; 1116 break;
1049 } 1117 }
1050 nv_wr32(priv, 0x419c98, 0x00000000); 1118 nv_wr32(priv, 0x419c98, 0x00000000);
@@ -1067,7 +1135,11 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1067 case 0xc4: 1135 case 0xc4:
1068 case 0xc1: 1136 case 0xc1:
1069 case 0xc8: 1137 case 0xc8:
1138 case 0xce:
1139 case 0xcf:
1140 break;
1070 default: 1141 default:
1142 BUG_ON(1);
1071 break; 1143 break;
1072 } 1144 }
1073 nv_wr32(priv, 0x419d2c, 0x00000000); 1145 nv_wr32(priv, 0x419d2c, 0x00000000);
@@ -1082,7 +1154,11 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1082 case 0xc4: 1154 case 0xc4:
1083 case 0xc1: 1155 case 0xc1:
1084 case 0xc8: 1156 case 0xc8:
1157 case 0xce:
1158 case 0xcf:
1159 break;
1085 default: 1160 default:
1161 BUG_ON(1);
1086 break; 1162 break;
1087 } 1163 }
1088 nv_wr32(priv, 0x419c0c, 0x00000000); 1164 nv_wr32(priv, 0x419c0c, 0x00000000);
@@ -1099,9 +1175,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1099 case 0xc4: 1175 case 0xc4:
1100 case 0xc1: 1176 case 0xc1:
1101 case 0xc8: 1177 case 0xc8:
1102 default: 1178 case 0xce:
1179 case 0xcf:
1103 nv_wr32(priv, 0x419ea8, 0x00001100); 1180 nv_wr32(priv, 0x419ea8, 0x00001100);
1104 break; 1181 break;
1182 default:
1183 BUG_ON(1);
1184 break;
1105 } 1185 }
1106 1186
1107 switch (nv_device(priv)->chipset) { 1187 switch (nv_device(priv)->chipset) {
@@ -1112,11 +1192,15 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1112 case 0xc3: 1192 case 0xc3:
1113 case 0xc4: 1193 case 0xc4:
1114 case 0xc1: 1194 case 0xc1:
1195 case 0xce:
1196 case 0xcf:
1115 case 0xd9: 1197 case 0xd9:
1116 case 0xd7: 1198 case 0xd7:
1117 default:
1118 nv_wr32(priv, 0x419eac, 0x11100702); 1199 nv_wr32(priv, 0x419eac, 0x11100702);
1119 break; 1200 break;
1201 default:
1202 BUG_ON(1);
1203 break;
1120 } 1204 }
1121 nv_wr32(priv, 0x419eb0, 0x00000003); 1205 nv_wr32(priv, 0x419eb0, 0x00000003);
1122 nv_wr32(priv, 0x419eb4, 0x00000000); 1206 nv_wr32(priv, 0x419eb4, 0x00000000);
@@ -1127,6 +1211,8 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1127 case 0xc3: 1211 case 0xc3:
1128 case 0xc4: 1212 case 0xc4:
1129 case 0xc1: 1213 case 0xc1:
1214 case 0xce:
1215 case 0xcf:
1130 case 0xd9: 1216 case 0xd9:
1131 case 0xd7: 1217 case 0xd7:
1132 nv_wr32(priv, 0x419ec8, 0x0e063818); 1218 nv_wr32(priv, 0x419ec8, 0x0e063818);
@@ -1135,10 +1221,12 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1135 break; 1221 break;
1136 case 0xc0: 1222 case 0xc0:
1137 case 0xc8: 1223 case 0xc8:
1138 default:
1139 nv_wr32(priv, 0x419ec8, 0x06060618); 1224 nv_wr32(priv, 0x419ec8, 0x06060618);
1140 nv_wr32(priv, 0x419ed0, 0x0eff0e38); 1225 nv_wr32(priv, 0x419ed0, 0x0eff0e38);
1141 break; 1226 break;
1227 default:
1228 BUG_ON(1);
1229 break;
1142 } 1230 }
1143 nv_wr32(priv, 0x419ed4, 0x011104f1); 1231 nv_wr32(priv, 0x419ed4, 0x011104f1);
1144 nv_wr32(priv, 0x419edc, 0x00000000); 1232 nv_wr32(priv, 0x419edc, 0x00000000);
@@ -1407,30 +1495,16 @@ nvc0_graph_init(struct nouveau_object *object)
1407 1495
1408 nvc0_graph_init_obj418880(priv); 1496 nvc0_graph_init_obj418880(priv);
1409 nvc0_graph_init_regs(priv); 1497 nvc0_graph_init_regs(priv);
1410 1498 nvc0_graph_init_unk40xx(priv);
1411 switch (nv_device(priv)->chipset) { 1499 nvc0_graph_init_unk44xx(priv);
1412 case 0xc0: 1500 nvc0_graph_init_unk78xx(priv);
1413 case 0xc3: 1501 nvc0_graph_init_unk60xx(priv);
1414 case 0xc4: 1502 nvc0_graph_init_unk64xx(priv);
1415 case 0xc1: 1503 nvc0_graph_init_unk58xx(priv);
1416 case 0xc8: 1504 nvc0_graph_init_unk80xx(priv);
1417 case 0xd9: 1505 nvc0_graph_init_gpc(priv);
1418 case 0xd7: 1506 nvc0_graph_init_tpc(priv);
1419 nvc0_graph_init_unk40xx(priv); 1507 nvc0_graph_init_unk88xx(priv);
1420 nvc0_graph_init_unk44xx(priv);
1421 nvc0_graph_init_unk78xx(priv);
1422 nvc0_graph_init_unk60xx(priv);
1423 nvc0_graph_init_unk64xx(priv);
1424 nvc0_graph_init_unk58xx(priv);
1425 nvc0_graph_init_unk80xx(priv);
1426 nvc0_graph_init_gpc(priv);
1427 nvc0_graph_init_tpc(priv);
1428 nvc0_graph_init_unk88xx(priv);
1429 break;
1430 default:
1431 break;
1432 }
1433
1434 nvc0_graph_init_gpc_0(priv); 1508 nvc0_graph_init_gpc_0(priv);
1435 /*nvc0_graph_init_unitplemented_c242(priv);*/ 1509 /*nvc0_graph_init_unitplemented_c242(priv);*/
1436 1510
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 11:22:45 -0400