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authorJon Mason <jon.mason@intel.com>2013-07-15 18:26:14 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-11-12 22:05:34 -0500
commit576db18cb68483e6e54f18dfda4b9c24f7e07dfe (patch)
tree8407c141f7b3fe74ce273425461016082a144286
parent21720562911f038d7406654e7ea0c171cfac47b8 (diff)
NTB: Correct Number of Scratch Pad Registers
commit 87034511519815259e37336f52edf06d114d43b6 upstream. The NTB Xeon hardware has 16 scratch pad registers and 16 back-to-back scratch pad registers. Correct the #define to represent this and update the variable names to reflect their usage. Signed-off-by: Jon Mason <jon.mason@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/ntb/ntb_hw.c2
-rw-r--r--drivers/ntb/ntb_regs.h4
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ntb/ntb_hw.c b/drivers/ntb/ntb_hw.c
index 515099ee12fe..3b0ab50e2d5c 100644
--- a/drivers/ntb/ntb_hw.c
+++ b/drivers/ntb/ntb_hw.c
@@ -547,7 +547,7 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
547 if (ndev->conn_type == NTB_CONN_B2B) { 547 if (ndev->conn_type == NTB_CONN_B2B) {
548 ndev->reg_ofs.sdb = ndev->reg_base + SNB_B2B_DOORBELL_OFFSET; 548 ndev->reg_ofs.sdb = ndev->reg_base + SNB_B2B_DOORBELL_OFFSET;
549 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_B2B_SPAD_OFFSET; 549 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_B2B_SPAD_OFFSET;
550 ndev->limits.max_spads = SNB_MAX_SPADS; 550 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
551 } else { 551 } else {
552 ndev->reg_ofs.sdb = ndev->reg_base + SNB_SDOORBELL_OFFSET; 552 ndev->reg_ofs.sdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
553 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET; 553 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
diff --git a/drivers/ntb/ntb_regs.h b/drivers/ntb/ntb_regs.h
index 5bfa8c06c059..96209b4abc22 100644
--- a/drivers/ntb/ntb_regs.h
+++ b/drivers/ntb/ntb_regs.h
@@ -53,8 +53,8 @@
53#define NTB_LINK_WIDTH_MASK 0x03f0 53#define NTB_LINK_WIDTH_MASK 0x03f0
54 54
55#define SNB_MSIX_CNT 4 55#define SNB_MSIX_CNT 4
56#define SNB_MAX_SPADS 16 56#define SNB_MAX_B2B_SPADS 16
57#define SNB_MAX_COMPAT_SPADS 8 57#define SNB_MAX_COMPAT_SPADS 16
58/* Reserve the uppermost bit for link interrupt */ 58/* Reserve the uppermost bit for link interrupt */
59#define SNB_MAX_DB_BITS 15 59#define SNB_MAX_DB_BITS 15
60#define SNB_DB_BITS_PER_VEC 5 60#define SNB_DB_BITS_PER_VEC 5