diff options
author | Vakul Garg <vakul@freescale.com> | 2013-03-12 04:25:21 -0400 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2013-03-22 06:13:54 -0400 |
commit | 575c1bd549ff6bc097b3669b086e54e01169379f (patch) | |
tree | 79f614dd0c7d6c62140cd199352ac37222ac8ffb | |
parent | a80c5422b1426699c279b74fe8d3e8a4e3c902de (diff) |
crypto: caam - set RDB bit in security configuration register
This change is required for post SEC-5.0 devices which have RNG4.
Setting RDB in security configuration register allows CAAM to use the
"Random Data Buffer" to be filled by a single request. The Random Data
Buffer is large enough for ten packets to get their IVs from a single
request. If the Random Data Buffer is not enabled, then each IV causes a
separate request, and RNG4 hardware cannot keep up resulting in lower
IPSEC throughput if random IVs are used.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r-- | drivers/crypto/caam/ctrl.c | 3 | ||||
-rw-r--r-- | drivers/crypto/caam/regs.h | 4 |
2 files changed, 6 insertions, 1 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 1c56f63524f2..19faea2c31d1 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c | |||
@@ -304,6 +304,9 @@ static int caam_probe(struct platform_device *pdev) | |||
304 | caam_remove(pdev); | 304 | caam_remove(pdev); |
305 | return ret; | 305 | return ret; |
306 | } | 306 | } |
307 | |||
308 | /* Enable RDB bit so that RNG works faster */ | ||
309 | setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE); | ||
307 | } | 310 | } |
308 | 311 | ||
309 | /* NOTE: RTIC detection ought to go here, around Si time */ | 312 | /* NOTE: RTIC detection ought to go here, around Si time */ |
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 3223fc6d647c..cd6fedad9935 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h | |||
@@ -252,7 +252,8 @@ struct caam_ctrl { | |||
252 | /* Read/Writable */ | 252 | /* Read/Writable */ |
253 | u32 rsvd1; | 253 | u32 rsvd1; |
254 | u32 mcr; /* MCFG Master Config Register */ | 254 | u32 mcr; /* MCFG Master Config Register */ |
255 | u32 rsvd2[2]; | 255 | u32 rsvd2; |
256 | u32 scfgr; /* SCFGR, Security Config Register */ | ||
256 | 257 | ||
257 | /* Bus Access Configuration Section 010-11f */ | 258 | /* Bus Access Configuration Section 010-11f */ |
258 | /* Read/Writable */ | 259 | /* Read/Writable */ |
@@ -299,6 +300,7 @@ struct caam_ctrl { | |||
299 | #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ | 300 | #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ |
300 | #define MCFGR_DMA_RESET 0x10000000 | 301 | #define MCFGR_DMA_RESET 0x10000000 |
301 | #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ | 302 | #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ |
303 | #define SCFGR_RDBENABLE 0x00000400 | ||
302 | 304 | ||
303 | /* AXI read cache control */ | 305 | /* AXI read cache control */ |
304 | #define MCFGR_ARCACHE_SHIFT 12 | 306 | #define MCFGR_ARCACHE_SHIFT 12 |