diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2012-04-20 12:01:34 -0400 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2012-04-30 07:22:54 -0400 |
commit | 575203b4747c371698dd686b1fa6d0a3a0c47ac6 (patch) | |
tree | 410c0c1ee4bbeb4db55ca822201b58def1aee4a6 | |
parent | d26ecc4894464318dce51d709e19dd9d88916bee (diff) |
x86, MCE, AMD: Disable error thresholding bank 4 on some models
Turn off MC4_MISC thresholding banks on models which have them but that
particular processor implementation does not supply applicable error
sources to be counted.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index d086a09c087d..888fbf9d0adf 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c | |||
@@ -1423,6 +1423,43 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) | |||
1423 | */ | 1423 | */ |
1424 | if (c->x86 == 6 && banks > 0) | 1424 | if (c->x86 == 6 && banks > 0) |
1425 | mce_banks[0].ctl = 0; | 1425 | mce_banks[0].ctl = 0; |
1426 | |||
1427 | /* | ||
1428 | * Turn off MC4_MISC thresholding banks on those models since | ||
1429 | * they're not supported there. | ||
1430 | */ | ||
1431 | if (c->x86 == 0x15 && | ||
1432 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | ||
1433 | int i; | ||
1434 | u64 val, hwcr; | ||
1435 | bool need_toggle; | ||
1436 | u32 msrs[] = { | ||
1437 | 0x00000413, /* MC4_MISC0 */ | ||
1438 | 0xc0000408, /* MC4_MISC1 */ | ||
1439 | }; | ||
1440 | |||
1441 | rdmsrl(MSR_K7_HWCR, hwcr); | ||
1442 | |||
1443 | /* McStatusWrEn has to be set */ | ||
1444 | need_toggle = !(hwcr & BIT(18)); | ||
1445 | |||
1446 | if (need_toggle) | ||
1447 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | ||
1448 | |||
1449 | for (i = 0; i < ARRAY_SIZE(msrs); i++) { | ||
1450 | rdmsrl(msrs[i], val); | ||
1451 | |||
1452 | /* CntP bit set? */ | ||
1453 | if (val & BIT(62)) { | ||
1454 | val &= ~BIT(62); | ||
1455 | wrmsrl(msrs[i], val); | ||
1456 | } | ||
1457 | } | ||
1458 | |||
1459 | /* restore old settings */ | ||
1460 | if (need_toggle) | ||
1461 | wrmsrl(MSR_K7_HWCR, hwcr); | ||
1462 | } | ||
1426 | } | 1463 | } |
1427 | 1464 | ||
1428 | if (c->x86_vendor == X86_VENDOR_INTEL) { | 1465 | if (c->x86_vendor == X86_VENDOR_INTEL) { |