Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Kevin Hilman:
 "Another round of fixes from arm-soc land, which are mostly DT fixes
  for:

   - OMAP: handful of DT fixes devices on newly supported hardware
   - davinci: fix 2nd EDMA channel
   - ux500: extend previous pinctrl fix to another board
   - at91: clock registration fixes, compatibility string precision

  And one more fix for event cleanup in drivers/bus/arm-ccn"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  bus: arm-ccn: Move event cleanup routine
  ARM: at91/dt: rm9200: fix usb clock definition
  ARM: at91: rm9200: fix clock registration
  ARM: at91/dt: sam9g20: set at91sam9g20 pllb driver
  ARM: dts: dra7-evm: Add vtt regulator support
  ARM: dts: dra7-evm: Fix spi1 mux documentation
  ARM: dts: am43x-epos-evm: Disable QSPI to prevent conflict with GPMC-NAND
  ARM: OMAP2+: gpmc: Don't complain if wait pin is used without r/w monitoring
  ARM: dts: am43xx-epos-evm: Don't use read/write wait monitoring
  ARM: dts: am437x-gp-evm: Don't use read/write wait monitoring
  ARM: dts: am437x-gp-evm: Use BCH16 ECC scheme instead of BCH8
  ARM: dts: am43x-epos-evm: Use BCH16 ECC scheme instead of BCH8
  ARM: dts: am4372: fix USB regs size
  ARM: dts: am437x-gp: switch i2c0 to 100KHz
  ARM: dts: dra7-evm: Fix 8th NAND partition's name
  ARM: dts: dra7-evm: Fix i2c3 pinmux and frequency
  ARM: ux500: disable msp2 node on Snowball
  ARM: edma: Fix configuration parsing for SoCs with multiple eDMA3 CC
  ARM: dts: set 'ti,set-rate-parent' for dpll4_m5x2 clock

12 files changed, 90 insertions, 59 deletions

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 9b3d2ba82f13..8689949bdba3 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -804,7 +804,7 @@
 
                         usb1: usb@48390000 {
                                 compatible = "synopsys,dwc3";
-                                reg = <0x48390000 0x17000>;
+                                reg = <0x48390000 0x10000>;
                                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
                                 phys = <&usb2_phy1>;
                                 phy-names = "usb2-phy";
@@ -826,7 +826,7 @@
 
                         usb2: usb@483d0000 {
                                 compatible = "synopsys,dwc3";
-                                reg = <0x483d0000 0x17000>;
+                                reg = <0x483d0000 0x10000>;
                                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                                 phys = <&usb2_phy2>;
                                 phy-names = "usb2-phy";
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 646a6eade788..e7ac47fa6615 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -260,7 +260,7 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&i2c0_pins>;
-        clock-frequency = <400000>;
+        clock-frequency = <100000>;
 
         tps65218: tps65218@24 {
                 reg = <0x24>;
@@ -424,7 +424,7 @@
         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
         nand@0,0 {
                 reg = <0 0 4>;          /* device IO registers */
-                ti,nand-ecc-opt = "bch8";
+                ti,nand-ecc-opt = "bch16";
                 ti,elm-id = <&elm>;
                 nand-bus-width = <8>;
                 gpmc,device-width = <1>;
@@ -443,8 +443,6 @@
                 gpmc,rd-cycle-ns = <40>;
                 gpmc,wr-cycle-ns = <40>;
                 gpmc,wait-pin = <0>;
-                gpmc,wait-on-read;
-                gpmc,wait-on-write;
                 gpmc,bus-turnaround-ns = <0>;
                 gpmc,cycle2cycle-delay-ns = <0>;
                 gpmc,clk-activation-ns = <0>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index ed7dd2395915..ac3e4859935f 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -435,13 +435,13 @@
 };
 
 &gpmc {
-        status = "okay";
+        status = "okay";        /* Disable QSPI when enabling GPMC (NAND) */
         pinctrl-names = "default";
         pinctrl-0 = <&nand_flash_x8>;
         ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
         nand@0,0 {
                 reg = <0 0 0>; /* CS0, offset 0 */
-                ti,nand-ecc-opt = "bch8";
+                ti,nand-ecc-opt = "bch16";
                 ti,elm-id = <&elm>;
                 nand-bus-width = <8>;
                 gpmc,device-width = <1>;
@@ -459,8 +459,7 @@
                 gpmc,access-ns = <30>; /* tCEA + 4*/
                 gpmc,rd-cycle-ns = <40>;
                 gpmc,wr-cycle-ns = <40>;
-                gpmc,wait-on-read = "true";
-                gpmc,wait-on-write = "true";
+                gpmc,wait-pin = <0>;
                 gpmc,bus-turnaround-ns = <0>;
                 gpmc,cycle2cycle-delay-ns = <0>;
                 gpmc,clk-activation-ns = <0>;
@@ -557,7 +556,7 @@
 };
 
 &qspi {
-        status = "okay";
+        status = "disabled";    /* Disable GPMC (NAND) when enabling QSPI */
         pinctrl-names = "default";
         pinctrl-0 = <&qspi1_default>;
 
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 65ccf564b9a5..6c97d4af61ee 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -149,7 +149,7 @@
                                 usb: usbck {
                                         compatible = "atmel,at91rm9200-clk-usb";
                                         #clock-cells = <0>;
-                                        atmel,clk-divisors = <1 2>;
+                                        atmel,clk-divisors = <1 2 0 0>;
                                         clocks = <&pllb>;
                                 };
 
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 31f7652612fc..4e0abbd9d655 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -40,6 +40,7 @@
                                 };
 
                                 pllb: pllbck {
+                                        compatible = "atmel,at91sam9g20-clk-pllb";
                                         atmel,clk-input-range = <2000000 32000000>;
                                         atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
                                 };
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022905a1..e03fbf3c6889 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "TI DRA742";
@@ -24,9 +25,29 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
         };
+
+        vtt_fixed: fixedregulator-vtt {
+                compatible = "regulator-fixed";
+                regulator-name = "vtt_fixed";
+                regulator-min-microvolt = <1350000>;
+                regulator-max-microvolt = <1350000>;
+                regulator-always-on;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+        };
 };
 
 &dra7_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <&vtt_pin>;
+
+        vtt_pin: pinmux_vtt_pin {
+                pinctrl-single,pins = <
+                        0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
+                >;
+        };
+
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
@@ -43,20 +64,19 @@
 
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
-                        0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
-                        0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
+                        0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
+                        0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
                 >;
         };
 
         mcspi1_pins: pinmux_mcspi1_pins {
                 pinctrl-single,pins = <
-                        0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
-                        0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
-                        0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
-                        0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
-                        0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
-                        0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
-                        0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
+                        0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
+                        0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
+                        0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
+                        0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
+                        0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
+                        0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
                 >;
         };
 
@@ -284,7 +304,7 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&i2c3_pins>;
-        clock-frequency = <3400000>;
+        clock-frequency = <400000>;
 };
 
 &mcspi1 {
@@ -483,7 +503,7 @@
                         reg = <0x001c0000 0x00020000>;
                 };
                 partition@7 {
-                        label = "NAND.u-boot-env";
+                        label = "NAND.u-boot-env.backup1";
                         reg = <0x001e0000 0x00020000>;
                 };
                 partition@8 {
@@ -504,3 +524,8 @@
 &usb2_phy2 {
         phy-supply = <&ldousb_reg>;
 };
+
+&gpio7 {
+        ti,no-reset-on-init;
+        ti,no-idle-on-init;
+};
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index e47ff69dcf70..5c375003bad1 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -467,6 +467,7 @@
                 ti,bit-shift = <0x1e>;
                 reg = <0x0d00>;
                 ti,set-bit-to-disable;
+                ti,set-rate-parent;
         };
 
         dpll4_m6_ck: dpll4_m6_ck {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 4a2000c620ad..3e97a669f15e 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -116,7 +116,6 @@
                 msp2: msp@80117000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&msp2_default_mode>;
-                        status = "okay";
                 };
 
                 msp3: msp@80125000 {
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 88099175fc56..d86771abbf57 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1443,14 +1443,14 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
 EXPORT_SYMBOL(edma_assign_channel_eventq);
 
 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
-                              struct edma *edma_cc)
+                              struct edma *edma_cc, int cc_id)
 {
         int i;
         u32 value, cccfg;
         s8 (*queue_priority_map)[2];
 
         /* Decode the eDMA3 configuration from CCCFG register */
-        cccfg = edma_read(0, EDMA_CCCFG);
+        cccfg = edma_read(cc_id, EDMA_CCCFG);
 
         value = GET_NUM_REGN(cccfg);
         edma_cc->num_region = BIT(value);
@@ -1464,7 +1464,8 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
         value = GET_NUM_EVQUE(cccfg);
         edma_cc->num_tc = value + 1;
 
-        dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
+        dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
+                cccfg);
         dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
         dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
         dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
@@ -1684,7 +1685,7 @@ static int edma_probe(struct platform_device *pdev)
                         return -ENOMEM;
 
                 /* Get eDMA3 configuration from IP */
-                ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
+                ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
                 if (ret)
                         return ret;
 
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3a185faee795..f4b6e91843e4 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -14,6 +14,7 @@
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/clk-provider.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -35,13 +36,21 @@ static void __init at91rm9200_dt_init_irq(void)
         of_irq_init(irq_of_match);
 }
 
+static void __init at91rm9200_dt_timer_init(void)
+{
+#if defined(CONFIG_COMMON_CLK)
+        of_clk_init(NULL);
+#endif
+        at91rm9200_timer_init();
+}
+
 static const char *at91rm9200_dt_board_compat[] __initdata = {
         "atmel,at91rm9200",
         NULL
 };
 
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
-        .init_time      = at91rm9200_timer_init,
+        .init_time      = at91rm9200_dt_timer_init,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = at91rm9200_dt_initialize,
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9f42d5437fcc..2f97228f188a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1207,8 +1207,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
                 }
         }
 
-        if ((p->wait_on_read || p->wait_on_write) &&
-            (p->wait_pin > gpmc_nr_waitpins)) {
+        if (p->wait_pin > gpmc_nr_waitpins) {
                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
                 return -EINVAL;
         }
@@ -1288,8 +1287,8 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
                 p->wait_on_write = of_property_read_bool(np,
                                                          "gpmc,wait-on-write");
                 if (!p->wait_on_read && !p->wait_on_write)
-                        pr_warn("%s: read/write wait monitoring not enabled!\n",
-                                __func__);
+                        pr_debug("%s: rd/wr wait monitoring not enabled!\n",
+                                 __func__);
         }
 }
 
diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c
index 6f550d9e7a2d..a60f26400705 100644
--- a/drivers/bus/arm-ccn.c
+++ b/drivers/bus/arm-ccn.c
@@ -586,6 +586,30 @@ static int arm_ccn_pmu_type_eq(u32 a, u32 b)
         return 0;
 }
 
+static void arm_ccn_pmu_event_destroy(struct perf_event *event)
+{
+        struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
+        struct hw_perf_event *hw = &event->hw;
+
+        if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
+                clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
+        } else {
+                struct arm_ccn_component *source =
+                                ccn->dt.pmu_counters[hw->idx].source;
+
+                if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
+                                CCN_CONFIG_EVENT(event->attr.config) ==
+                                CCN_EVENT_WATCHPOINT)
+                        clear_bit(hw->config_base, source->xp.dt_cmp_mask);
+                else
+                        clear_bit(hw->config_base, source->pmu_events_mask);
+                clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
+        }
+
+        ccn->dt.pmu_counters[hw->idx].source = NULL;
+        ccn->dt.pmu_counters[hw->idx].event = NULL;
+}
+
 static int arm_ccn_pmu_event_init(struct perf_event *event)
 {
         struct arm_ccn *ccn;
@@ -599,6 +623,7 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
                 return -ENOENT;
 
         ccn = pmu_to_arm_ccn(event->pmu);
+        event->destroy = arm_ccn_pmu_event_destroy;
 
         if (hw->sample_period) {
                 dev_warn(ccn->dev, "Sampling not supported!\n");
@@ -731,30 +756,6 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
         return 0;
 }
 
-static void arm_ccn_pmu_event_free(struct perf_event *event)
-{
-        struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
-        struct hw_perf_event *hw = &event->hw;
-
-        if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
-                clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
-        } else {
-                struct arm_ccn_component *source =
-                                ccn->dt.pmu_counters[hw->idx].source;
-
-                if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
-                                CCN_CONFIG_EVENT(event->attr.config) ==
-                                CCN_EVENT_WATCHPOINT)
-                        clear_bit(hw->config_base, source->xp.dt_cmp_mask);
-                else
-                        clear_bit(hw->config_base, source->pmu_events_mask);
-                clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
-        }
-
-        ccn->dt.pmu_counters[hw->idx].source = NULL;
-        ccn->dt.pmu_counters[hw->idx].event = NULL;
-}
-
 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
 {
         u64 res;
@@ -1027,8 +1028,6 @@ static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
 {
         arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
-
-        arm_ccn_pmu_event_free(event);
 }
 
 static void arm_ccn_pmu_event_read(struct perf_event *event)