MIPS: perf: Add hardware events for P5600

Add cases in perf_event_mipsxx.c for CPU_P5600. All the event numbers
listed for proAptiv also apply to P5600, so we use mipsxxcore_event_map2
and mipsxxcore_cache_map2 too, but the P5600 has 8-bit event numbers so
bit 8 (256) of the user ABI config is used for the parity bit (to
specify odd/even counter events).

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7242/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 21 insertions, 0 deletions

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index ef8b3d994c5a..14bf74b0f51c 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1386,6 +1386,9 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 /* proAptiv */
 #define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b)                              \
         ((b) == 0 || (b) == 1)
+/* P5600 */
+#define IS_BOTH_COUNTERS_P5600_EVENT(b)                                 \
+        ((b) == 0 || (b) == 1)
 
 /* 1004K */
 #define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
@@ -1488,6 +1491,19 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
                 raw_event.range = P;
 #endif
                 break;
+        case CPU_P5600:
+                /* 8-bit event numbers */
+                raw_id = config & 0x1ff;
+                base_id = raw_id & 0xff;
+                if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                raw_event.range = P;
+#endif
+                break;
         case CPU_1004K:
                 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
@@ -1638,6 +1654,11 @@ init_hw_perf_events(void)
                 mipspmu.general_event_map = &mipsxxcore_event_map2;
                 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
                 break;
+        case CPU_P5600:
+                mipspmu.name = "mips/P5600";
+                mipspmu.general_event_map = &mipsxxcore_event_map2;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map2;
+                break;
         case CPU_1004K:
                 mipspmu.name = "mips/1004K";
                 mipspmu.general_event_map = &mipsxxcore_event_map;