diff options
author | Stephen Boyd <sboyd@codeaurora.org> | 2013-07-18 19:21:21 -0400 |
---|---|---|
committer | John Stultz <john.stultz@linaro.org> | 2013-07-30 14:24:52 -0400 |
commit | 5602d7c808aa99230ab1ef1598e2425cf2acedc5 (patch) | |
tree | f0c230f9dc72b7be2522d14211bca78c696aff05 | |
parent | 18952f20fadef0a5e099f5c4cac34b97644ccc35 (diff) |
clocksource: dbx500-prcmu: Switch to sched_clock_register()
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
-rw-r--r-- | drivers/clocksource/clksrc-dbx500-prcmu.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index a9fd4ad25674..b375106844d8 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c | |||
@@ -53,7 +53,7 @@ static struct clocksource clocksource_dbx500_prcmu = { | |||
53 | 53 | ||
54 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | 54 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK |
55 | 55 | ||
56 | static u32 notrace dbx500_prcmu_sched_clock_read(void) | 56 | static u64 notrace dbx500_prcmu_sched_clock_read(void) |
57 | { | 57 | { |
58 | if (unlikely(!clksrc_dbx500_timer_base)) | 58 | if (unlikely(!clksrc_dbx500_timer_base)) |
59 | return 0; | 59 | return 0; |
@@ -81,8 +81,7 @@ void __init clksrc_dbx500_prcmu_init(void __iomem *base) | |||
81 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); | 81 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); |
82 | } | 82 | } |
83 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | 83 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK |
84 | setup_sched_clock(dbx500_prcmu_sched_clock_read, | 84 | sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K); |
85 | 32, RATE_32K); | ||
86 | #endif | 85 | #endif |
87 | clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); | 86 | clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); |
88 | } | 87 | } |