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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2009-11-27 13:29:02 -0500
committerJeff Garzik <jgarzik@redhat.com>2009-12-03 14:36:16 -0500
commit5600c70e576199a7552e1c0fff43f3fe16f5566e (patch)
tree811a21c65c52b1b166cc518b5200fab1d9991d73
parent8e182a90f91456335756d2ce304ad470795d98e1 (diff)
pata_hpt{37x|3x2n}: fix timing register masks (take 2)
These drivers inherited from the older 'hpt366' IDE driver the buggy timing register masks in their set_piomode() metods. As a result, too low command cycle active time is programmed for slow PIO modes. Quite fortunately, it's later "fixed up" by the set_dmamode() methods which also "helpfully" reprogram the command timings, usually to PIO mode 4; unfortunately, setting an UltraDMA mode #N also reprograms already set PIO data timings, usually to MWDMA mode # max(N, 2) timings... However, the drivers added some breakage of their own too: the bit that they set/clear to control the FIFO is sometimes wrong -- it's actually the MSB of the command cycle setup time; also, setting it in DMA mode is wrong as this bit is only for PIO actually and clearing it for PIO modes is not needed as no mode in any timing table has it set... Fix all this, inverting the masks while at it, like in the 'hpt366' and 'pata_hpt366' drivers; bump the drivers' versions, accounting for recent patches that forgot to do it... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r--drivers/ata/pata_hpt37x.c32
-rw-r--r--drivers/ata/pata_hpt3x2n.c17
2 files changed, 23 insertions, 26 deletions
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index 9f5189c700bb..defd9b8456ed 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -24,7 +24,7 @@
24#include <linux/libata.h> 24#include <linux/libata.h>
25 25
26#define DRV_NAME "pata_hpt37x" 26#define DRV_NAME "pata_hpt37x"
27#define DRV_VERSION "0.6.12" 27#define DRV_VERSION "0.6.14"
28 28
29struct hpt_clock { 29struct hpt_clock {
30 u8 xfer_speed; 30 u8 xfer_speed;
@@ -411,9 +411,8 @@ static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
411 411
412 pci_read_config_dword(pdev, addr1, &reg); 412 pci_read_config_dword(pdev, addr1, &reg);
413 mode = hpt37x_find_mode(ap, adev->pio_mode); 413 mode = hpt37x_find_mode(ap, adev->pio_mode);
414 mode &= ~0x8000000; /* No FIFO in PIO */ 414 mode &= 0xCFC3FFFF; /* Leave DMA bits alone */
415 mode &= ~0x30070000; /* Leave config bits alone */ 415 reg &= ~0xCFC3FFFF; /* Strip timing bits */
416 reg &= 0x30070000; /* Strip timing bits */
417 pci_write_config_dword(pdev, addr1, reg | mode); 416 pci_write_config_dword(pdev, addr1, reg | mode);
418} 417}
419 418
@@ -430,8 +429,7 @@ static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
430{ 429{
431 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 430 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
432 u32 addr1, addr2; 431 u32 addr1, addr2;
433 u32 reg; 432 u32 reg, mode, mask;
434 u32 mode;
435 u8 fast; 433 u8 fast;
436 434
437 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 435 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
@@ -443,11 +441,12 @@ static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
443 fast |= 0x01; 441 fast |= 0x01;
444 pci_write_config_byte(pdev, addr2, fast); 442 pci_write_config_byte(pdev, addr2, fast);
445 443
444 mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
445
446 pci_read_config_dword(pdev, addr1, &reg); 446 pci_read_config_dword(pdev, addr1, &reg);
447 mode = hpt37x_find_mode(ap, adev->dma_mode); 447 mode = hpt37x_find_mode(ap, adev->dma_mode);
448 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ 448 mode &= mask;
449 mode &= ~0xC0000000; /* Leave config bits alone */ 449 reg &= ~mask;
450 reg &= 0xC0000000; /* Strip timing bits */
451 pci_write_config_dword(pdev, addr1, reg | mode); 450 pci_write_config_dword(pdev, addr1, reg | mode);
452} 451}
453 452
@@ -515,9 +514,8 @@ static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
515 mode = hpt37x_find_mode(ap, adev->pio_mode); 514 mode = hpt37x_find_mode(ap, adev->pio_mode);
516 515
517 printk("Find mode for %d reports %X\n", adev->pio_mode, mode); 516 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
518 mode &= ~0x80000000; /* No FIFO in PIO */ 517 mode &= 0xCFC3FFFF; /* Leave DMA bits alone */
519 mode &= ~0x30070000; /* Leave config bits alone */ 518 reg &= ~0xCFC3FFFF; /* Strip timing bits */
520 reg &= 0x30070000; /* Strip timing bits */
521 pci_write_config_dword(pdev, addr1, reg | mode); 519 pci_write_config_dword(pdev, addr1, reg | mode);
522} 520}
523 521
@@ -534,8 +532,7 @@ static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
534{ 532{
535 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 533 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
536 u32 addr1, addr2; 534 u32 addr1, addr2;
537 u32 reg; 535 u32 reg, mode, mask;
538 u32 mode;
539 u8 fast; 536 u8 fast;
540 537
541 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 538 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
@@ -546,12 +543,13 @@ static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
546 fast &= ~0x07; 543 fast &= ~0x07;
547 pci_write_config_byte(pdev, addr2, fast); 544 pci_write_config_byte(pdev, addr2, fast);
548 545
546 mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
547
549 pci_read_config_dword(pdev, addr1, &reg); 548 pci_read_config_dword(pdev, addr1, &reg);
550 mode = hpt37x_find_mode(ap, adev->dma_mode); 549 mode = hpt37x_find_mode(ap, adev->dma_mode);
551 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode); 550 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
552 mode &= ~0xC0000000; /* Leave config bits alone */ 551 mode &= mask;
553 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */ 552 reg &= ~mask;
554 reg &= 0xC0000000; /* Strip timing bits */
555 pci_write_config_dword(pdev, addr1, reg | mode); 553 pci_write_config_dword(pdev, addr1, reg | mode);
556} 554}
557 555
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index 8d63eba782ff..26f50af0ad89 100644
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -25,7 +25,7 @@
25#include <linux/libata.h> 25#include <linux/libata.h>
26 26
27#define DRV_NAME "pata_hpt3x2n" 27#define DRV_NAME "pata_hpt3x2n"
28#define DRV_VERSION "0.3.4" 28#define DRV_VERSION "0.3.7"
29 29
30enum { 30enum {
31 HPT_PCI_FAST = (1 << 31), 31 HPT_PCI_FAST = (1 << 31),
@@ -188,9 +188,8 @@ static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
188 188
189 pci_read_config_dword(pdev, addr1, &reg); 189 pci_read_config_dword(pdev, addr1, &reg);
190 mode = hpt3x2n_find_mode(ap, adev->pio_mode); 190 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
191 mode &= ~0x8000000; /* No FIFO in PIO */ 191 mode &= 0xCFC3FFFF; /* Leave DMA bits alone */
192 mode &= ~0x30070000; /* Leave config bits alone */ 192 reg &= ~0xCFC3FFFF; /* Strip timing bits */
193 reg &= 0x30070000; /* Strip timing bits */
194 pci_write_config_dword(pdev, addr1, reg | mode); 193 pci_write_config_dword(pdev, addr1, reg | mode);
195} 194}
196 195
@@ -207,8 +206,7 @@ static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
207{ 206{
208 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 207 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
209 u32 addr1, addr2; 208 u32 addr1, addr2;
210 u32 reg; 209 u32 reg, mode, mask;
211 u32 mode;
212 u8 fast; 210 u8 fast;
213 211
214 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 212 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
@@ -219,11 +217,12 @@ static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
219 fast &= ~0x07; 217 fast &= ~0x07;
220 pci_write_config_byte(pdev, addr2, fast); 218 pci_write_config_byte(pdev, addr2, fast);
221 219
220 mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
221
222 pci_read_config_dword(pdev, addr1, &reg); 222 pci_read_config_dword(pdev, addr1, &reg);
223 mode = hpt3x2n_find_mode(ap, adev->dma_mode); 223 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
224 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ 224 mode &= mask;
225 mode &= ~0xC0000000; /* Leave config bits alone */ 225 reg &= ~mask;
226 reg &= 0xC0000000; /* Strip timing bits */
227 pci_write_config_dword(pdev, addr1, reg | mode); 226 pci_write_config_dword(pdev, addr1, reg | mode);
228} 227}
229 228