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authorThomas Abraham <thomas.abraham@linaro.org>2012-10-29 06:46:49 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-10-29 06:48:54 -0400
commit55b6ef7a7dad269f4438404cc63ba4718c4f8805 (patch)
tree779660280e5092c5acd36eb81bfcb8d32008fc09
parentfe267b8781981e70bbf233c3483387409785fae1 (diff)
ARM: EXYNOS: Remove unused static uart resource information
All supported EXYNOS5 platforms are device tree enabled and hence the unused static uart resource information is removed. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> [kgene.kim@samsung.com: changed to exynos4_init_uarts() clearly] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--arch/arm/mach-exynos/common.c16
-rw-r--r--arch/arm/mach-exynos/dev-uart.c24
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h1
4 files changed, 6 insertions, 40 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index bb9f98b161a1..0e8436176e3b 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -62,7 +62,7 @@ static void exynos4_map_io(void);
62static void exynos5_map_io(void); 62static void exynos5_map_io(void);
63static void exynos4_init_clocks(int xtal); 63static void exynos4_init_clocks(int xtal);
64static void exynos5_init_clocks(int xtal); 64static void exynos5_init_clocks(int xtal);
65static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no); 65static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
66static int exynos_init(void); 66static int exynos_init(void);
67 67
68static struct cpu_table cpu_ids[] __initdata = { 68static struct cpu_table cpu_ids[] __initdata = {
@@ -71,7 +71,7 @@ static struct cpu_table cpu_ids[] __initdata = {
71 .idmask = EXYNOS4_CPU_MASK, 71 .idmask = EXYNOS4_CPU_MASK,
72 .map_io = exynos4_map_io, 72 .map_io = exynos4_map_io,
73 .init_clocks = exynos4_init_clocks, 73 .init_clocks = exynos4_init_clocks,
74 .init_uarts = exynos_init_uarts, 74 .init_uarts = exynos4_init_uarts,
75 .init = exynos_init, 75 .init = exynos_init,
76 .name = name_exynos4210, 76 .name = name_exynos4210,
77 }, { 77 }, {
@@ -79,7 +79,7 @@ static struct cpu_table cpu_ids[] __initdata = {
79 .idmask = EXYNOS4_CPU_MASK, 79 .idmask = EXYNOS4_CPU_MASK,
80 .map_io = exynos4_map_io, 80 .map_io = exynos4_map_io,
81 .init_clocks = exynos4_init_clocks, 81 .init_clocks = exynos4_init_clocks,
82 .init_uarts = exynos_init_uarts, 82 .init_uarts = exynos4_init_uarts,
83 .init = exynos_init, 83 .init = exynos_init,
84 .name = name_exynos4212, 84 .name = name_exynos4212,
85 }, { 85 }, {
@@ -87,7 +87,7 @@ static struct cpu_table cpu_ids[] __initdata = {
87 .idmask = EXYNOS4_CPU_MASK, 87 .idmask = EXYNOS4_CPU_MASK,
88 .map_io = exynos4_map_io, 88 .map_io = exynos4_map_io,
89 .init_clocks = exynos4_init_clocks, 89 .init_clocks = exynos4_init_clocks,
90 .init_uarts = exynos_init_uarts, 90 .init_uarts = exynos4_init_uarts,
91 .init = exynos_init, 91 .init = exynos_init,
92 .name = name_exynos4412, 92 .name = name_exynos4412,
93 }, { 93 }, {
@@ -95,7 +95,6 @@ static struct cpu_table cpu_ids[] __initdata = {
95 .idmask = EXYNOS5_SOC_MASK, 95 .idmask = EXYNOS5_SOC_MASK,
96 .map_io = exynos5_map_io, 96 .map_io = exynos5_map_io,
97 .init_clocks = exynos5_init_clocks, 97 .init_clocks = exynos5_init_clocks,
98 .init_uarts = exynos_init_uarts,
99 .init = exynos_init, 98 .init = exynos_init,
100 .name = name_exynos5250, 99 .name = name_exynos5250,
101 }, 100 },
@@ -707,7 +706,7 @@ static int __init exynos_init(void)
707 706
708/* uart registration process */ 707/* uart registration process */
709 708
710static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no) 709static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
711{ 710{
712 struct s3c2410_uartcfg *tcfg = cfg; 711 struct s3c2410_uartcfg *tcfg = cfg;
713 u32 ucnt; 712 u32 ucnt;
@@ -715,10 +714,7 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
715 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) 714 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
716 tcfg->has_fracval = 1; 715 tcfg->has_fracval = 1;
717 716
718 if (soc_is_exynos5250()) 717 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
719 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
720 else
721 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
722} 718}
723 719
724static void __iomem *exynos_eint_base; 720static void __iomem *exynos_eint_base;
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
index 2e85c022fd16..7c42f4b7c8be 100644
--- a/arch/arm/mach-exynos/dev-uart.c
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -52,27 +52,3 @@ struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
52 .nr_resources = ARRAY_SIZE(exynos4_uart3_resource), 52 .nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
53 }, 53 },
54}; 54};
55
56EXYNOS_UART_RESOURCE(5, 0)
57EXYNOS_UART_RESOURCE(5, 1)
58EXYNOS_UART_RESOURCE(5, 2)
59EXYNOS_UART_RESOURCE(5, 3)
60
61struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
62 [0] = {
63 .resources = exynos5_uart0_resource,
64 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
65 },
66 [1] = {
67 .resources = exynos5_uart1_resource,
68 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
69 },
70 [2] = {
71 .resources = exynos5_uart2_resource,
72 .nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
73 },
74 [3] = {
75 .resources = exynos5_uart3_resource,
76 .nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
77 },
78};
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6f9092..6da31152de3a 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -259,11 +259,6 @@
259#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48) 259#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
260#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49) 260#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
261#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50) 261#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
262#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
263#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
264#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
265#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
266#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
267#define EXYNOS5_IRQ_IIC IRQ_SPI(56) 262#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
268#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57) 263#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
269#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58) 264#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675b3e4b..151b4a4a1c3c 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -271,7 +271,6 @@
271#define EXYNOS5_PA_UART1 0x12C10000 271#define EXYNOS5_PA_UART1 0x12C10000
272#define EXYNOS5_PA_UART2 0x12C20000 272#define EXYNOS5_PA_UART2 0x12C20000
273#define EXYNOS5_PA_UART3 0x12C30000 273#define EXYNOS5_PA_UART3 0x12C30000
274#define EXYNOS5_SZ_UART SZ_256
275 274
276#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 275#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
277 276