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authorDavid S. Miller <davem@davemloft.net>2014-06-21 17:59:54 -0400
committerDavid S. Miller <davem@davemloft.net>2014-06-21 17:59:54 -0400
commit545a112bb3dcf8e4574fc985f07bf7ea03a7f809 (patch)
tree2350153f7d83fe7fa015a35d59b6e2d0fc426130
parent88729dd18995a87f0f8fe0423518b171a877d7b6 (diff)
parent7974d5e5ed88f4214b0d931e96040e45d2db1e88 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next
Jeff Kirsher says: ==================== Intel Wired LAN Driver Updates 2014-06-20 This series contains updates to i40e and i40evf. Anjali provides an update to the registers to handle the updates from the hardware. Also provides a fix so that we do not try to access the rings through the qvectors at the time of freeing the qvectors. Jesse provides a workaround for some older NVM versions where the NVM was not filling in the GLQF_HKEY register, so made sure that the critical register is initialized. Michal provides a fix to reset the head and tail on admin queue initialization where head and tail are not reset by the hardware. Neerav adds a helper routine that would wait for the Rx/Tx queue to reach the enable or disable state that is requested. Also provides a fix to the debugfs command "lldp get remote" which was dumping the local LLDPDU instead of the peer's LLDPDU. Fixed a bug when all the Tx hang recovery mechanisms have failed and the driver tries to bring down the interface in the interrupt context. Shannon provides a patch to clear the Virtual Ethernet Bridge (VEB) stats when the PF stats are cleared. Also cleans the service tasks so that they do not run while a reset is in progress. Mitch fixes an issue in i40evf_get_rxfh() where only fifteen registers were being read instead of all sixteen. Carolyn provides a change to the RSS configuration to set table size and write to the hardware to confirm the RSS table size being used. Kamil makes a change to the admin queue debug prints so that they will not cause segmentation faults in some of our tool applications. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e.h3
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_adminq.c36
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_common.c7
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_debugfs.c2
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_main.c209
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_register.h5011
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_type.h6
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40e_adminq.c36
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40e_register.h5011
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40e_type.h6
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c4
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40evf_main.c2
12 files changed, 3954 insertions, 6379 deletions
diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h
index 65985846345d..817e179dc3f9 100644
--- a/drivers/net/ethernet/intel/i40e/i40e.h
+++ b/drivers/net/ethernet/intel/i40e/i40e.h
@@ -84,6 +84,7 @@
84#define I40E_AQ_WORK_LIMIT 16 84#define I40E_AQ_WORK_LIMIT 16
85#define I40E_MAX_USER_PRIORITY 8 85#define I40E_MAX_USER_PRIORITY 8
86#define I40E_DEFAULT_MSG_ENABLE 4 86#define I40E_DEFAULT_MSG_ENABLE 4
87#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
87 88
88#define I40E_NVM_VERSION_LO_SHIFT 0 89#define I40E_NVM_VERSION_LO_SHIFT 0
89#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 90#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
@@ -134,6 +135,7 @@ enum i40e_state_t {
134 __I40E_FILTER_OVERFLOW_PROMISC, 135 __I40E_FILTER_OVERFLOW_PROMISC,
135 __I40E_SUSPENDED, 136 __I40E_SUSPENDED,
136 __I40E_BAD_EEPROM, 137 __I40E_BAD_EEPROM,
138 __I40E_DOWN_REQUESTED,
137}; 139};
138 140
139enum i40e_interrupt_policy { 141enum i40e_interrupt_policy {
@@ -348,6 +350,7 @@ struct i40e_pf {
348 u32 rx_hwtstamp_cleared; 350 u32 rx_hwtstamp_cleared;
349 bool ptp_tx; 351 bool ptp_tx;
350 bool ptp_rx; 352 bool ptp_rx;
353 u16 rss_table_size;
351}; 354};
352 355
353struct i40e_mac_filter { 356struct i40e_mac_filter {
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
index 7a027499fc57..95aab708a88d 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
@@ -296,6 +296,10 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
296 i40e_status ret_code = 0; 296 i40e_status ret_code = 0;
297 u32 reg = 0; 297 u32 reg = 0;
298 298
299 /* Clear Head and Tail */
300 wr32(hw, hw->aq.asq.head, 0);
301 wr32(hw, hw->aq.asq.tail, 0);
302
299 if (hw->mac.type == I40E_MAC_VF) { 303 if (hw->mac.type == I40E_MAC_VF) {
300 /* configure the transmit queue */ 304 /* configure the transmit queue */
301 wr32(hw, I40E_VF_ATQBAH1, 305 wr32(hw, I40E_VF_ATQBAH1,
@@ -334,6 +338,10 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
334 i40e_status ret_code = 0; 338 i40e_status ret_code = 0;
335 u32 reg = 0; 339 u32 reg = 0;
336 340
341 /* Clear Head and Tail */
342 wr32(hw, hw->aq.arq.head, 0);
343 wr32(hw, hw->aq.arq.tail, 0);
344
337 if (hw->mac.type == I40E_MAC_VF) { 345 if (hw->mac.type == I40E_MAC_VF) {
338 /* configure the receive queue */ 346 /* configure the receive queue */
339 wr32(hw, I40E_VF_ARQBAH1, 347 wr32(hw, I40E_VF_ARQBAH1,
@@ -677,6 +685,10 @@ static u16 i40e_clean_asq(struct i40e_hw *hw)
677 desc = I40E_ADMINQ_DESC(*asq, ntc); 685 desc = I40E_ADMINQ_DESC(*asq, ntc);
678 details = I40E_ADMINQ_DETAILS(*asq, ntc); 686 details = I40E_ADMINQ_DETAILS(*asq, ntc);
679 while (rd32(hw, hw->aq.asq.head) != ntc) { 687 while (rd32(hw, hw->aq.asq.head) != ntc) {
688 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
689 "%s: ntc %d head %d.\n", __func__, ntc,
690 rd32(hw, hw->aq.asq.head));
691
680 if (details->callback) { 692 if (details->callback) {
681 I40E_ADMINQ_CALLBACK cb_func = 693 I40E_ADMINQ_CALLBACK cb_func =
682 (I40E_ADMINQ_CALLBACK)details->callback; 694 (I40E_ADMINQ_CALLBACK)details->callback;
@@ -736,6 +748,15 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
736 struct i40e_aq_desc *desc_on_ring; 748 struct i40e_aq_desc *desc_on_ring;
737 bool cmd_completed = false; 749 bool cmd_completed = false;
738 u16 retval = 0; 750 u16 retval = 0;
751 u32 val = 0;
752
753 val = rd32(hw, hw->aq.asq.head);
754 if (val >= hw->aq.num_asq_entries) {
755 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
756 "AQTX: head overrun at %d\n", val);
757 status = I40E_ERR_QUEUE_EMPTY;
758 goto asq_send_command_exit;
759 }
739 760
740 if (hw->aq.asq.count == 0) { 761 if (hw->aq.asq.count == 0) {
741 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 762 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
@@ -829,6 +850,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
829 } 850 }
830 851
831 /* bump the tail */ 852 /* bump the tail */
853 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
832 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff); 854 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
833 (hw->aq.asq.next_to_use)++; 855 (hw->aq.asq.next_to_use)++;
834 if (hw->aq.asq.next_to_use == hw->aq.asq.count) 856 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
@@ -866,6 +888,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
866 I40E_DEBUG_AQ_MESSAGE, 888 I40E_DEBUG_AQ_MESSAGE,
867 "AQTX: Command completed with error 0x%X.\n", 889 "AQTX: Command completed with error 0x%X.\n",
868 retval); 890 retval);
891
869 /* strip off FW internal code */ 892 /* strip off FW internal code */
870 retval &= 0xff; 893 retval &= 0xff;
871 } 894 }
@@ -880,6 +903,12 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
880 if (i40e_is_nvm_update_op(desc)) 903 if (i40e_is_nvm_update_op(desc))
881 hw->aq.nvm_busy = true; 904 hw->aq.nvm_busy = true;
882 905
906 if (le16_to_cpu(desc->datalen) == buff_size) {
907 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
908 "AQTX: desc and buffer writeback:\n");
909 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
910 }
911
883 /* update the error if time out occurred */ 912 /* update the error if time out occurred */
884 if ((!cmd_completed) && 913 if ((!cmd_completed) &&
885 (!details->async && !details->postpone)) { 914 (!details->async && !details->postpone)) {
@@ -951,10 +980,6 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
951 /* now clean the next descriptor */ 980 /* now clean the next descriptor */
952 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); 981 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
953 desc_idx = ntc; 982 desc_idx = ntc;
954 i40e_debug_aq(hw,
955 I40E_DEBUG_AQ_COMMAND,
956 (void *)desc,
957 hw->aq.arq.r.arq_bi[desc_idx].va);
958 983
959 flags = le16_to_cpu(desc->flags); 984 flags = le16_to_cpu(desc->flags);
960 if (flags & I40E_AQ_FLAG_ERR) { 985 if (flags & I40E_AQ_FLAG_ERR) {
@@ -977,6 +1002,9 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
977 if (i40e_is_nvm_update_op(&e->desc)) 1002 if (i40e_is_nvm_update_op(&e->desc))
978 hw->aq.nvm_busy = false; 1003 hw->aq.nvm_busy = false;
979 1004
1005 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
1006 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
1007
980 /* Restore the original datalen and buffer address in the desc, 1008 /* Restore the original datalen and buffer address in the desc,
981 * FW updates datalen to indicate the event message 1009 * FW updates datalen to indicate the event message
982 * size 1010 * size
diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
index 6e65f19dd6e5..a51bba634718 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_common.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
@@ -1839,7 +1839,6 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1839 struct i40e_aqc_list_capabilities_element_resp *cap; 1839 struct i40e_aqc_list_capabilities_element_resp *cap;
1840 u32 number, logical_id, phys_id; 1840 u32 number, logical_id, phys_id;
1841 struct i40e_hw_capabilities *p; 1841 struct i40e_hw_capabilities *p;
1842 u32 reg_val;
1843 u32 i = 0; 1842 u32 i = 0;
1844 u16 id; 1843 u16 id;
1845 1844
@@ -1910,11 +1909,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1910 break; 1909 break;
1911 case I40E_DEV_FUNC_CAP_RSS: 1910 case I40E_DEV_FUNC_CAP_RSS:
1912 p->rss = true; 1911 p->rss = true;
1913 reg_val = rd32(hw, I40E_PFQF_CTL_0); 1912 p->rss_table_size = number;
1914 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1915 p->rss_table_size = number;
1916 else
1917 p->rss_table_size = 128;
1918 p->rss_table_entry_width = logical_id; 1913 p->rss_table_entry_width = logical_id;
1919 break; 1914 break;
1920 case I40E_DEV_FUNC_CAP_RX_QUEUES: 1915 case I40E_DEV_FUNC_CAP_RX_QUEUES:
diff --git a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c
index cffdfc21290f..910b01b90cdc 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c
@@ -1830,7 +1830,7 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
1830 1830
1831 ret = i40e_aq_get_lldp_mib(&pf->hw, 1831 ret = i40e_aq_get_lldp_mib(&pf->hw,
1832 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, 1832 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
1833 I40E_AQ_LLDP_MIB_LOCAL, 1833 I40E_AQ_LLDP_MIB_REMOTE,
1834 buff, I40E_LLDPDU_SIZE, 1834 buff, I40E_LLDPDU_SIZE,
1835 &llen, &rlen, NULL); 1835 &llen, &rlen, NULL);
1836 if (ret) { 1836 if (ret) {
diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 275ca9a1719e..b167fc2c4abe 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -39,7 +39,7 @@ static const char i40e_driver_string[] =
39 39
40#define DRV_VERSION_MAJOR 0 40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 4 41#define DRV_VERSION_MINOR 4
42#define DRV_VERSION_BUILD 10 42#define DRV_VERSION_BUILD 13
43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \ 44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN 45 __stringify(DRV_VERSION_BUILD) DRV_KERN
@@ -304,8 +304,8 @@ static void i40e_tx_timeout(struct net_device *netdev)
304 break; 304 break;
305 default: 305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); 306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
307 set_bit(__I40E_DOWN, &vsi->state); 307 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
308 i40e_down(vsi); 308 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
309 break; 309 break;
310 } 310 }
311 i40e_service_event_schedule(pf); 311 i40e_service_event_schedule(pf);
@@ -444,9 +444,21 @@ void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
444 **/ 444 **/
445void i40e_pf_reset_stats(struct i40e_pf *pf) 445void i40e_pf_reset_stats(struct i40e_pf *pf)
446{ 446{
447 int i;
448
447 memset(&pf->stats, 0, sizeof(pf->stats)); 449 memset(&pf->stats, 0, sizeof(pf->stats));
448 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); 450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
449 pf->stat_offsets_loaded = false; 451 pf->stat_offsets_loaded = false;
452
453 for (i = 0; i < I40E_MAX_VEB; i++) {
454 if (pf->veb[i]) {
455 memset(&pf->veb[i]->stats, 0,
456 sizeof(pf->veb[i]->stats));
457 memset(&pf->veb[i]->stats_offsets, 0,
458 sizeof(pf->veb[i]->stats_offsets));
459 pf->veb[i]->stat_offsets_loaded = false;
460 }
461 }
450} 462}
451 463
452/** 464/**
@@ -3151,8 +3163,12 @@ static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3151 3163
3152 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to 3164 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3153 * group them so there are multiple queues per vector. 3165 * group them so there are multiple queues per vector.
3166 * It is also important to go through all the vectors available to be
3167 * sure that if we don't use all the vectors, that the remaining vectors
3168 * are cleared. This is especially important when decreasing the
3169 * number of queues in use.
3154 */ 3170 */
3155 for (; v_start < q_vectors && qp_remaining; v_start++) { 3171 for (; v_start < q_vectors; v_start++) {
3156 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; 3172 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3157 3173
3158 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); 3174 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
@@ -3228,6 +3244,35 @@ static void i40e_netpoll(struct net_device *netdev)
3228#endif 3244#endif
3229 3245
3230/** 3246/**
3247 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3248 * @pf: the PF being configured
3249 * @pf_q: the PF queue
3250 * @enable: enable or disable state of the queue
3251 *
3252 * This routine will wait for the given Tx queue of the PF to reach the
3253 * enabled or disabled state.
3254 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3255 * multiple retries; else will return 0 in case of success.
3256 **/
3257static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3258{
3259 int i;
3260 u32 tx_reg;
3261
3262 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3263 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3264 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3265 break;
3266
3267 udelay(10);
3268 }
3269 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3270 return -ETIMEDOUT;
3271
3272 return 0;
3273}
3274
3275/**
3231 * i40e_vsi_control_tx - Start or stop a VSI's rings 3276 * i40e_vsi_control_tx - Start or stop a VSI's rings
3232 * @vsi: the VSI being configured 3277 * @vsi: the VSI being configured
3233 * @enable: start or stop the rings 3278 * @enable: start or stop the rings
@@ -3236,7 +3281,7 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3236{ 3281{
3237 struct i40e_pf *pf = vsi->back; 3282 struct i40e_pf *pf = vsi->back;
3238 struct i40e_hw *hw = &pf->hw; 3283 struct i40e_hw *hw = &pf->hw;
3239 int i, j, pf_q; 3284 int i, j, pf_q, ret = 0;
3240 u32 tx_reg; 3285 u32 tx_reg;
3241 3286
3242 pf_q = vsi->base_queue; 3287 pf_q = vsi->base_queue;
@@ -3269,22 +3314,46 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3269 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); 3314 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3270 3315
3271 /* wait for the change to finish */ 3316 /* wait for the change to finish */
3272 for (j = 0; j < 10; j++) { 3317 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3273 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); 3318 if (ret) {
3274 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3319 dev_info(&pf->pdev->dev,
3275 break; 3320 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3276 3321 __func__, vsi->seid, pf_q,
3277 udelay(10); 3322 (enable ? "en" : "dis"));
3278 } 3323 break;
3279 if (j >= 10) {
3280 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3281 pf_q, (enable ? "en" : "dis"));
3282 return -ETIMEDOUT;
3283 } 3324 }
3284 } 3325 }
3285 3326
3286 if (hw->revision_id == 0) 3327 if (hw->revision_id == 0)
3287 mdelay(50); 3328 mdelay(50);
3329 return ret;
3330}
3331
3332/**
3333 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3334 * @pf: the PF being configured
3335 * @pf_q: the PF queue
3336 * @enable: enable or disable state of the queue
3337 *
3338 * This routine will wait for the given Rx queue of the PF to reach the
3339 * enabled or disabled state.
3340 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3341 * multiple retries; else will return 0 in case of success.
3342 **/
3343static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3344{
3345 int i;
3346 u32 rx_reg;
3347
3348 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3349 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3350 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3351 break;
3352
3353 udelay(10);
3354 }
3355 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3356 return -ETIMEDOUT;
3288 3357
3289 return 0; 3358 return 0;
3290} 3359}
@@ -3298,7 +3367,7 @@ static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3298{ 3367{
3299 struct i40e_pf *pf = vsi->back; 3368 struct i40e_pf *pf = vsi->back;
3300 struct i40e_hw *hw = &pf->hw; 3369 struct i40e_hw *hw = &pf->hw;
3301 int i, j, pf_q; 3370 int i, j, pf_q, ret = 0;
3302 u32 rx_reg; 3371 u32 rx_reg;
3303 3372
3304 pf_q = vsi->base_queue; 3373 pf_q = vsi->base_queue;
@@ -3323,22 +3392,17 @@ static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3323 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); 3392 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3324 3393
3325 /* wait for the change to finish */ 3394 /* wait for the change to finish */
3326 for (j = 0; j < 10; j++) { 3395 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3327 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); 3396 if (ret) {
3328 3397 dev_info(&pf->pdev->dev,
3329 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3398 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3330 break; 3399 __func__, vsi->seid, pf_q,
3331 3400 (enable ? "en" : "dis"));
3332 udelay(10); 3401 break;
3333 }
3334 if (j >= 10) {
3335 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3336 pf_q, (enable ? "en" : "dis"));
3337 return -ETIMEDOUT;
3338 } 3402 }
3339 } 3403 }
3340 3404
3341 return 0; 3405 return ret;
3342} 3406}
3343 3407
3344/** 3408/**
@@ -4640,6 +4704,23 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4640 4704
4641 /* no further action needed, so return now */ 4705 /* no further action needed, so return now */
4642 return; 4706 return;
4707 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4708 int v;
4709
4710 /* Find the VSI(s) that needs to be brought down */
4711 dev_info(&pf->pdev->dev, "VSI down requested\n");
4712 for (v = 0; v < pf->num_alloc_vsi; v++) {
4713 struct i40e_vsi *vsi = pf->vsi[v];
4714 if (vsi != NULL &&
4715 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4716 set_bit(__I40E_DOWN, &vsi->state);
4717 i40e_down(vsi);
4718 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4719 }
4720 }
4721
4722 /* no further action needed, so return now */
4723 return;
4643 } else { 4724 } else {
4644 dev_info(&pf->pdev->dev, 4725 dev_info(&pf->pdev->dev,
4645 "bad reset request 0x%08x\n", reset_flags); 4726 "bad reset request 0x%08x\n", reset_flags);
@@ -5110,6 +5191,10 @@ static void i40e_reset_subtask(struct i40e_pf *pf)
5110 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED); 5191 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5111 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state); 5192 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5112 } 5193 }
5194 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5195 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5196 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5197 }
5113 5198
5114 /* If there's a recovery already waiting, it takes 5199 /* If there's a recovery already waiting, it takes
5115 * precedence before starting a new reset sequence. 5200 * precedence before starting a new reset sequence.
@@ -5463,6 +5548,20 @@ static void i40e_fdir_sb_setup(struct i40e_pf *pf)
5463 struct i40e_vsi *vsi; 5548 struct i40e_vsi *vsi;
5464 int i; 5549 int i;
5465 5550
5551 /* quick workaround for an NVM issue that leaves a critical register
5552 * uninitialized
5553 */
5554 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5555 static const u32 hkey[] = {
5556 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5557 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5558 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5559 0x95b3a76d};
5560
5561 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5562 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5563 }
5564
5466 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) 5565 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
5467 return; 5566 return;
5468 5567
@@ -5744,26 +5843,28 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)
5744 /* find what triggered the MDD event */ 5843 /* find what triggered the MDD event */
5745 reg = rd32(hw, I40E_GL_MDET_TX); 5844 reg = rd32(hw, I40E_GL_MDET_TX);
5746 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 5845 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5747 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK) 5846 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
5748 >> I40E_GL_MDET_TX_FUNCTION_SHIFT; 5847 I40E_GL_MDET_TX_PF_NUM_SHIFT;
5749 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) 5848 u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
5750 >> I40E_GL_MDET_TX_EVENT_SHIFT; 5849 I40E_GL_MDET_TX_VF_NUM_SHIFT;
5751 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) 5850 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) >>
5752 >> I40E_GL_MDET_TX_QUEUE_SHIFT; 5851 I40E_GL_MDET_TX_EVENT_SHIFT;
5852 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
5853 I40E_GL_MDET_TX_QUEUE_SHIFT;
5753 dev_info(&pf->pdev->dev, 5854 dev_info(&pf->pdev->dev,
5754 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n", 5855 "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
5755 event, queue, func); 5856 event, queue, pf_num, vf_num);
5756 wr32(hw, I40E_GL_MDET_TX, 0xffffffff); 5857 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5757 mdd_detected = true; 5858 mdd_detected = true;
5758 } 5859 }
5759 reg = rd32(hw, I40E_GL_MDET_RX); 5860 reg = rd32(hw, I40E_GL_MDET_RX);
5760 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 5861 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5761 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) 5862 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
5762 >> I40E_GL_MDET_RX_FUNCTION_SHIFT; 5863 I40E_GL_MDET_RX_FUNCTION_SHIFT;
5763 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) 5864 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) >>
5764 >> I40E_GL_MDET_RX_EVENT_SHIFT; 5865 I40E_GL_MDET_RX_EVENT_SHIFT;
5765 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) 5866 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
5766 >> I40E_GL_MDET_RX_QUEUE_SHIFT; 5867 I40E_GL_MDET_RX_QUEUE_SHIFT;
5767 dev_info(&pf->pdev->dev, 5868 dev_info(&pf->pdev->dev,
5768 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", 5869 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
5769 event, queue, func); 5870 event, queue, func);
@@ -5860,6 +5961,12 @@ static void i40e_service_task(struct work_struct *work)
5860 service_task); 5961 service_task);
5861 unsigned long start_time = jiffies; 5962 unsigned long start_time = jiffies;
5862 5963
5964 /* don't bother with service tasks if a reset is in progress */
5965 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5966 i40e_service_event_complete(pf);
5967 return;
5968 }
5969
5863 i40e_reset_subtask(pf); 5970 i40e_reset_subtask(pf);
5864 i40e_handle_mdd_event(pf); 5971 i40e_handle_mdd_event(pf);
5865 i40e_vc_process_vflr_event(pf); 5972 i40e_vc_process_vflr_event(pf);
@@ -6492,6 +6599,7 @@ static int i40e_config_rss(struct i40e_pf *pf)
6492 u32 lut = 0; 6599 u32 lut = 0;
6493 int i, j; 6600 int i, j;
6494 u64 hena; 6601 u64 hena;
6602 u32 reg_val;
6495 6603
6496 /* Fill out hash function seed */ 6604 /* Fill out hash function seed */
6497 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) 6605 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
@@ -6504,8 +6612,19 @@ static int i40e_config_rss(struct i40e_pf *pf)
6504 wr32(hw, I40E_PFQF_HENA(0), (u32)hena); 6612 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6505 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); 6613 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6506 6614
6615 /* Check capability and Set table size and register per hw expectation*/
6616 reg_val = rd32(hw, I40E_PFQF_CTL_0);
6617 if (hw->func_caps.rss_table_size == 512) {
6618 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6619 pf->rss_table_size = 512;
6620 } else {
6621 pf->rss_table_size = 128;
6622 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6623 }
6624 wr32(hw, I40E_PFQF_CTL_0, reg_val);
6625
6507 /* Populate the LUT with max no. of queues in round robin fashion */ 6626 /* Populate the LUT with max no. of queues in round robin fashion */
6508 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) { 6627 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
6509 6628
6510 /* The assumption is that lan qp count will be the highest 6629 /* The assumption is that lan qp count will be the highest
6511 * qp count for any PF VSI that needs RSS. 6630 * qp count for any PF VSI that needs RSS.
diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h
index 947de98500f3..65d3c8bb2d5b 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_register.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_register.h
@@ -27,4648 +27,3343 @@
27#ifndef _I40E_REGISTER_H_ 27#ifndef _I40E_REGISTER_H_
28#define _I40E_REGISTER_H_ 28#define _I40E_REGISTER_H_
29 29
30#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ 30#define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
31#define I40E_GL_GP_FUSE_MAX_INDEX 28 31#define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
32#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0 32#define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
33#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK (0xFFFFFFFF << I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT) 33#define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */
34#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 34#define I40E_GL_ARQBAL_ARQBAL_SHIFT 0
35#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0 35#define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
36#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT) 36#define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */
37#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16 37#define I40E_GL_ARQH_ARQH_SHIFT 0
38#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT) 38#define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
39#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 39#define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */
40#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0 40#define I40E_GL_ARQT_ARQT_SHIFT 0
41#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT) 41#define I40E_GL_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT)
42#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16 42#define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */
43#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT) 43#define I40E_GL_ATQBAH_ATQBAH_SHIFT 0
44#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC 44#define I40E_GL_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT)
45#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0 45#define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */
46#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT) 46#define I40E_GL_ATQBAL_ATQBAL_SHIFT 0
47#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8 47#define I40E_GL_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT)
48#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT) 48#define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */
49#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 49#define I40E_GL_ATQH_ATQH_SHIFT 0
50#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0 50#define I40E_GL_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT)
51#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT) 51#define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */
52#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC 52#define I40E_GL_ATQLEN_ATQLEN_SHIFT 0
53#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0 53#define I40E_GL_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT)
54#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT) 54#define I40E_GL_ATQLEN_ATQVFE_SHIFT 28
55#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 55#define I40E_GL_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQVFE_SHIFT)
56#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 56#define I40E_GL_ATQLEN_ATQOVFL_SHIFT 29
57#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT) 57#define I40E_GL_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQOVFL_SHIFT)
58#define I40E_PFPCI_VF_FLUSH_DONE 0x0009C600 58#define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30
59#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 59#define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
60#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT) 60#define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31
61#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ 61#define I40E_GL_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT)
62#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127 62#define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */
63#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0 63#define I40E_GL_ATQT_ATQT_SHIFT 0
64#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT) 64#define I40E_GL_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT)
65#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 65#define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
66#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
67#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
68
69#define I40E_PF_ARQBAH 0x00080180
70#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0 66#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0
71#define I40E_PF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_PF_ARQBAH_ARQBAH_SHIFT) 67#define I40E_PF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT)
72#define I40E_PF_ARQBAL 0x00080080 68#define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
73#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0 69#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0
74#define I40E_PF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_PF_ARQBAL_ARQBAL_SHIFT) 70#define I40E_PF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT)
75#define I40E_PF_ARQH 0x00080380 71#define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
76#define I40E_PF_ARQH_ARQH_SHIFT 0 72#define I40E_PF_ARQH_ARQH_SHIFT 0
77#define I40E_PF_ARQH_ARQH_MASK (0x3FF << I40E_PF_ARQH_ARQH_SHIFT) 73#define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
78#define I40E_PF_ARQLEN 0x00080280 74#define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
79#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0 75#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0
80#define I40E_PF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_PF_ARQLEN_ARQLEN_SHIFT) 76#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)
81#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 77#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28
82#define I40E_PF_ARQLEN_ARQVFE_MASK (0x1 << I40E_PF_ARQLEN_ARQVFE_SHIFT) 78#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
83#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 79#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29
84#define I40E_PF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_PF_ARQLEN_ARQOVFL_SHIFT) 80#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
85#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 81#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
86#define I40E_PF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_PF_ARQLEN_ARQCRIT_SHIFT) 82#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
87#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 83#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
88#define I40E_PF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_PF_ARQLEN_ARQENABLE_SHIFT) 84#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
89#define I40E_PF_ARQT 0x00080480 85#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
90#define I40E_PF_ARQT_ARQT_SHIFT 0 86#define I40E_PF_ARQT_ARQT_SHIFT 0
91#define I40E_PF_ARQT_ARQT_MASK (0x3FF << I40E_PF_ARQT_ARQT_SHIFT) 87#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
92#define I40E_PF_ATQBAH 0x00080100 88#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */
93#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 89#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0
94#define I40E_PF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_PF_ATQBAH_ATQBAH_SHIFT) 90#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)
95#define I40E_PF_ATQBAL 0x00080000 91#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */
96#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 92#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0
97#define I40E_PF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_PF_ATQBAL_ATQBAL_SHIFT) 93#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)
98#define I40E_PF_ATQH 0x00080300 94#define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */
99#define I40E_PF_ATQH_ATQH_SHIFT 0 95#define I40E_PF_ATQH_ATQH_SHIFT 0
100#define I40E_PF_ATQH_ATQH_MASK (0x3FF << I40E_PF_ATQH_ATQH_SHIFT) 96#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)
101#define I40E_PF_ATQLEN 0x00080200 97#define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */
102#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0 98#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0
103#define I40E_PF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_PF_ATQLEN_ATQLEN_SHIFT) 99#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)
104#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 100#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28
105#define I40E_PF_ATQLEN_ATQVFE_MASK (0x1 << I40E_PF_ATQLEN_ATQVFE_SHIFT) 101#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)
106#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 102#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29
107#define I40E_PF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_PF_ATQLEN_ATQOVFL_SHIFT) 103#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)
108#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 104#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
109#define I40E_PF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_PF_ATQLEN_ATQCRIT_SHIFT) 105#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
110#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 106#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
111#define I40E_PF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_PF_ATQLEN_ATQENABLE_SHIFT) 107#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
112#define I40E_PF_ATQT 0x00080400 108#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
113#define I40E_PF_ATQT_ATQT_SHIFT 0 109#define I40E_PF_ATQT_ATQT_SHIFT 0
114#define I40E_PF_ATQT_ATQT_MASK (0x3FF << I40E_PF_ATQT_ATQT_SHIFT) 110#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
115#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ 111#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
116#define I40E_VF_ARQBAH_MAX_INDEX 127 112#define I40E_VF_ARQBAH_MAX_INDEX 127
117#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 113#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0
118#define I40E_VF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH_ARQBAH_SHIFT) 114#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)
119#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ 115#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
120#define I40E_VF_ARQBAL_MAX_INDEX 127 116#define I40E_VF_ARQBAL_MAX_INDEX 127
121#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0 117#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0
122#define I40E_VF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL_ARQBAL_SHIFT) 118#define I40E_VF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT)
123#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ 119#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
124#define I40E_VF_ARQH_MAX_INDEX 127 120#define I40E_VF_ARQH_MAX_INDEX 127
125#define I40E_VF_ARQH_ARQH_SHIFT 0 121#define I40E_VF_ARQH_ARQH_SHIFT 0
126#define I40E_VF_ARQH_ARQH_MASK (0x3FF << I40E_VF_ARQH_ARQH_SHIFT) 122#define I40E_VF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT)
127#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ 123#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
128#define I40E_VF_ARQLEN_MAX_INDEX 127 124#define I40E_VF_ARQLEN_MAX_INDEX 127
129#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0 125#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0
130#define I40E_VF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN_ARQLEN_SHIFT) 126#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)
131#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 127#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28
132#define I40E_VF_ARQLEN_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN_ARQVFE_SHIFT) 128#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT)
133#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 129#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29
134#define I40E_VF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN_ARQOVFL_SHIFT) 130#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT)
135#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 131#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30
136#define I40E_VF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN_ARQCRIT_SHIFT) 132#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
137#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 133#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
138#define I40E_VF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN_ARQENABLE_SHIFT) 134#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
139#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ 135#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
140#define I40E_VF_ARQT_MAX_INDEX 127 136#define I40E_VF_ARQT_MAX_INDEX 127
141#define I40E_VF_ARQT_ARQT_SHIFT 0 137#define I40E_VF_ARQT_ARQT_SHIFT 0
142#define I40E_VF_ARQT_ARQT_MASK (0x3FF << I40E_VF_ARQT_ARQT_SHIFT) 138#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)
143#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ 139#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
144#define I40E_VF_ATQBAH_MAX_INDEX 127 140#define I40E_VF_ATQBAH_MAX_INDEX 127
145#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 141#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0
146#define I40E_VF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH_ATQBAH_SHIFT) 142#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)
147#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ 143#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
148#define I40E_VF_ATQBAL_MAX_INDEX 127 144#define I40E_VF_ATQBAL_MAX_INDEX 127
149#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0 145#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0
150#define I40E_VF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL_ATQBAL_SHIFT) 146#define I40E_VF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT)
151#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ 147#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
152#define I40E_VF_ATQH_MAX_INDEX 127 148#define I40E_VF_ATQH_MAX_INDEX 127
153#define I40E_VF_ATQH_ATQH_SHIFT 0 149#define I40E_VF_ATQH_ATQH_SHIFT 0
154#define I40E_VF_ATQH_ATQH_MASK (0x3FF << I40E_VF_ATQH_ATQH_SHIFT) 150#define I40E_VF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT)
155#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ 151#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
156#define I40E_VF_ATQLEN_MAX_INDEX 127 152#define I40E_VF_ATQLEN_MAX_INDEX 127
157#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0 153#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0
158#define I40E_VF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN_ATQLEN_SHIFT) 154#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)
159#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 155#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28
160#define I40E_VF_ATQLEN_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN_ATQVFE_SHIFT) 156#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT)
161#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 157#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29
162#define I40E_VF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN_ATQOVFL_SHIFT) 158#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT)
163#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 159#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30
164#define I40E_VF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN_ATQCRIT_SHIFT) 160#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
165#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 161#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
166#define I40E_VF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN_ATQENABLE_SHIFT) 162#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
167#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ 163#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
168#define I40E_VF_ATQT_MAX_INDEX 127 164#define I40E_VF_ATQT_MAX_INDEX 127
169#define I40E_VF_ATQT_ATQT_SHIFT 0 165#define I40E_VF_ATQT_ATQT_SHIFT 0
170#define I40E_VF_ATQT_ATQT_MASK (0x3FF << I40E_VF_ATQT_ATQT_SHIFT) 166#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)
171#define I40E_PRT_L2TAGSEN 0x001C0B20 167#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */
172#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 168#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0
173#define I40E_PRT_L2TAGSEN_ENABLE_MASK (0xFF << I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 169#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
174#define I40E_PFCM_LAN_ERRDATA 0x0010C080 170#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */
175#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0 171#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0
176#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT) 172#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)
177#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4 173#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4
178#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT) 174#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)
179#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8 175#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8
180#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK (0xFFF << I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT) 176#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)
181#define I40E_PFCM_LAN_ERRINFO 0x0010C000 177#define I40E_PFCM_LAN_ERRINFO 0x0010C000 /* Reset: PFR */
182#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0 178#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0
183#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT) 179#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)
184#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4 180#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4
185#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT) 181#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT)
186#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8 182#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8
187#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT) 183#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT)
188#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16 184#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16
189#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT) 185#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
190#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24 186#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24
191#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT) 187#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
192#define I40E_PFCM_LANCTXCTL 0x0010C300 188#define I40E_PFCM_LANCTXCTL 0x0010C300 /* Reset: CORER */
193#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0 189#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0
194#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK (0xFFF << I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT) 190#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
195#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12 191#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12
196#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK (0x7 << I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT) 192#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT)
197#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15 193#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15
198#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK (0x3 << I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT) 194#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
199#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17 195#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17
200#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK (0x3 << I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT) 196#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
201#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ 197#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */
202#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3 198#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3
203#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0 199#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0
204#define I40E_PFCM_LANCTXDATA_DATA_MASK (0xFFFFFFFF << I40E_PFCM_LANCTXDATA_DATA_SHIFT) 200#define I40E_PFCM_LANCTXDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT)
205#define I40E_PFCM_LANCTXSTAT 0x0010C380 201#define I40E_PFCM_LANCTXSTAT 0x0010C380 /* Reset: CORER */
206#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0 202#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0
207#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT) 203#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
208#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1 204#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
209#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT) 205#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)
210#define I40E_PFCM_PE_ERRDATA 0x00138D00 206#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
211#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
212#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
213#define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
214#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT)
215#define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8
216#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT)
217#define I40E_PFCM_PE_ERRINFO 0x00138C80
218#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
219#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
220#define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
221#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT)
222#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
223#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
224#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
225#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
226#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
227#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
228#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */
229#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127 207#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127
230#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0 208#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0
231#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT) 209#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)
232#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4 210#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4
233#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT) 211#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)
234#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8 212#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8
235#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT) 213#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)
236#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ 214#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
237#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127 215#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127
238#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0 216#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0
239#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT) 217#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)
240#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4 218#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4
241#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT) 219#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT)
242#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8 220#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8
243#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT) 221#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT)
244#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16 222#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16
245#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) 223#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
246#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 224#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
247#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) 225#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
248#define I40E_GLDCB_GENC 0x00083044 226#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */
249#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 227#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
250#define I40E_GLDCB_GENC_PCIRTT_MASK (0xFFFF << I40E_GLDCB_GENC_PCIRTT_SHIFT) 228#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)
251#define I40E_GLDCB_RUPTI 0x00122618 229#define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */
252#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0 230#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0
253#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK (0xFFFFFFFF << I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT) 231#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)
254#define I40E_PRTDCB_FCCFG 0x001E4640 232#define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */
255#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 233#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3
256#define I40E_PRTDCB_FCCFG_TFCE_MASK (0x3 << I40E_PRTDCB_FCCFG_TFCE_SHIFT) 234#define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
257#define I40E_PRTDCB_FCRTV 0x001E4600 235#define I40E_PRTDCB_FCRTV 0x001E4600 /* Reset: GLOBR */
258#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0 236#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0
259#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK (0xFFFF << I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT) 237#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)
260#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ 238#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */
261#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3 239#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3
262#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0 240#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0
263#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT) 241#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
264#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16 242#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16
265#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT) 243#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
266#define I40E_PRTDCB_GENC 0x00083000 244#define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */
267#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0 245#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0
268#define I40E_PRTDCB_GENC_RESERVED_1_MASK (0x3 << I40E_PRTDCB_GENC_RESERVED_1_SHIFT) 246#define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
269#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2 247#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2
270#define I40E_PRTDCB_GENC_NUMTC_MASK (0xF << I40E_PRTDCB_GENC_NUMTC_SHIFT) 248#define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT)
271#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6 249#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6
272#define I40E_PRTDCB_GENC_FCOEUP_MASK (0x7 << I40E_PRTDCB_GENC_FCOEUP_SHIFT) 250#define I40E_PRTDCB_GENC_FCOEUP_MASK I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT)
273#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9 251#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9
274#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK (0x1 << I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT) 252#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
275#define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 253#define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16
276#define I40E_PRTDCB_GENC_PFCLDA_MASK (0xFFFF << I40E_PRTDCB_GENC_PFCLDA_SHIFT) 254#define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
277#define I40E_PRTDCB_GENS 0x00083020 255#define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */
278#define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 256#define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
279#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK (0x7 << I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 257#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
280#define I40E_PRTDCB_MFLCN 0x001E2400 258#define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */
281#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0 259#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0
282#define I40E_PRTDCB_MFLCN_PMCF_MASK (0x1 << I40E_PRTDCB_MFLCN_PMCF_SHIFT) 260#define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
283#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1 261#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1
284#define I40E_PRTDCB_MFLCN_DPF_MASK (0x1 << I40E_PRTDCB_MFLCN_DPF_SHIFT) 262#define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT)
285#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2 263#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2
286#define I40E_PRTDCB_MFLCN_RPFCM_MASK (0x1 << I40E_PRTDCB_MFLCN_RPFCM_SHIFT) 264#define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT)
287#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3 265#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3
288#define I40E_PRTDCB_MFLCN_RFCE_MASK (0x1 << I40E_PRTDCB_MFLCN_RFCE_SHIFT) 266#define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT)
289#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4 267#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4
290#define I40E_PRTDCB_MFLCN_RPFCE_MASK (0xFF << I40E_PRTDCB_MFLCN_RPFCE_SHIFT) 268#define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
291#define I40E_PRTDCB_RETSC 0x001223E0 269#define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */
292#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0 270#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0
293#define I40E_PRTDCB_RETSC_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) 271#define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
294#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1 272#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1
295#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) 273#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)
296#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2 274#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2
297#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK (0xF << I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) 275#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
298#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8 276#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8
299#define I40E_PRTDCB_RETSC_LLTC_MASK (0xFF << I40E_PRTDCB_RETSC_LLTC_SHIFT) 277#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
300#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ 278#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
301#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 279#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7
302#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 280#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0
303#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK (0x7F << I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 281#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
304#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 282#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
305#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK (0x1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 283#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
306#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 284#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
307#define I40E_PRTDCB_RETSTCC_ETSTC_MASK (0x1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) 285#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
308#define I40E_PRTDCB_RPPMC 0x001223A0 286#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */
309#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 287#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
310#define I40E_PRTDCB_RPPMC_LANRPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 288#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
311#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 289#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8
312#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 290#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
313#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 291#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
314#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK (0xFF << I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 292#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
315#define I40E_PRTDCB_RUP 0x001C0B00 293#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */
316#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0 294#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0
317#define I40E_PRTDCB_RUP_NOVLANUP_MASK (0x7 << I40E_PRTDCB_RUP_NOVLANUP_SHIFT) 295#define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
318#define I40E_PRTDCB_RUP2TC 0x001C09A0 296#define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */
319#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0 297#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0
320#define I40E_PRTDCB_RUP2TC_UP0TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP0TC_SHIFT) 298#define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
321#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3 299#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3
322#define I40E_PRTDCB_RUP2TC_UP1TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP1TC_SHIFT) 300#define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)
323#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6 301#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6
324#define I40E_PRTDCB_RUP2TC_UP2TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP2TC_SHIFT) 302#define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)
325#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9 303#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9
326#define I40E_PRTDCB_RUP2TC_UP3TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP3TC_SHIFT) 304#define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)
327#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 305#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12
328#define I40E_PRTDCB_RUP2TC_UP4TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 306#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)
329#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 307#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15
330#define I40E_PRTDCB_RUP2TC_UP5TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 308#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)
331#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 309#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18
332#define I40E_PRTDCB_RUP2TC_UP6TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 310#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
333#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 311#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
334#define I40E_PRTDCB_RUP2TC_UP7TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) 312#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
335#define I40E_PRTDCB_TC2PFC 0x001C0980 313#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */
336#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 314#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
337#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK (0xFF << I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 315#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
338#define I40E_PRTDCB_TCPMC 0x000A21A0 316#define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
317#define I40E_PRTDCB_TCMSTC_MAX_INDEX 7
318#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0
319#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)
320#define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */
339#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0 321#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0
340#define I40E_PRTDCB_TCPMC_CPM_MASK (0x1FFF << I40E_PRTDCB_TCPMC_CPM_SHIFT) 322#define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)
341#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13 323#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13
342#define I40E_PRTDCB_TCPMC_LLTC_MASK (0xFF << I40E_PRTDCB_TCPMC_LLTC_SHIFT) 324#define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)
343#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30 325#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30
344#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) 326#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
345#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ 327#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
346#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7 328#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7
347#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0 329#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0
348#define I40E_PRTDCB_TCWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TCWSTC_MSTC_SHIFT) 330#define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
349#define I40E_PRTDCB_TDPMC 0x000A0180 331#define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */
350#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0 332#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0
351#define I40E_PRTDCB_TDPMC_DPM_MASK (0xFF << I40E_PRTDCB_TDPMC_DPM_SHIFT) 333#define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)
352#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30 334#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30
353#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) 335#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
354#define I40E_PRTDCB_TDPUC 0x00044100 336#define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */
355#define I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT 0
356#define I40E_PRTDCB_TDPUC_MAX_TXFRAME_MASK (0xFFFF << I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT)
357#define I40E_PRTDCB_TETSC_TCB 0x000AE060
358#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0 337#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0
359#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT) 338#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
360#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8 339#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8
361#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT) 340#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
362#define I40E_PRTDCB_TETSC_TPB 0x00098060 341#define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */
363#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0 342#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0
364#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT) 343#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
365#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8 344#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8
366#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT) 345#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
367#define I40E_PRTDCB_TFCS 0x001E4560 346#define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */
368#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0 347#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0
369#define I40E_PRTDCB_TFCS_TXOFF_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF_SHIFT) 348#define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT)
370#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8 349#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
371#define I40E_PRTDCB_TFCS_TXOFF0_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF0_SHIFT) 350#define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT)
372#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9 351#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9
373#define I40E_PRTDCB_TFCS_TXOFF1_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF1_SHIFT) 352#define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT)
374#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10 353#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10
375#define I40E_PRTDCB_TFCS_TXOFF2_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF2_SHIFT) 354#define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT)
376#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11 355#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11
377#define I40E_PRTDCB_TFCS_TXOFF3_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF3_SHIFT) 356#define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT)
378#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12 357#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12
379#define I40E_PRTDCB_TFCS_TXOFF4_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF4_SHIFT) 358#define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT)
380#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13 359#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13
381#define I40E_PRTDCB_TFCS_TXOFF5_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF5_SHIFT) 360#define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT)
382#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14 361#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14
383#define I40E_PRTDCB_TFCS_TXOFF6_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF6_SHIFT) 362#define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
384#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15 363#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15
385#define I40E_PRTDCB_TFCS_TXOFF7_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF7_SHIFT) 364#define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
386#define I40E_PRTDCB_TFWSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ 365#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */
387#define I40E_PRTDCB_TFWSTC_MAX_INDEX 7
388#define I40E_PRTDCB_TFWSTC_MSTC_SHIFT 0
389#define I40E_PRTDCB_TFWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TFWSTC_MSTC_SHIFT)
390#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */
391#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7 366#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7
392#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 367#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0
393#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK (0x3FFF << I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) 368#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
394#define I40E_GLFCOE_RCTL 0x00269B94 369#define I40E_GLFCOE_RCTL 0x00269B94 /* Reset: CORER */
395#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0 370#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0
396#define I40E_GLFCOE_RCTL_FCOEVER_MASK (0xF << I40E_GLFCOE_RCTL_FCOEVER_SHIFT) 371#define I40E_GLFCOE_RCTL_FCOEVER_MASK I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT)
397#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4 372#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4
398#define I40E_GLFCOE_RCTL_SAVBAD_MASK (0x1 << I40E_GLFCOE_RCTL_SAVBAD_SHIFT) 373#define I40E_GLFCOE_RCTL_SAVBAD_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_SAVBAD_SHIFT)
399#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5 374#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5
400#define I40E_GLFCOE_RCTL_ICRC_MASK (0x1 << I40E_GLFCOE_RCTL_ICRC_SHIFT) 375#define I40E_GLFCOE_RCTL_ICRC_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT)
401#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16 376#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16
402#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK (0x3FFF << I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 377#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
403#define I40E_GL_FWSTS 0x00083048 378#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */
404#define I40E_GL_FWSTS_FWS0B_SHIFT 0 379#define I40E_GL_FWSTS_FWS0B_SHIFT 0
405#define I40E_GL_FWSTS_FWS0B_MASK (0xFF << I40E_GL_FWSTS_FWS0B_SHIFT) 380#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)
406#define I40E_GL_FWSTS_FWRI_SHIFT 9 381#define I40E_GL_FWSTS_FWRI_SHIFT 9
407#define I40E_GL_FWSTS_FWRI_MASK (0x1 << I40E_GL_FWSTS_FWRI_SHIFT) 382#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)
408#define I40E_GL_FWSTS_FWS1B_SHIFT 16 383#define I40E_GL_FWSTS_FWS1B_SHIFT 16
409#define I40E_GL_FWSTS_FWS1B_MASK (0xFF << I40E_GL_FWSTS_FWS1B_SHIFT) 384#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
410#define I40E_GLGEN_CLKSTAT 0x000B8184 385#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */
411#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 386#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0
412#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK (0x1 << I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 387#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
413#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 388#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4
414#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK (0x3 << I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 389#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
415#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 390#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8
416#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 391#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)
417#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 392#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12
418#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT) 393#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT)
419#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16 394#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16
420#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT) 395#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)
421#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20 396#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20
422#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT) 397#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)
423#define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ 398#define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
424#define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 399#define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29
425#define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 400#define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0
426#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK (0x3 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 401#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
427#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 402#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3
428#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 403#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
429#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4 404#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4
430#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 405#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
431#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5 406#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5
432#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 407#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
433#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6 408#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6
434#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 409#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
435#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 410#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7
436#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK (0x7 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 411#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
437#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10 412#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10
438#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT) 413#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT)
439#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 414#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11
440#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT) 415#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)
441#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 416#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12
442#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK (0xF << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 417#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
443#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17 418#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17
444#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK (0x3 << I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT) 419#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
445#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 420#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19
446#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 421#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
447#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 422#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
448#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 423#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
449#define I40E_GLGEN_GPIO_SET 0x00088184 424#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */
450#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 425#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
451#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK (0x1F << I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) 426#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
452#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 427#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5
453#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK (0x1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 428#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
454#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 429#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6
455#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK (0x1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 430#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
456#define I40E_GLGEN_GPIO_STAT 0x0008817C 431#define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */
457#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0 432#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0
458#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT) 433#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)
459#define I40E_GLGEN_GPIO_TRANSIT 0x00088180 434#define I40E_GLGEN_GPIO_TRANSIT 0x00088180 /* Reset: POR */
460#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0 435#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0
461#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT) 436#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)
462#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ 437#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
463#define I40E_GLGEN_I2CCMD_MAX_INDEX 3 438#define I40E_GLGEN_I2CCMD_MAX_INDEX 3
464#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0 439#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0
465#define I40E_GLGEN_I2CCMD_DATA_MASK (0xFFFF << I40E_GLGEN_I2CCMD_DATA_SHIFT) 440#define I40E_GLGEN_I2CCMD_DATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT)
466#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16 441#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16
467#define I40E_GLGEN_I2CCMD_REGADD_MASK (0xFF << I40E_GLGEN_I2CCMD_REGADD_SHIFT) 442#define I40E_GLGEN_I2CCMD_REGADD_MASK I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT)
468#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24 443#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24
469#define I40E_GLGEN_I2CCMD_PHYADD_MASK (0x7 << I40E_GLGEN_I2CCMD_PHYADD_SHIFT) 444#define I40E_GLGEN_I2CCMD_PHYADD_MASK I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT)
470#define I40E_GLGEN_I2CCMD_OP_SHIFT 27 445#define I40E_GLGEN_I2CCMD_OP_SHIFT 27
471#define I40E_GLGEN_I2CCMD_OP_MASK (0x1 << I40E_GLGEN_I2CCMD_OP_SHIFT) 446#define I40E_GLGEN_I2CCMD_OP_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_OP_SHIFT)
472#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28 447#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28
473#define I40E_GLGEN_I2CCMD_RESET_MASK (0x1 << I40E_GLGEN_I2CCMD_RESET_SHIFT) 448#define I40E_GLGEN_I2CCMD_RESET_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_RESET_SHIFT)
474#define I40E_GLGEN_I2CCMD_R_SHIFT 29 449#define I40E_GLGEN_I2CCMD_R_SHIFT 29
475#define I40E_GLGEN_I2CCMD_R_MASK (0x1 << I40E_GLGEN_I2CCMD_R_SHIFT) 450#define I40E_GLGEN_I2CCMD_R_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT)
476#define I40E_GLGEN_I2CCMD_E_SHIFT 31 451#define I40E_GLGEN_I2CCMD_E_SHIFT 31
477#define I40E_GLGEN_I2CCMD_E_MASK (0x1 << I40E_GLGEN_I2CCMD_E_SHIFT) 452#define I40E_GLGEN_I2CCMD_E_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT)
478#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ 453#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
479#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3 454#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3
480#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0 455#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0
481#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK (0x1F << I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT) 456#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)
482#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5 457#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5
483#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK (0x7 << I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT) 458#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT)
484#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8 459#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8
485#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT) 460#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT)
486#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9 461#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9
487#define I40E_GLGEN_I2CPARAMS_CLK_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_SHIFT) 462#define I40E_GLGEN_I2CPARAMS_CLK_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_SHIFT)
488#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10 463#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10
489#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT) 464#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT)
490#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11 465#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11
491#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT) 466#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT)
492#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12 467#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12
493#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT) 468#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT)
494#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13 469#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13
495#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT) 470#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT)
496#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14 471#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14
497#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT) 472#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT)
498#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15 473#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15
499#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT) 474#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)
500#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31 475#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31
501#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT) 476#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)
502#define I40E_GLGEN_LED_CTL 0x00088178 477#define I40E_GLGEN_LED_CTL 0x00088178 /* Reset: POR */
503#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0 478#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0
504#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK (0x1 << I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT) 479#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)
505#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ 480#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
506#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3 481#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3
507#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0 482#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0
508#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK (0x1FFFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT) 483#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)
509#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 484#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17
510#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK (0x1 << I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) 485#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
511#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 486#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
512#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK (0x3FFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) 487#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
513#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ 488#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
514#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 489#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3
515#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 490#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
516#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT) 491#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)
517#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1 492#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1
518#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT) 493#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)
519#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5 494#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5
520#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT) 495#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT)
521#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10 496#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10
522#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT) 497#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT)
523#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15 498#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15
524#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT) 499#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT)
525#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20 500#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20
526#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT) 501#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT)
527#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25 502#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25
528#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT) 503#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)
529#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31 504#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31
530#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT) 505#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)
531#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ 506#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
532#define I40E_GLGEN_MSCA_MAX_INDEX 3 507#define I40E_GLGEN_MSCA_MAX_INDEX 3
533#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 508#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0
534#define I40E_GLGEN_MSCA_MDIADD_MASK (0xFFFF << I40E_GLGEN_MSCA_MDIADD_SHIFT) 509#define I40E_GLGEN_MSCA_MDIADD_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT)
535#define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 510#define I40E_GLGEN_MSCA_DEVADD_SHIFT 16
536#define I40E_GLGEN_MSCA_DEVADD_MASK (0x1F << I40E_GLGEN_MSCA_DEVADD_SHIFT) 511#define I40E_GLGEN_MSCA_DEVADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT)
537#define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 512#define I40E_GLGEN_MSCA_PHYADD_SHIFT 21
538#define I40E_GLGEN_MSCA_PHYADD_MASK (0x1F << I40E_GLGEN_MSCA_PHYADD_SHIFT) 513#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)
539#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 514#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26
540#define I40E_GLGEN_MSCA_OPCODE_MASK (0x3 << I40E_GLGEN_MSCA_OPCODE_SHIFT) 515#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)
541#define I40E_GLGEN_MSCA_STCODE_SHIFT 28 516#define I40E_GLGEN_MSCA_STCODE_SHIFT 28
542#define I40E_GLGEN_MSCA_STCODE_MASK (0x3 << I40E_GLGEN_MSCA_STCODE_SHIFT) 517#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)
543#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 518#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
544#define I40E_GLGEN_MSCA_MDICMD_MASK (0x1 << I40E_GLGEN_MSCA_MDICMD_SHIFT) 519#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
545#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 520#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
546#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK (0x1 << I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 521#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
547#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ 522#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
548#define I40E_GLGEN_MSRWD_MAX_INDEX 3 523#define I40E_GLGEN_MSRWD_MAX_INDEX 3
549#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 524#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
550#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 525#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
551#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 526#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
552#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 527#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
553#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 528#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */
554#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 529#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
555#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK (0x1F << I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) 530#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
556#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 531#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
557#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK (0xFF << I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) 532#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
558#define I40E_GLGEN_PE_ENA 0x000B81A0 533#define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */
559#define I40E_GLGEN_PE_ENA_PE_ENA_SHIFT 0
560#define I40E_GLGEN_PE_ENA_PE_ENA_MASK (0x1 << I40E_GLGEN_PE_ENA_PE_ENA_SHIFT)
561#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT 1
562#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_MASK (0x3 << I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT)
563#define I40E_GLGEN_RSTAT 0x000B8188
564#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 534#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
565#define I40E_GLGEN_RSTAT_DEVSTATE_MASK (0x3 << I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 535#define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
566#define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 536#define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2
567#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK (0x3 << I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 537#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)
568#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4 538#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4
569#define I40E_GLGEN_RSTAT_CORERCNT_MASK (0x3 << I40E_GLGEN_RSTAT_CORERCNT_SHIFT) 539#define I40E_GLGEN_RSTAT_CORERCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT)
570#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6 540#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6
571#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT) 541#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT)
572#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8 542#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8
573#define I40E_GLGEN_RSTAT_EMPRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_EMPRCNT_SHIFT) 543#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)
574#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10 544#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10
575#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK (0x3F << I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT) 545#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)
576#define I40E_GLGEN_RSTCTL 0x000B8180 546#define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */
577#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 547#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0
578#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK (0x3F << I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 548#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
579#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 549#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
580#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) 550#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
581#define I40E_GLGEN_RSTENA_EMP 0x000B818C 551#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR */
582#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0 552#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0
583#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT) 553#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)
584#define I40E_GLGEN_RTRIG 0x000B8190 554#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */
585#define I40E_GLGEN_RTRIG_CORER_SHIFT 0 555#define I40E_GLGEN_RTRIG_CORER_SHIFT 0
586#define I40E_GLGEN_RTRIG_CORER_MASK (0x1 << I40E_GLGEN_RTRIG_CORER_SHIFT) 556#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
587#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 557#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1
588#define I40E_GLGEN_RTRIG_GLOBR_MASK (0x1 << I40E_GLGEN_RTRIG_GLOBR_SHIFT) 558#define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT)
589#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2 559#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2
590#define I40E_GLGEN_RTRIG_EMPFWR_MASK (0x1 << I40E_GLGEN_RTRIG_EMPFWR_SHIFT) 560#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT)
591#define I40E_GLGEN_STAT 0x000B612C 561#define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
592#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0 562#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0
593#define I40E_GLGEN_STAT_HWRSVD0_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD0_SHIFT) 563#define I40E_GLGEN_STAT_HWRSVD0_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT)
594#define I40E_GLGEN_STAT_DCBEN_SHIFT 2 564#define I40E_GLGEN_STAT_DCBEN_SHIFT 2
595#define I40E_GLGEN_STAT_DCBEN_MASK (0x1 << I40E_GLGEN_STAT_DCBEN_SHIFT) 565#define I40E_GLGEN_STAT_DCBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_DCBEN_SHIFT)
596#define I40E_GLGEN_STAT_VTEN_SHIFT 3 566#define I40E_GLGEN_STAT_VTEN_SHIFT 3
597#define I40E_GLGEN_STAT_VTEN_MASK (0x1 << I40E_GLGEN_STAT_VTEN_SHIFT) 567#define I40E_GLGEN_STAT_VTEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_VTEN_SHIFT)
598#define I40E_GLGEN_STAT_FCOEN_SHIFT 4 568#define I40E_GLGEN_STAT_FCOEN_SHIFT 4
599#define I40E_GLGEN_STAT_FCOEN_MASK (0x1 << I40E_GLGEN_STAT_FCOEN_SHIFT) 569#define I40E_GLGEN_STAT_FCOEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_FCOEN_SHIFT)
600#define I40E_GLGEN_STAT_EVBEN_SHIFT 5 570#define I40E_GLGEN_STAT_EVBEN_SHIFT 5
601#define I40E_GLGEN_STAT_EVBEN_MASK (0x1 << I40E_GLGEN_STAT_EVBEN_SHIFT) 571#define I40E_GLGEN_STAT_EVBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT)
602#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6 572#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6
603#define I40E_GLGEN_STAT_HWRSVD1_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD1_SHIFT) 573#define I40E_GLGEN_STAT_HWRSVD1_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT)
604#define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ 574#define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
605#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3 575#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3
606#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0 576#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0
607#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK (0xFFFFFFFF << I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT) 577#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)
608#define I40E_GLVFGEN_TIMER 0x000881BC 578#define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */
609#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0 579#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0
610#define I40E_GLVFGEN_TIMER_GTIME_MASK (0xFFFFFFFF << I40E_GLVFGEN_TIMER_GTIME_SHIFT) 580#define I40E_GLVFGEN_TIMER_GTIME_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT)
611#define I40E_PFGEN_CTRL 0x00092400 581#define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */
612#define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 582#define I40E_PFGEN_CTRL_PFSWR_SHIFT 0
613#define I40E_PFGEN_CTRL_PFSWR_MASK (0x1 << I40E_PFGEN_CTRL_PFSWR_SHIFT) 583#define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT)
614#define I40E_PFGEN_DRUN 0x00092500 584#define I40E_PFGEN_DRUN 0x00092500 /* Reset: CORER */
615#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0 585#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0
616#define I40E_PFGEN_DRUN_DRVUNLD_MASK (0x1 << I40E_PFGEN_DRUN_DRVUNLD_SHIFT) 586#define I40E_PFGEN_DRUN_DRVUNLD_MASK I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT)
617#define I40E_PFGEN_PORTNUM 0x001C0480 587#define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */
618#define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 588#define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0
619#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 589#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
620#define I40E_PFGEN_STATE 0x00088000 590#define I40E_PFGEN_STATE 0x00088000 /* Reset: CORER */
621#define I40E_PFGEN_STATE_PFPEEN_SHIFT 0 591#define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0
622#define I40E_PFGEN_STATE_PFPEEN_MASK (0x1 << I40E_PFGEN_STATE_PFPEEN_SHIFT) 592#define I40E_PFGEN_STATE_RESERVED_0_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT)
623#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1 593#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1
624#define I40E_PFGEN_STATE_PFFCEN_MASK (0x1 << I40E_PFGEN_STATE_PFFCEN_SHIFT) 594#define I40E_PFGEN_STATE_PFFCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFFCEN_SHIFT)
625#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2 595#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2
626#define I40E_PFGEN_STATE_PFLINKEN_MASK (0x1 << I40E_PFGEN_STATE_PFLINKEN_SHIFT) 596#define I40E_PFGEN_STATE_PFLINKEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT)
627#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3 597#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3
628#define I40E_PFGEN_STATE_PFSCEN_MASK (0x1 << I40E_PFGEN_STATE_PFSCEN_SHIFT) 598#define I40E_PFGEN_STATE_PFSCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT)
629#define I40E_PRTGEN_CNF 0x000B8120 599#define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */
630#define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 600#define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0
631#define I40E_PRTGEN_CNF_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 601#define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
632#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1 602#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1
633#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT) 603#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)
634#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2 604#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2
635#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT) 605#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)
636#define I40E_PRTGEN_CNF2 0x000B8160 606#define I40E_PRTGEN_CNF2 0x000B8160 /* Reset: POR */
637#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0 607#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0
638#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK (0x1 << I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT) 608#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)
639#define I40E_PRTGEN_STATUS 0x000B8100 609#define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */
640#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0 610#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0
641#define I40E_PRTGEN_STATUS_PORT_VALID_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_VALID_SHIFT) 611#define I40E_PRTGEN_STATUS_PORT_VALID_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)
642#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1 612#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1
643#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT) 613#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)
644#define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ 614#define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
645#define I40E_VFGEN_RSTAT1_MAX_INDEX 127 615#define I40E_VFGEN_RSTAT1_MAX_INDEX 127
646#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0 616#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0
647#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT) 617#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)
648#define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ 618#define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
649#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127 619#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127
650#define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 620#define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0
651#define I40E_VPGEN_VFRSTAT_VFRD_MASK (0x1 << I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 621#define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
652#define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ 622#define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
653#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127 623#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127
654#define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 624#define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0
655#define I40E_VPGEN_VFRTRIG_VFSWR_MASK (0x1 << I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 625#define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
656#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ 626#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
657#define I40E_VSIGEN_RSTAT_MAX_INDEX 383 627#define I40E_VSIGEN_RSTAT_MAX_INDEX 383
658#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0 628#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0
659#define I40E_VSIGEN_RSTAT_VMRD_MASK (0x1 << I40E_VSIGEN_RSTAT_VMRD_SHIFT) 629#define I40E_VSIGEN_RSTAT_VMRD_MASK I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT)
660#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ 630#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
661#define I40E_VSIGEN_RTRIG_MAX_INDEX 383 631#define I40E_VSIGEN_RTRIG_MAX_INDEX 383
662#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0 632#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0
663#define I40E_VSIGEN_RTRIG_VMSWR_MASK (0x1 << I40E_VSIGEN_RTRIG_VMSWR_SHIFT) 633#define I40E_VSIGEN_RTRIG_VMSWR_MASK I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT)
664#define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) 634#define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
665#define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15
666#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
667#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
668#define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */
669#define I40E_GLHMC_CEQPART_MAX_INDEX 15
670#define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0
671#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT)
672#define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16
673#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT)
674#define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */
675#define I40E_GLHMC_DBCQPART_MAX_INDEX 15
676#define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0
677#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT)
678#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16
679#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT)
680#define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */
681#define I40E_GLHMC_DBQPPART_MAX_INDEX 15
682#define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0
683#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT)
684#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16
685#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT)
686#define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */
687#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15 635#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15
688#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 636#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0
689#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 637#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
690#define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ 638#define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
691#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15 639#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15
692#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0 640#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0
693#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK (0xFFFFF << I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT) 641#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)
694#define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 642#define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */
695#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0 643#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0
696#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK (0xF << I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT) 644#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)
697#define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ 645#define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
698#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15 646#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15
699#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 647#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0
700#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 648#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
701#define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ 649#define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
702#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15 650#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15
703#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0 651#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0
704#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK (0x7FFFFF << I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT) 652#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)
705#define I40E_GLHMC_FCOEFMAX 0x000C20D0 653#define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */
706#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 654#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0
707#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK (0xFFFF << I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 655#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
708#define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 656#define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */
709#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0 657#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0
710#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK (0xF << I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT) 658#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)
711#define I40E_GLHMC_FCOEMAX 0x000C2014 659#define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */
712#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0 660#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0
713#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK (0x1FFF << I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT) 661#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)
714#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ 662#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
715#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15 663#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15
716#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0 664#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0
717#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT) 665#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)
718#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ 666#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
719#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15 667#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15
720#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0 668#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0
721#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT) 669#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)
722#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29 670#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29
723#define I40E_GLHMC_FSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_FSIAVCNT_RSVD_SHIFT) 671#define I40E_GLHMC_FSIAVCNT_RSVD_MASK I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)
724#define I40E_GLHMC_FSIAVMAX 0x000C2068 672#define I40E_GLHMC_FSIAVMAX 0x000C2068 /* Reset: CORER */
725#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0 673#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0
726#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK (0x1FFFF << I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT) 674#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)
727#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 675#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 /* Reset: CORER */
728#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0 676#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0
729#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK (0xF << I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT) 677#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)
730#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ 678#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
731#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15 679#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15
732#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0 680#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0
733#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT) 681#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)
734#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ 682#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
735#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15 683#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15
736#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0 684#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0
737#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK (0x1FFFFFFF << I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT) 685#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)
738#define I40E_GLHMC_FSIMCMAX 0x000C2060 686#define I40E_GLHMC_FSIMCMAX 0x000C2060 /* Reset: CORER */
739#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0 687#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0
740#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK (0x3FFF << I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT) 688#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)
741#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c 689#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c /* Reset: CORER */
742#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0 690#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0
743#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK (0xF << I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT) 691#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)
744#define I40E_GLHMC_LANQMAX 0x000C2008 692#define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */
745#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0 693#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0
746#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK (0x7FF << I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT) 694#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)
747#define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ 695#define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
748#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15 696#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15
749#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 697#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0
750#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 698#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
751#define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ 699#define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
752#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15 700#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15
753#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0 701#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0
754#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK (0x7FF << I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT) 702#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)
755#define I40E_GLHMC_LANRXOBJSZ 0x000C200c 703#define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */
756#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0 704#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0
757#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK (0xF << I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT) 705#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)
758#define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ 706#define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
759#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15 707#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15
760#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 708#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0
761#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 709#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
762#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24 710#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24
763#define I40E_GLHMC_LANTXBASE_RSVD_MASK (0xFF << I40E_GLHMC_LANTXBASE_RSVD_SHIFT) 711#define I40E_GLHMC_LANTXBASE_RSVD_MASK I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT)
764#define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ 712#define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
765#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15 713#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15
766#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0 714#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0
767#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK (0x7FF << I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT) 715#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)
768#define I40E_GLHMC_LANTXOBJSZ 0x000C2004 716#define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */
769#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0 717#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0
770#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK (0xF << I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT) 718#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)
771#define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */ 719#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
772#define I40E_GLHMC_PEARPBASE_MAX_INDEX 15
773#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0
774#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT)
775#define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */
776#define I40E_GLHMC_PEARPCNT_MAX_INDEX 15
777#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0
778#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT)
779#define I40E_GLHMC_PEARPMAX 0x000C2038
780#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0
781#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK (0x1FFFF << I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT)
782#define I40E_GLHMC_PEARPOBJSZ 0x000C2034
783#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0
784#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK (0x7 << I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT)
785#define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */
786#define I40E_GLHMC_PECQBASE_MAX_INDEX 15
787#define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0
788#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT)
789#define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */
790#define I40E_GLHMC_PECQCNT_MAX_INDEX 15
791#define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0
792#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT)
793#define I40E_GLHMC_PECQOBJSZ 0x000C2020
794#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0
795#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK (0xF << I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT)
796#define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */
797#define I40E_GLHMC_PEHTCNT_MAX_INDEX 15
798#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0
799#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT)
800#define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */
801#define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15
802#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0
803#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT)
804#define I40E_GLHMC_PEHTEOBJSZ 0x000C202c
805#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0
806#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK (0xF << I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT)
807#define I40E_GLHMC_PEHTMAX 0x000C2030
808#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0
809#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK (0x1FFFFF << I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT)
810#define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */
811#define I40E_GLHMC_PEMRBASE_MAX_INDEX 15
812#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0
813#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT)
814#define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */
815#define I40E_GLHMC_PEMRCNT_MAX_INDEX 15
816#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0
817#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT)
818#define I40E_GLHMC_PEMRMAX 0x000C2040
819#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0
820#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK (0x7FFFFF << I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT)
821#define I40E_GLHMC_PEMROBJSZ 0x000C203c
822#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0
823#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK (0xF << I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT)
824#define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */
825#define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15
826#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0
827#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT)
828#define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */
829#define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15
830#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0
831#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT)
832#define I40E_GLHMC_PEPBLMAX 0x000C206c
833#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0
834#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT)
835#define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */
836#define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15
837#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0
838#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT)
839#define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */
840#define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15
841#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0
842#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT)
843#define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */
844#define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15
845#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
846#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
847#define I40E_GLHMC_PEQ1FLCNT(_i) (0x000C5500 + ((_i) * 4)) /* _i=0...15 */
848#define I40E_GLHMC_PEQ1FLCNT_MAX_INDEX 15
849#define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0
850#define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT)
851#define I40E_GLHMC_PEQ1FLMAX 0x000C2058
852#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0
853#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
854#define I40E_GLHMC_PEQ1MAX 0x000C2054
855#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0
856#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
857#define I40E_GLHMC_PEQ1OBJSZ 0x000C2050
858#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0
859#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK (0xF << I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT)
860#define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */
861#define I40E_GLHMC_PEQPBASE_MAX_INDEX 15
862#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0
863#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT)
864#define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */
865#define I40E_GLHMC_PEQPCNT_MAX_INDEX 15
866#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0
867#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT)
868#define I40E_GLHMC_PEQPOBJSZ 0x000C201c
869#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0
870#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK (0xF << I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT)
871#define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */
872#define I40E_GLHMC_PESRQBASE_MAX_INDEX 15
873#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0
874#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT)
875#define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */
876#define I40E_GLHMC_PESRQCNT_MAX_INDEX 15
877#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0
878#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT)
879#define I40E_GLHMC_PESRQMAX 0x000C2028
880#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0
881#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK (0xFFFF << I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT)
882#define I40E_GLHMC_PESRQOBJSZ 0x000C2024
883#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0
884#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK (0xF << I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT)
885#define I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT 4
886#define I40E_GLHMC_PESRQOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT)
887#define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */
888#define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15
889#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0
890#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT)
891#define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */
892#define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15
893#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0
894#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT)
895#define I40E_GLHMC_PETIMERMAX 0x000C2084
896#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0
897#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT)
898#define I40E_GLHMC_PETIMEROBJSZ 0x000C2080
899#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0
900#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK (0xF << I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT)
901#define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */
902#define I40E_GLHMC_PEXFBASE_MAX_INDEX 15
903#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0
904#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT)
905#define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */
906#define I40E_GLHMC_PEXFCNT_MAX_INDEX 15
907#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0
908#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT)
909#define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */
910#define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15
911#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
912#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT)
913#define I40E_GLHMC_PEXFFLCNT(_i) (0x000C5100 + ((_i) * 4)) /* _i=0...15 */
914#define I40E_GLHMC_PEXFFLCNT_MAX_INDEX 15
915#define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT 0
916#define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT)
917#define I40E_GLHMC_PEXFFLMAX 0x000C204c
918#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0
919#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK (0x1FFFFFF << I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
920#define I40E_GLHMC_PEXFMAX 0x000C2048
921#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
922#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
923#define I40E_GLHMC_PEXFOBJSZ 0x000C2044
924#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0
925#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK (0xF << I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT)
926#define I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT 4
927#define I40E_GLHMC_PEXFOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT)
928#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */
929#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15 720#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15
930#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0 721#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0
931#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK (0xF << I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT) 722#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)
932#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ 723#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
933#define I40E_GLHMC_SDPART_MAX_INDEX 15 724#define I40E_GLHMC_SDPART_MAX_INDEX 15
934#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0 725#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0
935#define I40E_GLHMC_SDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_SDPART_PMSDBASE_SHIFT) 726#define I40E_GLHMC_SDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT)
936#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16 727#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16
937#define I40E_GLHMC_SDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_SDPART_PMSDSIZE_SHIFT) 728#define I40E_GLHMC_SDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)
938#define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) 729#define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */
939#define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
940#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
941#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
942#define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */
943#define I40E_GLHMC_VFCEQPART_MAX_INDEX 31
944#define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0
945#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT)
946#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16
947#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT)
948#define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */
949#define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31
950#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0
951#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT)
952#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16
953#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT)
954#define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */
955#define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31
956#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0
957#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT)
958#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16
959#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT)
960#define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */
961#define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31
962#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0
963#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT)
964#define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */
965#define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31
966#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0
967#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT)
968#define I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT 29
969#define I40E_GLHMC_VFFSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT)
970#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */
971#define I40E_GLHMC_VFPDINV_MAX_INDEX 31
972#define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0
973#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK (0xFFF << I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT)
974#define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16
975#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK (0x1FF << I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT)
976#define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */
977#define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31
978#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0
979#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT)
980#define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */
981#define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31
982#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0
983#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT)
984#define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */
985#define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31
986#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0
987#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT)
988#define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */
989#define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31
990#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0
991#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT)
992#define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */
993#define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31
994#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0
995#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT)
996#define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */
997#define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31
998#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0
999#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT)
1000#define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */
1001#define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31
1002#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0
1003#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT)
1004#define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */
1005#define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31
1006#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0
1007#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT)
1008#define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */
1009#define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31
1010#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0
1011#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT)
1012#define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */
1013#define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31
1014#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0
1015#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT)
1016#define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */
1017#define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31
1018#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0
1019#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT)
1020#define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */
1021#define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31
1022#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0
1023#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT)
1024#define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */
1025#define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
1026#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
1027#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
1028#define I40E_GLHMC_VFPEQ1FLCNT(_i) (0x000Cd500 + ((_i) * 4)) /* _i=0...31 */
1029#define I40E_GLHMC_VFPEQ1FLCNT_MAX_INDEX 31
1030#define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0
1031#define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT)
1032#define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */
1033#define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31
1034#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0
1035#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT)
1036#define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */
1037#define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31
1038#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0
1039#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT)
1040#define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */
1041#define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31
1042#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0
1043#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT)
1044#define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */
1045#define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31
1046#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0
1047#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT)
1048#define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */
1049#define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31
1050#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0
1051#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT)
1052#define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */
1053#define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31
1054#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0
1055#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT)
1056#define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */
1057#define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31
1058#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0
1059#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT)
1060#define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */
1061#define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31
1062#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0
1063#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT)
1064#define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */
1065#define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31
1066#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
1067#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT)
1068#define I40E_GLHMC_VFPEXFFLCNT(_i) (0x000Cd100 + ((_i) * 4)) /* _i=0...31 */
1069#define I40E_GLHMC_VFPEXFFLCNT_MAX_INDEX 31
1070#define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT 0
1071#define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT)
1072#define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */
1073#define I40E_GLHMC_VFSDPART_MAX_INDEX 31
1074#define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0
1075#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT)
1076#define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16
1077#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT)
1078#define I40E_PFHMC_ERRORDATA 0x000C0500
1079#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0 730#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0
1080#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK (0x3FFFFFFF << I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT) 731#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)
1081#define I40E_PFHMC_ERRORINFO 0x000C0400 732#define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */
1082#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0 733#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0
1083#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK (0x1F << I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT) 734#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)
1084#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7 735#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7
1085#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK (0x1 << I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT) 736#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT)
1086#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8 737#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8
1087#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK (0xF << I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT) 738#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT)
1088#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16 739#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16
1089#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK (0x1F << I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT) 740#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)
1090#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31 741#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31
1091#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK (0x1 << I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT) 742#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)
1092#define I40E_PFHMC_PDINV 0x000C0300 743#define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
1093#define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 744#define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
1094#define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) 745#define I40E_PFHMC_PDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
1095#define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 746#define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16
1096#define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT) 747#define I40E_PFHMC_PDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
1097#define I40E_PFHMC_SDCMD 0x000C0000 748#define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */
1098#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0 749#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0
1099#define I40E_PFHMC_SDCMD_PMSDIDX_MASK (0xFFF << I40E_PFHMC_SDCMD_PMSDIDX_SHIFT) 750#define I40E_PFHMC_SDCMD_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)
1100#define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 751#define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
1101#define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) 752#define I40E_PFHMC_SDCMD_PMSDWR_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
1102#define I40E_PFHMC_SDDATAHIGH 0x000C0200 753#define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */
1103#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0 754#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0
1104#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK (0xFFFFFFFF << I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT) 755#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)
1105#define I40E_PFHMC_SDDATALOW 0x000C0100 756#define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */
1106#define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 757#define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0
1107#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT) 758#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)
1108#define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 759#define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1
1109#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) 760#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT)
1110#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 761#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2
1111#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK (0x3FF << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) 762#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)
1112#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12 763#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12
1113#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK (0xFFFFF << I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT) 764#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)
1114#define I40E_GL_UFUSE 0x00094008 765#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */
766#define I40E_GL_GP_FUSE_MAX_INDEX 28
767#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0
768#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)
769#define I40E_GL_UFUSE 0x00094008 /* Reset: POR */
1115#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1 770#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1
1116#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK (0x1 << I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT) 771#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)
1117#define I40E_GL_UFUSE_NIC_ID_SHIFT 2 772#define I40E_GL_UFUSE_NIC_ID_SHIFT 2
1118#define I40E_GL_UFUSE_NIC_ID_MASK (0x1 << I40E_GL_UFUSE_NIC_ID_SHIFT) 773#define I40E_GL_UFUSE_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_NIC_ID_SHIFT)
1119#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10 774#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10
1120#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT) 775#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)
1121#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11 776#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11
1122#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT) 777#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)
1123#define I40E_EMPINT_GPIO_ENA 0x00088188 778#define I40E_EMPINT_GPIO_ENA 0x00088188 /* Reset: POR */
1124#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 779#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
1125#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT) 780#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)
1126#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 781#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
1127#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT) 782#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT)
1128#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 783#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
1129#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT) 784#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT)
1130#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 785#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
1131#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT) 786#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT)
1132#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 787#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
1133#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT) 788#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT)
1134#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 789#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
1135#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT) 790#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT)
1136#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 791#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
1137#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT) 792#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT)
1138#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 793#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
1139#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT) 794#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT)
1140#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 795#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
1141#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT) 796#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT)
1142#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 797#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
1143#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT) 798#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT)
1144#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 799#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
1145#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT) 800#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT)
1146#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 801#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
1147#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT) 802#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT)
1148#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 803#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
1149#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT) 804#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT)
1150#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 805#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
1151#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT) 806#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT)
1152#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 807#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
1153#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT) 808#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT)
1154#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 809#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
1155#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT) 810#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT)
1156#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 811#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
1157#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT) 812#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT)
1158#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 813#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
1159#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT) 814#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT)
1160#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 815#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
1161#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT) 816#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT)
1162#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 817#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
1163#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT) 818#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT)
1164#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 819#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
1165#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT) 820#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT)
1166#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 821#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
1167#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT) 822#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT)
1168#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 823#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
1169#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT) 824#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT)
1170#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 825#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
1171#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT) 826#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT)
1172#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 827#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
1173#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT) 828#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT)
1174#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 829#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
1175#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT) 830#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT)
1176#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 831#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
1177#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT) 832#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT)
1178#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 833#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
1179#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT) 834#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT)
1180#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 835#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
1181#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT) 836#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)
1182#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 837#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
1183#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT) 838#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)
1184#define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 839#define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */
1185#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0 840#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0
1186#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT) 841#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)
1187#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 842#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4
1188#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK (0x1 << I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 843#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
1189#define I40E_PFINT_AEQCTL 0x00038700 844#define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */
1190#define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 845#define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0
1191#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT) 846#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)
1192#define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 847#define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11
1193#define I40E_PFINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_AEQCTL_ITR_INDX_SHIFT) 848#define I40E_PFINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT)
1194#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13 849#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13
1195#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT) 850#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT)
1196#define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 851#define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30
1197#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 852#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
1198#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31 853#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31
1199#define I40E_PFINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_AEQCTL_INTEVENT_SHIFT) 854#define I40E_PFINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT)
1200#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ 855#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
1201#define I40E_PFINT_CEQCTL_MAX_INDEX 511 856#define I40E_PFINT_CEQCTL_MAX_INDEX 511
1202#define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 857#define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0
1203#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT) 858#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)
1204#define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 859#define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11
1205#define I40E_PFINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_CEQCTL_ITR_INDX_SHIFT) 860#define I40E_PFINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT)
1206#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13 861#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13
1207#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT) 862#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT)
1208#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 863#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1209#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT) 864#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT)
1210#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 865#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1211#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT) 866#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1212#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 867#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30
1213#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 868#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
1214#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31 869#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31
1215#define I40E_PFINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_CEQCTL_INTEVENT_SHIFT) 870#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
1216#define I40E_PFINT_DYN_CTL0 0x00038480 871#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */
1217#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 872#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0
1218#define I40E_PFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 873#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
1219#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 874#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1
1220#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 875#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT)
1221#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 876#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
1222#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 877#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1223#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 878#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3
1224#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 879#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)
1225#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5 880#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5
1226#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT) 881#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT)
1227#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 882#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1228#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 883#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1229#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 884#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
1230#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 885#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1231#define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 886#define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
1232#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 887#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1233#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ 888#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1234#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511 889#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511
1235#define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 890#define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0
1236#define I40E_PFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 891#define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
1237#define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 892#define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1
1238#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 893#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT)
1239#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 894#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
1240#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 895#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1241#define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 896#define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3
1242#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 897#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)
1243#define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 898#define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5
1244#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT) 899#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)
1245#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 900#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1246#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 901#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1247#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 902#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
1248#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 903#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1249#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 904#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
1250#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT) 905#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1251#define I40E_PFINT_GPIO_ENA 0x00088080 906#define I40E_PFINT_GPIO_ENA 0x00088080 /* Reset: CORER */
1252#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 907#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
1253#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT) 908#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)
1254#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 909#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
1255#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT) 910#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT)
1256#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 911#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
1257#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT) 912#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT)
1258#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 913#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
1259#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT) 914#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT)
1260#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 915#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
1261#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT) 916#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT)
1262#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 917#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
1263#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT) 918#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT)
1264#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 919#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
1265#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT) 920#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT)
1266#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 921#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
1267#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT) 922#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT)
1268#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 923#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
1269#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT) 924#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT)
1270#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 925#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
1271#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT) 926#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT)
1272#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 927#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
1273#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT) 928#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT)
1274#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 929#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
1275#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT) 930#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT)
1276#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 931#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
1277#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT) 932#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT)
1278#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 933#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
1279#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT) 934#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT)
1280#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 935#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
1281#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT) 936#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT)
1282#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 937#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
1283#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT) 938#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT)
1284#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 939#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
1285#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT) 940#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT)
1286#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 941#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
1287#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT) 942#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT)
1288#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 943#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
1289#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT) 944#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT)
1290#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 945#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
1291#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT) 946#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT)
1292#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 947#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
1293#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT) 948#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT)
1294#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 949#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
1295#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT) 950#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT)
1296#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 951#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
1297#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT) 952#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT)
1298#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 953#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
1299#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT) 954#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT)
1300#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 955#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
1301#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT) 956#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT)
1302#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 957#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
1303#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT) 958#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT)
1304#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 959#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
1305#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT) 960#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT)
1306#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 961#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
1307#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT) 962#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT)
1308#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 963#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
1309#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT) 964#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)
1310#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 965#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
1311#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT) 966#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)
1312#define I40E_PFINT_ICR0 0x00038780 967#define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */
1313#define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 968#define I40E_PFINT_ICR0_INTEVENT_SHIFT 0
1314#define I40E_PFINT_ICR0_INTEVENT_MASK (0x1 << I40E_PFINT_ICR0_INTEVENT_SHIFT) 969#define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT)
1315#define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 970#define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1
1316#define I40E_PFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_0_SHIFT) 971#define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT)
1317#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2 972#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2
1318#define I40E_PFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_1_SHIFT) 973#define I40E_PFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_1_SHIFT)
1319#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3 974#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3
1320#define I40E_PFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_2_SHIFT) 975#define I40E_PFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_2_SHIFT)
1321#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4 976#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4
1322#define I40E_PFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_3_SHIFT) 977#define I40E_PFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_3_SHIFT)
1323#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5 978#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5
1324#define I40E_PFINT_ICR0_QUEUE_4_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_4_SHIFT) 979#define I40E_PFINT_ICR0_QUEUE_4_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_4_SHIFT)
1325#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6 980#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6
1326#define I40E_PFINT_ICR0_QUEUE_5_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_5_SHIFT) 981#define I40E_PFINT_ICR0_QUEUE_5_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_5_SHIFT)
1327#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7 982#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7
1328#define I40E_PFINT_ICR0_QUEUE_6_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_6_SHIFT) 983#define I40E_PFINT_ICR0_QUEUE_6_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_6_SHIFT)
1329#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8 984#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8
1330#define I40E_PFINT_ICR0_QUEUE_7_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_7_SHIFT) 985#define I40E_PFINT_ICR0_QUEUE_7_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_7_SHIFT)
1331#define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 986#define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16
1332#define I40E_PFINT_ICR0_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ECC_ERR_SHIFT) 987#define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT)
1333#define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 988#define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19
1334#define I40E_PFINT_ICR0_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_MAL_DETECT_SHIFT) 989#define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT)
1335#define I40E_PFINT_ICR0_GRST_SHIFT 20 990#define I40E_PFINT_ICR0_GRST_SHIFT 20
1336#define I40E_PFINT_ICR0_GRST_MASK (0x1 << I40E_PFINT_ICR0_GRST_SHIFT) 991#define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT)
1337#define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 992#define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21
1338#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 993#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)
1339#define I40E_PFINT_ICR0_GPIO_SHIFT 22 994#define I40E_PFINT_ICR0_GPIO_SHIFT 22
1340#define I40E_PFINT_ICR0_GPIO_MASK (0x1 << I40E_PFINT_ICR0_GPIO_SHIFT) 995#define I40E_PFINT_ICR0_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GPIO_SHIFT)
1341#define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 996#define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23
1342#define I40E_PFINT_ICR0_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_TIMESYNC_SHIFT) 997#define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT)
998#define I40E_PFINT_ICR0_STORM_DETECT_SHIFT 24
999#define I40E_PFINT_ICR0_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_STORM_DETECT_SHIFT)
1343#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 1000#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1344#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 1001#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1345#define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 1002#define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26
1346#define I40E_PFINT_ICR0_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_HMC_ERR_SHIFT) 1003#define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT)
1347#define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 1004#define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28
1348#define I40E_PFINT_ICR0_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_PE_CRITERR_SHIFT) 1005#define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT)
1349#define I40E_PFINT_ICR0_VFLR_SHIFT 29 1006#define I40E_PFINT_ICR0_VFLR_SHIFT 29
1350#define I40E_PFINT_ICR0_VFLR_MASK (0x1 << I40E_PFINT_ICR0_VFLR_SHIFT) 1007#define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT)
1351#define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 1008#define I40E_PFINT_ICR0_ADMINQ_SHIFT 30
1352#define I40E_PFINT_ICR0_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ADMINQ_SHIFT) 1009#define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT)
1353#define I40E_PFINT_ICR0_SWINT_SHIFT 31 1010#define I40E_PFINT_ICR0_SWINT_SHIFT 31
1354#define I40E_PFINT_ICR0_SWINT_MASK (0x1 << I40E_PFINT_ICR0_SWINT_SHIFT) 1011#define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT)
1355#define I40E_PFINT_ICR0_ENA 0x00038800 1012#define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */
1356#define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 1013#define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16
1357#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) 1014#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)
1358#define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 1015#define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19
1359#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) 1016#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT)
1360#define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 1017#define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20
1361#define I40E_PFINT_ICR0_ENA_GRST_MASK (0x1 << I40E_PFINT_ICR0_ENA_GRST_SHIFT) 1018#define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT)
1362#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 1019#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21
1363#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) 1020#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT)
1364#define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 1021#define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22
1365#define I40E_PFINT_ICR0_ENA_GPIO_MASK (0x1 << I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 1022#define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT)
1366#define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 1023#define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23
1367#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 1024#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)
1025#define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT 24
1026#define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT)
1368#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 1027#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1369#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 1028#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1370#define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 1029#define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26
1371#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 1030#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)
1372#define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 1031#define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28
1373#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) 1032#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT)
1374#define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 1033#define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29
1375#define I40E_PFINT_ICR0_ENA_VFLR_MASK (0x1 << I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 1034#define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT)
1376#define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 1035#define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30
1377#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 1036#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
1378#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31 1037#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31
1379#define I40E_PFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_PFINT_ICR0_ENA_RSVD_SHIFT) 1038#define I40E_PFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT)
1380#define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ 1039#define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */
1381#define I40E_PFINT_ITR0_MAX_INDEX 2 1040#define I40E_PFINT_ITR0_MAX_INDEX 2
1382#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0 1041#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0
1383#define I40E_PFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_PFINT_ITR0_INTERVAL_SHIFT) 1042#define I40E_PFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT)
1384#define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) 1043#define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */
1385#define I40E_PFINT_ITRN_MAX_INDEX 2 1044#define I40E_PFINT_ITRN_MAX_INDEX 2
1386#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0 1045#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0
1387#define I40E_PFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_PFINT_ITRN_INTERVAL_SHIFT) 1046#define I40E_PFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT)
1388#define I40E_PFINT_LNKLST0 0x00038500 1047#define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */
1389#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 1048#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1390#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) 1049#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1391#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 1050#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1392#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 1051#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1393#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ 1052#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1394#define I40E_PFINT_LNKLSTN_MAX_INDEX 511 1053#define I40E_PFINT_LNKLSTN_MAX_INDEX 511
1395#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 1054#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1396#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 1055#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1397#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 1056#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1398#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 1057#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1399#define I40E_PFINT_RATE0 0x00038580 1058#define I40E_PFINT_RATE0 0x00038580 /* Reset: PFR */
1400#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0 1059#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0
1401#define I40E_PFINT_RATE0_INTERVAL_MASK (0x3F << I40E_PFINT_RATE0_INTERVAL_SHIFT) 1060#define I40E_PFINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT)
1402#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6 1061#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6
1403#define I40E_PFINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATE0_INTRL_ENA_SHIFT) 1062#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT)
1404#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ 1063#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1405#define I40E_PFINT_RATEN_MAX_INDEX 511 1064#define I40E_PFINT_RATEN_MAX_INDEX 511
1406#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0 1065#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0
1407#define I40E_PFINT_RATEN_INTERVAL_MASK (0x3F << I40E_PFINT_RATEN_INTERVAL_SHIFT) 1066#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
1408#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 1067#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
1409#define I40E_PFINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATEN_INTRL_ENA_SHIFT) 1068#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
1410#define I40E_PFINT_STAT_CTL0 0x00038400 1069#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: PFR */
1411#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1070#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1412#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1071#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1413#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ 1072#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1414#define I40E_QINT_RQCTL_MAX_INDEX 1535 1073#define I40E_QINT_RQCTL_MAX_INDEX 1535
1415#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 1074#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0
1416#define I40E_QINT_RQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 1075#define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
1417#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 1076#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11
1418#define I40E_QINT_RQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_RQCTL_ITR_INDX_SHIFT) 1077#define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT)
1419#define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 1078#define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13
1420#define I40E_QINT_RQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) 1079#define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT)
1421#define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 1080#define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16
1422#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 1081#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)
1423#define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 1082#define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27
1424#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) 1083#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)
1425#define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 1084#define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30
1426#define I40E_QINT_RQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 1085#define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
1427#define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 1086#define I40E_QINT_RQCTL_INTEVENT_SHIFT 31
1428#define I40E_QINT_RQCTL_INTEVENT_MASK (0x1 << I40E_QINT_RQCTL_INTEVENT_SHIFT) 1087#define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT)
1429#define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ 1088#define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1430#define I40E_QINT_TQCTL_MAX_INDEX 1535 1089#define I40E_QINT_TQCTL_MAX_INDEX 1535
1431#define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 1090#define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0
1432#define I40E_QINT_TQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 1091#define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
1433#define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 1092#define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11
1434#define I40E_QINT_TQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_TQCTL_ITR_INDX_SHIFT) 1093#define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT)
1435#define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 1094#define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13
1436#define I40E_QINT_TQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) 1095#define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT)
1437#define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 1096#define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16
1438#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 1097#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)
1439#define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 1098#define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27
1440#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) 1099#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)
1441#define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 1100#define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30
1442#define I40E_QINT_TQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 1101#define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
1443#define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 1102#define I40E_QINT_TQCTL_INTEVENT_SHIFT 31
1444#define I40E_QINT_TQCTL_INTEVENT_MASK (0x1 << I40E_QINT_TQCTL_INTEVENT_SHIFT) 1103#define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT)
1445#define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ 1104#define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1446#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127 1105#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127
1447#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0 1106#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0
1448#define I40E_VFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_SHIFT) 1107#define I40E_VFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT)
1449#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1 1108#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1
1450#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT) 1109#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT)
1451#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 1110#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
1452#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 1111#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1453#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3 1112#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3
1454#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) 1113#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)
1455#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5 1114#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5
1456#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT) 1115#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)
1457#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 1116#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1458#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 1117#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1459#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 1118#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
1460#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 1119#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1461#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 1120#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
1462#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT) 1121#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1463#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ 1122#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1464#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511 1123#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511
1465#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0 1124#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0
1466#define I40E_VFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_SHIFT) 1125#define I40E_VFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT)
1467#define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 1126#define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1
1468#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 1127#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)
1469#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 1128#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
1470#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 1129#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1471#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3 1130#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3
1472#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) 1131#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT)
1473#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5 1132#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5
1474#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT) 1133#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT)
1475#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 1134#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1476#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 1135#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1477#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 1136#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
1478#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 1137#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1479#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 1138#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
1480#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT) 1139#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1481#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ 1140#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1482#define I40E_VFINT_ICR0_MAX_INDEX 127 1141#define I40E_VFINT_ICR0_MAX_INDEX 127
1483#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0 1142#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0
1484#define I40E_VFINT_ICR0_INTEVENT_MASK (0x1 << I40E_VFINT_ICR0_INTEVENT_SHIFT) 1143#define I40E_VFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT)
1485#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1 1144#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1
1486#define I40E_VFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_0_SHIFT) 1145#define I40E_VFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_0_SHIFT)
1487#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2 1146#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2
1488#define I40E_VFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_1_SHIFT) 1147#define I40E_VFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_1_SHIFT)
1489#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3 1148#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3
1490#define I40E_VFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_2_SHIFT) 1149#define I40E_VFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_2_SHIFT)
1491#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4 1150#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4
1492#define I40E_VFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_3_SHIFT) 1151#define I40E_VFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_3_SHIFT)
1493#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 1152#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1494#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 1153#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1495#define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 1154#define I40E_VFINT_ICR0_ADMINQ_SHIFT 30
1496#define I40E_VFINT_ICR0_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ADMINQ_SHIFT) 1155#define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT)
1497#define I40E_VFINT_ICR0_SWINT_SHIFT 31 1156#define I40E_VFINT_ICR0_SWINT_SHIFT 31
1498#define I40E_VFINT_ICR0_SWINT_MASK (0x1 << I40E_VFINT_ICR0_SWINT_SHIFT) 1157#define I40E_VFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT)
1499#define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ 1158#define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1500#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127 1159#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127
1501#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 1160#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1502#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 1161#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1503#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30 1162#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30
1504#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT) 1163#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)
1505#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31 1164#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31
1506#define I40E_VFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA_RSVD_SHIFT) 1165#define I40E_VFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT)
1507#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ 1166#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */
1508#define I40E_VFINT_ITR0_MAX_INDEX 2 1167#define I40E_VFINT_ITR0_MAX_INDEX 2
1509#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0 1168#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0
1510#define I40E_VFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR0_INTERVAL_SHIFT) 1169#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT)
1511#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) 1170#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */
1512#define I40E_VFINT_ITRN_MAX_INDEX 2 1171#define I40E_VFINT_ITRN_MAX_INDEX 2
1513#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 1172#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
1514#define I40E_VFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN_INTERVAL_SHIFT) 1173#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
1515#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ 1174#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1516#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 1175#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127
1517#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1176#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1518#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1177#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1519#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ 1178#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1520#define I40E_VPINT_AEQCTL_MAX_INDEX 127 1179#define I40E_VPINT_AEQCTL_MAX_INDEX 127
1521#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 1180#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0
1522#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) 1181#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)
1523#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 1182#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11
1524#define I40E_VPINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_AEQCTL_ITR_INDX_SHIFT) 1183#define I40E_VPINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT)
1525#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13 1184#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13
1526#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT) 1185#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT)
1527#define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 1186#define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30
1528#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 1187#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
1529#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31 1188#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31
1530#define I40E_VPINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_AEQCTL_INTEVENT_SHIFT) 1189#define I40E_VPINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT)
1531#define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ 1190#define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */
1532#define I40E_VPINT_CEQCTL_MAX_INDEX 511 1191#define I40E_VPINT_CEQCTL_MAX_INDEX 511
1533#define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 1192#define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0
1534#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT) 1193#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)
1535#define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 1194#define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11
1536#define I40E_VPINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_CEQCTL_ITR_INDX_SHIFT) 1195#define I40E_VPINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT)
1537#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13 1196#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13
1538#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT) 1197#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT)
1539#define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 1198#define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1540#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 1199#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)
1541#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 1200#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1542#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 1201#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1543#define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 1202#define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30
1544#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 1203#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
1545#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31 1204#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31
1546#define I40E_VPINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_CEQCTL_INTEVENT_SHIFT) 1205#define I40E_VPINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT)
1547#define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ 1206#define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1548#define I40E_VPINT_LNKLST0_MAX_INDEX 127 1207#define I40E_VPINT_LNKLST0_MAX_INDEX 127
1549#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 1208#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1550#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 1209#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1551#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 1210#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1552#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 1211#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1553#define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ 1212#define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1554#define I40E_VPINT_LNKLSTN_MAX_INDEX 511 1213#define I40E_VPINT_LNKLSTN_MAX_INDEX 511
1555#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 1214#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1556#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 1215#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1557#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 1216#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1558#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 1217#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1559#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ 1218#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1560#define I40E_VPINT_RATE0_MAX_INDEX 127 1219#define I40E_VPINT_RATE0_MAX_INDEX 127
1561#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0 1220#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0
1562#define I40E_VPINT_RATE0_INTERVAL_MASK (0x3F << I40E_VPINT_RATE0_INTERVAL_SHIFT) 1221#define I40E_VPINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT)
1563#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6 1222#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6
1564#define I40E_VPINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATE0_INTRL_ENA_SHIFT) 1223#define I40E_VPINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT)
1565#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ 1224#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1566#define I40E_VPINT_RATEN_MAX_INDEX 511 1225#define I40E_VPINT_RATEN_MAX_INDEX 511
1567#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0 1226#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0
1568#define I40E_VPINT_RATEN_INTERVAL_MASK (0x3F << I40E_VPINT_RATEN_INTERVAL_SHIFT) 1227#define I40E_VPINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT)
1569#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6 1228#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6
1570#define I40E_VPINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATEN_INTRL_ENA_SHIFT) 1229#define I40E_VPINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT)
1571#define I40E_GL_RDPU_CNTRL 0x00051060 1230#define I40E_GL_RDPU_CNTRL 0x00051060 /* Reset: CORER */
1572#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0 1231#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0
1573#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK (0x1 << I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT) 1232#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)
1574#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1 1233#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1
1575#define I40E_GL_RDPU_CNTRL_ECO_MASK (0x7FFFFFFF << I40E_GL_RDPU_CNTRL_ECO_SHIFT) 1234#define I40E_GL_RDPU_CNTRL_ECO_MASK I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT)
1576#define I40E_GLLAN_RCTL_0 0x0012A500 1235#define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */
1577#define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 1236#define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0
1578#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK (0x1 << I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 1237#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
1579#define I40E_GLLAN_TSOMSK_F 0x000442D8 1238#define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */
1580#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0 1239#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0
1581#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK (0xFFF << I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT) 1240#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)
1582#define I40E_GLLAN_TSOMSK_L 0x000442E0 1241#define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */
1583#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0 1242#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0
1584#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK (0xFFF << I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT) 1243#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)
1585#define I40E_GLLAN_TSOMSK_M 0x000442DC 1244#define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */
1586#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0 1245#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0
1587#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK (0xFFF << I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT) 1246#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)
1588#define I40E_GLLAN_TXPRE_QDIS(_i) (0x000E6500 + ((_i) * 4)) /* i=0..11 */ 1247#define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */
1248#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11
1589#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 1249#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0
1590#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK (0x7FF << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 1250#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
1251#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16
1252#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)
1591#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 1253#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30
1592#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 1254#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
1593#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 1255#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
1594#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) 1256#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
1595 1257#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */
1596#define I40E_PFLAN_QALLOC 0x001C0400
1597#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 1258#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
1598#define I40E_PFLAN_QALLOC_FIRSTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 1259#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
1599#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 1260#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
1600#define I40E_PFLAN_QALLOC_LASTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_LASTQ_SHIFT) 1261#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
1601#define I40E_PFLAN_QALLOC_VALID_SHIFT 31 1262#define I40E_PFLAN_QALLOC_VALID_SHIFT 31
1602#define I40E_PFLAN_QALLOC_VALID_MASK (0x1 << I40E_PFLAN_QALLOC_VALID_SHIFT) 1263#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)
1603#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ 1264#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1604#define I40E_QRX_ENA_MAX_INDEX 1535 1265#define I40E_QRX_ENA_MAX_INDEX 1535
1605#define I40E_QRX_ENA_QENA_REQ_SHIFT 0 1266#define I40E_QRX_ENA_QENA_REQ_SHIFT 0
1606#define I40E_QRX_ENA_QENA_REQ_MASK (0x1 << I40E_QRX_ENA_QENA_REQ_SHIFT) 1267#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)
1607#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 1268#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1
1608#define I40E_QRX_ENA_FAST_QDIS_MASK (0x1 << I40E_QRX_ENA_FAST_QDIS_SHIFT) 1269#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)
1609#define I40E_QRX_ENA_QENA_STAT_SHIFT 2 1270#define I40E_QRX_ENA_QENA_STAT_SHIFT 2
1610#define I40E_QRX_ENA_QENA_STAT_MASK (0x1 << I40E_QRX_ENA_QENA_STAT_SHIFT) 1271#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)
1611#define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ 1272#define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1612#define I40E_QRX_TAIL_MAX_INDEX 1535 1273#define I40E_QRX_TAIL_MAX_INDEX 1535
1613#define I40E_QRX_TAIL_TAIL_SHIFT 0 1274#define I40E_QRX_TAIL_TAIL_SHIFT 0
1614#define I40E_QRX_TAIL_TAIL_MASK (0x1FFF << I40E_QRX_TAIL_TAIL_SHIFT) 1275#define I40E_QRX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT)
1615#define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ 1276#define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1616#define I40E_QTX_CTL_MAX_INDEX 1535 1277#define I40E_QTX_CTL_MAX_INDEX 1535
1617#define I40E_QTX_CTL_PFVF_Q_SHIFT 0 1278#define I40E_QTX_CTL_PFVF_Q_SHIFT 0
1618#define I40E_QTX_CTL_PFVF_Q_MASK (0x3 << I40E_QTX_CTL_PFVF_Q_SHIFT) 1279#define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)
1619#define I40E_QTX_CTL_PF_INDX_SHIFT 2 1280#define I40E_QTX_CTL_PF_INDX_SHIFT 2
1620#define I40E_QTX_CTL_PF_INDX_MASK (0xF << I40E_QTX_CTL_PF_INDX_SHIFT) 1281#define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT)
1621#define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 1282#define I40E_QTX_CTL_VFVM_INDX_SHIFT 7
1622#define I40E_QTX_CTL_VFVM_INDX_MASK (0x1FF << I40E_QTX_CTL_VFVM_INDX_SHIFT) 1283#define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)
1623#define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ 1284#define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1624#define I40E_QTX_ENA_MAX_INDEX 1535 1285#define I40E_QTX_ENA_MAX_INDEX 1535
1625#define I40E_QTX_ENA_QENA_REQ_SHIFT 0 1286#define I40E_QTX_ENA_QENA_REQ_SHIFT 0
1626#define I40E_QTX_ENA_QENA_REQ_MASK (0x1 << I40E_QTX_ENA_QENA_REQ_SHIFT) 1287#define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT)
1627#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1 1288#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1
1628#define I40E_QTX_ENA_FAST_QDIS_MASK (0x1 << I40E_QTX_ENA_FAST_QDIS_SHIFT) 1289#define I40E_QTX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT)
1629#define I40E_QTX_ENA_QENA_STAT_SHIFT 2 1290#define I40E_QTX_ENA_QENA_STAT_SHIFT 2
1630#define I40E_QTX_ENA_QENA_STAT_MASK (0x1 << I40E_QTX_ENA_QENA_STAT_SHIFT) 1291#define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT)
1631#define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ 1292#define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1632#define I40E_QTX_HEAD_MAX_INDEX 1535 1293#define I40E_QTX_HEAD_MAX_INDEX 1535
1633#define I40E_QTX_HEAD_HEAD_SHIFT 0 1294#define I40E_QTX_HEAD_HEAD_SHIFT 0
1634#define I40E_QTX_HEAD_HEAD_MASK (0x1FFF << I40E_QTX_HEAD_HEAD_SHIFT) 1295#define I40E_QTX_HEAD_HEAD_MASK I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT)
1635#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16 1296#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16
1636#define I40E_QTX_HEAD_RS_PENDING_MASK (0x1 << I40E_QTX_HEAD_RS_PENDING_SHIFT) 1297#define I40E_QTX_HEAD_RS_PENDING_MASK I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT)
1637#define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ 1298#define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1638#define I40E_QTX_TAIL_MAX_INDEX 1535 1299#define I40E_QTX_TAIL_MAX_INDEX 1535
1639#define I40E_QTX_TAIL_TAIL_SHIFT 0 1300#define I40E_QTX_TAIL_TAIL_SHIFT 0
1640#define I40E_QTX_TAIL_TAIL_MASK (0x1FFF << I40E_QTX_TAIL_TAIL_SHIFT) 1301#define I40E_QTX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT)
1641#define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ 1302#define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1642#define I40E_VPLAN_MAPENA_MAX_INDEX 127 1303#define I40E_VPLAN_MAPENA_MAX_INDEX 127
1643#define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 1304#define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0
1644#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK (0x1 << I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 1305#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
1645#define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ 1306#define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */
1646#define I40E_VPLAN_QTABLE_MAX_INDEX 15 1307#define I40E_VPLAN_QTABLE_MAX_INDEX 15
1647#define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 1308#define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0
1648#define I40E_VPLAN_QTABLE_QINDEX_MASK (0x7FF << I40E_VPLAN_QTABLE_QINDEX_SHIFT) 1309#define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)
1649#define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ 1310#define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
1650#define I40E_VSILAN_QBASE_MAX_INDEX 383 1311#define I40E_VSILAN_QBASE_MAX_INDEX 383
1651#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0 1312#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0
1652#define I40E_VSILAN_QBASE_VSIBASE_MASK (0x7FF << I40E_VSILAN_QBASE_VSIBASE_SHIFT) 1313#define I40E_VSILAN_QBASE_VSIBASE_MASK I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT)
1653#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 1314#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
1654#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK (0x1 << I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 1315#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
1655#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) 1316#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */
1656#define I40E_VSILAN_QTABLE_MAX_INDEX 7 1317#define I40E_VSILAN_QTABLE_MAX_INDEX 7
1657#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0 1318#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0
1658#define I40E_VSILAN_QTABLE_QINDEX_0_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_0_SHIFT) 1319#define I40E_VSILAN_QTABLE_QINDEX_0_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
1659#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16 1320#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16
1660#define I40E_VSILAN_QTABLE_QINDEX_1_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) 1321#define I40E_VSILAN_QTABLE_QINDEX_1_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)
1661#define I40E_PRTGL_SAH 0x001E2140 1322#define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */
1662#define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 1323#define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
1663#define I40E_PRTGL_SAH_FC_SAH_MASK (0xFFFF << I40E_PRTGL_SAH_FC_SAH_SHIFT) 1324#define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
1664#define I40E_PRTGL_SAH_MFS_SHIFT 16 1325#define I40E_PRTGL_SAH_MFS_SHIFT 16
1665#define I40E_PRTGL_SAH_MFS_MASK (0xFFFF << I40E_PRTGL_SAH_MFS_SHIFT) 1326#define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT)
1666#define I40E_PRTGL_SAL 0x001E2120 1327#define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */
1667#define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 1328#define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
1668#define I40E_PRTGL_SAL_FC_SAL_MASK (0xFFFFFFFF << I40E_PRTGL_SAL_FC_SAL_SHIFT) 1329#define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
1669#define I40E_PRTMAC_HLCTLA 0x001E4760 1330#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 /* Reset: GLOBR */
1670#define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT 0
1671#define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT)
1672#define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT 1
1673#define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_MASK (0x1 << I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT)
1674#define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT 2
1675#define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT)
1676#define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT 4
1677#define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT)
1678#define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT 7
1679#define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT)
1680#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP 0x001E3130
1681#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT 0
1682#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT)
1683#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP 0x001E3290
1684#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT 0
1685#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT)
1686#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP 0x001E3310
1687#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT 0
1688#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT)
1689#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP 0x001E3100
1690#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT 0
1691#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT)
1692#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP 0x001E3280
1693#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT 0
1694#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT)
1695#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP 0x001E3300
1696#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT 0
1697#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT)
1698#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0
1699#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0 1331#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0
1700#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT) 1332#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)
1701#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 1333#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */
1702#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0 1334#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0
1703#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT) 1335#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
1704#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 1336#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */
1705#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0 1337#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0
1706#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT) 1338#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
1707#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 1339#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 /* Reset: GLOBR */
1708#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0 1340#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0
1709#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT) 1341#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)
1710#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 1342#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 /* Reset: GLOBR */
1711#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0 1343#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0
1712#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT) 1344#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)
1713#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 1345#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 /* Reset: GLOBR */
1714#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0 1346#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0
1715#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT) 1347#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)
1716#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 1348#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */
1717#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0 1349#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0
1718#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) 1350#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
1719#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 1351#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 /* Reset: GLOBR */
1720#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0 1352#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0
1721#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT) 1353#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)
1722#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 1354#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 /* Reset: GLOBR */
1723#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0 1355#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0
1724#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT) 1356#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)
1725#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE 0x001E3000 1357#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */
1726#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT 0
1727#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT)
1728#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0
1729#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0 1358#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0
1730#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) 1359#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
1731#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) 1360#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1732#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8 1361#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
1733#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0 1362#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0
1734#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT) 1363#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)
1735#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) 1364#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1736#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 1365#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
1737#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0 1366#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0
1738#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) 1367#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
1739#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 1368#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 /* Reset: GLOBR */
1740#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0 1369#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0
1741#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT) 1370#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)
1742#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 1371#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 /* Reset: GLOBR */
1743#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0 1372#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0
1744#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT) 1373#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)
1745#define I40E_PRTMAC_HSECTL1 0x001E3560 1374#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 /* Reset: GLOBR */
1746#define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT 0
1747#define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT)
1748#define I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT 3
1749#define I40E_PRTMAC_HSECTL1_PAD_US_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT)
1750#define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT 4
1751#define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT)
1752#define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT 7
1753#define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT)
1754#define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT 30
1755#define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT)
1756#define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT 31
1757#define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT)
1758#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480
1759#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0 1375#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0
1760#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT) 1376#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)
1761#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2 1377#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2
1762#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT) 1378#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT)
1763#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4 1379#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4
1764#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT) 1380#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT)
1765#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6 1381#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6
1766#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT) 1382#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT)
1767#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8 1383#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8
1768#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT) 1384#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT)
1769#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10 1385#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10
1770#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT) 1386#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT)
1771#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12 1387#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12
1772#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT) 1388#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)
1773#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14 1389#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14
1774#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT) 1390#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)
1775#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 1391#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 /* Reset: GLOBR */
1776#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0 1392#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0
1777#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT) 1393#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)
1778#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2 1394#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2
1779#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT) 1395#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT)
1780#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4 1396#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4
1781#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT) 1397#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT)
1782#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6 1398#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6
1783#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT) 1399#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT)
1784#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8 1400#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8
1785#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT) 1401#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT)
1786#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10 1402#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10
1787#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT) 1403#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT)
1788#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12 1404#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12
1789#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT) 1405#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
1790#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14 1406#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
1791#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT) 1407#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
1792#define I40E_GL_MNG_FWSM 0x000B6134 1408#define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */
1793#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 1 1409#define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0
1794#define I40E_GL_MNG_FWSM_FW_MODES_MASK (0x7 << I40E_GL_MNG_FWSM_FW_MODES_SHIFT) 1410#define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)
1795#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 6 1411#define I40E_GL_MNG_FWSM 0x000B6134 /* Reset: POR */
1796#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK (0x1 << I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT) 1412#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0
1413#define I40E_GL_MNG_FWSM_FW_MODES_MASK I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
1414#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10
1415#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)
1797#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11 1416#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11
1798#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK (0xF << I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT) 1417#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)
1799#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15 1418#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15
1800#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK (0x1 << I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT) 1419#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)
1801#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16 1420#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16
1802#define I40E_GL_MNG_FWSM_RESET_CNT_MASK (0x7 << I40E_GL_MNG_FWSM_RESET_CNT_SHIFT) 1421#define I40E_GL_MNG_FWSM_RESET_CNT_MASK I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT)
1803#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19 1422#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19
1804#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK (0x3F << I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT) 1423#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)
1805#define I40E_GL_MNG_FWSM_RSVD_SHIFT 25
1806#define I40E_GL_MNG_FWSM_RSVD_MASK (0x1 << I40E_GL_MNG_FWSM_RSVD_SHIFT)
1807#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26 1424#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26
1808#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT) 1425#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)
1809#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27 1426#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27
1810#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT) 1427#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT)
1811#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28 1428#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28
1812#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT) 1429#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)
1813#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29 1430#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29
1814#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT) 1431#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)
1815#define I40E_GL_MNG_HWARB_CTRL 0x000B6130 1432#define I40E_GL_MNG_HWARB_CTRL 0x000B6130 /* Reset: POR */
1816#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0 1433#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0
1817#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK (0x1 << I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT) 1434#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)
1818#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ 1435#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */
1819#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31 1436#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31
1820#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0 1437#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0
1821#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK (0xFFFFFFFF << I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT) 1438#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)
1822#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 1439#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 /* Reset: POR */
1823#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0 1440#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0
1824#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK (0xFF << I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT) 1441#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)
1825#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ 1442#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1826#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7 1443#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7
1827#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0 1444#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0
1828#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK (0xFFFF << I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT) 1445#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)
1829#define I40E_PRT_MNG_MANC 0x00256A20 1446#define I40E_PRT_MNG_MANC 0x00256A20 /* Reset: POR */
1830#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0 1447#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0
1831#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT) 1448#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)
1832#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1 1449#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1
1833#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT) 1450#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT)
1834#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17 1451#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17
1835#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT) 1452#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT)
1836#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19 1453#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19
1837#define I40E_PRT_MNG_MANC_RCV_ALL_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_ALL_SHIFT) 1454#define I40E_PRT_MNG_MANC_RCV_ALL_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT)
1838#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25 1455#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25
1839#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT) 1456#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT)
1840#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26 1457#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26
1841#define I40E_PRT_MNG_MANC_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_NET_TYPE_SHIFT) 1458#define I40E_PRT_MNG_MANC_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT)
1842#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28 1459#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28
1843#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT) 1460#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)
1844#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29 1461#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29
1845#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT) 1462#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)
1846#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ 1463#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1847#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7 1464#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7
1848#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0 1465#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0
1849#define I40E_PRT_MNG_MAVTV_VID_MASK (0xFFF << I40E_PRT_MNG_MAVTV_VID_SHIFT) 1466#define I40E_PRT_MNG_MAVTV_VID_MASK I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT)
1850#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) 1467#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1851#define I40E_PRT_MNG_MDEF_MAX_INDEX 7 1468#define I40E_PRT_MNG_MDEF_MAX_INDEX 7
1852#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0 1469#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0
1853#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT) 1470#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)
1854#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4 1471#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4
1855#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT) 1472#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT)
1856#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5 1473#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5
1857#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK (0xFF << I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT) 1474#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT)
1858#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13 1475#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13
1859#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT) 1476#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT)
1860#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17 1477#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17
1861#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT) 1478#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT)
1862#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21 1479#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21
1863#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT) 1480#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT)
1864#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25 1481#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25
1865#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT) 1482#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT)
1866#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26 1483#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26
1867#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT) 1484#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT)
1868#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27 1485#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27
1869#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT) 1486#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT)
1870#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28 1487#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28
1871#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT) 1488#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT)
1872#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29 1489#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29
1873#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT) 1490#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT)
1874#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30 1491#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30
1875#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT) 1492#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)
1876#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31 1493#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31
1877#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT) 1494#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)
1878#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) 1495#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1879#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7 1496#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7
1880#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0 1497#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0
1881#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT) 1498#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)
1882#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4 1499#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4
1883#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT) 1500#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT)
1884#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8 1501#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8
1885#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK (0xFFFF << I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT) 1502#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT)
1886#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24 1503#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24
1887#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT) 1504#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT)
1888#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25 1505#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25
1889#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT) 1506#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT)
1890#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26 1507#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26
1891#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT) 1508#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT)
1892#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27 1509#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27
1893#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT) 1510#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT)
1894#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28 1511#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28
1895#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT) 1512#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT)
1896#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29 1513#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29
1897#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT) 1514#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT)
1898#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30 1515#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30
1899#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT) 1516#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)
1900#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31 1517#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31
1901#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT) 1518#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)
1902#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ 1519#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1903#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3 1520#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3
1904#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0 1521#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0
1905#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT) 1522#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
1906#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16 1523#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16
1907#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT) 1524#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
1908#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ 1525#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1909#define I40E_PRT_MNG_METF_MAX_INDEX 3 1526#define I40E_PRT_MNG_METF_MAX_INDEX 3
1910#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0 1527#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0
1911#define I40E_PRT_MNG_METF_ETYPE_MASK (0xFFFF << I40E_PRT_MNG_METF_ETYPE_SHIFT) 1528#define I40E_PRT_MNG_METF_ETYPE_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT)
1912#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30 1529#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30
1913#define I40E_PRT_MNG_METF_POLARITY_MASK (0x1 << I40E_PRT_MNG_METF_POLARITY_SHIFT) 1530#define I40E_PRT_MNG_METF_POLARITY_MASK I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT)
1914#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ 1531#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1915#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15 1532#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15
1916#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0 1533#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0
1917#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK (0xFFFF << I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT) 1534#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)
1918#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16 1535#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16
1919#define I40E_PRT_MNG_MFUTP_UDP_MASK (0x1 << I40E_PRT_MNG_MFUTP_UDP_SHIFT) 1536#define I40E_PRT_MNG_MFUTP_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_UDP_SHIFT)
1920#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17 1537#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17
1921#define I40E_PRT_MNG_MFUTP_TCP_MASK (0x1 << I40E_PRT_MNG_MFUTP_TCP_SHIFT) 1538#define I40E_PRT_MNG_MFUTP_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT)
1922#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18 1539#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18
1923#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK (0x1 << I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT) 1540#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)
1924#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ 1541#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1925#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3 1542#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3
1926#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0 1543#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0
1927#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT) 1544#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)
1928#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ 1545#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1929#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15 1546#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15
1930#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0 1547#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0
1931#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT) 1548#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)
1932#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ 1549#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1933#define I40E_PRT_MNG_MMAH_MAX_INDEX 3 1550#define I40E_PRT_MNG_MMAH_MAX_INDEX 3
1934#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0 1551#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0
1935#define I40E_PRT_MNG_MMAH_MMAH_MASK (0xFFFF << I40E_PRT_MNG_MMAH_MMAH_SHIFT) 1552#define I40E_PRT_MNG_MMAH_MMAH_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT)
1936#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ 1553#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1937#define I40E_PRT_MNG_MMAL_MAX_INDEX 3 1554#define I40E_PRT_MNG_MMAL_MAX_INDEX 3
1938#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0 1555#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0
1939#define I40E_PRT_MNG_MMAL_MMAL_MASK (0xFFFFFFFF << I40E_PRT_MNG_MMAL_MMAL_SHIFT) 1556#define I40E_PRT_MNG_MMAL_MMAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT)
1940#define I40E_PRT_MNG_MNGONLY 0x00256A60 1557#define I40E_PRT_MNG_MNGONLY 0x00256A60 /* Reset: POR */
1941#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0 1558#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0
1942#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK (0xFF << I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT) 1559#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)
1943#define I40E_PRT_MNG_MSFM 0x00256AA0 1560#define I40E_PRT_MNG_MSFM 0x00256AA0 /* Reset: POR */
1944#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0 1561#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0
1945#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT) 1562#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)
1946#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1 1563#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1
1947#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT) 1564#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT)
1948#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2 1565#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2
1949#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT) 1566#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT)
1950#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3 1567#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3
1951#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT) 1568#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT)
1952#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4 1569#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4
1953#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT) 1570#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT)
1954#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5 1571#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5
1955#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT) 1572#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT)
1956#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6 1573#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6
1957#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT) 1574#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)
1958#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7 1575#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7
1959#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT) 1576#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)
1960#define I40E_MSIX_PBA(_i) (0x00004900 + ((_i) * 4)) /* _i=0...5 */ 1577#define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */
1961#define I40E_MSIX_PBA_MAX_INDEX 5 1578#define I40E_MSIX_PBA_MAX_INDEX 5
1962#define I40E_MSIX_PBA_PENBIT_SHIFT 0 1579#define I40E_MSIX_PBA_PENBIT_SHIFT 0
1963#define I40E_MSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_MSIX_PBA_PENBIT_SHIFT) 1580#define I40E_MSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT)
1964#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ 1581#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1965#define I40E_MSIX_TADD_MAX_INDEX 128 1582#define I40E_MSIX_TADD_MAX_INDEX 128
1966#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0 1583#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0
1967#define I40E_MSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_MSIX_TADD_MSIXTADD10_SHIFT) 1584#define I40E_MSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT)
1968#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2 1585#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2
1969#define I40E_MSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_MSIX_TADD_MSIXTADD_SHIFT) 1586#define I40E_MSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT)
1970#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ 1587#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1971#define I40E_MSIX_TMSG_MAX_INDEX 128 1588#define I40E_MSIX_TMSG_MAX_INDEX 128
1972#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0 1589#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0
1973#define I40E_MSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_MSIX_TMSG_MSIXTMSG_SHIFT) 1590#define I40E_MSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT)
1974#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ 1591#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1975#define I40E_MSIX_TUADD_MAX_INDEX 128 1592#define I40E_MSIX_TUADD_MAX_INDEX 128
1976#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0 1593#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0
1977#define I40E_MSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_MSIX_TUADD_MSIXTUADD_SHIFT) 1594#define I40E_MSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT)
1978#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ 1595#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1979#define I40E_MSIX_TVCTRL_MAX_INDEX 128 1596#define I40E_MSIX_TVCTRL_MAX_INDEX 128
1980#define I40E_MSIX_TVCTRL_MASK_SHIFT 0 1597#define I40E_MSIX_TVCTRL_MASK_SHIFT 0
1981#define I40E_MSIX_TVCTRL_MASK_MASK (0x1 << I40E_MSIX_TVCTRL_MASK_SHIFT) 1598#define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT)
1982#define I40E_VFMSIX_PBA1(_i) (0x00004944 + ((_i) * 4)) /* _i=0...19 */ 1599#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
1983#define I40E_VFMSIX_PBA1_MAX_INDEX 19 1600#define I40E_VFMSIX_PBA1_MAX_INDEX 19
1984#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 1601#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
1985#define I40E_VFMSIX_PBA1_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA1_PENBIT_SHIFT) 1602#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
1986#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ 1603#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1987#define I40E_VFMSIX_TADD1_MAX_INDEX 639 1604#define I40E_VFMSIX_TADD1_MAX_INDEX 639
1988#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 1605#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
1989#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) 1606#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
1990#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 1607#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2
1991#define I40E_VFMSIX_TADD1_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) 1608#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
1992#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ 1609#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1993#define I40E_VFMSIX_TMSG1_MAX_INDEX 639 1610#define I40E_VFMSIX_TMSG1_MAX_INDEX 639
1994#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 1611#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
1995#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) 1612#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
1996#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ 1613#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1997#define I40E_VFMSIX_TUADD1_MAX_INDEX 639 1614#define I40E_VFMSIX_TUADD1_MAX_INDEX 639
1998#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 1615#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
1999#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) 1616#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
2000#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ 1617#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
2001#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 1618#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639
2002#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 1619#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
2003#define I40E_VFMSIX_TVCTRL1_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL1_MASK_SHIFT) 1620#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
2004#define I40E_GLNVM_FLA 0x000B6108 1621#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
2005#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0 1622#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0
2006#define I40E_GLNVM_FLA_FL_SCK_MASK (0x1 << I40E_GLNVM_FLA_FL_SCK_SHIFT) 1623#define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT)
2007#define I40E_GLNVM_FLA_FL_CE_SHIFT 1 1624#define I40E_GLNVM_FLA_FL_CE_SHIFT 1
2008#define I40E_GLNVM_FLA_FL_CE_MASK (0x1 << I40E_GLNVM_FLA_FL_CE_SHIFT) 1625#define I40E_GLNVM_FLA_FL_CE_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_CE_SHIFT)
2009#define I40E_GLNVM_FLA_FL_SI_SHIFT 2 1626#define I40E_GLNVM_FLA_FL_SI_SHIFT 2
2010#define I40E_GLNVM_FLA_FL_SI_MASK (0x1 << I40E_GLNVM_FLA_FL_SI_SHIFT) 1627#define I40E_GLNVM_FLA_FL_SI_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SI_SHIFT)
2011#define I40E_GLNVM_FLA_FL_SO_SHIFT 3 1628#define I40E_GLNVM_FLA_FL_SO_SHIFT 3
2012#define I40E_GLNVM_FLA_FL_SO_MASK (0x1 << I40E_GLNVM_FLA_FL_SO_SHIFT) 1629#define I40E_GLNVM_FLA_FL_SO_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SO_SHIFT)
2013#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4 1630#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4
2014#define I40E_GLNVM_FLA_FL_REQ_MASK (0x1 << I40E_GLNVM_FLA_FL_REQ_SHIFT) 1631#define I40E_GLNVM_FLA_FL_REQ_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_REQ_SHIFT)
2015#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5 1632#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5
2016#define I40E_GLNVM_FLA_FL_GNT_MASK (0x1 << I40E_GLNVM_FLA_FL_GNT_SHIFT) 1633#define I40E_GLNVM_FLA_FL_GNT_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_GNT_SHIFT)
2017#define I40E_GLNVM_FLA_LOCKED_SHIFT 6 1634#define I40E_GLNVM_FLA_LOCKED_SHIFT 6
2018#define I40E_GLNVM_FLA_LOCKED_MASK (0x1 << I40E_GLNVM_FLA_LOCKED_SHIFT) 1635#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
2019#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18 1636#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18
2020#define I40E_GLNVM_FLA_FL_SADDR_MASK (0x7FF << I40E_GLNVM_FLA_FL_SADDR_SHIFT) 1637#define I40E_GLNVM_FLA_FL_SADDR_MASK I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT)
2021#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30 1638#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30
2022#define I40E_GLNVM_FLA_FL_BUSY_MASK (0x1 << I40E_GLNVM_FLA_FL_BUSY_SHIFT) 1639#define I40E_GLNVM_FLA_FL_BUSY_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT)
2023#define I40E_GLNVM_FLA_FL_DER_SHIFT 31 1640#define I40E_GLNVM_FLA_FL_DER_SHIFT 31
2024#define I40E_GLNVM_FLA_FL_DER_MASK (0x1 << I40E_GLNVM_FLA_FL_DER_SHIFT) 1641#define I40E_GLNVM_FLA_FL_DER_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT)
2025#define I40E_GLNVM_FLASHID 0x000B6104 1642#define I40E_GLNVM_FLASHID 0x000B6104 /* Reset: POR */
2026#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0 1643#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0
2027#define I40E_GLNVM_FLASHID_FLASHID_MASK (0xFFFFFF << I40E_GLNVM_FLASHID_FLASHID_SHIFT) 1644#define I40E_GLNVM_FLASHID_FLASHID_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT)
2028#define I40E_GLNVM_GENS 0x000B6100 1645#define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31
1646#define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT)
1647#define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */
2029#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0 1648#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0
2030#define I40E_GLNVM_GENS_NVM_PRES_MASK (0x1 << I40E_GLNVM_GENS_NVM_PRES_SHIFT) 1649#define I40E_GLNVM_GENS_NVM_PRES_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT)
2031#define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 1650#define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5
2032#define I40E_GLNVM_GENS_SR_SIZE_MASK (0x7 << I40E_GLNVM_GENS_SR_SIZE_SHIFT) 1651#define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT)
2033#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8 1652#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8
2034#define I40E_GLNVM_GENS_BANK1VAL_MASK (0x1 << I40E_GLNVM_GENS_BANK1VAL_SHIFT) 1653#define I40E_GLNVM_GENS_BANK1VAL_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_BANK1VAL_SHIFT)
2035#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23 1654#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23
2036#define I40E_GLNVM_GENS_ALT_PRST_MASK (0x1 << I40E_GLNVM_GENS_ALT_PRST_SHIFT) 1655#define I40E_GLNVM_GENS_ALT_PRST_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT)
2037#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25 1656#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25
2038#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK (0x1 << I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT) 1657#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)
2039#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ 1658#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */
2040#define I40E_GLNVM_PROTCSR_MAX_INDEX 59 1659#define I40E_GLNVM_PROTCSR_MAX_INDEX 59
2041#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0 1660#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0
2042#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK (0xFFFFFF << I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT) 1661#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)
2043#define I40E_GLNVM_SRCTL 0x000B6110 1662#define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */
2044#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0 1663#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0
2045#define I40E_GLNVM_SRCTL_SRBUSY_MASK (0x1 << I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 1664#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
2046#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 1665#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14
2047#define I40E_GLNVM_SRCTL_ADDR_MASK (0x7FFF << I40E_GLNVM_SRCTL_ADDR_SHIFT) 1666#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)
2048#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 1667#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29
2049#define I40E_GLNVM_SRCTL_WRITE_MASK (0x1 << I40E_GLNVM_SRCTL_WRITE_SHIFT) 1668#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT)
2050#define I40E_GLNVM_SRCTL_START_SHIFT 30 1669#define I40E_GLNVM_SRCTL_START_SHIFT 30
2051#define I40E_GLNVM_SRCTL_START_MASK (0x1 << I40E_GLNVM_SRCTL_START_SHIFT) 1670#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
2052#define I40E_GLNVM_SRCTL_DONE_SHIFT 31 1671#define I40E_GLNVM_SRCTL_DONE_SHIFT 31
2053#define I40E_GLNVM_SRCTL_DONE_MASK (0x1 << I40E_GLNVM_SRCTL_DONE_SHIFT) 1672#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)
2054#define I40E_GLNVM_SRDATA 0x000B6114 1673#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */
2055#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 1674#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
2056#define I40E_GLNVM_SRDATA_WRDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_WRDATA_SHIFT) 1675#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
2057#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 1676#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
2058#define I40E_GLNVM_SRDATA_RDDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_RDDATA_SHIFT) 1677#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
2059#define I40E_GLNVM_ULD 0x000B6008 1678#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
2060#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 1679#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0
2061#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) 1680#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
2062#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1 1681#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1
2063#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT) 1682#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT)
2064#define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2 1683#define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2
2065#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT) 1684#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT)
2066#define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 1685#define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3
2067#define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 1686#define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT)
2068#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 1687#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4
2069#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 1688#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT)
2070#define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5 1689#define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5
2071#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT) 1690#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT)
2072#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6 1691#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6
2073#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT) 1692#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT)
2074#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7 1693#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7
2075#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT) 1694#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT)
2076#define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8 1695#define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8
2077#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT) 1696#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT)
2078#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9 1697#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9
2079#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT) 1698#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT)
2080 1699#define I40E_GLPCI_BYTCTH 0x0009C484 /* Reset: PCIR */
2081#define I40E_GLPCI_BYTCTH 0x0009C484
2082#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0 1700#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0
2083#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT) 1701#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)
2084#define I40E_GLPCI_BYTCTL 0x0009C488 1702#define I40E_GLPCI_BYTCTL 0x0009C488 /* Reset: PCIR */
2085#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0 1703#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0
2086#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT) 1704#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)
2087#define I40E_GLPCI_CAPCTRL 0x000BE4A4 1705#define I40E_GLPCI_CAPCTRL 0x000BE4A4 /* Reset: PCIR */
2088#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0 1706#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0
2089#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK (0x1 << I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT) 1707#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)
2090#define I40E_GLPCI_CAPSUP 0x000BE4A8 1708#define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */
2091#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0 1709#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0
2092#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK (0x1 << I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT) 1710#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)
2093#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2 1711#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2
2094#define I40E_GLPCI_CAPSUP_LTR_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_LTR_EN_SHIFT) 1712#define I40E_GLPCI_CAPSUP_LTR_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT)
2095#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3 1713#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3
2096#define I40E_GLPCI_CAPSUP_TPH_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_TPH_EN_SHIFT) 1714#define I40E_GLPCI_CAPSUP_TPH_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT)
2097#define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 1715#define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4
2098#define I40E_GLPCI_CAPSUP_ARI_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 1716#define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)
2099#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5 1717#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5
2100#define I40E_GLPCI_CAPSUP_IOV_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IOV_EN_SHIFT) 1718#define I40E_GLPCI_CAPSUP_IOV_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT)
2101#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6 1719#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6
2102#define I40E_GLPCI_CAPSUP_ACS_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ACS_EN_SHIFT) 1720#define I40E_GLPCI_CAPSUP_ACS_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT)
2103#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7 1721#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7
2104#define I40E_GLPCI_CAPSUP_SEC_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_SEC_EN_SHIFT) 1722#define I40E_GLPCI_CAPSUP_SEC_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT)
2105#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16 1723#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16
2106#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT) 1724#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT)
2107#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17 1725#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17
2108#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT) 1726#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT)
2109#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18 1727#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18
2110#define I40E_GLPCI_CAPSUP_IDO_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IDO_EN_SHIFT) 1728#define I40E_GLPCI_CAPSUP_IDO_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT)
2111#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19 1729#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19
2112#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK (0x1 << I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT) 1730#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT)
2113#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20 1731#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20
2114#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT) 1732#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT)
2115#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30 1733#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30
2116#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT) 1734#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)
2117#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31 1735#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31
2118#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT) 1736#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)
2119#define I40E_GLPCI_CNF 0x000BE4C0 1737#define I40E_GLPCI_CNF 0x000BE4C0 /* Reset: POR */
2120#define I40E_GLPCI_CNF_FLEX10_SHIFT 1 1738#define I40E_GLPCI_CNF_FLEX10_SHIFT 1
2121#define I40E_GLPCI_CNF_FLEX10_MASK (0x1 << I40E_GLPCI_CNF_FLEX10_SHIFT) 1739#define I40E_GLPCI_CNF_FLEX10_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT)
2122#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2 1740#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2
2123#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK (0x1 << I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT) 1741#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)
2124#define I40E_GLPCI_CNF2 0x000BE494 1742#define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */
2125#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0 1743#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0
2126#define I40E_GLPCI_CNF2_RO_DIS_MASK (0x1 << I40E_GLPCI_CNF2_RO_DIS_SHIFT) 1744#define I40E_GLPCI_CNF2_RO_DIS_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT)
2127#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1 1745#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1
2128#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK (0x1 << I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT) 1746#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT)
2129#define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 1747#define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2
2130#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 1748#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
2131#define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 1749#define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13
2132#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 1750#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
2133#define I40E_GLPCI_DREVID 0x0009C480 1751#define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */
2134#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0 1752#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0
2135#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK (0xFF << I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT) 1753#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)
2136#define I40E_GLPCI_GSCL_1 0x0009C48C 1754#define I40E_GLPCI_GSCL_1 0x0009C48C /* Reset: PCIR */
2137#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0 1755#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0
2138#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT) 1756#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)
2139#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1 1757#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1
2140#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT) 1758#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT)
2141#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2 1759#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2
2142#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT) 1760#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT)
2143#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3 1761#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3
2144#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT) 1762#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT)
2145#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4 1763#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4
2146#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT) 1764#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT)
2147#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5 1765#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5
2148#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT) 1766#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT)
2149#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6 1767#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6
2150#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT) 1768#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT)
2151#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7 1769#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7
2152#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT) 1770#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT)
2153#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8 1771#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8
2154#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT) 1772#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT)
2155#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9 1773#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9
2156#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT) 1774#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT)
2157#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14 1775#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14
2158#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT) 1776#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT)
2159#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15 1777#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15
2160#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT) 1778#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT)
2161#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28 1779#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28
2162#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT) 1780#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT)
2163#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29 1781#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29
2164#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT) 1782#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT)
2165#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30 1783#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30
2166#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT) 1784#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)
2167#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31 1785#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31
2168#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT) 1786#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)
2169#define I40E_GLPCI_GSCL_2 0x0009C490 1787#define I40E_GLPCI_GSCL_2 0x0009C490 /* Reset: PCIR */
2170#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0 1788#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0
2171#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT) 1789#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)
2172#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8 1790#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8
2173#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT) 1791#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT)
2174#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16 1792#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16
2175#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT) 1793#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)
2176#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24 1794#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24
2177#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT) 1795#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)
2178#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ 1796#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
2179#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3 1797#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3
2180#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0 1798#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0
2181#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT) 1799#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
2182#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16 1800#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16
2183#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT) 1801#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
2184#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ 1802#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
2185#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 1803#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3
2186#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 1804#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
2187#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK (0xFFFFFFFF << I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) 1805#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
2188#define I40E_GLPCI_LATCT 0x0009C4B4 1806#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCIR */
2189#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0 1807#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0
2190#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK (0xFFFFFFFF << I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT) 1808#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)
2191#define I40E_GLPCI_LBARCTRL 0x000BE484 1809#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
2192#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 1810#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0
2193#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK (0x1 << I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) 1811#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
2194#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1 1812#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1
2195#define I40E_GLPCI_LBARCTRL_BAR32_MASK (0x1 << I40E_GLPCI_LBARCTRL_BAR32_SHIFT) 1813#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT)
2196#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3 1814#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3
2197#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK (0x1 << I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT) 1815#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT)
2198#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4 1816#define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4
2199#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK (0x3 << I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT) 1817#define I40E_GLPCI_LBARCTRL_RSVD_4_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT)
2200#define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 1818#define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6
2201#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 1819#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)
2202#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10 1820#define I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT 10
2203#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK (0x1 << I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT) 1821#define I40E_GLPCI_LBARCTRL_RSVD_10_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT)
2204#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11 1822#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11
2205#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT) 1823#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)
2206#define I40E_GLPCI_LINKCAP 0x000BE4AC 1824#define I40E_GLPCI_LINKCAP 0x000BE4AC /* Reset: PCIR */
2207#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0 1825#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0
2208#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK (0x3F << I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT) 1826#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)
2209#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6 1827#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6
2210#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK (0x7 << I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT) 1828#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)
2211#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9 1829#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9
2212#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK (0xF << I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT) 1830#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)
2213#define I40E_GLPCI_PCIERR 0x000BE4FC 1831#define I40E_GLPCI_PCIERR 0x000BE4FC /* Reset: PCIR */
2214#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0 1832#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
2215#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK (0xFFFFFFFF << I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT) 1833#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
2216#define I40E_GLPCI_PCITEST2 0x000BE4BC 1834#define I40E_GLPCI_PKTCT 0x0009C4BC /* Reset: PCIR */
2217#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT 0
2218#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_MASK (0x1 << I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT)
2219#define I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT 1
2220#define I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK (0x1 << I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT)
2221
2222#define I40E_GLPCI_PKTCT 0x0009C4BC
2223#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0 1835#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
2224#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK (0xFFFFFFFF << I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT) 1836#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
2225#define I40E_GLPCI_PMSUP 0x000BE4B0 1837#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 /* Reset: PCIR */
1838#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0
1839#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
1840#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16
1841#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)
1842#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 /* Reset: PCIR */
1843#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0
1844#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
1845#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16
1846#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
1847#define I40E_GLPCI_PMSUP 0x000BE4B0 /* Reset: PCIR */
2226#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0 1848#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0
2227#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT) 1849#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)
2228#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2 1850#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2
2229#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT) 1851#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT)
2230#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5 1852#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5
2231#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT) 1853#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT)
2232#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8 1854#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8
2233#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT) 1855#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT)
2234#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11 1856#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11
2235#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT) 1857#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT)
2236#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14 1858#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14
2237#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK (0x1 << I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT) 1859#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)
2238#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15 1860#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15
2239#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT) 1861#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)
2240#define I40E_GLPCI_PWRDATA 0x000BE490 1862#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC /* Reset: PCIR */
1863#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0
1864#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)
1865#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8
1866#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)
1867#define I40E_GLPCI_PWRDATA 0x000BE490 /* Reset: PCIR */
2241#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0 1868#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0
2242#define I40E_GLPCI_PWRDATA_D0_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D0_POWER_SHIFT) 1869#define I40E_GLPCI_PWRDATA_D0_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)
2243#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8 1870#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8
2244#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT) 1871#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT)
2245#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16 1872#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16
2246#define I40E_GLPCI_PWRDATA_D3_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D3_POWER_SHIFT) 1873#define I40E_GLPCI_PWRDATA_D3_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)
2247#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24 1874#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24
2248#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK (0x3 << I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT) 1875#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)
2249#define I40E_GLPCI_REVID 0x000BE4B4 1876#define I40E_GLPCI_REVID 0x000BE4B4 /* Reset: PCIR */
2250#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0 1877#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0
2251#define I40E_GLPCI_REVID_NVM_REVID_MASK (0xFF << I40E_GLPCI_REVID_NVM_REVID_SHIFT) 1878#define I40E_GLPCI_REVID_NVM_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT)
2252#define I40E_GLPCI_SERH 0x000BE49C 1879#define I40E_GLPCI_SERH 0x000BE49C /* Reset: PCIR */
2253#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0 1880#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0
2254#define I40E_GLPCI_SERH_SER_NUM_H_MASK (0xFFFF << I40E_GLPCI_SERH_SER_NUM_H_SHIFT) 1881#define I40E_GLPCI_SERH_SER_NUM_H_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT)
2255#define I40E_GLPCI_SERL 0x000BE498 1882#define I40E_GLPCI_SERL 0x000BE498 /* Reset: PCIR */
2256#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0 1883#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0
2257#define I40E_GLPCI_SERL_SER_NUM_L_MASK (0xFFFFFFFF << I40E_GLPCI_SERL_SER_NUM_L_SHIFT) 1884#define I40E_GLPCI_SERL_SER_NUM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT)
2258#define I40E_GLPCI_SUBSYSID 0x000BE48C 1885#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 /* Reset: PCIR */
2259#define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT 0 1886#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0
2260#define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT) 1887#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
2261#define I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT 16 1888#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC /* Reset: PCIR */
2262#define I40E_GLPCI_SUBSYSID_SUB_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT) 1889#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0
2263#define I40E_GLPCI_UPADD 0x000BE4F8 1890#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)
1891#define I40E_GLPCI_SUBVENID 0x000BE48C /* Reset: PCIR */
1892#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0
1893#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT)
1894#define I40E_GLPCI_UPADD 0x000BE4F8 /* Reset: PCIR */
2264#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1 1895#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1
2265#define I40E_GLPCI_UPADD_ADDRESS_MASK (0x7FFFFFFF << I40E_GLPCI_UPADD_ADDRESS_SHIFT) 1896#define I40E_GLPCI_UPADD_ADDRESS_MASK I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT)
2266#define I40E_GLPCI_VFSUP 0x000BE4B8 1897#define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */
1898#define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0
1899#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT)
1900#define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */
2267#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0 1901#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0
2268#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK (0x1 << I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) 1902#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
2269#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 1903#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
2270#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK (0x1 << I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) 1904#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
2271#define I40E_PF_FUNC_RID 0x0009C000 1905#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */
2272#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 1906#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
2273#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK (0x7 << I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) 1907#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
2274#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3 1908#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3
2275#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK (0x1F << I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT) 1909#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)
2276#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8 1910#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8
2277#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK (0xFF << I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT) 1911#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)
2278#define I40E_PF_PCI_CIAA 0x0009C080 1912#define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */
2279#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0 1913#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0
2280#define I40E_PF_PCI_CIAA_ADDRESS_MASK (0xFFF << I40E_PF_PCI_CIAA_ADDRESS_SHIFT) 1914#define I40E_PF_PCI_CIAA_ADDRESS_MASK I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT)
2281#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 1915#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12
2282#define I40E_PF_PCI_CIAA_VF_NUM_MASK (0x7F << I40E_PF_PCI_CIAA_VF_NUM_SHIFT) 1916#define I40E_PF_PCI_CIAA_VF_NUM_MASK I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT)
2283#define I40E_PF_PCI_CIAD 0x0009C100 1917#define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */
2284#define I40E_PF_PCI_CIAD_DATA_SHIFT 0 1918#define I40E_PF_PCI_CIAD_DATA_SHIFT 0
2285#define I40E_PF_PCI_CIAD_DATA_MASK (0xFFFFFFFF << I40E_PF_PCI_CIAD_DATA_SHIFT) 1919#define I40E_PF_PCI_CIAD_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT)
2286#define I40E_PFPCI_CLASS 0x000BE400 1920#define I40E_PFPCI_CLASS 0x000BE400 /* Reset: PCIR */
2287#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0 1921#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0
2288#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK (0x1 << I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT) 1922#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)
2289#define I40E_PFPCI_CNF 0x000BE000 1923#define I40E_PFPCI_CLASS_RESERVED_1_SHIFT 1
1924#define I40E_PFPCI_CLASS_RESERVED_1_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT)
1925#define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT 2
1926#define I40E_PFPCI_CLASS_PF_IS_LAN_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT)
1927#define I40E_PFPCI_CNF 0x000BE000 /* Reset: PCIR */
2290#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2 1928#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2
2291#define I40E_PFPCI_CNF_MSI_EN_MASK (0x1 << I40E_PFPCI_CNF_MSI_EN_SHIFT) 1929#define I40E_PFPCI_CNF_MSI_EN_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT)
2292#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3 1930#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3
2293#define I40E_PFPCI_CNF_EXROM_DIS_MASK (0x1 << I40E_PFPCI_CNF_EXROM_DIS_SHIFT) 1931#define I40E_PFPCI_CNF_EXROM_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_EXROM_DIS_SHIFT)
2294#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4 1932#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4
2295#define I40E_PFPCI_CNF_IO_BAR_MASK (0x1 << I40E_PFPCI_CNF_IO_BAR_SHIFT) 1933#define I40E_PFPCI_CNF_IO_BAR_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT)
2296#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5 1934#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5
2297#define I40E_PFPCI_CNF_INT_PIN_MASK (0x3 << I40E_PFPCI_CNF_INT_PIN_SHIFT) 1935#define I40E_PFPCI_CNF_INT_PIN_MASK I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT)
2298#define I40E_PFPCI_FACTPS 0x0009C180 1936#define I40E_PFPCI_DEVID 0x000BE080 /* Reset: PCIR */
1937#define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0
1938#define I40E_PFPCI_DEVID_PF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)
1939#define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16
1940#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
1941#define I40E_PFPCI_FACTPS 0x0009C180 /* Reset: FLR */
2299#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0 1942#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0
2300#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK (0x3 << I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT) 1943#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
2301#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3 1944#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3
2302#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK (0x1 << I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT) 1945#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)
2303#define I40E_PFPCI_FUNC 0x000BE200 1946#define I40E_PFPCI_FUNC 0x000BE200 /* Reset: POR */
2304#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0 1947#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0
2305#define I40E_PFPCI_FUNC_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_FUNC_DIS_SHIFT) 1948#define I40E_PFPCI_FUNC_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)
2306#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1 1949#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1
2307#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT) 1950#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)
2308#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2 1951#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2
2309#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK (0x1 << I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT) 1952#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)
2310#define I40E_PFPCI_FUNC2 0x000BE180 1953#define I40E_PFPCI_FUNC2 0x000BE180 /* Reset: PCIR */
2311#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0 1954#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0
2312#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT) 1955#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)
2313#define I40E_PFPCI_ICAUSE 0x0009C200 1956#define I40E_PFPCI_ICAUSE 0x0009C200 /* Reset: PFR */
2314#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0 1957#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0
2315#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK (0xFFFFFFFF << I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT) 1958#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)
2316#define I40E_PFPCI_IENA 0x0009C280 1959#define I40E_PFPCI_IENA 0x0009C280 /* Reset: PFR */
2317#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0 1960#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0
2318#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK (0xFFFFFFFF << I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT) 1961#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)
2319#define I40E_PFPCI_PFDEVID 0x000BE080 1962#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 /* Reset: PCIR */
2320#define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT 0 1963#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
2321#define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT) 1964#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)
2322#define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT 16 1965#define I40E_PFPCI_PM 0x000BE300 /* Reset: POR */
2323#define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT)
2324#define I40E_PFPCI_PM 0x000BE300
2325#define I40E_PFPCI_PM_PME_EN_SHIFT 0 1966#define I40E_PFPCI_PM_PME_EN_SHIFT 0
2326#define I40E_PFPCI_PM_PME_EN_MASK (0x1 << I40E_PFPCI_PM_PME_EN_SHIFT) 1967#define I40E_PFPCI_PM_PME_EN_MASK I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT)
2327#define I40E_PFPCI_STATUS1 0x000BE280 1968#define I40E_PFPCI_STATUS1 0x000BE280 /* Reset: POR */
2328#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0 1969#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0
2329#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK (0x1 << I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT) 1970#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)
2330#define I40E_PFPCI_VFDEVID 0x000BE100 1971#define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */
2331#define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT 0 1972#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0
2332#define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT) 1973#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)
2333#define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT 16 1974#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16
2334#define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT) 1975#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
2335#define I40E_PFPCI_VMINDEX 0x0009C300 1976#define I40E_PFPCI_VF_FLUSH_DONE 0x0000E400 /* Reset: PCIR */
1977#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1978#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
1979#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */
1980#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127
1981#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0
1982#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)
1983#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 /* Reset: PCIR */
1984#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1985#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
1986#define I40E_PFPCI_VMINDEX 0x0009C300 /* Reset: PCIR */
2336#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0 1987#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0
2337#define I40E_PFPCI_VMINDEX_VMINDEX_MASK (0x1FF << I40E_PFPCI_VMINDEX_VMINDEX_SHIFT) 1988#define I40E_PFPCI_VMINDEX_VMINDEX_MASK I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)
2338#define I40E_PFPCI_VMPEND 0x0009C380 1989#define I40E_PFPCI_VMPEND 0x0009C380 /* Reset: PCIR */
2339#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0 1990#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0
2340#define I40E_PFPCI_VMPEND_PENDING_MASK (0x1 << I40E_PFPCI_VMPEND_PENDING_SHIFT) 1991#define I40E_PFPCI_VMPEND_PENDING_MASK I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT)
2341#define I40E_GLPE_CPUSTATUS0 0x0000D040 1992#define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */
2342#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0
2343#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
2344#define I40E_GLPE_CPUSTATUS1 0x0000D044
2345#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0
2346#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT)
2347#define I40E_GLPE_CPUSTATUS2 0x0000D048
2348#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0
2349#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT)
2350#define I40E_GLPE_PFFLMOBJCTRL(_i) (0x0000D480 + ((_i) * 4)) /* _i=0...15 */
2351#define I40E_GLPE_PFFLMOBJCTRL_MAX_INDEX 15
2352#define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
2353#define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
2354#define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
2355#define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
2356#define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */
2357#define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31
2358#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
2359#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
2360#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
2361#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
2362#define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */
2363#define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
2364#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
2365#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
2366#define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */
2367#define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
2368#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
2369#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT)
2370#define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */
2371#define I40E_GLPE_VFUDACTRL_MAX_INDEX 31
2372#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0
2373#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT)
2374#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1
2375#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT)
2376#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2
2377#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT)
2378#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3
2379#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT)
2380#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
2381#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT)
2382#define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */
2383#define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31
2384#define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0
2385#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT)
2386#define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31
2387#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK (0x1 << I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT)
2388#define I40E_PFPE_AEQALLOC 0x00131180
2389#define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0
2390#define I40E_PFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_PFPE_AEQALLOC_AECOUNT_SHIFT)
2391#define I40E_PFPE_CCQPHIGH 0x00008200
2392#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
2393#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
2394#define I40E_PFPE_CCQPLOW 0x00008180
2395#define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0
2396#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT)
2397#define I40E_PFPE_CCQPSTATUS 0x00008100
2398#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
2399#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
2400#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
2401#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
2402#define I40E_PFPE_CQACK 0x00131100
2403#define I40E_PFPE_CQACK_PECQID_SHIFT 0
2404#define I40E_PFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_PFPE_CQACK_PECQID_SHIFT)
2405#define I40E_PFPE_CQARM 0x00131080
2406#define I40E_PFPE_CQARM_PECQID_SHIFT 0
2407#define I40E_PFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_PFPE_CQARM_PECQID_SHIFT)
2408#define I40E_PFPE_CQPDB 0x00008000
2409#define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0
2410#define I40E_PFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_PFPE_CQPDB_WQHEAD_SHIFT)
2411#define I40E_PFPE_CQPERRCODES 0x00008880
2412#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
2413#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
2414#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
2415#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
2416#define I40E_PFPE_CQPTAIL 0x00008080
2417#define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0
2418#define I40E_PFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
2419#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
2420#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
2421#define I40E_PFPE_FLMQ1ALLOCERR 0x00008980
2422#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
2423#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
2424#define I40E_PFPE_FLMXMITALLOCERR 0x00008900
2425#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
2426#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT)
2427#define I40E_PFPE_IPCONFIG0 0x00008280
2428#define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0
2429#define I40E_PFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
2430#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
2431#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
2432
2433#define I40E_PFPE_MRTEIDXMASK 0x00008600
2434#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
2435#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
2436#define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680
2437#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
2438#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
2439#define I40E_PFPE_TCPNOWTIMER 0x00008580
2440#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
2441#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
2442#define I40E_PFPE_UDACTRL 0x00008700
2443#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0
2444#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT)
2445#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1
2446#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT)
2447#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2
2448#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT)
2449#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3
2450#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT)
2451#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
2452#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT)
2453#define I40E_PFPE_UDAUCFBQPN 0x00008780
2454#define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0
2455#define I40E_PFPE_UDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_PFPE_UDAUCFBQPN_QPN_SHIFT)
2456#define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31
2457#define I40E_PFPE_UDAUCFBQPN_VALID_MASK (0x1 << I40E_PFPE_UDAUCFBQPN_VALID_SHIFT)
2458#define I40E_PFPE_WQEALLOC 0x00138C00
2459#define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0
2460#define I40E_PFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_PFPE_WQEALLOC_PEQPID_SHIFT)
2461#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
2462#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
2463#define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */
2464#define I40E_VFPE_AEQALLOC_MAX_INDEX 127
2465#define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0
2466#define I40E_VFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC_AECOUNT_SHIFT)
2467#define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */
2468#define I40E_VFPE_CCQPHIGH_MAX_INDEX 127
2469#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
2470#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
2471#define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */
2472#define I40E_VFPE_CCQPLOW_MAX_INDEX 127
2473#define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0
2474#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT)
2475#define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */
2476#define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127
2477#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
2478#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
2479#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
2480#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
2481#define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */
2482#define I40E_VFPE_CQACK_MAX_INDEX 127
2483#define I40E_VFPE_CQACK_PECQID_SHIFT 0
2484#define I40E_VFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK_PECQID_SHIFT)
2485#define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */
2486#define I40E_VFPE_CQARM_MAX_INDEX 127
2487#define I40E_VFPE_CQARM_PECQID_SHIFT 0
2488#define I40E_VFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM_PECQID_SHIFT)
2489#define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */
2490#define I40E_VFPE_CQPDB_MAX_INDEX 127
2491#define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0
2492#define I40E_VFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB_WQHEAD_SHIFT)
2493#define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */
2494#define I40E_VFPE_CQPERRCODES_MAX_INDEX 127
2495#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
2496#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
2497#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
2498#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
2499#define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */
2500#define I40E_VFPE_CQPTAIL_MAX_INDEX 127
2501#define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0
2502#define I40E_VFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL_WQTAIL_SHIFT)
2503#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
2504#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
2505#define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */
2506#define I40E_VFPE_IPCONFIG0_MAX_INDEX 127
2507#define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0
2508#define I40E_VFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
2509#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
2510#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
2511#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */
2512#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127
2513#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
2514#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
2515#define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4))
2516#define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127
2517#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
2518#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
2519#define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */
2520#define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127
2521#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
2522#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
2523#define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */
2524#define I40E_VFPE_WQEALLOC_MAX_INDEX 127
2525#define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0
2526#define I40E_VFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC_PEQPID_SHIFT)
2527#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
2528#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
2529#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */
2530#define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15
2531#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
2532#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
2533#define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */
2534#define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15
2535#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
2536#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
2537#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */
2538#define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15
2539#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
2540#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
2541#define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8))
2542#define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15
2543#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
2544#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
2545#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8))
2546#define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15
2547#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
2548#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
2549#define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8))
2550#define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15
2551#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
2552#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
2553#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8))
2554#define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15
2555#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
2556#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
2557#define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */
2558#define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15
2559#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
2560#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
2561#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */
2562#define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15
2563#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
2564#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
2565#define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */
2566#define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15
2567#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
2568#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
2569#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */
2570#define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15
2571#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
2572#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
2573#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */
2574#define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15
2575#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
2576#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
2577#define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */
2578#define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15
2579#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
2580#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
2581#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */
2582#define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15
2583#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
2584#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
2585#define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8))
2586#define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15
2587#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
2588#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
2589#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8))
2590#define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15
2591#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
2592#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
2593#define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8))
2594#define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15
2595#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
2596#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
2597#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8))
2598#define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15
2599#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
2600#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
2601#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */
2602#define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15
2603#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
2604#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
2605#define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */
2606#define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15
2607#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
2608#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
2609#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */
2610#define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15
2611#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
2612#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
2613#define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */
2614#define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15
2615#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
2616#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
2617#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */
2618#define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15
2619#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
2620#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
2621#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */
2622#define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15
2623#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
2624#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
2625#define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */
2626#define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15
2627#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
2628#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
2629#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */
2630#define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15
2631#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
2632#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
2633#define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8))
2634#define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15
2635#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
2636#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
2637#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8))
2638#define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15
2639#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
2640#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
2641#define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8))
2642#define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15
2643#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
2644#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
2645#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8))
2646#define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15
2647#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
2648#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
2649#define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */
2650#define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15
2651#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
2652#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
2653#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */
2654#define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15
2655#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
2656#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
2657#define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */
2658#define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15
2659#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
2660#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
2661#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */
2662#define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15
2663#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
2664#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
2665#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */
2666#define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15
2667#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
2668#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
2669#define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */
2670#define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15
2671#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
2672#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
2673#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */
2674#define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15
2675#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
2676#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
2677#define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8))
2678#define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15
2679#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
2680#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
2681#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8))
2682#define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15
2683#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
2684#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
2685#define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8))
2686#define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15
2687#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
2688#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
2689#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8))
2690#define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15
2691#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
2692#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
2693#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */
2694#define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15
2695#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
2696#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
2697#define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */
2698#define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15
2699#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
2700#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
2701#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */
2702#define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15
2703#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
2704#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
2705#define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */
2706#define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15
2707#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
2708#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
2709#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */
2710#define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15
2711#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
2712#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
2713#define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */
2714#define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15
2715#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
2716#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
2717#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */
2718#define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15
2719#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
2720#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
2721#define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */
2722#define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15
2723#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
2724#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
2725#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */
2726#define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15
2727#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
2728#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
2729#define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */
2730#define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15
2731#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
2732#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
2733#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */
2734#define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15
2735#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
2736#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
2737#define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */
2738#define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15
2739#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
2740#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
2741#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */
2742#define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15
2743#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
2744#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
2745#define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */
2746#define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15
2747#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
2748#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
2749#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */
2750#define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15
2751#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
2752#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
2753#define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */
2754#define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15
2755#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
2756#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
2757#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */
2758#define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15
2759#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
2760#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
2761#define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */
2762#define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15
2763#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
2764#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
2765#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */
2766#define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15
2767#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
2768#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
2769#define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */
2770#define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15
2771#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0
2772#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT)
2773#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */
2774#define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15
2775#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0
2776#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT)
2777#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */
2778#define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15
2779#define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0
2780#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT)
2781#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */
2782#define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15
2783#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0
2784#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT)
2785#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */
2786#define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15
2787#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
2788#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
2789#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4))
2790#define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15
2791#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
2792#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
2793#define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */
2794#define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15
2795#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
2796#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
2797#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */
2798#define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15
2799#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
2800#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
2801#define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */
2802#define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15
2803#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
2804#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
2805#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */
2806#define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15
2807#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
2808#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
2809#define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */
2810#define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15
2811#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
2812#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
2813#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */
2814#define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15
2815#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
2816#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
2817#define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */
2818#define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15
2819#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
2820#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
2821#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */
2822#define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15
2823#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
2824#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
2825#define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014
2826#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0
2827#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT)
2828#define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010
2829#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0
2830#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT)
2831#define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C
2832#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0
2833#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT)
2834#define I40E_GLPES_RDMARXOOODDPLO 0x0001E018
2835#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0
2836#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT)
2837#define I40E_GLPES_RDMARXOOONOMARK 0x0001E004
2838#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0
2839#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT)
2840#define I40E_GLPES_RDMARXUNALIGN 0x0001E000
2841#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0
2842#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT)
2843#define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044
2844#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0
2845#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT)
2846#define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040
2847#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0
2848#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT)
2849#define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C
2850#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0
2851#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT)
2852#define I40E_GLPES_TCPRXONEHOLELO 0x0001E028
2853#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0
2854#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT)
2855#define I40E_GLPES_TCPRXPUREACKHI 0x0001E024
2856#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0
2857#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT)
2858#define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020
2859#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0
2860#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT)
2861#define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C
2862#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0
2863#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT)
2864#define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038
2865#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0
2866#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT)
2867#define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034
2868#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0
2869#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT)
2870#define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030
2871#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0
2872#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT)
2873#define I40E_GLPES_TCPRXUNEXPERR 0x0001E008
2874#define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT 0
2875#define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_MASK (0xFFFFFF << I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT)
2876#define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C
2877#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0
2878#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT)
2879#define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048
2880#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0
2881#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT)
2882#define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054
2883#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0
2884#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT)
2885#define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050
2886#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0
2887#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT)
2888#define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C
2889#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0
2890#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT)
2891#define I40E_GLPES_TCPTXTOUTSLO 0x0001E058
2892#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0
2893#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT)
2894#define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */
2895#define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31
2896#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
2897#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
2898#define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 4)) /* _i=0...31 */
2899#define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31
2900#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
2901#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
2902#define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 4)) /* _i=0...31 */
2903#define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31
2904#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
2905#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
2906#define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 4))
2907#define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31
2908#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
2909#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
2910#define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 4))
2911#define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31
2912#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
2913#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
2914#define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 4))
2915#define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31
2916#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
2917#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
2918#define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 4))
2919#define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31
2920#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
2921#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
2922#define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 4)) /* _i=0...31 */
2923#define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31
2924#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
2925#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
2926#define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 4)) /* _i=0...31 */
2927#define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31
2928#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
2929#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
2930#define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 4)) /* _i=0...31 */
2931#define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31
2932#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
2933#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
2934#define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 4)) /* _i=0...31 */
2935#define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31
2936#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
2937#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
2938#define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */
2939#define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31
2940#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
2941#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
2942#define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 4)) /* _i=0...31 */
2943#define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31
2944#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
2945#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
2946#define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 4)) /* _i=0...31 */
2947#define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31
2948#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
2949#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
2950#define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 4))
2951#define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31
2952#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
2953#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
2954#define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 4))
2955#define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31
2956#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
2957#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
2958#define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 4))
2959#define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31
2960#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
2961#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
2962#define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 4))
2963#define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31
2964#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
2965#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
2966#define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */
2967#define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31
2968#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
2969#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
2970#define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 4)) /* _i=0...31 */
2971#define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31
2972#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
2973#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
2974#define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 4)) /* _i=0...31 */
2975#define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31
2976#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
2977#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
2978#define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 4)) /* _i=0...31 */
2979#define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31
2980#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
2981#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
2982#define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 4)) /* _i=0...31 */
2983#define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31
2984#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
2985#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
2986#define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */
2987#define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31
2988#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
2989#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
2990#define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 4)) /* _i=0...31 */
2991#define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31
2992#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
2993#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
2994#define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 4)) /* _i=0...31 */
2995#define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31
2996#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
2997#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
2998#define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 4))
2999#define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31
3000#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
3001#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
3002#define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 4))
3003#define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31
3004#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
3005#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
3006#define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 4))
3007#define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31
3008#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
3009#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
3010#define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 4))
3011#define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31
3012#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
3013#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
3014#define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 4)) /* _i=0...31 */
3015#define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31
3016#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
3017#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
3018#define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 4)) /* _i=0...31 */
3019#define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31
3020#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
3021#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
3022#define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 4)) /* _i=0...31 */
3023#define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31
3024#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
3025#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
3026#define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 4)) /* _i=0...31 */
3027#define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31
3028#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
3029#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
3030#define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */
3031#define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31
3032#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
3033#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
3034#define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 4)) /* _i=0...31 */
3035#define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31
3036#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
3037#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
3038#define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 4)) /* _i=0...31 */
3039#define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31
3040#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
3041#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
3042#define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 4))
3043#define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31
3044#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
3045#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
3046#define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 4))
3047#define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31
3048#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
3049#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
3050#define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 4))
3051#define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31
3052#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
3053#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
3054#define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 4))
3055#define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31
3056#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
3057#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
3058#define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */
3059#define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31
3060#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
3061#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
3062#define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 4)) /* _i=0...31 */
3063#define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31
3064#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
3065#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
3066#define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 4)) /* _i=0...31 */
3067#define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31
3068#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
3069#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
3070#define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 4)) /* _i=0...31 */
3071#define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31
3072#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
3073#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
3074#define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 4)) /* _i=0...31 */
3075#define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31
3076#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
3077#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
3078#define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 4)) /* _i=0...31 */
3079#define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31
3080#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
3081#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
3082#define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 4)) /* _i=0...31 */
3083#define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31
3084#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
3085#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
3086#define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 4)) /* _i=0...31 */
3087#define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31
3088#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
3089#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
3090#define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 4)) /* _i=0...31 */
3091#define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31
3092#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
3093#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
3094#define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 4)) /* _i=0...31 */
3095#define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31
3096#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
3097#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
3098#define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 4)) /* _i=0...31 */
3099#define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31
3100#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
3101#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
3102#define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 4)) /* _i=0...31 */
3103#define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31
3104#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
3105#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
3106#define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 4)) /* _i=0...31 */
3107#define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31
3108#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
3109#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
3110#define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 4)) /* _i=0...31 */
3111#define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31
3112#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
3113#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
3114#define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 4)) /* _i=0...31 */
3115#define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31
3116#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
3117#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
3118#define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 4)) /* _i=0...31 */
3119#define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31
3120#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
3121#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
3122#define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 4)) /* _i=0...31 */
3123#define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31
3124#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
3125#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
3126#define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 4)) /* _i=0...31 */
3127#define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31
3128#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
3129#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
3130#define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 4)) /* _i=0...31 */
3131#define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31
3132#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
3133#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
3134#define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 4)) /* _i=0...31 */
3135#define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31
3136#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0
3137#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT)
3138#define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 4)) /* _i=0...31 */
3139#define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31
3140#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0
3141#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT)
3142#define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */
3143#define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31
3144#define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0
3145#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT)
3146#define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */
3147#define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31
3148#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0
3149#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT)
3150#define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */
3151#define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31
3152#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
3153#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
3154#define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4))
3155#define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31
3156#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
3157#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
3158#define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 4)) /* _i=0...31 */
3159#define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31
3160#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
3161#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
3162#define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 4)) /* _i=0...31 */
3163#define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31
3164#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
3165#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
3166#define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 4)) /* _i=0...31 */
3167#define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31
3168#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
3169#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
3170#define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 4)) /* _i=0...31 */
3171#define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31
3172#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
3173#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
3174#define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 4)) /* _i=0...31 */
3175#define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31
3176#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
3177#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
3178#define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 4)) /* _i=0...31 */
3179#define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31
3180#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
3181#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
3182#define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 4)) /* _i=0...31 */
3183#define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31
3184#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
3185#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
3186#define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 4)) /* _i=0...31 */
3187#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31
3188#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
3189#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
3190#define I40E_PRTPM_EEE_STAT 0x001E4320
3191#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29 1993#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29
3192#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK (0x1 << I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT) 1994#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
3193#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 1995#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30
3194#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 1996#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
3195#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 1997#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
3196#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 1998#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
3197#define I40E_PRTPM_EEEC 0x001E4380 1999#define I40E_PRTPM_EEEC 0x001E4380 /* Reset: GLOBR */
3198#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16 2000#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16
3199#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK (0x3F << I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT) 2001#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)
3200#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24 2002#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24
3201#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK (0x3 << I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT) 2003#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)
3202#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26 2004#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26
3203#define I40E_PRTPM_EEEC_TEEE_DLY_MASK (0x3F << I40E_PRTPM_EEEC_TEEE_DLY_SHIFT) 2005#define I40E_PRTPM_EEEC_TEEE_DLY_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)
3204#define I40E_PRTPM_EEEFWD 0x001E4400 2006#define I40E_PRTPM_EEEFWD 0x001E4400 /* Reset: GLOBR */
3205#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31 2007#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31
3206#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK (0x1 << I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT) 2008#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)
3207#define I40E_PRTPM_EEER 0x001E4360 2009#define I40E_PRTPM_EEER 0x001E4360 /* Reset: GLOBR */
3208#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0 2010#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0
3209#define I40E_PRTPM_EEER_TW_SYSTEM_MASK (0xFFFF << I40E_PRTPM_EEER_TW_SYSTEM_SHIFT) 2011#define I40E_PRTPM_EEER_TW_SYSTEM_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)
3210#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16 2012#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16
3211#define I40E_PRTPM_EEER_TX_LPI_EN_MASK (0x1 << I40E_PRTPM_EEER_TX_LPI_EN_SHIFT) 2013#define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
3212#define I40E_PRTPM_EEETXC 0x001E43E0 2014#define I40E_PRTPM_EEETXC 0x001E43E0 /* Reset: GLOBR */
3213#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0 2015#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0
3214#define I40E_PRTPM_EEETXC_TW_PHY_MASK (0xFFFF << I40E_PRTPM_EEETXC_TW_PHY_SHIFT) 2016#define I40E_PRTPM_EEETXC_TW_PHY_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT)
3215#define I40E_PRTPM_GC 0x000B8140 2017#define I40E_PRTPM_GC 0x000B8140 /* Reset: POR */
3216#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0 2018#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0
3217#define I40E_PRTPM_GC_EMP_LINK_ON_MASK (0x1 << I40E_PRTPM_GC_EMP_LINK_ON_SHIFT) 2019#define I40E_PRTPM_GC_EMP_LINK_ON_MASK I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)
3218#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1 2020#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1
3219#define I40E_PRTPM_GC_MNG_VETO_MASK (0x1 << I40E_PRTPM_GC_MNG_VETO_SHIFT) 2021#define I40E_PRTPM_GC_MNG_VETO_MASK I40E_MASK(0x1, I40E_PRTPM_GC_MNG_VETO_SHIFT)
3220#define I40E_PRTPM_GC_RATD_SHIFT 2 2022#define I40E_PRTPM_GC_RATD_SHIFT 2
3221#define I40E_PRTPM_GC_RATD_MASK (0x1 << I40E_PRTPM_GC_RATD_SHIFT) 2023#define I40E_PRTPM_GC_RATD_MASK I40E_MASK(0x1, I40E_PRTPM_GC_RATD_SHIFT)
3222#define I40E_PRTPM_GC_LCDMP_SHIFT 3 2024#define I40E_PRTPM_GC_LCDMP_SHIFT 3
3223#define I40E_PRTPM_GC_LCDMP_MASK (0x1 << I40E_PRTPM_GC_LCDMP_SHIFT) 2025#define I40E_PRTPM_GC_LCDMP_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT)
3224#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31 2026#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
3225#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK (0x1 << I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT) 2027#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
3226#define I40E_PRTPM_RLPIC 0x001E43A0 2028#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */
3227#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0 2029#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
3228#define I40E_PRTPM_RLPIC_ERLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_RLPIC_ERLPIC_SHIFT) 2030#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
3229#define I40E_PRTPM_TLPIC 0x001E43C0 2031#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */
3230#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0 2032#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
3231#define I40E_PRTPM_TLPIC_ETLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_TLPIC_ETLPIC_SHIFT) 2033#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
3232#define I40E_GLRPB_DPSS 0x000AC828 2034#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */
3233#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0 2035#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
3234#define I40E_GLRPB_DPSS_DPS_TCN_MASK (0xFFFFF << I40E_GLRPB_DPSS_DPS_TCN_SHIFT) 2036#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
3235#define I40E_GLRPB_GHW 0x000AC830 2037#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */
3236#define I40E_GLRPB_GHW_GHW_SHIFT 0 2038#define I40E_GLRPB_GHW_GHW_SHIFT 0
3237#define I40E_GLRPB_GHW_GHW_MASK (0xFFFFF << I40E_GLRPB_GHW_GHW_SHIFT) 2039#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)
3238#define I40E_GLRPB_GLW 0x000AC834 2040#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */
3239#define I40E_GLRPB_GLW_GLW_SHIFT 0 2041#define I40E_GLRPB_GLW_GLW_SHIFT 0
3240#define I40E_GLRPB_GLW_GLW_MASK (0xFFFFF << I40E_GLRPB_GLW_GLW_SHIFT) 2042#define I40E_GLRPB_GLW_GLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT)
3241#define I40E_GLRPB_PHW 0x000AC844 2043#define I40E_GLRPB_PHW 0x000AC844 /* Reset: CORER */
3242#define I40E_GLRPB_PHW_PHW_SHIFT 0 2044#define I40E_GLRPB_PHW_PHW_SHIFT 0
3243#define I40E_GLRPB_PHW_PHW_MASK (0xFFFFF << I40E_GLRPB_PHW_PHW_SHIFT) 2045#define I40E_GLRPB_PHW_PHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT)
3244#define I40E_GLRPB_PLW 0x000AC848 2046#define I40E_GLRPB_PLW 0x000AC848 /* Reset: CORER */
3245#define I40E_GLRPB_PLW_PLW_SHIFT 0 2047#define I40E_GLRPB_PLW_PLW_SHIFT 0
3246#define I40E_GLRPB_PLW_PLW_MASK (0xFFFFF << I40E_GLRPB_PLW_PLW_SHIFT) 2048#define I40E_GLRPB_PLW_PLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT)
3247#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ 2049#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3248#define I40E_PRTRPB_DHW_MAX_INDEX 7 2050#define I40E_PRTRPB_DHW_MAX_INDEX 7
3249#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0 2051#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0
3250#define I40E_PRTRPB_DHW_DHW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) 2052#define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
3251#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ 2053#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3252#define I40E_PRTRPB_DLW_MAX_INDEX 7 2054#define I40E_PRTRPB_DLW_MAX_INDEX 7
3253#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0 2055#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0
3254#define I40E_PRTRPB_DLW_DLW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) 2056#define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
3255#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ 2057#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3256#define I40E_PRTRPB_DPS_MAX_INDEX 7 2058#define I40E_PRTRPB_DPS_MAX_INDEX 7
3257#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0 2059#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0
3258#define I40E_PRTRPB_DPS_DPS_TCN_MASK (0xFFFFF << I40E_PRTRPB_DPS_DPS_TCN_SHIFT) 2060#define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
3259#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ 2061#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3260#define I40E_PRTRPB_SHT_MAX_INDEX 7 2062#define I40E_PRTRPB_SHT_MAX_INDEX 7
3261#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0 2063#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0
3262#define I40E_PRTRPB_SHT_SHT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) 2064#define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
3263#define I40E_PRTRPB_SHW 0x000AC580 2065#define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */
3264#define I40E_PRTRPB_SHW_SHW_SHIFT 0 2066#define I40E_PRTRPB_SHW_SHW_SHIFT 0
3265#define I40E_PRTRPB_SHW_SHW_MASK (0xFFFFF << I40E_PRTRPB_SHW_SHW_SHIFT) 2067#define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)
3266#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ 2068#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3267#define I40E_PRTRPB_SLT_MAX_INDEX 7 2069#define I40E_PRTRPB_SLT_MAX_INDEX 7
3268#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0 2070#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0
3269#define I40E_PRTRPB_SLT_SLT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) 2071#define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
3270#define I40E_PRTRPB_SLW 0x000AC6A0 2072#define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */
3271#define I40E_PRTRPB_SLW_SLW_SHIFT 0 2073#define I40E_PRTRPB_SLW_SLW_SHIFT 0
3272#define I40E_PRTRPB_SLW_SLW_MASK (0xFFFFF << I40E_PRTRPB_SLW_SLW_SHIFT) 2074#define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)
3273#define I40E_PRTRPB_SPS 0x000AC7C0 2075#define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */
3274#define I40E_PRTRPB_SPS_SPS_SHIFT 0 2076#define I40E_PRTRPB_SPS_SPS_SHIFT 0
3275#define I40E_PRTRPB_SPS_SPS_MASK (0xFFFFF << I40E_PRTRPB_SPS_SPS_SHIFT) 2077#define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)
3276#define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */ 2078#define I40E_GLQF_CTL 0x00269BA4 /* Reset: CORER */
3277#define I40E_GLQF_APBVT_MAX_INDEX 2047
3278#define I40E_GLQF_APBVT_APBVT_SHIFT 0
3279#define I40E_GLQF_APBVT_APBVT_MASK (0xFFFFFFFF << I40E_GLQF_APBVT_APBVT_SHIFT)
3280#define I40E_GLQF_CTL 0x00269BA4
3281#define I40E_GLQF_CTL_HTOEP_SHIFT 1 2079#define I40E_GLQF_CTL_HTOEP_SHIFT 1
3282#define I40E_GLQF_CTL_HTOEP_MASK (0x1 << I40E_GLQF_CTL_HTOEP_SHIFT) 2080#define I40E_GLQF_CTL_HTOEP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT)
3283#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2 2081#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2
3284#define I40E_GLQF_CTL_HTOEP_FCOE_MASK (0x1 << I40E_GLQF_CTL_HTOEP_FCOE_SHIFT) 2082#define I40E_GLQF_CTL_HTOEP_FCOE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)
3285#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3 2083#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3
3286#define I40E_GLQF_CTL_PCNT_ALLOC_MASK (0x7 << I40E_GLQF_CTL_PCNT_ALLOC_SHIFT) 2084#define I40E_GLQF_CTL_PCNT_ALLOC_MASK I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)
2085#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT 6
2086#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT)
3287#define I40E_GLQF_CTL_RSVD_SHIFT 7 2087#define I40E_GLQF_CTL_RSVD_SHIFT 7
3288#define I40E_GLQF_CTL_RSVD_MASK (0x1 << I40E_GLQF_CTL_RSVD_SHIFT) 2088#define I40E_GLQF_CTL_RSVD_MASK I40E_MASK(0x1, I40E_GLQF_CTL_RSVD_SHIFT)
3289#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8 2089#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8
3290#define I40E_GLQF_CTL_MAXPEBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXPEBLEN_SHIFT) 2090#define I40E_GLQF_CTL_MAXPEBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT)
3291#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11 2091#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11
3292#define I40E_GLQF_CTL_MAXFCBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFCBLEN_SHIFT) 2092#define I40E_GLQF_CTL_MAXFCBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT)
3293#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14 2093#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14
3294#define I40E_GLQF_CTL_MAXFDBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFDBLEN_SHIFT) 2094#define I40E_GLQF_CTL_MAXFDBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT)
3295#define I40E_GLQF_CTL_FDBEST_SHIFT 17 2095#define I40E_GLQF_CTL_FDBEST_SHIFT 17
3296#define I40E_GLQF_CTL_FDBEST_MASK (0xFF << I40E_GLQF_CTL_FDBEST_SHIFT) 2096#define I40E_GLQF_CTL_FDBEST_MASK I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT)
3297#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25 2097#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25
3298#define I40E_GLQF_CTL_PROGPRIO_MASK (0x1 << I40E_GLQF_CTL_PROGPRIO_SHIFT) 2098#define I40E_GLQF_CTL_PROGPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_PROGPRIO_SHIFT)
3299#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26 2099#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26
3300#define I40E_GLQF_CTL_INVALPRIO_MASK (0x1 << I40E_GLQF_CTL_INVALPRIO_SHIFT) 2100#define I40E_GLQF_CTL_INVALPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT)
3301#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27 2101#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27
3302#define I40E_GLQF_CTL_IGNORE_IP_MASK (0x1 << I40E_GLQF_CTL_IGNORE_IP_SHIFT) 2102#define I40E_GLQF_CTL_IGNORE_IP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT)
3303#define I40E_GLQF_FDCNT_0 0x00269BAC 2103#define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */
3304#define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 2104#define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0
3305#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) 2105#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
3306#define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 2106#define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13
3307#define I40E_GLQF_FDCNT_0_BESTCNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 2107#define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
3308#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ 2108#define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
2109#define I40E_GLQF_HKEY_MAX_INDEX 12
2110#define I40E_GLQF_HKEY_KEY_0_SHIFT 0
2111#define I40E_GLQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT)
2112#define I40E_GLQF_HKEY_KEY_1_SHIFT 8
2113#define I40E_GLQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT)
2114#define I40E_GLQF_HKEY_KEY_2_SHIFT 16
2115#define I40E_GLQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT)
2116#define I40E_GLQF_HKEY_KEY_3_SHIFT 24
2117#define I40E_GLQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT)
2118#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
3309#define I40E_GLQF_HSYM_MAX_INDEX 63 2119#define I40E_GLQF_HSYM_MAX_INDEX 63
3310#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0 2120#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0
3311#define I40E_GLQF_HSYM_SYMH_ENA_MASK (0x1 << I40E_GLQF_HSYM_SYMH_ENA_SHIFT) 2121#define I40E_GLQF_HSYM_SYMH_ENA_MASK I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT)
3312#define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ 2122#define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */
3313#define I40E_GLQF_PCNT_MAX_INDEX 511 2123#define I40E_GLQF_PCNT_MAX_INDEX 511
3314#define I40E_GLQF_PCNT_PCNT_SHIFT 0 2124#define I40E_GLQF_PCNT_PCNT_SHIFT 0
3315#define I40E_GLQF_PCNT_PCNT_MASK (0xFFFFFFFF << I40E_GLQF_PCNT_PCNT_SHIFT) 2125#define I40E_GLQF_PCNT_PCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT)
3316#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ 2126#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
3317#define I40E_GLQF_SWAP_MAX_INDEX 1 2127#define I40E_GLQF_SWAP_MAX_INDEX 1
3318#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0 2128#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0
3319#define I40E_GLQF_SWAP_OFF0_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT) 2129#define I40E_GLQF_SWAP_OFF0_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)
3320#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6 2130#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6
3321#define I40E_GLQF_SWAP_OFF0_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC1_SHIFT) 2131#define I40E_GLQF_SWAP_OFF0_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT)
3322#define I40E_GLQF_SWAP_FLEN0_SHIFT 12 2132#define I40E_GLQF_SWAP_FLEN0_SHIFT 12
3323#define I40E_GLQF_SWAP_FLEN0_MASK (0xF << I40E_GLQF_SWAP_FLEN0_SHIFT) 2133#define I40E_GLQF_SWAP_FLEN0_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT)
3324#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16 2134#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16
3325#define I40E_GLQF_SWAP_OFF1_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC0_SHIFT) 2135#define I40E_GLQF_SWAP_OFF1_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT)
3326#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22 2136#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22
3327#define I40E_GLQF_SWAP_OFF1_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC1_SHIFT) 2137#define I40E_GLQF_SWAP_OFF1_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)
3328#define I40E_GLQF_SWAP_FLEN1_SHIFT 28 2138#define I40E_GLQF_SWAP_FLEN1_SHIFT 28
3329#define I40E_GLQF_SWAP_FLEN1_MASK (0xF << I40E_GLQF_SWAP_FLEN1_SHIFT) 2139#define I40E_GLQF_SWAP_FLEN1_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT)
3330#define I40E_PFQF_CTL_0 0x001C0AC0 2140#define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */
3331#define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 2141#define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0
3332#define I40E_PFQF_CTL_0_PEHSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) 2142#define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
3333#define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 2143#define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5
3334#define I40E_PFQF_CTL_0_PEDSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) 2144#define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT)
3335#define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 2145#define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10
3336#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) 2146#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT)
3337#define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 2147#define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14
3338#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) 2148#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT)
3339#define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 2149#define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16
3340#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK (0x1 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) 2150#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT)
3341#define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 2151#define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17
3342#define I40E_PFQF_CTL_0_FD_ENA_MASK (0x1 << I40E_PFQF_CTL_0_FD_ENA_SHIFT) 2152#define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT)
3343#define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 2153#define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18
3344#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK (0x1 << I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 2154#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)
3345#define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 2155#define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19
3346#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK (0x1 << I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 2156#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)
3347#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20 2157#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20
3348#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT) 2158#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)
3349#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24 2159#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24
3350#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT) 2160#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)
3351#define I40E_PFQF_CTL_1 0x00245D80 2161#define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */
3352#define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 2162#define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0
3353#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK (0x1 << I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 2163#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
3354#define I40E_PFQF_FDALLOC 0x00246280 2164#define I40E_PFQF_FDALLOC 0x00246280 /* Reset: CORER */
3355#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0 2165#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0
3356#define I40E_PFQF_FDALLOC_FDALLOC_MASK (0xFF << I40E_PFQF_FDALLOC_FDALLOC_SHIFT) 2166#define I40E_PFQF_FDALLOC_FDALLOC_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT)
3357#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8 2167#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8
3358#define I40E_PFQF_FDALLOC_FDBEST_MASK (0xFF << I40E_PFQF_FDALLOC_FDBEST_SHIFT) 2168#define I40E_PFQF_FDALLOC_FDBEST_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT)
3359#define I40E_PFQF_FDSTAT 0x00246380 2169#define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */
3360#define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 2170#define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0
3361#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 2171#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
3362#define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 2172#define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16
3363#define I40E_PFQF_FDSTAT_BEST_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 2173#define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
3364#define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ 2174#define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */
3365#define I40E_PFQF_HENA_MAX_INDEX 1 2175#define I40E_PFQF_HENA_MAX_INDEX 1
3366#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0 2176#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0
3367#define I40E_PFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_PFQF_HENA_PTYPE_ENA_SHIFT) 2177#define I40E_PFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT)
3368#define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ 2178#define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */
3369#define I40E_PFQF_HKEY_MAX_INDEX 12 2179#define I40E_PFQF_HKEY_MAX_INDEX 12
3370#define I40E_PFQF_HKEY_KEY_0_SHIFT 0 2180#define I40E_PFQF_HKEY_KEY_0_SHIFT 0
3371#define I40E_PFQF_HKEY_KEY_0_MASK (0xFF << I40E_PFQF_HKEY_KEY_0_SHIFT) 2181#define I40E_PFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT)
3372#define I40E_PFQF_HKEY_KEY_1_SHIFT 8 2182#define I40E_PFQF_HKEY_KEY_1_SHIFT 8
3373#define I40E_PFQF_HKEY_KEY_1_MASK (0xFF << I40E_PFQF_HKEY_KEY_1_SHIFT) 2183#define I40E_PFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_1_SHIFT)
3374#define I40E_PFQF_HKEY_KEY_2_SHIFT 16 2184#define I40E_PFQF_HKEY_KEY_2_SHIFT 16
3375#define I40E_PFQF_HKEY_KEY_2_MASK (0xFF << I40E_PFQF_HKEY_KEY_2_SHIFT) 2185#define I40E_PFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT)
3376#define I40E_PFQF_HKEY_KEY_3_SHIFT 24 2186#define I40E_PFQF_HKEY_KEY_3_SHIFT 24
3377#define I40E_PFQF_HKEY_KEY_3_MASK (0xFF << I40E_PFQF_HKEY_KEY_3_SHIFT) 2187#define I40E_PFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT)
3378#define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ 2188#define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */
3379#define I40E_PFQF_HLUT_MAX_INDEX 127 2189#define I40E_PFQF_HLUT_MAX_INDEX 127
3380#define I40E_PFQF_HLUT_LUT0_SHIFT 0 2190#define I40E_PFQF_HLUT_LUT0_SHIFT 0
3381#define I40E_PFQF_HLUT_LUT0_MASK (0x3F << I40E_PFQF_HLUT_LUT0_SHIFT) 2191#define I40E_PFQF_HLUT_LUT0_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT)
3382#define I40E_PFQF_HLUT_LUT1_SHIFT 8 2192#define I40E_PFQF_HLUT_LUT1_SHIFT 8
3383#define I40E_PFQF_HLUT_LUT1_MASK (0x3F << I40E_PFQF_HLUT_LUT1_SHIFT) 2193#define I40E_PFQF_HLUT_LUT1_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT1_SHIFT)
3384#define I40E_PFQF_HLUT_LUT2_SHIFT 16 2194#define I40E_PFQF_HLUT_LUT2_SHIFT 16
3385#define I40E_PFQF_HLUT_LUT2_MASK (0x3F << I40E_PFQF_HLUT_LUT2_SHIFT) 2195#define I40E_PFQF_HLUT_LUT2_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT)
3386#define I40E_PFQF_HLUT_LUT3_SHIFT 24 2196#define I40E_PFQF_HLUT_LUT3_SHIFT 24
3387#define I40E_PFQF_HLUT_LUT3_MASK (0x3F << I40E_PFQF_HLUT_LUT3_SHIFT) 2197#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)
3388#define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */ 2198#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */
3389#define I40E_PFQF_HREGION_MAX_INDEX 7
3390#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
3391#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
3392#define I40E_PFQF_HREGION_REGION_0_SHIFT 1
3393#define I40E_PFQF_HREGION_REGION_0_MASK (0x7 << I40E_PFQF_HREGION_REGION_0_SHIFT)
3394#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
3395#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
3396#define I40E_PFQF_HREGION_REGION_1_SHIFT 5
3397#define I40E_PFQF_HREGION_REGION_1_MASK (0x7 << I40E_PFQF_HREGION_REGION_1_SHIFT)
3398#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
3399#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
3400#define I40E_PFQF_HREGION_REGION_2_SHIFT 9
3401#define I40E_PFQF_HREGION_REGION_2_MASK (0x7 << I40E_PFQF_HREGION_REGION_2_SHIFT)
3402#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
3403#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
3404#define I40E_PFQF_HREGION_REGION_3_SHIFT 13
3405#define I40E_PFQF_HREGION_REGION_3_MASK (0x7 << I40E_PFQF_HREGION_REGION_3_SHIFT)
3406#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
3407#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
3408#define I40E_PFQF_HREGION_REGION_4_SHIFT 17
3409#define I40E_PFQF_HREGION_REGION_4_MASK (0x7 << I40E_PFQF_HREGION_REGION_4_SHIFT)
3410#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
3411#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
3412#define I40E_PFQF_HREGION_REGION_5_SHIFT 21
3413#define I40E_PFQF_HREGION_REGION_5_MASK (0x7 << I40E_PFQF_HREGION_REGION_5_SHIFT)
3414#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
3415#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
3416#define I40E_PFQF_HREGION_REGION_6_SHIFT 25
3417#define I40E_PFQF_HREGION_REGION_6_MASK (0x7 << I40E_PFQF_HREGION_REGION_6_SHIFT)
3418#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
3419#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
3420#define I40E_PFQF_HREGION_REGION_7_SHIFT 29
3421#define I40E_PFQF_HREGION_REGION_7_MASK (0x7 << I40E_PFQF_HREGION_REGION_7_SHIFT)
3422#define I40E_PRTQF_CTL_0 0x00256E60
3423#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0 2199#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0
3424#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK (0x1 << I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT) 2200#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)
3425#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ 2201#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */
3426#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63 2202#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63
3427#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0 2203#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0
3428#define I40E_PRTQF_FD_FLXINSET_INSET_MASK (0xFF << I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) 2204#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
3429#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ 2205#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
3430#define I40E_PRTQF_FD_MSK_MAX_INDEX 63 2206#define I40E_PRTQF_FD_MSK_MAX_INDEX 63
3431#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0 2207#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0
3432#define I40E_PRTQF_FD_MSK_MASK_MASK (0xFFFF << I40E_PRTQF_FD_MSK_MASK_SHIFT) 2208#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)
3433#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16 2209#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16
3434#define I40E_PRTQF_FD_MSK_OFFSET_MASK (0x3F << I40E_PRTQF_FD_MSK_OFFSET_SHIFT) 2210#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)
3435#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ 2211#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */
3436#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8 2212#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8
3437#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 2213#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0
3438#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK (0x1F << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 2214#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
3439#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 2215#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5
3440#define I40E_PRTQF_FLX_PIT_FSIZE_MASK (0x1F << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 2216#define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
3441#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 2217#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10
3442#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK (0x3F << I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 2218#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
3443#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) 2219#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */
3444#define I40E_VFQF_HENA1_MAX_INDEX 1 2220#define I40E_VFQF_HENA1_MAX_INDEX 1
3445#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0 2221#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0
3446#define I40E_VFQF_HENA1_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA1_PTYPE_ENA_SHIFT) 2222#define I40E_VFQF_HENA1_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT)
3447#define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ 2223#define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */
3448#define I40E_VFQF_HKEY1_MAX_INDEX 12 2224#define I40E_VFQF_HKEY1_MAX_INDEX 12
3449#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0 2225#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0
3450#define I40E_VFQF_HKEY1_KEY_0_MASK (0xFF << I40E_VFQF_HKEY1_KEY_0_SHIFT) 2226#define I40E_VFQF_HKEY1_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT)
3451#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8 2227#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8
3452#define I40E_VFQF_HKEY1_KEY_1_MASK (0xFF << I40E_VFQF_HKEY1_KEY_1_SHIFT) 2228#define I40E_VFQF_HKEY1_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_1_SHIFT)
3453#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16 2229#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16
3454#define I40E_VFQF_HKEY1_KEY_2_MASK (0xFF << I40E_VFQF_HKEY1_KEY_2_SHIFT) 2230#define I40E_VFQF_HKEY1_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT)
3455#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24 2231#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24
3456#define I40E_VFQF_HKEY1_KEY_3_MASK (0xFF << I40E_VFQF_HKEY1_KEY_3_SHIFT) 2232#define I40E_VFQF_HKEY1_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT)
3457#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ 2233#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
3458#define I40E_VFQF_HLUT1_MAX_INDEX 15 2234#define I40E_VFQF_HLUT1_MAX_INDEX 15
3459#define I40E_VFQF_HLUT1_LUT0_SHIFT 0 2235#define I40E_VFQF_HLUT1_LUT0_SHIFT 0
3460#define I40E_VFQF_HLUT1_LUT0_MASK (0xF << I40E_VFQF_HLUT1_LUT0_SHIFT) 2236#define I40E_VFQF_HLUT1_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT)
3461#define I40E_VFQF_HLUT1_LUT1_SHIFT 8 2237#define I40E_VFQF_HLUT1_LUT1_SHIFT 8
3462#define I40E_VFQF_HLUT1_LUT1_MASK (0xF << I40E_VFQF_HLUT1_LUT1_SHIFT) 2238#define I40E_VFQF_HLUT1_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT1_SHIFT)
3463#define I40E_VFQF_HLUT1_LUT2_SHIFT 16 2239#define I40E_VFQF_HLUT1_LUT2_SHIFT 16
3464#define I40E_VFQF_HLUT1_LUT2_MASK (0xF << I40E_VFQF_HLUT1_LUT2_SHIFT) 2240#define I40E_VFQF_HLUT1_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT)
3465#define I40E_VFQF_HLUT1_LUT3_SHIFT 24 2241#define I40E_VFQF_HLUT1_LUT3_SHIFT 24
3466#define I40E_VFQF_HLUT1_LUT3_MASK (0xF << I40E_VFQF_HLUT1_LUT3_SHIFT) 2242#define I40E_VFQF_HLUT1_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT)
3467#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) 2243#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */
3468#define I40E_VFQF_HREGION1_MAX_INDEX 7 2244#define I40E_VFQF_HREGION1_MAX_INDEX 7
3469#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0 2245#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0
3470#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT) 2246#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT)
3471#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1 2247#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1
3472#define I40E_VFQF_HREGION1_REGION_0_MASK (0x7 << I40E_VFQF_HREGION1_REGION_0_SHIFT) 2248#define I40E_VFQF_HREGION1_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_0_SHIFT)
3473#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4 2249#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4
3474#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT) 2250#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT)
3475#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5 2251#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5
3476#define I40E_VFQF_HREGION1_REGION_1_MASK (0x7 << I40E_VFQF_HREGION1_REGION_1_SHIFT) 2252#define I40E_VFQF_HREGION1_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_1_SHIFT)
3477#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8 2253#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8
3478#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT) 2254#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT)
3479#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9 2255#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9
3480#define I40E_VFQF_HREGION1_REGION_2_MASK (0x7 << I40E_VFQF_HREGION1_REGION_2_SHIFT) 2256#define I40E_VFQF_HREGION1_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_2_SHIFT)
3481#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12 2257#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12
3482#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT) 2258#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT)
3483#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13 2259#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13
3484#define I40E_VFQF_HREGION1_REGION_3_MASK (0x7 << I40E_VFQF_HREGION1_REGION_3_SHIFT) 2260#define I40E_VFQF_HREGION1_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_3_SHIFT)
3485#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16 2261#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16
3486#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT) 2262#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT)
3487#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17 2263#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17
3488#define I40E_VFQF_HREGION1_REGION_4_MASK (0x7 << I40E_VFQF_HREGION1_REGION_4_SHIFT) 2264#define I40E_VFQF_HREGION1_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_4_SHIFT)
3489#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20 2265#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20
3490#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT) 2266#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT)
3491#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21 2267#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21
3492#define I40E_VFQF_HREGION1_REGION_5_MASK (0x7 << I40E_VFQF_HREGION1_REGION_5_SHIFT) 2268#define I40E_VFQF_HREGION1_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_5_SHIFT)
3493#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24 2269#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24
3494#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT) 2270#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT)
3495#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25 2271#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25
3496#define I40E_VFQF_HREGION1_REGION_6_MASK (0x7 << I40E_VFQF_HREGION1_REGION_6_SHIFT) 2272#define I40E_VFQF_HREGION1_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_6_SHIFT)
3497#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28 2273#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28
3498#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT) 2274#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT)
3499#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29 2275#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29
3500#define I40E_VFQF_HREGION1_REGION_7_MASK (0x7 << I40E_VFQF_HREGION1_REGION_7_SHIFT) 2276#define I40E_VFQF_HREGION1_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT)
3501#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ 2277#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
3502#define I40E_VPQF_CTL_MAX_INDEX 127 2278#define I40E_VPQF_CTL_MAX_INDEX 127
3503#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0 2279#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0
3504#define I40E_VPQF_CTL_PEHSIZE_MASK (0x1F << I40E_VPQF_CTL_PEHSIZE_SHIFT) 2280#define I40E_VPQF_CTL_PEHSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT)
3505#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5 2281#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5
3506#define I40E_VPQF_CTL_PEDSIZE_MASK (0x1F << I40E_VPQF_CTL_PEDSIZE_SHIFT) 2282#define I40E_VPQF_CTL_PEDSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEDSIZE_SHIFT)
3507#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10 2283#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10
3508#define I40E_VPQF_CTL_FCHSIZE_MASK (0xF << I40E_VPQF_CTL_FCHSIZE_SHIFT) 2284#define I40E_VPQF_CTL_FCHSIZE_MASK I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT)
3509#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14 2285#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14
3510#define I40E_VPQF_CTL_FCDSIZE_MASK (0x3 << I40E_VPQF_CTL_FCDSIZE_SHIFT) 2286#define I40E_VPQF_CTL_FCDSIZE_MASK I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT)
3511#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ 2287#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
3512#define I40E_VSIQF_CTL_MAX_INDEX 383 2288#define I40E_VSIQF_CTL_MAX_INDEX 383
3513#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0 2289#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0
3514#define I40E_VSIQF_CTL_FCOE_ENA_MASK (0x1 << I40E_VSIQF_CTL_FCOE_ENA_SHIFT) 2290#define I40E_VSIQF_CTL_FCOE_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_FCOE_ENA_SHIFT)
3515#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1 2291#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1
3516#define I40E_VSIQF_CTL_PETCP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PETCP_ENA_SHIFT) 2292#define I40E_VSIQF_CTL_PETCP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PETCP_ENA_SHIFT)
3517#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2 2293#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2
3518#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT) 2294#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT)
3519#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3 2295#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3
3520#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT) 2296#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT)
3521#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4 2297#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4
3522#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT) 2298#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT)
3523#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5 2299#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5
3524#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT) 2300#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)
3525#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) 2301#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */
3526#define I40E_VSIQF_TCREGION_MAX_INDEX 3 2302#define I40E_VSIQF_TCREGION_MAX_INDEX 3
3527#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0 2303#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0
3528#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT) 2304#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)
3529#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9 2305#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9
3530#define I40E_VSIQF_TCREGION_TC_SIZE_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE_SHIFT) 2306#define I40E_VSIQF_TCREGION_TC_SIZE_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE_SHIFT)
3531#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16 2307#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16
3532#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT) 2308#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT)
3533#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25 2309#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25
3534#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT) 2310#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT)
3535#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ 2311#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3536#define I40E_GL_FCOECRC_MAX_INDEX 143 2312#define I40E_GL_FCOECRC_MAX_INDEX 143
3537#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0 2313#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0
3538#define I40E_GL_FCOECRC_FCOECRC_MASK (0xFFFFFFFF << I40E_GL_FCOECRC_FCOECRC_SHIFT) 2314#define I40E_GL_FCOECRC_FCOECRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT)
3539#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ 2315#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3540#define I40E_GL_FCOEDDPC_MAX_INDEX 143 2316#define I40E_GL_FCOEDDPC_MAX_INDEX 143
3541#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0 2317#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0
3542#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK (0xFFFFFFFF << I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT) 2318#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)
3543/* _i=0...143 */ 2319#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3544#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */
3545#define I40E_GL_FCOEDIFEC_MAX_INDEX 143 2320#define I40E_GL_FCOEDIFEC_MAX_INDEX 143
3546#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0 2321#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0
3547#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT) 2322#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT)
3548#define I40E_GL_FCOEDIFRC(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ 2323#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3549#define I40E_GL_FCOEDIFRC_MAX_INDEX 143
3550#define I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT 0
3551#define I40E_GL_FCOEDIFRC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT)
3552#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */
3553#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143 2324#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143
3554#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0 2325#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0
3555#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT) 2326#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT)
3556#define I40E_GL_FCOEDIXAC(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ 2327#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3557#define I40E_GL_FCOEDIXAC_MAX_INDEX 143
3558#define I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT 0
3559#define I40E_GL_FCOEDIXAC_FCOEDIXAC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT)
3560#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */
3561#define I40E_GL_FCOEDIXEC_MAX_INDEX 143 2328#define I40E_GL_FCOEDIXEC_MAX_INDEX 143
3562#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0 2329#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0
3563#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT) 2330#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT)
3564#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ 2331#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3565#define I40E_GL_FCOEDIXVC_MAX_INDEX 143 2332#define I40E_GL_FCOEDIXVC_MAX_INDEX 143
3566#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0 2333#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0
3567#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT) 2334#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT)
3568#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ 2335#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3569#define I40E_GL_FCOEDWRCH_MAX_INDEX 143 2336#define I40E_GL_FCOEDWRCH_MAX_INDEX 143
3570#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0 2337#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0
3571#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK (0xFFFF << I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT) 2338#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT)
3572#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ 2339#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3573#define I40E_GL_FCOEDWRCL_MAX_INDEX 143 2340#define I40E_GL_FCOEDWRCL_MAX_INDEX 143
3574#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0 2341#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0
3575#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT) 2342#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT)
3576#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ 2343#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3577#define I40E_GL_FCOEDWTCH_MAX_INDEX 143 2344#define I40E_GL_FCOEDWTCH_MAX_INDEX 143
3578#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0 2345#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0
3579#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK (0xFFFF << I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT) 2346#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT)
3580#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ 2347#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3581#define I40E_GL_FCOEDWTCL_MAX_INDEX 143 2348#define I40E_GL_FCOEDWTCL_MAX_INDEX 143
3582#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0 2349#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0
3583#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT) 2350#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT)
3584#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ 2351#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3585#define I40E_GL_FCOELAST_MAX_INDEX 143 2352#define I40E_GL_FCOELAST_MAX_INDEX 143
3586#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0 2353#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0
3587#define I40E_GL_FCOELAST_FCOELAST_MASK (0xFFFFFFFF << I40E_GL_FCOELAST_FCOELAST_SHIFT) 2354#define I40E_GL_FCOELAST_FCOELAST_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT)
3588#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ 2355#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3589#define I40E_GL_FCOEPRC_MAX_INDEX 143 2356#define I40E_GL_FCOEPRC_MAX_INDEX 143
3590#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0 2357#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0
3591#define I40E_GL_FCOEPRC_FCOEPRC_MASK (0xFFFFFFFF << I40E_GL_FCOEPRC_FCOEPRC_SHIFT) 2358#define I40E_GL_FCOEPRC_FCOEPRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT)
3592#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ 2359#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3593#define I40E_GL_FCOEPTC_MAX_INDEX 143 2360#define I40E_GL_FCOEPTC_MAX_INDEX 143
3594#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0 2361#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0
3595#define I40E_GL_FCOEPTC_FCOEPTC_MASK (0xFFFFFFFF << I40E_GL_FCOEPTC_FCOEPTC_SHIFT) 2362#define I40E_GL_FCOEPTC_FCOEPTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT)
3596#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ 2363#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3597#define I40E_GL_FCOERPDC_MAX_INDEX 143 2364#define I40E_GL_FCOERPDC_MAX_INDEX 143
3598#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0 2365#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0
3599#define I40E_GL_FCOERPDC_FCOERPDC_MASK (0xFFFFFFFF << I40E_GL_FCOERPDC_FCOERPDC_SHIFT) 2366#define I40E_GL_FCOERPDC_FCOERPDC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT)
3600#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ 2367#define I40E_GL_RXERR1_L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2368#define I40E_GL_RXERR1_L_MAX_INDEX 143
2369#define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0
2370#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT)
2371#define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2372#define I40E_GL_RXERR2_L_MAX_INDEX 143
2373#define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0
2374#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
2375#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3601#define I40E_GLPRT_BPRCH_MAX_INDEX 3 2376#define I40E_GLPRT_BPRCH_MAX_INDEX 3
3602#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0 2377#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0
3603#define I40E_GLPRT_BPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPRCH_UPRCH_SHIFT) 2378#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_UPRCH_SHIFT)
3604#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ 2379#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3605#define I40E_GLPRT_BPRCL_MAX_INDEX 3 2380#define I40E_GLPRT_BPRCL_MAX_INDEX 3
3606#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0 2381#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0
3607#define I40E_GLPRT_BPRCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPRCL_UPRCH_SHIFT) 2382#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_UPRCH_SHIFT)
3608#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ 2383#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3609#define I40E_GLPRT_BPTCH_MAX_INDEX 3 2384#define I40E_GLPRT_BPTCH_MAX_INDEX 3
3610#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0 2385#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0
3611#define I40E_GLPRT_BPTCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPTCH_UPRCH_SHIFT) 2386#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_UPRCH_SHIFT)
3612#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ 2387#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3613#define I40E_GLPRT_BPTCL_MAX_INDEX 3 2388#define I40E_GLPRT_BPTCL_MAX_INDEX 3
3614#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0 2389#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0
3615#define I40E_GLPRT_BPTCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPTCL_UPRCH_SHIFT) 2390#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_UPRCH_SHIFT)
3616#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ 2391#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3617#define I40E_GLPRT_CRCERRS_MAX_INDEX 3 2392#define I40E_GLPRT_CRCERRS_MAX_INDEX 3
3618#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 2393#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0
3619#define I40E_GLPRT_CRCERRS_CRCERRS_MASK (0xFFFFFFFF << I40E_GLPRT_CRCERRS_CRCERRS_SHIFT) 2394#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT)
3620#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ 2395#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3621#define I40E_GLPRT_GORCH_MAX_INDEX 3 2396#define I40E_GLPRT_GORCH_MAX_INDEX 3
3622#define I40E_GLPRT_GORCH_GORCH_SHIFT 0 2397#define I40E_GLPRT_GORCH_GORCH_SHIFT 0
3623#define I40E_GLPRT_GORCH_GORCH_MASK (0xFFFF << I40E_GLPRT_GORCH_GORCH_SHIFT) 2398#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT)
3624#define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ 2399#define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3625#define I40E_GLPRT_GORCL_MAX_INDEX 3 2400#define I40E_GLPRT_GORCL_MAX_INDEX 3
3626#define I40E_GLPRT_GORCL_GORCL_SHIFT 0 2401#define I40E_GLPRT_GORCL_GORCL_SHIFT 0
3627#define I40E_GLPRT_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLPRT_GORCL_GORCL_SHIFT) 2402#define I40E_GLPRT_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT)
3628#define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ 2403#define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3629#define I40E_GLPRT_GOTCH_MAX_INDEX 3 2404#define I40E_GLPRT_GOTCH_MAX_INDEX 3
3630#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0 2405#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0
3631#define I40E_GLPRT_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLPRT_GOTCH_GOTCH_SHIFT) 2406#define I40E_GLPRT_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT)
3632#define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ 2407#define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3633#define I40E_GLPRT_GOTCL_MAX_INDEX 3 2408#define I40E_GLPRT_GOTCL_MAX_INDEX 3
3634#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0 2409#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0
3635#define I40E_GLPRT_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLPRT_GOTCL_GOTCL_SHIFT) 2410#define I40E_GLPRT_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT)
3636#define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ 2411#define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3637#define I40E_GLPRT_ILLERRC_MAX_INDEX 3 2412#define I40E_GLPRT_ILLERRC_MAX_INDEX 3
3638#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0 2413#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0
3639#define I40E_GLPRT_ILLERRC_ILLERRC_MASK (0xFFFFFFFF << I40E_GLPRT_ILLERRC_ILLERRC_SHIFT) 2414#define I40E_GLPRT_ILLERRC_ILLERRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT)
3640#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ 2415#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3641#define I40E_GLPRT_LDPC_MAX_INDEX 3 2416#define I40E_GLPRT_LDPC_MAX_INDEX 3
3642#define I40E_GLPRT_LDPC_LDPC_SHIFT 0 2417#define I40E_GLPRT_LDPC_LDPC_SHIFT 0
3643#define I40E_GLPRT_LDPC_LDPC_MASK (0xFFFFFFFF << I40E_GLPRT_LDPC_LDPC_SHIFT) 2418#define I40E_GLPRT_LDPC_LDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT)
3644#define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ 2419#define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3645#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3 2420#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3
3646#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0 2421#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0
3647#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT) 2422#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT)
3648#define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ 2423#define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3649#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3 2424#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3
3650#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0 2425#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0
3651#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT) 2426#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT)
3652#define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ 2427#define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3653#define I40E_GLPRT_LXONRXC_MAX_INDEX 3 2428#define I40E_GLPRT_LXONRXC_MAX_INDEX 3
3654#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0 2429#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0
3655#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT) 2430#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT)
3656#define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ 2431#define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3657#define I40E_GLPRT_LXONTXC_MAX_INDEX 3 2432#define I40E_GLPRT_LXONTXC_MAX_INDEX 3
3658#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0 2433#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0
3659#define I40E_GLPRT_LXONTXC_LXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXONTXC_LXONTXC_SHIFT) 2434#define I40E_GLPRT_LXONTXC_LXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT)
3660#define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ 2435#define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3661#define I40E_GLPRT_MLFC_MAX_INDEX 3 2436#define I40E_GLPRT_MLFC_MAX_INDEX 3
3662#define I40E_GLPRT_MLFC_MLFC_SHIFT 0 2437#define I40E_GLPRT_MLFC_MLFC_SHIFT 0
3663#define I40E_GLPRT_MLFC_MLFC_MASK (0xFFFFFFFF << I40E_GLPRT_MLFC_MLFC_SHIFT) 2438#define I40E_GLPRT_MLFC_MLFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT)
3664#define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ 2439#define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3665#define I40E_GLPRT_MPRCH_MAX_INDEX 3 2440#define I40E_GLPRT_MPRCH_MAX_INDEX 3
3666#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0 2441#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0
3667#define I40E_GLPRT_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLPRT_MPRCH_MPRCH_SHIFT) 2442#define I40E_GLPRT_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT)
3668#define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ 2443#define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3669#define I40E_GLPRT_MPRCL_MAX_INDEX 3 2444#define I40E_GLPRT_MPRCL_MAX_INDEX 3
3670#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0 2445#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0
3671#define I40E_GLPRT_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPRCL_MPRCL_SHIFT) 2446#define I40E_GLPRT_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT)
3672#define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ 2447#define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3673#define I40E_GLPRT_MPTCH_MAX_INDEX 3 2448#define I40E_GLPRT_MPTCH_MAX_INDEX 3
3674#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0 2449#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0
3675#define I40E_GLPRT_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLPRT_MPTCH_MPTCH_SHIFT) 2450#define I40E_GLPRT_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT)
3676#define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ 2451#define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3677#define I40E_GLPRT_MPTCL_MAX_INDEX 3 2452#define I40E_GLPRT_MPTCL_MAX_INDEX 3
3678#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0 2453#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0
3679#define I40E_GLPRT_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPTCL_MPTCL_SHIFT) 2454#define I40E_GLPRT_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT)
3680#define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ 2455#define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3681#define I40E_GLPRT_MRFC_MAX_INDEX 3 2456#define I40E_GLPRT_MRFC_MAX_INDEX 3
3682#define I40E_GLPRT_MRFC_MRFC_SHIFT 0 2457#define I40E_GLPRT_MRFC_MRFC_SHIFT 0
3683#define I40E_GLPRT_MRFC_MRFC_MASK (0xFFFFFFFF << I40E_GLPRT_MRFC_MRFC_SHIFT) 2458#define I40E_GLPRT_MRFC_MRFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT)
3684#define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ 2459#define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3685#define I40E_GLPRT_PRC1023H_MAX_INDEX 3 2460#define I40E_GLPRT_PRC1023H_MAX_INDEX 3
3686#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0 2461#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0
3687#define I40E_GLPRT_PRC1023H_PRC1023H_MASK (0xFFFF << I40E_GLPRT_PRC1023H_PRC1023H_SHIFT) 2462#define I40E_GLPRT_PRC1023H_PRC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT)
3688#define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ 2463#define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3689#define I40E_GLPRT_PRC1023L_MAX_INDEX 3 2464#define I40E_GLPRT_PRC1023L_MAX_INDEX 3
3690#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0 2465#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0
3691#define I40E_GLPRT_PRC1023L_PRC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1023L_PRC1023L_SHIFT) 2466#define I40E_GLPRT_PRC1023L_PRC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT)
3692#define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ 2467#define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3693#define I40E_GLPRT_PRC127H_MAX_INDEX 3 2468#define I40E_GLPRT_PRC127H_MAX_INDEX 3
3694#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0 2469#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0
3695#define I40E_GLPRT_PRC127H_PRC127H_MASK (0xFFFF << I40E_GLPRT_PRC127H_PRC127H_SHIFT) 2470#define I40E_GLPRT_PRC127H_PRC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT)
3696#define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ 2471#define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3697#define I40E_GLPRT_PRC127L_MAX_INDEX 3 2472#define I40E_GLPRT_PRC127L_MAX_INDEX 3
3698#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0 2473#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0
3699#define I40E_GLPRT_PRC127L_PRC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC127L_PRC127L_SHIFT) 2474#define I40E_GLPRT_PRC127L_PRC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT)
3700#define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ 2475#define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3701#define I40E_GLPRT_PRC1522H_MAX_INDEX 3 2476#define I40E_GLPRT_PRC1522H_MAX_INDEX 3
3702#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0 2477#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0
3703#define I40E_GLPRT_PRC1522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC1522H_PRC1522H_SHIFT) 2478#define I40E_GLPRT_PRC1522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT)
3704#define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ 2479#define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3705#define I40E_GLPRT_PRC1522L_MAX_INDEX 3 2480#define I40E_GLPRT_PRC1522L_MAX_INDEX 3
3706#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0 2481#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0
3707#define I40E_GLPRT_PRC1522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1522L_PRC1522L_SHIFT) 2482#define I40E_GLPRT_PRC1522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT)
3708#define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ 2483#define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3709#define I40E_GLPRT_PRC255H_MAX_INDEX 3 2484#define I40E_GLPRT_PRC255H_MAX_INDEX 3
3710#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0 2485#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0
3711#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK (0xFFFF << I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT) 2486#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT)
3712#define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ 2487#define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3713#define I40E_GLPRT_PRC255L_MAX_INDEX 3 2488#define I40E_GLPRT_PRC255L_MAX_INDEX 3
3714#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0 2489#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0
3715#define I40E_GLPRT_PRC255L_PRC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC255L_PRC255L_SHIFT) 2490#define I40E_GLPRT_PRC255L_PRC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT)
3716#define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ 2491#define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3717#define I40E_GLPRT_PRC511H_MAX_INDEX 3 2492#define I40E_GLPRT_PRC511H_MAX_INDEX 3
3718#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0 2493#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0
3719#define I40E_GLPRT_PRC511H_PRC511H_MASK (0xFFFF << I40E_GLPRT_PRC511H_PRC511H_SHIFT) 2494#define I40E_GLPRT_PRC511H_PRC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT)
3720#define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ 2495#define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3721#define I40E_GLPRT_PRC511L_MAX_INDEX 3 2496#define I40E_GLPRT_PRC511L_MAX_INDEX 3
3722#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0 2497#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0
3723#define I40E_GLPRT_PRC511L_PRC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC511L_PRC511L_SHIFT) 2498#define I40E_GLPRT_PRC511L_PRC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT)
3724#define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ 2499#define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3725#define I40E_GLPRT_PRC64H_MAX_INDEX 3 2500#define I40E_GLPRT_PRC64H_MAX_INDEX 3
3726#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0 2501#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0
3727#define I40E_GLPRT_PRC64H_PRC64H_MASK (0xFFFF << I40E_GLPRT_PRC64H_PRC64H_SHIFT) 2502#define I40E_GLPRT_PRC64H_PRC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT)
3728#define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ 2503#define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3729#define I40E_GLPRT_PRC64L_MAX_INDEX 3 2504#define I40E_GLPRT_PRC64L_MAX_INDEX 3
3730#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0 2505#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0
3731#define I40E_GLPRT_PRC64L_PRC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC64L_PRC64L_SHIFT) 2506#define I40E_GLPRT_PRC64L_PRC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT)
3732#define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ 2507#define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3733#define I40E_GLPRT_PRC9522H_MAX_INDEX 3 2508#define I40E_GLPRT_PRC9522H_MAX_INDEX 3
3734#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0 2509#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0
3735#define I40E_GLPRT_PRC9522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC9522H_PRC1522H_SHIFT) 2510#define I40E_GLPRT_PRC9522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT)
3736#define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ 2511#define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3737#define I40E_GLPRT_PRC9522L_MAX_INDEX 3 2512#define I40E_GLPRT_PRC9522L_MAX_INDEX 3
3738#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0 2513#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0
3739#define I40E_GLPRT_PRC9522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC9522L_PRC1522L_SHIFT) 2514#define I40E_GLPRT_PRC9522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT)
3740#define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ 2515#define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3741#define I40E_GLPRT_PTC1023H_MAX_INDEX 3 2516#define I40E_GLPRT_PTC1023H_MAX_INDEX 3
3742#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0 2517#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0
3743#define I40E_GLPRT_PTC1023H_PTC1023H_MASK (0xFFFF << I40E_GLPRT_PTC1023H_PTC1023H_SHIFT) 2518#define I40E_GLPRT_PTC1023H_PTC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT)
3744#define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ 2519#define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3745#define I40E_GLPRT_PTC1023L_MAX_INDEX 3 2520#define I40E_GLPRT_PTC1023L_MAX_INDEX 3
3746#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0 2521#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0
3747#define I40E_GLPRT_PTC1023L_PTC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1023L_PTC1023L_SHIFT) 2522#define I40E_GLPRT_PTC1023L_PTC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT)
3748#define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ 2523#define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3749#define I40E_GLPRT_PTC127H_MAX_INDEX 3 2524#define I40E_GLPRT_PTC127H_MAX_INDEX 3
3750#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0 2525#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0
3751#define I40E_GLPRT_PTC127H_PTC127H_MASK (0xFFFF << I40E_GLPRT_PTC127H_PTC127H_SHIFT) 2526#define I40E_GLPRT_PTC127H_PTC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT)
3752#define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ 2527#define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3753#define I40E_GLPRT_PTC127L_MAX_INDEX 3 2528#define I40E_GLPRT_PTC127L_MAX_INDEX 3
3754#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0 2529#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0
3755#define I40E_GLPRT_PTC127L_PTC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC127L_PTC127L_SHIFT) 2530#define I40E_GLPRT_PTC127L_PTC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT)
3756#define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ 2531#define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3757#define I40E_GLPRT_PTC1522H_MAX_INDEX 3 2532#define I40E_GLPRT_PTC1522H_MAX_INDEX 3
3758#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0 2533#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0
3759#define I40E_GLPRT_PTC1522H_PTC1522H_MASK (0xFFFF << I40E_GLPRT_PTC1522H_PTC1522H_SHIFT) 2534#define I40E_GLPRT_PTC1522H_PTC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT)
3760#define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ 2535#define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3761#define I40E_GLPRT_PTC1522L_MAX_INDEX 3 2536#define I40E_GLPRT_PTC1522L_MAX_INDEX 3
3762#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0 2537#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0
3763#define I40E_GLPRT_PTC1522L_PTC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1522L_PTC1522L_SHIFT) 2538#define I40E_GLPRT_PTC1522L_PTC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT)
3764#define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ 2539#define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3765#define I40E_GLPRT_PTC255H_MAX_INDEX 3 2540#define I40E_GLPRT_PTC255H_MAX_INDEX 3
3766#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0 2541#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0
3767#define I40E_GLPRT_PTC255H_PTC255H_MASK (0xFFFF << I40E_GLPRT_PTC255H_PTC255H_SHIFT) 2542#define I40E_GLPRT_PTC255H_PTC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT)
3768#define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ 2543#define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3769#define I40E_GLPRT_PTC255L_MAX_INDEX 3 2544#define I40E_GLPRT_PTC255L_MAX_INDEX 3
3770#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0 2545#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0
3771#define I40E_GLPRT_PTC255L_PTC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC255L_PTC255L_SHIFT) 2546#define I40E_GLPRT_PTC255L_PTC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT)
3772#define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ 2547#define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3773#define I40E_GLPRT_PTC511H_MAX_INDEX 3 2548#define I40E_GLPRT_PTC511H_MAX_INDEX 3
3774#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0 2549#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0
3775#define I40E_GLPRT_PTC511H_PTC511H_MASK (0xFFFF << I40E_GLPRT_PTC511H_PTC511H_SHIFT) 2550#define I40E_GLPRT_PTC511H_PTC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT)
3776#define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ 2551#define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3777#define I40E_GLPRT_PTC511L_MAX_INDEX 3 2552#define I40E_GLPRT_PTC511L_MAX_INDEX 3
3778#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0 2553#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0
3779#define I40E_GLPRT_PTC511L_PTC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC511L_PTC511L_SHIFT) 2554#define I40E_GLPRT_PTC511L_PTC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT)
3780#define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ 2555#define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3781#define I40E_GLPRT_PTC64H_MAX_INDEX 3 2556#define I40E_GLPRT_PTC64H_MAX_INDEX 3
3782#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0 2557#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0
3783#define I40E_GLPRT_PTC64H_PTC64H_MASK (0xFFFF << I40E_GLPRT_PTC64H_PTC64H_SHIFT) 2558#define I40E_GLPRT_PTC64H_PTC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT)
3784#define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ 2559#define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3785#define I40E_GLPRT_PTC64L_MAX_INDEX 3 2560#define I40E_GLPRT_PTC64L_MAX_INDEX 3
3786#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0 2561#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0
3787#define I40E_GLPRT_PTC64L_PTC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC64L_PTC64L_SHIFT) 2562#define I40E_GLPRT_PTC64L_PTC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT)
3788#define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ 2563#define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3789#define I40E_GLPRT_PTC9522H_MAX_INDEX 3 2564#define I40E_GLPRT_PTC9522H_MAX_INDEX 3
3790#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0 2565#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0
3791#define I40E_GLPRT_PTC9522H_PTC9522H_MASK (0xFFFF << I40E_GLPRT_PTC9522H_PTC9522H_SHIFT) 2566#define I40E_GLPRT_PTC9522H_PTC9522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT)
3792#define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ 2567#define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3793#define I40E_GLPRT_PTC9522L_MAX_INDEX 3 2568#define I40E_GLPRT_PTC9522L_MAX_INDEX 3
3794#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0 2569#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0
3795#define I40E_GLPRT_PTC9522L_PTC9522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC9522L_PTC9522L_SHIFT) 2570#define I40E_GLPRT_PTC9522L_PTC9522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT)
3796#define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) 2571#define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3797#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3 2572#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3
3798#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0 2573#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0
3799#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT) 2574#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT)
3800#define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) 2575#define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3801#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3 2576#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3
3802#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0 2577#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0
3803#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT) 2578#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT)
3804#define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) 2579#define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3805#define I40E_GLPRT_PXONRXC_MAX_INDEX 3 2580#define I40E_GLPRT_PXONRXC_MAX_INDEX 3
3806#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0 2581#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0
3807#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT) 2582#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT)
3808#define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) 2583#define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3809#define I40E_GLPRT_PXONTXC_MAX_INDEX 3 2584#define I40E_GLPRT_PXONTXC_MAX_INDEX 3
3810#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0 2585#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0
3811#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT) 2586#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT)
3812#define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ 2587#define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3813#define I40E_GLPRT_RDPC_MAX_INDEX 3 2588#define I40E_GLPRT_RDPC_MAX_INDEX 3
3814#define I40E_GLPRT_RDPC_RDPC_SHIFT 0 2589#define I40E_GLPRT_RDPC_RDPC_SHIFT 0
3815#define I40E_GLPRT_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLPRT_RDPC_RDPC_SHIFT) 2590#define I40E_GLPRT_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT)
3816#define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ 2591#define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3817#define I40E_GLPRT_RFC_MAX_INDEX 3 2592#define I40E_GLPRT_RFC_MAX_INDEX 3
3818#define I40E_GLPRT_RFC_RFC_SHIFT 0 2593#define I40E_GLPRT_RFC_RFC_SHIFT 0
3819#define I40E_GLPRT_RFC_RFC_MASK (0xFFFFFFFF << I40E_GLPRT_RFC_RFC_SHIFT) 2594#define I40E_GLPRT_RFC_RFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT)
3820#define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ 2595#define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3821#define I40E_GLPRT_RJC_MAX_INDEX 3 2596#define I40E_GLPRT_RJC_MAX_INDEX 3
3822#define I40E_GLPRT_RJC_RJC_SHIFT 0 2597#define I40E_GLPRT_RJC_RJC_SHIFT 0
3823#define I40E_GLPRT_RJC_RJC_MASK (0xFFFFFFFF << I40E_GLPRT_RJC_RJC_SHIFT) 2598#define I40E_GLPRT_RJC_RJC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT)
3824#define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ 2599#define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3825#define I40E_GLPRT_RLEC_MAX_INDEX 3 2600#define I40E_GLPRT_RLEC_MAX_INDEX 3
3826#define I40E_GLPRT_RLEC_RLEC_SHIFT 0 2601#define I40E_GLPRT_RLEC_RLEC_SHIFT 0
3827#define I40E_GLPRT_RLEC_RLEC_MASK (0xFFFFFFFF << I40E_GLPRT_RLEC_RLEC_SHIFT) 2602#define I40E_GLPRT_RLEC_RLEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT)
3828#define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ 2603#define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3829#define I40E_GLPRT_ROC_MAX_INDEX 3 2604#define I40E_GLPRT_ROC_MAX_INDEX 3
3830#define I40E_GLPRT_ROC_ROC_SHIFT 0 2605#define I40E_GLPRT_ROC_ROC_SHIFT 0
3831#define I40E_GLPRT_ROC_ROC_MASK (0xFFFFFFFF << I40E_GLPRT_ROC_ROC_SHIFT) 2606#define I40E_GLPRT_ROC_ROC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT)
3832#define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ 2607#define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3833#define I40E_GLPRT_RUC_MAX_INDEX 3 2608#define I40E_GLPRT_RUC_MAX_INDEX 3
3834#define I40E_GLPRT_RUC_RUC_SHIFT 0 2609#define I40E_GLPRT_RUC_RUC_SHIFT 0
3835#define I40E_GLPRT_RUC_RUC_MASK (0xFFFFFFFF << I40E_GLPRT_RUC_RUC_SHIFT) 2610#define I40E_GLPRT_RUC_RUC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT)
3836#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ 2611#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3837#define I40E_GLPRT_RUPP_MAX_INDEX 3 2612#define I40E_GLPRT_RUPP_MAX_INDEX 3
3838#define I40E_GLPRT_RUPP_RUPP_SHIFT 0 2613#define I40E_GLPRT_RUPP_RUPP_SHIFT 0
3839#define I40E_GLPRT_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLPRT_RUPP_RUPP_SHIFT) 2614#define I40E_GLPRT_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT)
3840#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) 2615#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3841#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3 2616#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3
3842#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0 2617#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0
3843#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK (0xFFFFFFFF << I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT) 2618#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT)
3844#define I40E_GLPRT_STDC(_i) (0x00300640 + ((_i) * 8)) /* _i=0...3 */ 2619#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3845#define I40E_GLPRT_STDC_MAX_INDEX 3
3846#define I40E_GLPRT_STDC_STDC_SHIFT 0
3847#define I40E_GLPRT_STDC_STDC_MASK (0xFFFFFFFF << I40E_GLPRT_STDC_STDC_SHIFT)
3848#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */
3849#define I40E_GLPRT_TDOLD_MAX_INDEX 3 2620#define I40E_GLPRT_TDOLD_MAX_INDEX 3
3850#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 2621#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0
3851#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK (0xFFFFFFFF << I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) 2622#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
3852#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ 2623#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3853#define I40E_GLPRT_TDPC_MAX_INDEX 3 2624#define I40E_GLPRT_TDPC_MAX_INDEX 3
3854#define I40E_GLPRT_TDPC_TDPC_SHIFT 0 2625#define I40E_GLPRT_TDPC_TDPC_SHIFT 0
3855#define I40E_GLPRT_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLPRT_TDPC_TDPC_SHIFT) 2626#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDPC_TDPC_SHIFT)
3856#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ 2627#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3857#define I40E_GLPRT_UPRCH_MAX_INDEX 3 2628#define I40E_GLPRT_UPRCH_MAX_INDEX 3
3858#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 2629#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
3859#define I40E_GLPRT_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_UPRCH_UPRCH_SHIFT) 2630#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT)
3860#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ 2631#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3861#define I40E_GLPRT_UPRCL_MAX_INDEX 3 2632#define I40E_GLPRT_UPRCL_MAX_INDEX 3
3862#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0 2633#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0
3863#define I40E_GLPRT_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_UPRCL_UPRCL_SHIFT) 2634#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT)
3864#define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ 2635#define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3865#define I40E_GLPRT_UPTCH_MAX_INDEX 3 2636#define I40E_GLPRT_UPTCH_MAX_INDEX 3
3866#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0 2637#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0
3867#define I40E_GLPRT_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLPRT_UPTCH_UPTCH_SHIFT) 2638#define I40E_GLPRT_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT)
3868#define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ 2639#define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3869#define I40E_GLPRT_UPTCL_MAX_INDEX 3 2640#define I40E_GLPRT_UPTCL_MAX_INDEX 3
3870#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0 2641#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0
3871#define I40E_GLPRT_UPTCL_VUPTCH_MASK (0xFFFFFFFF << I40E_GLPRT_UPTCL_VUPTCH_SHIFT) 2642#define I40E_GLPRT_UPTCL_VUPTCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT)
3872#define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ 2643#define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3873#define I40E_GLSW_BPRCH_MAX_INDEX 15 2644#define I40E_GLSW_BPRCH_MAX_INDEX 15
3874#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0 2645#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0
3875#define I40E_GLSW_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLSW_BPRCH_BPRCH_SHIFT) 2646#define I40E_GLSW_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT)
3876#define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ 2647#define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3877#define I40E_GLSW_BPRCL_MAX_INDEX 15 2648#define I40E_GLSW_BPRCL_MAX_INDEX 15
3878#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0 2649#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0
3879#define I40E_GLSW_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLSW_BPRCL_BPRCL_SHIFT) 2650#define I40E_GLSW_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT)
3880#define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ 2651#define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3881#define I40E_GLSW_BPTCH_MAX_INDEX 15 2652#define I40E_GLSW_BPTCH_MAX_INDEX 15
3882#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0 2653#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0
3883#define I40E_GLSW_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLSW_BPTCH_BPTCH_SHIFT) 2654#define I40E_GLSW_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT)
3884#define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ 2655#define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3885#define I40E_GLSW_BPTCL_MAX_INDEX 15 2656#define I40E_GLSW_BPTCL_MAX_INDEX 15
3886#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0 2657#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0
3887#define I40E_GLSW_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLSW_BPTCL_BPTCL_SHIFT) 2658#define I40E_GLSW_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT)
3888#define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ 2659#define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3889#define I40E_GLSW_GORCH_MAX_INDEX 15 2660#define I40E_GLSW_GORCH_MAX_INDEX 15
3890#define I40E_GLSW_GORCH_GORCH_SHIFT 0 2661#define I40E_GLSW_GORCH_GORCH_SHIFT 0
3891#define I40E_GLSW_GORCH_GORCH_MASK (0xFFFF << I40E_GLSW_GORCH_GORCH_SHIFT) 2662#define I40E_GLSW_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT)
3892#define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ 2663#define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3893#define I40E_GLSW_GORCL_MAX_INDEX 15 2664#define I40E_GLSW_GORCL_MAX_INDEX 15
3894#define I40E_GLSW_GORCL_GORCL_SHIFT 0 2665#define I40E_GLSW_GORCL_GORCL_SHIFT 0
3895#define I40E_GLSW_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLSW_GORCL_GORCL_SHIFT) 2666#define I40E_GLSW_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT)
3896#define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ 2667#define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3897#define I40E_GLSW_GOTCH_MAX_INDEX 15 2668#define I40E_GLSW_GOTCH_MAX_INDEX 15
3898#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0 2669#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0
3899#define I40E_GLSW_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLSW_GOTCH_GOTCH_SHIFT) 2670#define I40E_GLSW_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT)
3900#define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ 2671#define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3901#define I40E_GLSW_GOTCL_MAX_INDEX 15 2672#define I40E_GLSW_GOTCL_MAX_INDEX 15
3902#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0 2673#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0
3903#define I40E_GLSW_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLSW_GOTCL_GOTCL_SHIFT) 2674#define I40E_GLSW_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT)
3904#define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ 2675#define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3905#define I40E_GLSW_MPRCH_MAX_INDEX 15 2676#define I40E_GLSW_MPRCH_MAX_INDEX 15
3906#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0 2677#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0
3907#define I40E_GLSW_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLSW_MPRCH_MPRCH_SHIFT) 2678#define I40E_GLSW_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT)
3908#define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ 2679#define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3909#define I40E_GLSW_MPRCL_MAX_INDEX 15 2680#define I40E_GLSW_MPRCL_MAX_INDEX 15
3910#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0 2681#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0
3911#define I40E_GLSW_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLSW_MPRCL_MPRCL_SHIFT) 2682#define I40E_GLSW_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT)
3912#define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ 2683#define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3913#define I40E_GLSW_MPTCH_MAX_INDEX 15 2684#define I40E_GLSW_MPTCH_MAX_INDEX 15
3914#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0 2685#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0
3915#define I40E_GLSW_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLSW_MPTCH_MPTCH_SHIFT) 2686#define I40E_GLSW_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT)
3916#define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ 2687#define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3917#define I40E_GLSW_MPTCL_MAX_INDEX 15 2688#define I40E_GLSW_MPTCL_MAX_INDEX 15
3918#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0 2689#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0
3919#define I40E_GLSW_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLSW_MPTCL_MPTCL_SHIFT) 2690#define I40E_GLSW_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT)
3920#define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ 2691#define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3921#define I40E_GLSW_RUPP_MAX_INDEX 15 2692#define I40E_GLSW_RUPP_MAX_INDEX 15
3922#define I40E_GLSW_RUPP_RUPP_SHIFT 0 2693#define I40E_GLSW_RUPP_RUPP_SHIFT 0
3923#define I40E_GLSW_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLSW_RUPP_RUPP_SHIFT) 2694#define I40E_GLSW_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT)
3924#define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ 2695#define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3925#define I40E_GLSW_TDPC_MAX_INDEX 15 2696#define I40E_GLSW_TDPC_MAX_INDEX 15
3926#define I40E_GLSW_TDPC_TDPC_SHIFT 0 2697#define I40E_GLSW_TDPC_TDPC_SHIFT 0
3927#define I40E_GLSW_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLSW_TDPC_TDPC_SHIFT) 2698#define I40E_GLSW_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT)
3928#define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ 2699#define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3929#define I40E_GLSW_UPRCH_MAX_INDEX 15 2700#define I40E_GLSW_UPRCH_MAX_INDEX 15
3930#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0 2701#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0
3931#define I40E_GLSW_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLSW_UPRCH_UPRCH_SHIFT) 2702#define I40E_GLSW_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT)
3932#define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ 2703#define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3933#define I40E_GLSW_UPRCL_MAX_INDEX 15 2704#define I40E_GLSW_UPRCL_MAX_INDEX 15
3934#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0 2705#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0
3935#define I40E_GLSW_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLSW_UPRCL_UPRCL_SHIFT) 2706#define I40E_GLSW_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT)
3936#define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ 2707#define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3937#define I40E_GLSW_UPTCH_MAX_INDEX 15 2708#define I40E_GLSW_UPTCH_MAX_INDEX 15
3938#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0 2709#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0
3939#define I40E_GLSW_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLSW_UPTCH_UPTCH_SHIFT) 2710#define I40E_GLSW_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT)
3940#define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ 2711#define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3941#define I40E_GLSW_UPTCL_MAX_INDEX 15 2712#define I40E_GLSW_UPTCL_MAX_INDEX 15
3942#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0 2713#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0
3943#define I40E_GLSW_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLSW_UPTCL_UPTCL_SHIFT) 2714#define I40E_GLSW_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT)
3944#define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ 2715#define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3945#define I40E_GLV_BPRCH_MAX_INDEX 383 2716#define I40E_GLV_BPRCH_MAX_INDEX 383
3946#define I40E_GLV_BPRCH_BPRCH_SHIFT 0 2717#define I40E_GLV_BPRCH_BPRCH_SHIFT 0
3947#define I40E_GLV_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLV_BPRCH_BPRCH_SHIFT) 2718#define I40E_GLV_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT)
3948#define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ 2719#define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3949#define I40E_GLV_BPRCL_MAX_INDEX 383 2720#define I40E_GLV_BPRCL_MAX_INDEX 383
3950#define I40E_GLV_BPRCL_BPRCL_SHIFT 0 2721#define I40E_GLV_BPRCL_BPRCL_SHIFT 0
3951#define I40E_GLV_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLV_BPRCL_BPRCL_SHIFT) 2722#define I40E_GLV_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT)
3952#define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ 2723#define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3953#define I40E_GLV_BPTCH_MAX_INDEX 383 2724#define I40E_GLV_BPTCH_MAX_INDEX 383
3954#define I40E_GLV_BPTCH_BPTCH_SHIFT 0 2725#define I40E_GLV_BPTCH_BPTCH_SHIFT 0
3955#define I40E_GLV_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLV_BPTCH_BPTCH_SHIFT) 2726#define I40E_GLV_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT)
3956#define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ 2727#define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3957#define I40E_GLV_BPTCL_MAX_INDEX 383 2728#define I40E_GLV_BPTCL_MAX_INDEX 383
3958#define I40E_GLV_BPTCL_BPTCL_SHIFT 0 2729#define I40E_GLV_BPTCL_BPTCL_SHIFT 0
3959#define I40E_GLV_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLV_BPTCL_BPTCL_SHIFT) 2730#define I40E_GLV_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT)
3960#define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ 2731#define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3961#define I40E_GLV_GORCH_MAX_INDEX 383 2732#define I40E_GLV_GORCH_MAX_INDEX 383
3962#define I40E_GLV_GORCH_GORCH_SHIFT 0 2733#define I40E_GLV_GORCH_GORCH_SHIFT 0
3963#define I40E_GLV_GORCH_GORCH_MASK (0xFFFF << I40E_GLV_GORCH_GORCH_SHIFT) 2734#define I40E_GLV_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT)
3964#define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ 2735#define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3965#define I40E_GLV_GORCL_MAX_INDEX 383 2736#define I40E_GLV_GORCL_MAX_INDEX 383
3966#define I40E_GLV_GORCL_GORCL_SHIFT 0 2737#define I40E_GLV_GORCL_GORCL_SHIFT 0
3967#define I40E_GLV_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLV_GORCL_GORCL_SHIFT) 2738#define I40E_GLV_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT)
3968#define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ 2739#define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3969#define I40E_GLV_GOTCH_MAX_INDEX 383 2740#define I40E_GLV_GOTCH_MAX_INDEX 383
3970#define I40E_GLV_GOTCH_GOTCH_SHIFT 0 2741#define I40E_GLV_GOTCH_GOTCH_SHIFT 0
3971#define I40E_GLV_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLV_GOTCH_GOTCH_SHIFT) 2742#define I40E_GLV_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT)
3972#define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ 2743#define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3973#define I40E_GLV_GOTCL_MAX_INDEX 383 2744#define I40E_GLV_GOTCL_MAX_INDEX 383
3974#define I40E_GLV_GOTCL_GOTCL_SHIFT 0 2745#define I40E_GLV_GOTCL_GOTCL_SHIFT 0
3975#define I40E_GLV_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLV_GOTCL_GOTCL_SHIFT) 2746#define I40E_GLV_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT)
3976#define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ 2747#define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3977#define I40E_GLV_MPRCH_MAX_INDEX 383 2748#define I40E_GLV_MPRCH_MAX_INDEX 383
3978#define I40E_GLV_MPRCH_MPRCH_SHIFT 0 2749#define I40E_GLV_MPRCH_MPRCH_SHIFT 0
3979#define I40E_GLV_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLV_MPRCH_MPRCH_SHIFT) 2750#define I40E_GLV_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT)
3980#define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ 2751#define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3981#define I40E_GLV_MPRCL_MAX_INDEX 383 2752#define I40E_GLV_MPRCL_MAX_INDEX 383
3982#define I40E_GLV_MPRCL_MPRCL_SHIFT 0 2753#define I40E_GLV_MPRCL_MPRCL_SHIFT 0
3983#define I40E_GLV_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLV_MPRCL_MPRCL_SHIFT) 2754#define I40E_GLV_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT)
3984#define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ 2755#define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3985#define I40E_GLV_MPTCH_MAX_INDEX 383 2756#define I40E_GLV_MPTCH_MAX_INDEX 383
3986#define I40E_GLV_MPTCH_MPTCH_SHIFT 0 2757#define I40E_GLV_MPTCH_MPTCH_SHIFT 0
3987#define I40E_GLV_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLV_MPTCH_MPTCH_SHIFT) 2758#define I40E_GLV_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT)
3988#define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ 2759#define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3989#define I40E_GLV_MPTCL_MAX_INDEX 383 2760#define I40E_GLV_MPTCL_MAX_INDEX 383
3990#define I40E_GLV_MPTCL_MPTCL_SHIFT 0 2761#define I40E_GLV_MPTCL_MPTCL_SHIFT 0
3991#define I40E_GLV_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLV_MPTCL_MPTCL_SHIFT) 2762#define I40E_GLV_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT)
3992#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ 2763#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3993#define I40E_GLV_RDPC_MAX_INDEX 383 2764#define I40E_GLV_RDPC_MAX_INDEX 383
3994#define I40E_GLV_RDPC_RDPC_SHIFT 0 2765#define I40E_GLV_RDPC_RDPC_SHIFT 0
3995#define I40E_GLV_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLV_RDPC_RDPC_SHIFT) 2766#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT)
3996#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ 2767#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3997#define I40E_GLV_RUPP_MAX_INDEX 383 2768#define I40E_GLV_RUPP_MAX_INDEX 383
3998#define I40E_GLV_RUPP_RUPP_SHIFT 0 2769#define I40E_GLV_RUPP_RUPP_SHIFT 0
3999#define I40E_GLV_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLV_RUPP_RUPP_SHIFT) 2770#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT)
4000#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 8)) /* _i=0...383 */ 2771#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
4001#define I40E_GLV_TEPC_MAX_INDEX 383 2772#define I40E_GLV_TEPC_MAX_INDEX 383
4002#define I40E_GLV_TEPC_TEPC_SHIFT 0 2773#define I40E_GLV_TEPC_TEPC_SHIFT 0
4003#define I40E_GLV_TEPC_TEPC_MASK (0xFFFFFFFF << I40E_GLV_TEPC_TEPC_SHIFT) 2774#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT)
4004#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ 2775#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4005#define I40E_GLV_UPRCH_MAX_INDEX 383 2776#define I40E_GLV_UPRCH_MAX_INDEX 383
4006#define I40E_GLV_UPRCH_UPRCH_SHIFT 0 2777#define I40E_GLV_UPRCH_UPRCH_SHIFT 0
4007#define I40E_GLV_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLV_UPRCH_UPRCH_SHIFT) 2778#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT)
4008#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ 2779#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4009#define I40E_GLV_UPRCL_MAX_INDEX 383 2780#define I40E_GLV_UPRCL_MAX_INDEX 383
4010#define I40E_GLV_UPRCL_UPRCL_SHIFT 0 2781#define I40E_GLV_UPRCL_UPRCL_SHIFT 0
4011#define I40E_GLV_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLV_UPRCL_UPRCL_SHIFT) 2782#define I40E_GLV_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT)
4012#define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ 2783#define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4013#define I40E_GLV_UPTCH_MAX_INDEX 383 2784#define I40E_GLV_UPTCH_MAX_INDEX 383
4014#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0 2785#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0
4015#define I40E_GLV_UPTCH_GLVUPTCH_MASK (0xFFFF << I40E_GLV_UPTCH_GLVUPTCH_SHIFT) 2786#define I40E_GLV_UPTCH_GLVUPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT)
4016#define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ 2787#define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4017#define I40E_GLV_UPTCL_MAX_INDEX 383 2788#define I40E_GLV_UPTCL_MAX_INDEX 383
4018#define I40E_GLV_UPTCL_UPTCL_SHIFT 0 2789#define I40E_GLV_UPTCL_UPTCL_SHIFT 0
4019#define I40E_GLV_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLV_UPTCL_UPTCL_SHIFT) 2790#define I40E_GLV_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT)
4020#define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2791#define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4021#define I40E_GLVEBTC_RBCH_MAX_INDEX 7 2792#define I40E_GLVEBTC_RBCH_MAX_INDEX 7
4022#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0 2793#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0
4023#define I40E_GLVEBTC_RBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_RBCH_TCBCH_SHIFT) 2794#define I40E_GLVEBTC_RBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT)
4024#define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2795#define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4025#define I40E_GLVEBTC_RBCL_MAX_INDEX 7 2796#define I40E_GLVEBTC_RBCL_MAX_INDEX 7
4026#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0 2797#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0
4027#define I40E_GLVEBTC_RBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RBCL_TCBCL_SHIFT) 2798#define I40E_GLVEBTC_RBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT)
4028#define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2799#define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4029#define I40E_GLVEBTC_RPCH_MAX_INDEX 7 2800#define I40E_GLVEBTC_RPCH_MAX_INDEX 7
4030#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0 2801#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0
4031#define I40E_GLVEBTC_RPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_RPCH_TCPCH_SHIFT) 2802#define I40E_GLVEBTC_RPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT)
4032#define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2803#define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4033#define I40E_GLVEBTC_RPCL_MAX_INDEX 7 2804#define I40E_GLVEBTC_RPCL_MAX_INDEX 7
4034#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0 2805#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0
4035#define I40E_GLVEBTC_RPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RPCL_TCPCL_SHIFT) 2806#define I40E_GLVEBTC_RPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT)
4036#define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2807#define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4037#define I40E_GLVEBTC_TBCH_MAX_INDEX 7 2808#define I40E_GLVEBTC_TBCH_MAX_INDEX 7
4038#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0 2809#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0
4039#define I40E_GLVEBTC_TBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_TBCH_TCBCH_SHIFT) 2810#define I40E_GLVEBTC_TBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT)
4040#define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2811#define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4041#define I40E_GLVEBTC_TBCL_MAX_INDEX 7 2812#define I40E_GLVEBTC_TBCL_MAX_INDEX 7
4042#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0 2813#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0
4043#define I40E_GLVEBTC_TBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TBCL_TCBCL_SHIFT) 2814#define I40E_GLVEBTC_TBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT)
4044#define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2815#define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4045#define I40E_GLVEBTC_TPCH_MAX_INDEX 7 2816#define I40E_GLVEBTC_TPCH_MAX_INDEX 7
4046#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0 2817#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0
4047#define I40E_GLVEBTC_TPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_TPCH_TCPCH_SHIFT) 2818#define I40E_GLVEBTC_TPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT)
4048#define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2819#define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4049#define I40E_GLVEBTC_TPCL_MAX_INDEX 7 2820#define I40E_GLVEBTC_TPCL_MAX_INDEX 7
4050#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0 2821#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0
4051#define I40E_GLVEBTC_TPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TPCL_TCPCL_SHIFT) 2822#define I40E_GLVEBTC_TPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT)
4052#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ 2823#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4053#define I40E_GLVEBVL_BPCH_MAX_INDEX 127 2824#define I40E_GLVEBVL_BPCH_MAX_INDEX 127
4054#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0 2825#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0
4055#define I40E_GLVEBVL_BPCH_VLBPCH_MASK (0xFFFF << I40E_GLVEBVL_BPCH_VLBPCH_SHIFT) 2826#define I40E_GLVEBVL_BPCH_VLBPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT)
4056#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ 2827#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4057#define I40E_GLVEBVL_BPCL_MAX_INDEX 127 2828#define I40E_GLVEBVL_BPCL_MAX_INDEX 127
4058#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0 2829#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0
4059#define I40E_GLVEBVL_BPCL_VLBPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_BPCL_VLBPCL_SHIFT) 2830#define I40E_GLVEBVL_BPCL_VLBPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT)
4060#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ 2831#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4061#define I40E_GLVEBVL_GORCH_MAX_INDEX 127 2832#define I40E_GLVEBVL_GORCH_MAX_INDEX 127
4062#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0 2833#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0
4063#define I40E_GLVEBVL_GORCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GORCH_VLBCH_SHIFT) 2834#define I40E_GLVEBVL_GORCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT)
4064#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ 2835#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4065#define I40E_GLVEBVL_GORCL_MAX_INDEX 127 2836#define I40E_GLVEBVL_GORCL_MAX_INDEX 127
4066#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0 2837#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0
4067#define I40E_GLVEBVL_GORCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GORCL_VLBCL_SHIFT) 2838#define I40E_GLVEBVL_GORCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT)
4068#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ 2839#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4069#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127 2840#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127
4070#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0 2841#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0
4071#define I40E_GLVEBVL_GOTCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GOTCH_VLBCH_SHIFT) 2842#define I40E_GLVEBVL_GOTCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT)
4072#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ 2843#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4073#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127 2844#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127
4074#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0 2845#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0
4075#define I40E_GLVEBVL_GOTCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GOTCL_VLBCL_SHIFT) 2846#define I40E_GLVEBVL_GOTCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT)
4076#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ 2847#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4077#define I40E_GLVEBVL_MPCH_MAX_INDEX 127 2848#define I40E_GLVEBVL_MPCH_MAX_INDEX 127
4078#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0 2849#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0
4079#define I40E_GLVEBVL_MPCH_VLMPCH_MASK (0xFFFF << I40E_GLVEBVL_MPCH_VLMPCH_SHIFT) 2850#define I40E_GLVEBVL_MPCH_VLMPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT)
4080#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ 2851#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4081#define I40E_GLVEBVL_MPCL_MAX_INDEX 127 2852#define I40E_GLVEBVL_MPCL_MAX_INDEX 127
4082#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0 2853#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0
4083#define I40E_GLVEBVL_MPCL_VLMPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_MPCL_VLMPCL_SHIFT) 2854#define I40E_GLVEBVL_MPCL_VLMPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT)
4084#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ 2855#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4085#define I40E_GLVEBVL_UPCH_MAX_INDEX 127 2856#define I40E_GLVEBVL_UPCH_MAX_INDEX 127
4086#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0 2857#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0
4087#define I40E_GLVEBVL_UPCH_VLUPCH_MASK (0xFFFF << I40E_GLVEBVL_UPCH_VLUPCH_SHIFT) 2858#define I40E_GLVEBVL_UPCH_VLUPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT)
4088#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ 2859#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4089#define I40E_GLVEBVL_UPCL_MAX_INDEX 127 2860#define I40E_GLVEBVL_UPCL_MAX_INDEX 127
4090#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0 2861#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0
4091#define I40E_GLVEBVL_UPCL_VLUPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_UPCL_VLUPCL_SHIFT) 2862#define I40E_GLVEBVL_UPCL_VLUPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT)
4092#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C 2863#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C /* Reset: CORER */
4093#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0 2864#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0
4094#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK (0xFFFF << I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT) 2865#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT)
4095#define I40E_GL_MTG_FLU_MSK_L 0x00269F44 2866#define I40E_GL_SWR_DEF_ACT(_i) (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */
4096#define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT 0 2867#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 35
4097#define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_MASK (0xFFFFFFFF << I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT)
4098#define I40E_GL_SWR_DEF_ACT(_i) (0x0026CF00 + ((_i) * 4)) /* _i=0...25 */
4099#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 25
4100#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0 2868#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0
4101#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT) 2869#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT)
4102#define I40E_GL_SWR_DEF_ACT_EN 0x0026CF84 2870#define I40E_GL_SWR_DEF_ACT_EN(_i) (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
2871#define I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX 1
4103#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0 2872#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0
4104#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT) 2873#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT)
4105#define I40E_PRT_MSCCNT 0x00256BA0 2874#define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */
4106#define I40E_PRT_MSCCNT_CCOUNT_SHIFT 0
4107#define I40E_PRT_MSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_MSCCNT_CCOUNT_SHIFT)
4108#define I40E_PRT_SCSTS 0x00256C20
4109#define I40E_PRT_SCSTS_BSCA_SHIFT 0
4110#define I40E_PRT_SCSTS_BSCA_MASK (0x1 << I40E_PRT_SCSTS_BSCA_SHIFT)
4111#define I40E_PRT_SCSTS_BSCAP_SHIFT 1
4112#define I40E_PRT_SCSTS_BSCAP_MASK (0x1 << I40E_PRT_SCSTS_BSCAP_SHIFT)
4113#define I40E_PRT_SCSTS_MSCA_SHIFT 2
4114#define I40E_PRT_SCSTS_MSCA_MASK (0x1 << I40E_PRT_SCSTS_MSCA_SHIFT)
4115#define I40E_PRT_SCSTS_MSCAP_SHIFT 3
4116#define I40E_PRT_SCSTS_MSCAP_MASK (0x1 << I40E_PRT_SCSTS_MSCAP_SHIFT)
4117#define I40E_PRT_SWT_BSCCNT 0x00256C60
4118#define I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT 0
4119#define I40E_PRT_SWT_BSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT)
4120#define I40E_PRTTSYN_ADJ 0x001E4280
4121#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0 2875#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0
4122#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK (0x7FFFFFFF << I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT) 2876#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT)
4123#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31 2877#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31
4124#define I40E_PRTTSYN_ADJ_SIGN_MASK (0x1 << I40E_PRTTSYN_ADJ_SIGN_SHIFT) 2878#define I40E_PRTTSYN_ADJ_SIGN_MASK I40E_MASK(0x1, I40E_PRTTSYN_ADJ_SIGN_SHIFT)
4125#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ 2879#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4126#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1 2880#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1
4127#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0 2881#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0
4128#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 2882#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
4129#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1 2883#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1
4130#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK (0x3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 2884#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
4131#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3 2885#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3
4132#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT) 2886#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT)
4133#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8 2887#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8
4134#define I40E_PRTTSYN_AUX_0_PULSEW_MASK (0xF << I40E_PRTTSYN_AUX_0_PULSEW_SHIFT) 2888#define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
4135#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 2889#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
4136#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK (0x3 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT) 2890#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
4137#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ 2891#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4138#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1 2892#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1
4139#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 2893#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0
4140#define I40E_PRTTSYN_AUX_1_INSTNT_MASK (0x1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 2894#define I40E_PRTTSYN_AUX_1_INSTNT_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
4141#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1 2895#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1
4142#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK (0x1 << I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT) 2896#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT)
4143#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ 2897#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4144#define I40E_PRTTSYN_CLKO_MAX_INDEX 1 2898#define I40E_PRTTSYN_CLKO_MAX_INDEX 1
4145#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0 2899#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0
4146#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK (0xFFFFFFFF << I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT) 2900#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT)
4147#define I40E_PRTTSYN_CTL0 0x001E4200 2901#define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */
4148#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0 2902#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0
4149#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK (0x1 << I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT) 2903#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT)
4150#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 2904#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1
4151#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 2905#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)
4152#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2 2906#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2
4153#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT) 2907#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)
4154#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3 2908#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3
4155#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT) 2909#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT)
4156#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 2910#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8
4157#define I40E_PRTTSYN_CTL0_PF_ID_MASK (0xF << I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 2911#define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT)
4158#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12 2912#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12
4159#define I40E_PRTTSYN_CTL0_TSYNACT_MASK (0x3 << I40E_PRTTSYN_CTL0_TSYNACT_SHIFT) 2913#define I40E_PRTTSYN_CTL0_TSYNACT_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT)
4160#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 2914#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31
4161#define I40E_PRTTSYN_CTL0_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 2915#define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)
4162#define I40E_PRTTSYN_CTL1 0x00085020 2916#define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */
4163#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 2917#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0
4164#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 2918#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)
4165#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8 2919#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8
4166#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT) 2920#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT)
4167#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 2921#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16
4168#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 2922#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)
4169#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20 2923#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20
4170#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT) 2924#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT)
4171#define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 2925#define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24
4172#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK (0x3 << I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 2926#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
4173#define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 2927#define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26
4174#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK (0x3 << I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 2928#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
4175#define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 2929#define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31
4176#define I40E_PRTTSYN_CTL1_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 2930#define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
4177#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ 2931#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4178#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1 2932#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1
4179#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0 2933#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0
4180#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT) 2934#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT)
4181#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ 2935#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4182#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1 2936#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1
4183#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0 2937#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0
4184#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT) 2938#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT)
4185#define I40E_PRTTSYN_INC_H 0x001E4060 2939#define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */
4186#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0 2940#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0
4187#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK (0x3F << I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT) 2941#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT)
4188#define I40E_PRTTSYN_INC_L 0x001E4040 2942#define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */
4189#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0 2943#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0
4190#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT) 2944#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT)
4191#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ 2945#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
4192#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3 2946#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3
4193#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0 2947#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0
4194#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT) 2948#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT)
4195#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ 2949#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
4196#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3 2950#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3
4197#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0 2951#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0
4198#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT) 2952#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT)
4199#define I40E_PRTTSYN_STAT_0 0x001E4220 2953#define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */
4200#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0 2954#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0
4201#define I40E_PRTTSYN_STAT_0_EVENT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT0_SHIFT) 2955#define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)
4202#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1 2956#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1
4203#define I40E_PRTTSYN_STAT_0_EVENT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT1_SHIFT) 2957#define I40E_PRTTSYN_STAT_0_EVENT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT1_SHIFT)
4204#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2 2958#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2
4205#define I40E_PRTTSYN_STAT_0_TGT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT0_SHIFT) 2959#define I40E_PRTTSYN_STAT_0_TGT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT0_SHIFT)
4206#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3 2960#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3
4207#define I40E_PRTTSYN_STAT_0_TGT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT1_SHIFT) 2961#define I40E_PRTTSYN_STAT_0_TGT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT1_SHIFT)
4208#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 2962#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4
4209#define I40E_PRTTSYN_STAT_0_TXTIME_MASK (0x1 << I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 2963#define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)
4210#define I40E_PRTTSYN_STAT_1 0x00085140 2964#define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */
4211#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0 2965#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0
4212#define I40E_PRTTSYN_STAT_1_RXT0_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT0_SHIFT) 2966#define I40E_PRTTSYN_STAT_1_RXT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT0_SHIFT)
4213#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1 2967#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1
4214#define I40E_PRTTSYN_STAT_1_RXT1_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT1_SHIFT) 2968#define I40E_PRTTSYN_STAT_1_RXT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT1_SHIFT)
4215#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2 2969#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2
4216#define I40E_PRTTSYN_STAT_1_RXT2_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT2_SHIFT) 2970#define I40E_PRTTSYN_STAT_1_RXT2_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT2_SHIFT)
4217#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3 2971#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3
4218#define I40E_PRTTSYN_STAT_1_RXT3_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT3_SHIFT) 2972#define I40E_PRTTSYN_STAT_1_RXT3_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT3_SHIFT)
4219#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ 2973#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4220#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1 2974#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1
4221#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0 2975#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0
4222#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT) 2976#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT)
4223#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ 2977#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4224#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1 2978#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1
4225#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0 2979#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0
4226#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT) 2980#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT)
4227#define I40E_PRTTSYN_TIME_H 0x001E4120 2981#define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */
4228#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0 2982#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0
4229#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT) 2983#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT)
4230#define I40E_PRTTSYN_TIME_L 0x001E4100 2984#define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */
4231#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0 2985#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0
4232#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT) 2986#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT)
4233#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 2987#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */
4234#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0 2988#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0
4235#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT) 2989#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT)
4236#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 2990#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */
4237#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 2991#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0
4238#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) 2992#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
4239#define I40E_GLSCD_QUANTA 0x000B2080 2993#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */
4240#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0 2994#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0
4241#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK (0x7 << I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT) 2995#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7, I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)
4242#define I40E_GL_MDET_RX 0x0012A510 2996#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */
4243#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 2997#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
4244#define I40E_GL_MDET_RX_FUNCTION_MASK (0xFF << I40E_GL_MDET_RX_FUNCTION_SHIFT) 2998#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
4245#define I40E_GL_MDET_RX_EVENT_SHIFT 8 2999#define I40E_GL_MDET_RX_EVENT_SHIFT 8
4246#define I40E_GL_MDET_RX_EVENT_MASK (0x1FF << I40E_GL_MDET_RX_EVENT_SHIFT) 3000#define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT)
4247#define I40E_GL_MDET_RX_QUEUE_SHIFT 17 3001#define I40E_GL_MDET_RX_QUEUE_SHIFT 17
4248#define I40E_GL_MDET_RX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_RX_QUEUE_SHIFT) 3002#define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT)
4249#define I40E_GL_MDET_RX_VALID_SHIFT 31 3003#define I40E_GL_MDET_RX_VALID_SHIFT 31
4250#define I40E_GL_MDET_RX_VALID_MASK (0x1 << I40E_GL_MDET_RX_VALID_SHIFT) 3004#define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT)
4251#define I40E_GL_MDET_TX 0x000E6480 3005#define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */
4252#define I40E_GL_MDET_TX_FUNCTION_SHIFT 0 3006#define I40E_GL_MDET_TX_QUEUE_SHIFT 0
4253#define I40E_GL_MDET_TX_FUNCTION_MASK (0xFF << I40E_GL_MDET_TX_FUNCTION_SHIFT) 3007#define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT)
4254#define I40E_GL_MDET_TX_EVENT_SHIFT 8 3008#define I40E_GL_MDET_TX_VF_NUM_SHIFT 12
4255#define I40E_GL_MDET_TX_EVENT_MASK (0x1FF << I40E_GL_MDET_TX_EVENT_SHIFT) 3009#define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT)
4256#define I40E_GL_MDET_TX_QUEUE_SHIFT 17 3010#define I40E_GL_MDET_TX_PF_NUM_SHIFT 21
4257#define I40E_GL_MDET_TX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_TX_QUEUE_SHIFT) 3011#define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT)
3012#define I40E_GL_MDET_TX_EVENT_SHIFT 25
3013#define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT)
4258#define I40E_GL_MDET_TX_VALID_SHIFT 31 3014#define I40E_GL_MDET_TX_VALID_SHIFT 31
4259#define I40E_GL_MDET_TX_VALID_MASK (0x1 << I40E_GL_MDET_TX_VALID_SHIFT) 3015#define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT)
4260#define I40E_PF_MDET_RX 0x0012A400 3016#define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */
4261#define I40E_PF_MDET_RX_VALID_SHIFT 0 3017#define I40E_PF_MDET_RX_VALID_SHIFT 0
4262#define I40E_PF_MDET_RX_VALID_MASK (0x1 << I40E_PF_MDET_RX_VALID_SHIFT) 3018#define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT)
4263#define I40E_PF_MDET_TX 0x000E6400 3019#define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */
4264#define I40E_PF_MDET_TX_VALID_SHIFT 0 3020#define I40E_PF_MDET_TX_VALID_SHIFT 0
4265#define I40E_PF_MDET_TX_VALID_MASK (0x1 << I40E_PF_MDET_TX_VALID_SHIFT) 3021#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT)
4266#define I40E_PF_VT_PFALLOC 0x001C0500 3022#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */
4267#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 3023#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0
4268#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 3024#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)
4269#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 3025#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
4270#define I40E_PF_VT_PFALLOC_LASTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 3026#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
4271#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 3027#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
4272#define I40E_PF_VT_PFALLOC_VALID_MASK (0x1 << I40E_PF_VT_PFALLOC_VALID_SHIFT) 3028#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)
4273#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ 3029#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
4274#define I40E_VP_MDET_RX_MAX_INDEX 127 3030#define I40E_VP_MDET_RX_MAX_INDEX 127
4275#define I40E_VP_MDET_RX_VALID_SHIFT 0 3031#define I40E_VP_MDET_RX_VALID_SHIFT 0
4276#define I40E_VP_MDET_RX_VALID_MASK (0x1 << I40E_VP_MDET_RX_VALID_SHIFT) 3032#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)
4277#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ 3033#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
4278#define I40E_VP_MDET_TX_MAX_INDEX 127 3034#define I40E_VP_MDET_TX_MAX_INDEX 127
4279#define I40E_VP_MDET_TX_VALID_SHIFT 0 3035#define I40E_VP_MDET_TX_VALID_SHIFT 0
4280#define I40E_VP_MDET_TX_VALID_MASK (0x1 << I40E_VP_MDET_TX_VALID_SHIFT) 3036#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)
4281#define I40E_GLPM_WUMC 0x0006C800 3037#define I40E_GLPM_WUMC 0x0006C800 /* Reset: POR */
4282#define I40E_GLPM_WUMC_NOTCO_SHIFT 0 3038#define I40E_GLPM_WUMC_NOTCO_SHIFT 0
4283#define I40E_GLPM_WUMC_NOTCO_MASK (0x1 << I40E_GLPM_WUMC_NOTCO_SHIFT) 3039#define I40E_GLPM_WUMC_NOTCO_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_NOTCO_SHIFT)
4284#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1 3040#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1
4285#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK (0x1 << I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT) 3041#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT)
4286#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2 3042#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2
4287#define I40E_GLPM_WUMC_ROL_MODE_MASK (0x1 << I40E_GLPM_WUMC_ROL_MODE_SHIFT) 3043#define I40E_GLPM_WUMC_ROL_MODE_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_ROL_MODE_SHIFT)
4288#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3 3044#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3
4289#define I40E_GLPM_WUMC_RESERVED_4_MASK (0x1FFF << I40E_GLPM_WUMC_RESERVED_4_SHIFT) 3045#define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)
4290#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16 3046#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16
4291#define I40E_GLPM_WUMC_MNG_WU_PF_MASK (0xFFFF << I40E_GLPM_WUMC_MNG_WU_PF_SHIFT) 3047#define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
4292#define I40E_PFPM_APM 0x000B8080 3048#define I40E_PFPM_APM 0x000B8080 /* Reset: POR */
4293#define I40E_PFPM_APM_APME_SHIFT 0 3049#define I40E_PFPM_APM_APME_SHIFT 0
4294#define I40E_PFPM_APM_APME_MASK (0x1 << I40E_PFPM_APM_APME_SHIFT) 3050#define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT)
4295#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ 3051#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */
4296#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7 3052#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7
4297#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0 3053#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0
4298#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK (0xFF << I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT) 3054#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
4299#define I40E_PFPM_WUC 0x0006B200 3055#define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */
4300#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5 3056#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5
4301#define I40E_PFPM_WUC_EN_APM_D0_MASK (0x1 << I40E_PFPM_WUC_EN_APM_D0_SHIFT) 3057#define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT)
4302#define I40E_PFPM_WUFC 0x0006B400 3058#define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */
4303#define I40E_PFPM_WUFC_LNKC_SHIFT 0 3059#define I40E_PFPM_WUFC_LNKC_SHIFT 0
4304#define I40E_PFPM_WUFC_LNKC_MASK (0x1 << I40E_PFPM_WUFC_LNKC_SHIFT) 3060#define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT)
4305#define I40E_PFPM_WUFC_MAG_SHIFT 1 3061#define I40E_PFPM_WUFC_MAG_SHIFT 1
4306#define I40E_PFPM_WUFC_MAG_MASK (0x1 << I40E_PFPM_WUFC_MAG_SHIFT) 3062#define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT)
4307#define I40E_PFPM_WUFC_MNG_SHIFT 3 3063#define I40E_PFPM_WUFC_MNG_SHIFT 3
4308#define I40E_PFPM_WUFC_MNG_MASK (0x1 << I40E_PFPM_WUFC_MNG_SHIFT) 3064#define I40E_PFPM_WUFC_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MNG_SHIFT)
4309#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4 3065#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4
4310#define I40E_PFPM_WUFC_FLX0_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX0_ACT_SHIFT) 3066#define I40E_PFPM_WUFC_FLX0_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_ACT_SHIFT)
4311#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5 3067#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5
4312#define I40E_PFPM_WUFC_FLX1_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX1_ACT_SHIFT) 3068#define I40E_PFPM_WUFC_FLX1_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_ACT_SHIFT)
4313#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6 3069#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6
4314#define I40E_PFPM_WUFC_FLX2_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX2_ACT_SHIFT) 3070#define I40E_PFPM_WUFC_FLX2_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_ACT_SHIFT)
4315#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7 3071#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7
4316#define I40E_PFPM_WUFC_FLX3_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX3_ACT_SHIFT) 3072#define I40E_PFPM_WUFC_FLX3_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_ACT_SHIFT)
4317#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8 3073#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8
4318#define I40E_PFPM_WUFC_FLX4_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX4_ACT_SHIFT) 3074#define I40E_PFPM_WUFC_FLX4_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_ACT_SHIFT)
4319#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9 3075#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9
4320#define I40E_PFPM_WUFC_FLX5_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX5_ACT_SHIFT) 3076#define I40E_PFPM_WUFC_FLX5_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_ACT_SHIFT)
4321#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10 3077#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10
4322#define I40E_PFPM_WUFC_FLX6_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX6_ACT_SHIFT) 3078#define I40E_PFPM_WUFC_FLX6_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_ACT_SHIFT)
4323#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11 3079#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11
4324#define I40E_PFPM_WUFC_FLX7_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX7_ACT_SHIFT) 3080#define I40E_PFPM_WUFC_FLX7_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_ACT_SHIFT)
4325#define I40E_PFPM_WUFC_FLX0_SHIFT 16 3081#define I40E_PFPM_WUFC_FLX0_SHIFT 16
4326#define I40E_PFPM_WUFC_FLX0_MASK (0x1 << I40E_PFPM_WUFC_FLX0_SHIFT) 3082#define I40E_PFPM_WUFC_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_SHIFT)
4327#define I40E_PFPM_WUFC_FLX1_SHIFT 17 3083#define I40E_PFPM_WUFC_FLX1_SHIFT 17
4328#define I40E_PFPM_WUFC_FLX1_MASK (0x1 << I40E_PFPM_WUFC_FLX1_SHIFT) 3084#define I40E_PFPM_WUFC_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_SHIFT)
4329#define I40E_PFPM_WUFC_FLX2_SHIFT 18 3085#define I40E_PFPM_WUFC_FLX2_SHIFT 18
4330#define I40E_PFPM_WUFC_FLX2_MASK (0x1 << I40E_PFPM_WUFC_FLX2_SHIFT) 3086#define I40E_PFPM_WUFC_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_SHIFT)
4331#define I40E_PFPM_WUFC_FLX3_SHIFT 19 3087#define I40E_PFPM_WUFC_FLX3_SHIFT 19
4332#define I40E_PFPM_WUFC_FLX3_MASK (0x1 << I40E_PFPM_WUFC_FLX3_SHIFT) 3088#define I40E_PFPM_WUFC_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_SHIFT)
4333#define I40E_PFPM_WUFC_FLX4_SHIFT 20 3089#define I40E_PFPM_WUFC_FLX4_SHIFT 20
4334#define I40E_PFPM_WUFC_FLX4_MASK (0x1 << I40E_PFPM_WUFC_FLX4_SHIFT) 3090#define I40E_PFPM_WUFC_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_SHIFT)
4335#define I40E_PFPM_WUFC_FLX5_SHIFT 21 3091#define I40E_PFPM_WUFC_FLX5_SHIFT 21
4336#define I40E_PFPM_WUFC_FLX5_MASK (0x1 << I40E_PFPM_WUFC_FLX5_SHIFT) 3092#define I40E_PFPM_WUFC_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_SHIFT)
4337#define I40E_PFPM_WUFC_FLX6_SHIFT 22 3093#define I40E_PFPM_WUFC_FLX6_SHIFT 22
4338#define I40E_PFPM_WUFC_FLX6_MASK (0x1 << I40E_PFPM_WUFC_FLX6_SHIFT) 3094#define I40E_PFPM_WUFC_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_SHIFT)
4339#define I40E_PFPM_WUFC_FLX7_SHIFT 23 3095#define I40E_PFPM_WUFC_FLX7_SHIFT 23
4340#define I40E_PFPM_WUFC_FLX7_MASK (0x1 << I40E_PFPM_WUFC_FLX7_SHIFT) 3096#define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT)
4341#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31 3097#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31
4342#define I40E_PFPM_WUFC_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUFC_FW_RST_WK_SHIFT) 3098#define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT)
4343#define I40E_PFPM_WUS 0x0006B600 3099#define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */
4344#define I40E_PFPM_WUS_LNKC_SHIFT 0 3100#define I40E_PFPM_WUS_LNKC_SHIFT 0
4345#define I40E_PFPM_WUS_LNKC_MASK (0x1 << I40E_PFPM_WUS_LNKC_SHIFT) 3101#define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT)
4346#define I40E_PFPM_WUS_MAG_SHIFT 1 3102#define I40E_PFPM_WUS_MAG_SHIFT 1
4347#define I40E_PFPM_WUS_MAG_MASK (0x1 << I40E_PFPM_WUS_MAG_SHIFT) 3103#define I40E_PFPM_WUS_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MAG_SHIFT)
4348#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2 3104#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2
4349#define I40E_PFPM_WUS_PME_STATUS_MASK (0x1 << I40E_PFPM_WUS_PME_STATUS_SHIFT) 3105#define I40E_PFPM_WUS_PME_STATUS_MASK I40E_MASK(0x1, I40E_PFPM_WUS_PME_STATUS_SHIFT)
4350#define I40E_PFPM_WUS_MNG_SHIFT 3 3106#define I40E_PFPM_WUS_MNG_SHIFT 3
4351#define I40E_PFPM_WUS_MNG_MASK (0x1 << I40E_PFPM_WUS_MNG_SHIFT) 3107#define I40E_PFPM_WUS_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MNG_SHIFT)
4352#define I40E_PFPM_WUS_FLX0_SHIFT 16 3108#define I40E_PFPM_WUS_FLX0_SHIFT 16
4353#define I40E_PFPM_WUS_FLX0_MASK (0x1 << I40E_PFPM_WUS_FLX0_SHIFT) 3109#define I40E_PFPM_WUS_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX0_SHIFT)
4354#define I40E_PFPM_WUS_FLX1_SHIFT 17 3110#define I40E_PFPM_WUS_FLX1_SHIFT 17
4355#define I40E_PFPM_WUS_FLX1_MASK (0x1 << I40E_PFPM_WUS_FLX1_SHIFT) 3111#define I40E_PFPM_WUS_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX1_SHIFT)
4356#define I40E_PFPM_WUS_FLX2_SHIFT 18 3112#define I40E_PFPM_WUS_FLX2_SHIFT 18
4357#define I40E_PFPM_WUS_FLX2_MASK (0x1 << I40E_PFPM_WUS_FLX2_SHIFT) 3113#define I40E_PFPM_WUS_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX2_SHIFT)
4358#define I40E_PFPM_WUS_FLX3_SHIFT 19 3114#define I40E_PFPM_WUS_FLX3_SHIFT 19
4359#define I40E_PFPM_WUS_FLX3_MASK (0x1 << I40E_PFPM_WUS_FLX3_SHIFT) 3115#define I40E_PFPM_WUS_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX3_SHIFT)
4360#define I40E_PFPM_WUS_FLX4_SHIFT 20 3116#define I40E_PFPM_WUS_FLX4_SHIFT 20
4361#define I40E_PFPM_WUS_FLX4_MASK (0x1 << I40E_PFPM_WUS_FLX4_SHIFT) 3117#define I40E_PFPM_WUS_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX4_SHIFT)
4362#define I40E_PFPM_WUS_FLX5_SHIFT 21 3118#define I40E_PFPM_WUS_FLX5_SHIFT 21
4363#define I40E_PFPM_WUS_FLX5_MASK (0x1 << I40E_PFPM_WUS_FLX5_SHIFT) 3119#define I40E_PFPM_WUS_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX5_SHIFT)
4364#define I40E_PFPM_WUS_FLX6_SHIFT 22 3120#define I40E_PFPM_WUS_FLX6_SHIFT 22
4365#define I40E_PFPM_WUS_FLX6_MASK (0x1 << I40E_PFPM_WUS_FLX6_SHIFT) 3121#define I40E_PFPM_WUS_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX6_SHIFT)
4366#define I40E_PFPM_WUS_FLX7_SHIFT 23 3122#define I40E_PFPM_WUS_FLX7_SHIFT 23
4367#define I40E_PFPM_WUS_FLX7_MASK (0x1 << I40E_PFPM_WUS_FLX7_SHIFT) 3123#define I40E_PFPM_WUS_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX7_SHIFT)
4368#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31 3124#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31
4369#define I40E_PFPM_WUS_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUS_FW_RST_WK_SHIFT) 3125#define I40E_PFPM_WUS_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FW_RST_WK_SHIFT)
4370#define I40E_PRTPM_FHFHR 0x0006C000 3126#define I40E_PRTPM_FHFHR 0x0006C000 /* Reset: POR */
4371#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0 3127#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0
4372#define I40E_PRTPM_FHFHR_UNICAST_MASK (0x1 << I40E_PRTPM_FHFHR_UNICAST_SHIFT) 3128#define I40E_PRTPM_FHFHR_UNICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_UNICAST_SHIFT)
4373#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1 3129#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1
4374#define I40E_PRTPM_FHFHR_MULTICAST_MASK (0x1 << I40E_PRTPM_FHFHR_MULTICAST_SHIFT) 3130#define I40E_PRTPM_FHFHR_MULTICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_MULTICAST_SHIFT)
4375#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ 3131#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
4376#define I40E_PRTPM_SAH_MAX_INDEX 3 3132#define I40E_PRTPM_SAH_MAX_INDEX 3
4377#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0 3133#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0
4378#define I40E_PRTPM_SAH_PFPM_SAH_MASK (0xFFFF << I40E_PRTPM_SAH_PFPM_SAH_SHIFT) 3134#define I40E_PRTPM_SAH_PFPM_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT)
4379#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26 3135#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26
4380#define I40E_PRTPM_SAH_PF_NUM_MASK (0xF << I40E_PRTPM_SAH_PF_NUM_SHIFT) 3136#define I40E_PRTPM_SAH_PF_NUM_MASK I40E_MASK(0xF, I40E_PRTPM_SAH_PF_NUM_SHIFT)
4381#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30 3137#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30
4382#define I40E_PRTPM_SAH_MC_MAG_EN_MASK (0x1 << I40E_PRTPM_SAH_MC_MAG_EN_SHIFT) 3138#define I40E_PRTPM_SAH_MC_MAG_EN_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT)
4383#define I40E_PRTPM_SAH_AV_SHIFT 31 3139#define I40E_PRTPM_SAH_AV_SHIFT 31
4384#define I40E_PRTPM_SAH_AV_MASK (0x1 << I40E_PRTPM_SAH_AV_SHIFT) 3140#define I40E_PRTPM_SAH_AV_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_AV_SHIFT)
4385#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ 3141#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
4386#define I40E_PRTPM_SAL_MAX_INDEX 3 3142#define I40E_PRTPM_SAL_MAX_INDEX 3
4387#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0 3143#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0
4388#define I40E_PRTPM_SAL_PFPM_SAL_MASK (0xFFFFFFFF << I40E_PRTPM_SAL_PFPM_SAL_SHIFT) 3144#define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT)
4389#define I40E_VF_ARQBAH1 0x00006000 3145#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
4390#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 3146#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
4391#define I40E_VF_ARQBAH1_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH1_ARQBAH_SHIFT) 3147#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
4392#define I40E_VF_ARQBAL1 0x00006C00 3148#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
4393#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 3149#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0
4394#define I40E_VF_ARQBAL1_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL1_ARQBAL_SHIFT) 3150#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)
4395#define I40E_VF_ARQH1 0x00007400 3151#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */
4396#define I40E_VF_ARQH1_ARQH_SHIFT 0 3152#define I40E_VF_ARQH1_ARQH_SHIFT 0
4397#define I40E_VF_ARQH1_ARQH_MASK (0x3FF << I40E_VF_ARQH1_ARQH_SHIFT) 3153#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)
4398#define I40E_VF_ARQLEN1 0x00008000 3154#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
4399#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 3155#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0
4400#define I40E_VF_ARQLEN1_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN1_ARQLEN_SHIFT) 3156#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
4401#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 3157#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28
4402#define I40E_VF_ARQLEN1_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN1_ARQVFE_SHIFT) 3158#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)
4403#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 3159#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29
4404#define I40E_VF_ARQLEN1_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 3160#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)
4405#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 3161#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
4406#define I40E_VF_ARQLEN1_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 3162#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
4407#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 3163#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
4408#define I40E_VF_ARQLEN1_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN1_ARQENABLE_SHIFT) 3164#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
4409#define I40E_VF_ARQT1 0x00007000 3165#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
4410#define I40E_VF_ARQT1_ARQT_SHIFT 0 3166#define I40E_VF_ARQT1_ARQT_SHIFT 0
4411#define I40E_VF_ARQT1_ARQT_MASK (0x3FF << I40E_VF_ARQT1_ARQT_SHIFT) 3167#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
4412#define I40E_VF_ATQBAH1 0x00007800 3168#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
4413#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 3169#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
4414#define I40E_VF_ATQBAH1_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH1_ATQBAH_SHIFT) 3170#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
4415#define I40E_VF_ATQBAL1 0x00007C00 3171#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
4416#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 3172#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
4417#define I40E_VF_ATQBAL1_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL1_ATQBAL_SHIFT) 3173#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
4418#define I40E_VF_ATQH1 0x00006400 3174#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
4419#define I40E_VF_ATQH1_ATQH_SHIFT 0 3175#define I40E_VF_ATQH1_ATQH_SHIFT 0
4420#define I40E_VF_ATQH1_ATQH_MASK (0x3FF << I40E_VF_ATQH1_ATQH_SHIFT) 3176#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
4421#define I40E_VF_ATQLEN1 0x00006800 3177#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
4422#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 3178#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0
4423#define I40E_VF_ATQLEN1_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN1_ATQLEN_SHIFT) 3179#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
4424#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 3180#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28
4425#define I40E_VF_ATQLEN1_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN1_ATQVFE_SHIFT) 3181#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)
4426#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 3182#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29
4427#define I40E_VF_ATQLEN1_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 3183#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)
4428#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 3184#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
4429#define I40E_VF_ATQLEN1_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 3185#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
4430#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 3186#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
4431#define I40E_VF_ATQLEN1_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN1_ATQENABLE_SHIFT) 3187#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
4432#define I40E_VF_ATQT1 0x00008400 3188#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
4433#define I40E_VF_ATQT1_ATQT_SHIFT 0 3189#define I40E_VF_ATQT1_ATQT_SHIFT 0
4434#define I40E_VF_ATQT1_ATQT_MASK (0x3FF << I40E_VF_ATQT1_ATQT_SHIFT) 3190#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
4435#define I40E_VFGEN_RSTAT 0x00008800 3191#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
4436#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 3192#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
4437#define I40E_VFGEN_RSTAT_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 3193#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
4438#define I40E_VFINT_DYN_CTL01 0x00005C00 3194#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
4439#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 3195#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0
4440#define I40E_VFINT_DYN_CTL01_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_SHIFT) 3196#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
4441#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 3197#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1
4442#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) 3198#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
4443#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 3199#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
4444#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) 3200#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
4445#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 3201#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
4446#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) 3202#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
4447#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 3203#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5
4448#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) 3204#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)
4449#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 3205#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
4450#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) 3206#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
4451#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 3207#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
4452#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) 3208#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
4453#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 3209#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31
4454#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) 3210#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
4455#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) 3211#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
4456#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 3212#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15
4457#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 3213#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0
4458#define I40E_VFINT_DYN_CTLN1_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) 3214#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
4459#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 3215#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
4460#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) 3216#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
4461#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 3217#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
4462#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) 3218#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
4463#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 3219#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
4464#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) 3220#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
4465#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 3221#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
4466#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) 3222#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
4467#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 3223#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
4468#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) 3224#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
4469#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 3225#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
4470#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) 3226#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
4471#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 3227#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31
4472#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) 3228#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
4473#define I40E_VFINT_ICR0_ENA1 0x00005000 3229#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
4474#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 3230#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
4475#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) 3231#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
4476#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 3232#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
4477#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) 3233#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
4478#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 3234#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31
4479#define I40E_VFINT_ICR0_ENA1_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) 3235#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
4480#define I40E_VFINT_ICR01 0x00004800 3236#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */
4481#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 3237#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0
4482#define I40E_VFINT_ICR01_INTEVENT_MASK (0x1 << I40E_VFINT_ICR01_INTEVENT_SHIFT) 3238#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)
4483#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 3239#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1
4484#define I40E_VFINT_ICR01_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_0_SHIFT) 3240#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT)
4485#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 3241#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2
4486#define I40E_VFINT_ICR01_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_1_SHIFT) 3242#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT)
4487#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 3243#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3
4488#define I40E_VFINT_ICR01_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_2_SHIFT) 3244#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT)
4489#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 3245#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4
4490#define I40E_VFINT_ICR01_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_3_SHIFT) 3246#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT)
4491#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 3247#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
4492#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) 3248#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
4493#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 3249#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30
4494#define I40E_VFINT_ICR01_ADMINQ_MASK (0x1 << I40E_VFINT_ICR01_ADMINQ_SHIFT) 3250#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)
4495#define I40E_VFINT_ICR01_SWINT_SHIFT 31 3251#define I40E_VFINT_ICR01_SWINT_SHIFT 31
4496#define I40E_VFINT_ICR01_SWINT_MASK (0x1 << I40E_VFINT_ICR01_SWINT_SHIFT) 3252#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)
4497#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ 3253#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
4498#define I40E_VFINT_ITR01_MAX_INDEX 2 3254#define I40E_VFINT_ITR01_MAX_INDEX 2
4499#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 3255#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0
4500#define I40E_VFINT_ITR01_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR01_INTERVAL_SHIFT) 3256#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)
4501#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) 3257#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
4502#define I40E_VFINT_ITRN1_MAX_INDEX 2 3258#define I40E_VFINT_ITRN1_MAX_INDEX 2
4503#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 3259#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
4504#define I40E_VFINT_ITRN1_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN1_INTERVAL_SHIFT) 3260#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
4505#define I40E_VFINT_STAT_CTL01 0x00005400 3261#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: VFR */
4506#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 3262#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
4507#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) 3263#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
4508#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ 3264#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
4509#define I40E_QRX_TAIL1_MAX_INDEX 15 3265#define I40E_QRX_TAIL1_MAX_INDEX 15
4510#define I40E_QRX_TAIL1_TAIL_SHIFT 0 3266#define I40E_QRX_TAIL1_TAIL_SHIFT 0
4511#define I40E_QRX_TAIL1_TAIL_MASK (0x1FFF << I40E_QRX_TAIL1_TAIL_SHIFT) 3267#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)
4512#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ 3268#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
4513#define I40E_QTX_TAIL1_MAX_INDEX 15 3269#define I40E_QTX_TAIL1_MAX_INDEX 15
4514#define I40E_QTX_TAIL1_TAIL_SHIFT 0 3270#define I40E_QTX_TAIL1_TAIL_SHIFT 0
4515#define I40E_QTX_TAIL1_TAIL_MASK (0x1FFF << I40E_QTX_TAIL1_TAIL_SHIFT) 3271#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)
4516#define I40E_VFMSIX_PBA 0x00002000 3272#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */
4517#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 3273#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
4518#define I40E_VFMSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA_PENBIT_SHIFT) 3274#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)
4519#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ 3275#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4520#define I40E_VFMSIX_TADD_MAX_INDEX 16 3276#define I40E_VFMSIX_TADD_MAX_INDEX 16
4521#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 3277#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
4522#define I40E_VFMSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) 3278#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
4523#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 3279#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2
4524#define I40E_VFMSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD_MSIXTADD_SHIFT) 3280#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
4525#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ 3281#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4526#define I40E_VFMSIX_TMSG_MAX_INDEX 16 3282#define I40E_VFMSIX_TMSG_MAX_INDEX 16
4527#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 3283#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
4528#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) 3284#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
4529#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ 3285#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4530#define I40E_VFMSIX_TUADD_MAX_INDEX 16 3286#define I40E_VFMSIX_TUADD_MAX_INDEX 16
4531#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 3287#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
4532#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) 3288#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
4533#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ 3289#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4534#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 3290#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16
4535#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 3291#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
4536#define I40E_VFMSIX_TVCTRL_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL_MASK_SHIFT) 3292#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)
4537#define I40E_VFCM_PE_ERRDATA 0x0000DC00 3293#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */
4538#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 3294#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
4539#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) 3295#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
4540#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 3296#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
4541#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) 3297#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
4542#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 3298#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8
4543#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) 3299#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
4544#define I40E_VFCM_PE_ERRINFO 0x0000D800 3300#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */
4545#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 3301#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
4546#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) 3302#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
4547#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 3303#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
4548#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) 3304#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)
4549#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 3305#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
4550#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) 3306#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
4551#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 3307#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
4552#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) 3308#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
4553#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 3309#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
4554#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) 3310#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
4555#define I40E_VFPE_AEQALLOC1 0x0000A400 3311#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
4556#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
4557#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
4558#define I40E_VFPE_CCQPHIGH1 0x00009800
4559#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
4560#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
4561#define I40E_VFPE_CCQPLOW1 0x0000AC00
4562#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
4563#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
4564#define I40E_VFPE_CCQPSTATUS1 0x0000B800
4565#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
4566#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
4567#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
4568#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
4569#define I40E_VFPE_CQACK1 0x0000B000
4570#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
4571#define I40E_VFPE_CQACK1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK1_PECQID_SHIFT)
4572#define I40E_VFPE_CQARM1 0x0000B400
4573#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
4574#define I40E_VFPE_CQARM1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM1_PECQID_SHIFT)
4575#define I40E_VFPE_CQPDB1 0x0000BC00
4576#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
4577#define I40E_VFPE_CQPDB1_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
4578#define I40E_VFPE_CQPERRCODES1 0x00009C00
4579#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
4580#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
4581#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
4582#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
4583#define I40E_VFPE_CQPTAIL1 0x0000A000
4584#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
4585#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
4586#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
4587#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
4588#define I40E_VFPE_IPCONFIG01 0x00008C00
4589#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
4590#define I40E_VFPE_IPCONFIG01_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
4591#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
4592#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
4593#define I40E_VFPE_MRTEIDXMASK1 0x00009000
4594#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
4595#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
4596#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400
4597#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
4598#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
4599#define I40E_VFPE_TCPNOWTIMER1 0x0000A800
4600#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
4601#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
4602#define I40E_VFPE_WQEALLOC1 0x0000C000
4603#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
4604#define I40E_VFPE_WQEALLOC1_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
4605#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
4606#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
4607#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */
4608#define I40E_VFQF_HENA_MAX_INDEX 1 3312#define I40E_VFQF_HENA_MAX_INDEX 1
4609#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 3313#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0
4610#define I40E_VFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA_PTYPE_ENA_SHIFT) 3314#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
4611#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ 3315#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
4612#define I40E_VFQF_HKEY_MAX_INDEX 12 3316#define I40E_VFQF_HKEY_MAX_INDEX 12
4613#define I40E_VFQF_HKEY_KEY_0_SHIFT 0 3317#define I40E_VFQF_HKEY_KEY_0_SHIFT 0
4614#define I40E_VFQF_HKEY_KEY_0_MASK (0xFF << I40E_VFQF_HKEY_KEY_0_SHIFT) 3318#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)
4615#define I40E_VFQF_HKEY_KEY_1_SHIFT 8 3319#define I40E_VFQF_HKEY_KEY_1_SHIFT 8
4616#define I40E_VFQF_HKEY_KEY_1_MASK (0xFF << I40E_VFQF_HKEY_KEY_1_SHIFT) 3320#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)
4617#define I40E_VFQF_HKEY_KEY_2_SHIFT 16 3321#define I40E_VFQF_HKEY_KEY_2_SHIFT 16
4618#define I40E_VFQF_HKEY_KEY_2_MASK (0xFF << I40E_VFQF_HKEY_KEY_2_SHIFT) 3322#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)
4619#define I40E_VFQF_HKEY_KEY_3_SHIFT 24 3323#define I40E_VFQF_HKEY_KEY_3_SHIFT 24
4620#define I40E_VFQF_HKEY_KEY_3_MASK (0xFF << I40E_VFQF_HKEY_KEY_3_SHIFT) 3324#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)
4621#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ 3325#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
4622#define I40E_VFQF_HLUT_MAX_INDEX 15 3326#define I40E_VFQF_HLUT_MAX_INDEX 15
4623#define I40E_VFQF_HLUT_LUT0_SHIFT 0 3327#define I40E_VFQF_HLUT_LUT0_SHIFT 0
4624#define I40E_VFQF_HLUT_LUT0_MASK (0xF << I40E_VFQF_HLUT_LUT0_SHIFT) 3328#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)
4625#define I40E_VFQF_HLUT_LUT1_SHIFT 8 3329#define I40E_VFQF_HLUT_LUT1_SHIFT 8
4626#define I40E_VFQF_HLUT_LUT1_MASK (0xF << I40E_VFQF_HLUT_LUT1_SHIFT) 3330#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)
4627#define I40E_VFQF_HLUT_LUT2_SHIFT 16 3331#define I40E_VFQF_HLUT_LUT2_SHIFT 16
4628#define I40E_VFQF_HLUT_LUT2_MASK (0xF << I40E_VFQF_HLUT_LUT2_SHIFT) 3332#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)
4629#define I40E_VFQF_HLUT_LUT3_SHIFT 24 3333#define I40E_VFQF_HLUT_LUT3_SHIFT 24
4630#define I40E_VFQF_HLUT_LUT3_MASK (0xF << I40E_VFQF_HLUT_LUT3_SHIFT) 3334#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)
4631#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ 3335#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
4632#define I40E_VFQF_HREGION_MAX_INDEX 7 3336#define I40E_VFQF_HREGION_MAX_INDEX 7
4633#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 3337#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
4634#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) 3338#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
4635#define I40E_VFQF_HREGION_REGION_0_SHIFT 1 3339#define I40E_VFQF_HREGION_REGION_0_SHIFT 1
4636#define I40E_VFQF_HREGION_REGION_0_MASK (0x7 << I40E_VFQF_HREGION_REGION_0_SHIFT) 3340#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)
4637#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 3341#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
4638#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) 3342#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
4639#define I40E_VFQF_HREGION_REGION_1_SHIFT 5 3343#define I40E_VFQF_HREGION_REGION_1_SHIFT 5
4640#define I40E_VFQF_HREGION_REGION_1_MASK (0x7 << I40E_VFQF_HREGION_REGION_1_SHIFT) 3344#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)
4641#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 3345#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
4642#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) 3346#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
4643#define I40E_VFQF_HREGION_REGION_2_SHIFT 9 3347#define I40E_VFQF_HREGION_REGION_2_SHIFT 9
4644#define I40E_VFQF_HREGION_REGION_2_MASK (0x7 << I40E_VFQF_HREGION_REGION_2_SHIFT) 3348#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)
4645#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 3349#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
4646#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) 3350#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
4647#define I40E_VFQF_HREGION_REGION_3_SHIFT 13 3351#define I40E_VFQF_HREGION_REGION_3_SHIFT 13
4648#define I40E_VFQF_HREGION_REGION_3_MASK (0x7 << I40E_VFQF_HREGION_REGION_3_SHIFT) 3352#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)
4649#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 3353#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
4650#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) 3354#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
4651#define I40E_VFQF_HREGION_REGION_4_SHIFT 17 3355#define I40E_VFQF_HREGION_REGION_4_SHIFT 17
4652#define I40E_VFQF_HREGION_REGION_4_MASK (0x7 << I40E_VFQF_HREGION_REGION_4_SHIFT) 3356#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)
4653#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 3357#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
4654#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) 3358#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
4655#define I40E_VFQF_HREGION_REGION_5_SHIFT 21 3359#define I40E_VFQF_HREGION_REGION_5_SHIFT 21
4656#define I40E_VFQF_HREGION_REGION_5_MASK (0x7 << I40E_VFQF_HREGION_REGION_5_SHIFT) 3360#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)
4657#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 3361#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
4658#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 3362#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
4659#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 3363#define I40E_VFQF_HREGION_REGION_6_SHIFT 25
4660#define I40E_VFQF_HREGION_REGION_6_MASK (0x7 << I40E_VFQF_HREGION_REGION_6_SHIFT) 3364#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)
4661#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 3365#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
4662#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 3366#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
4663#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 3367#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
4664#define I40E_VFQF_HREGION_REGION_7_MASK (0x7 << I40E_VFQF_HREGION_REGION_7_SHIFT) 3368#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
4665#define I40E_RCU_PST_FOC_ACCESS_STATUS 0x00270110
4666#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT 0
4667#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT)
4668#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT 8
4669#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT)
4670#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT 16
4671#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT)
4672#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT 24
4673#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_MASK (0x7 << I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT)
4674#endif 3369#endif
diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h
index 9d39ff23c5fb..1c0d5a70b892 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_type.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h
@@ -50,6 +50,9 @@
50 (d) == I40E_DEV_ID_QSFP_B || \ 50 (d) == I40E_DEV_ID_QSFP_B || \
51 (d) == I40E_DEV_ID_QSFP_C) 51 (d) == I40E_DEV_ID_QSFP_C)
52 52
53/* I40E_MASK is a macro used on 32 bit registers */
54#define I40E_MASK(mask, shift) (mask << shift)
55
53#define I40E_MAX_VSI_QP 16 56#define I40E_MAX_VSI_QP 16
54#define I40E_MAX_VF_VSI 3 57#define I40E_MAX_VF_VSI 3
55#define I40E_MAX_CHAINED_RX_BUFFERS 5 58#define I40E_MAX_CHAINED_RX_BUFFERS 5
@@ -1162,4 +1165,7 @@ enum i40e_reset_type {
1162 I40E_RESET_GLOBR = 2, 1165 I40E_RESET_GLOBR = 2,
1163 I40E_RESET_EMPR = 3, 1166 I40E_RESET_EMPR = 3,
1164}; 1167};
1168
1169/* RSS Hash Table Size */
1170#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1165#endif /* _I40E_TYPE_H_ */ 1171#endif /* _I40E_TYPE_H_ */
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
index eb67cce3e8f9..15853fd699a4 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
@@ -294,6 +294,10 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
294 i40e_status ret_code = 0; 294 i40e_status ret_code = 0;
295 u32 reg = 0; 295 u32 reg = 0;
296 296
297 /* Clear Head and Tail */
298 wr32(hw, hw->aq.asq.head, 0);
299 wr32(hw, hw->aq.asq.tail, 0);
300
297 if (hw->mac.type == I40E_MAC_VF) { 301 if (hw->mac.type == I40E_MAC_VF) {
298 /* configure the transmit queue */ 302 /* configure the transmit queue */
299 wr32(hw, I40E_VF_ATQBAH1, 303 wr32(hw, I40E_VF_ATQBAH1,
@@ -332,6 +336,10 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
332 i40e_status ret_code = 0; 336 i40e_status ret_code = 0;
333 u32 reg = 0; 337 u32 reg = 0;
334 338
339 /* Clear Head and Tail */
340 wr32(hw, hw->aq.arq.head, 0);
341 wr32(hw, hw->aq.arq.tail, 0);
342
335 if (hw->mac.type == I40E_MAC_VF) { 343 if (hw->mac.type == I40E_MAC_VF) {
336 /* configure the receive queue */ 344 /* configure the receive queue */
337 wr32(hw, I40E_VF_ARQBAH1, 345 wr32(hw, I40E_VF_ARQBAH1,
@@ -630,6 +638,10 @@ static u16 i40e_clean_asq(struct i40e_hw *hw)
630 desc = I40E_ADMINQ_DESC(*asq, ntc); 638 desc = I40E_ADMINQ_DESC(*asq, ntc);
631 details = I40E_ADMINQ_DETAILS(*asq, ntc); 639 details = I40E_ADMINQ_DETAILS(*asq, ntc);
632 while (rd32(hw, hw->aq.asq.head) != ntc) { 640 while (rd32(hw, hw->aq.asq.head) != ntc) {
641 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
642 "%s: ntc %d head %d.\n", __func__, ntc,
643 rd32(hw, hw->aq.asq.head));
644
633 if (details->callback) { 645 if (details->callback) {
634 I40E_ADMINQ_CALLBACK cb_func = 646 I40E_ADMINQ_CALLBACK cb_func =
635 (I40E_ADMINQ_CALLBACK)details->callback; 647 (I40E_ADMINQ_CALLBACK)details->callback;
@@ -690,6 +702,15 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
690 struct i40e_aq_desc *desc_on_ring; 702 struct i40e_aq_desc *desc_on_ring;
691 bool cmd_completed = false; 703 bool cmd_completed = false;
692 u16 retval = 0; 704 u16 retval = 0;
705 u32 val = 0;
706
707 val = rd32(hw, hw->aq.asq.head);
708 if (val >= hw->aq.num_asq_entries) {
709 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
710 "AQTX: head overrun at %d\n", val);
711 status = I40E_ERR_QUEUE_EMPTY;
712 goto asq_send_command_exit;
713 }
693 714
694 if (hw->aq.asq.count == 0) { 715 if (hw->aq.asq.count == 0) {
695 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 716 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
@@ -783,6 +804,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
783 } 804 }
784 805
785 /* bump the tail */ 806 /* bump the tail */
807 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
786 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff); 808 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
787 (hw->aq.asq.next_to_use)++; 809 (hw->aq.asq.next_to_use)++;
788 if (hw->aq.asq.next_to_use == hw->aq.asq.count) 810 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
@@ -820,6 +842,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
820 I40E_DEBUG_AQ_MESSAGE, 842 I40E_DEBUG_AQ_MESSAGE,
821 "AQTX: Command completed with error 0x%X.\n", 843 "AQTX: Command completed with error 0x%X.\n",
822 retval); 844 retval);
845
823 /* strip off FW internal code */ 846 /* strip off FW internal code */
824 retval &= 0xff; 847 retval &= 0xff;
825 } 848 }
@@ -834,6 +857,12 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
834 if (i40e_is_nvm_update_op(desc)) 857 if (i40e_is_nvm_update_op(desc))
835 hw->aq.nvm_busy = true; 858 hw->aq.nvm_busy = true;
836 859
860 if (le16_to_cpu(desc->datalen) == buff_size) {
861 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
862 "AQTX: desc and buffer writeback:\n");
863 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
864 }
865
837 /* update the error if time out occurred */ 866 /* update the error if time out occurred */
838 if ((!cmd_completed) && 867 if ((!cmd_completed) &&
839 (!details->async && !details->postpone)) { 868 (!details->async && !details->postpone)) {
@@ -905,10 +934,6 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
905 /* now clean the next descriptor */ 934 /* now clean the next descriptor */
906 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); 935 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
907 desc_idx = ntc; 936 desc_idx = ntc;
908 i40evf_debug_aq(hw,
909 I40E_DEBUG_AQ_COMMAND,
910 (void *)desc,
911 hw->aq.arq.r.arq_bi[desc_idx].va);
912 937
913 flags = le16_to_cpu(desc->flags); 938 flags = le16_to_cpu(desc->flags);
914 if (flags & I40E_AQ_FLAG_ERR) { 939 if (flags & I40E_AQ_FLAG_ERR) {
@@ -931,6 +956,9 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
931 if (i40e_is_nvm_update_op(&e->desc)) 956 if (i40e_is_nvm_update_op(&e->desc))
932 hw->aq.nvm_busy = false; 957 hw->aq.nvm_busy = false;
933 958
959 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
960 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
961
934 /* Restore the original datalen and buffer address in the desc, 962 /* Restore the original datalen and buffer address in the desc,
935 * FW updates datalen to indicate the event message 963 * FW updates datalen to indicate the event message
936 * size 964 * size
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_register.h b/drivers/net/ethernet/intel/i40evf/i40e_register.h
index 369839655818..c1f6a59bfea0 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_register.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_register.h
@@ -27,4648 +27,3343 @@
27#ifndef _I40E_REGISTER_H_ 27#ifndef _I40E_REGISTER_H_
28#define _I40E_REGISTER_H_ 28#define _I40E_REGISTER_H_
29 29
30#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ 30#define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
31#define I40E_GL_GP_FUSE_MAX_INDEX 28 31#define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
32#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0 32#define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
33#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK (0xFFFFFFFF << I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT) 33#define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */
34#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 34#define I40E_GL_ARQBAL_ARQBAL_SHIFT 0
35#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0 35#define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
36#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT) 36#define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */
37#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16 37#define I40E_GL_ARQH_ARQH_SHIFT 0
38#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT) 38#define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
39#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 39#define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */
40#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0 40#define I40E_GL_ARQT_ARQT_SHIFT 0
41#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT) 41#define I40E_GL_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT)
42#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16 42#define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */
43#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT) 43#define I40E_GL_ATQBAH_ATQBAH_SHIFT 0
44#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC 44#define I40E_GL_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT)
45#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0 45#define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */
46#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT) 46#define I40E_GL_ATQBAL_ATQBAL_SHIFT 0
47#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8 47#define I40E_GL_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT)
48#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT) 48#define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */
49#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 49#define I40E_GL_ATQH_ATQH_SHIFT 0
50#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0 50#define I40E_GL_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT)
51#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT) 51#define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */
52#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC 52#define I40E_GL_ATQLEN_ATQLEN_SHIFT 0
53#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0 53#define I40E_GL_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT)
54#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT) 54#define I40E_GL_ATQLEN_ATQVFE_SHIFT 28
55#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 55#define I40E_GL_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQVFE_SHIFT)
56#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 56#define I40E_GL_ATQLEN_ATQOVFL_SHIFT 29
57#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT) 57#define I40E_GL_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQOVFL_SHIFT)
58#define I40E_PFPCI_VF_FLUSH_DONE 0x0009C600 58#define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30
59#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 59#define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
60#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT) 60#define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31
61#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ 61#define I40E_GL_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT)
62#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127 62#define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */
63#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0 63#define I40E_GL_ATQT_ATQT_SHIFT 0
64#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT) 64#define I40E_GL_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT)
65#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 65#define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
66#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
67#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
68
69#define I40E_PF_ARQBAH 0x00080180
70#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0 66#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0
71#define I40E_PF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_PF_ARQBAH_ARQBAH_SHIFT) 67#define I40E_PF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT)
72#define I40E_PF_ARQBAL 0x00080080 68#define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
73#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0 69#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0
74#define I40E_PF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_PF_ARQBAL_ARQBAL_SHIFT) 70#define I40E_PF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT)
75#define I40E_PF_ARQH 0x00080380 71#define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
76#define I40E_PF_ARQH_ARQH_SHIFT 0 72#define I40E_PF_ARQH_ARQH_SHIFT 0
77#define I40E_PF_ARQH_ARQH_MASK (0x3FF << I40E_PF_ARQH_ARQH_SHIFT) 73#define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
78#define I40E_PF_ARQLEN 0x00080280 74#define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
79#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0 75#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0
80#define I40E_PF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_PF_ARQLEN_ARQLEN_SHIFT) 76#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)
81#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 77#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28
82#define I40E_PF_ARQLEN_ARQVFE_MASK (0x1 << I40E_PF_ARQLEN_ARQVFE_SHIFT) 78#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
83#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 79#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29
84#define I40E_PF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_PF_ARQLEN_ARQOVFL_SHIFT) 80#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
85#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 81#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
86#define I40E_PF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_PF_ARQLEN_ARQCRIT_SHIFT) 82#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
87#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 83#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
88#define I40E_PF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_PF_ARQLEN_ARQENABLE_SHIFT) 84#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
89#define I40E_PF_ARQT 0x00080480 85#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
90#define I40E_PF_ARQT_ARQT_SHIFT 0 86#define I40E_PF_ARQT_ARQT_SHIFT 0
91#define I40E_PF_ARQT_ARQT_MASK (0x3FF << I40E_PF_ARQT_ARQT_SHIFT) 87#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
92#define I40E_PF_ATQBAH 0x00080100 88#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */
93#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 89#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0
94#define I40E_PF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_PF_ATQBAH_ATQBAH_SHIFT) 90#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)
95#define I40E_PF_ATQBAL 0x00080000 91#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */
96#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 92#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0
97#define I40E_PF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_PF_ATQBAL_ATQBAL_SHIFT) 93#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)
98#define I40E_PF_ATQH 0x00080300 94#define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */
99#define I40E_PF_ATQH_ATQH_SHIFT 0 95#define I40E_PF_ATQH_ATQH_SHIFT 0
100#define I40E_PF_ATQH_ATQH_MASK (0x3FF << I40E_PF_ATQH_ATQH_SHIFT) 96#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)
101#define I40E_PF_ATQLEN 0x00080200 97#define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */
102#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0 98#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0
103#define I40E_PF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_PF_ATQLEN_ATQLEN_SHIFT) 99#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)
104#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 100#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28
105#define I40E_PF_ATQLEN_ATQVFE_MASK (0x1 << I40E_PF_ATQLEN_ATQVFE_SHIFT) 101#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)
106#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 102#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29
107#define I40E_PF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_PF_ATQLEN_ATQOVFL_SHIFT) 103#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)
108#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 104#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
109#define I40E_PF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_PF_ATQLEN_ATQCRIT_SHIFT) 105#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
110#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 106#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
111#define I40E_PF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_PF_ATQLEN_ATQENABLE_SHIFT) 107#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
112#define I40E_PF_ATQT 0x00080400 108#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
113#define I40E_PF_ATQT_ATQT_SHIFT 0 109#define I40E_PF_ATQT_ATQT_SHIFT 0
114#define I40E_PF_ATQT_ATQT_MASK (0x3FF << I40E_PF_ATQT_ATQT_SHIFT) 110#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
115#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ 111#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
116#define I40E_VF_ARQBAH_MAX_INDEX 127 112#define I40E_VF_ARQBAH_MAX_INDEX 127
117#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 113#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0
118#define I40E_VF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH_ARQBAH_SHIFT) 114#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)
119#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ 115#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
120#define I40E_VF_ARQBAL_MAX_INDEX 127 116#define I40E_VF_ARQBAL_MAX_INDEX 127
121#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0 117#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0
122#define I40E_VF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL_ARQBAL_SHIFT) 118#define I40E_VF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT)
123#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ 119#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
124#define I40E_VF_ARQH_MAX_INDEX 127 120#define I40E_VF_ARQH_MAX_INDEX 127
125#define I40E_VF_ARQH_ARQH_SHIFT 0 121#define I40E_VF_ARQH_ARQH_SHIFT 0
126#define I40E_VF_ARQH_ARQH_MASK (0x3FF << I40E_VF_ARQH_ARQH_SHIFT) 122#define I40E_VF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT)
127#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ 123#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
128#define I40E_VF_ARQLEN_MAX_INDEX 127 124#define I40E_VF_ARQLEN_MAX_INDEX 127
129#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0 125#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0
130#define I40E_VF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN_ARQLEN_SHIFT) 126#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)
131#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 127#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28
132#define I40E_VF_ARQLEN_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN_ARQVFE_SHIFT) 128#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT)
133#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 129#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29
134#define I40E_VF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN_ARQOVFL_SHIFT) 130#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT)
135#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 131#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30
136#define I40E_VF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN_ARQCRIT_SHIFT) 132#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
137#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 133#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
138#define I40E_VF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN_ARQENABLE_SHIFT) 134#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
139#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ 135#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
140#define I40E_VF_ARQT_MAX_INDEX 127 136#define I40E_VF_ARQT_MAX_INDEX 127
141#define I40E_VF_ARQT_ARQT_SHIFT 0 137#define I40E_VF_ARQT_ARQT_SHIFT 0
142#define I40E_VF_ARQT_ARQT_MASK (0x3FF << I40E_VF_ARQT_ARQT_SHIFT) 138#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)
143#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ 139#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
144#define I40E_VF_ATQBAH_MAX_INDEX 127 140#define I40E_VF_ATQBAH_MAX_INDEX 127
145#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 141#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0
146#define I40E_VF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH_ATQBAH_SHIFT) 142#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)
147#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ 143#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
148#define I40E_VF_ATQBAL_MAX_INDEX 127 144#define I40E_VF_ATQBAL_MAX_INDEX 127
149#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0 145#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0
150#define I40E_VF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL_ATQBAL_SHIFT) 146#define I40E_VF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT)
151#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ 147#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
152#define I40E_VF_ATQH_MAX_INDEX 127 148#define I40E_VF_ATQH_MAX_INDEX 127
153#define I40E_VF_ATQH_ATQH_SHIFT 0 149#define I40E_VF_ATQH_ATQH_SHIFT 0
154#define I40E_VF_ATQH_ATQH_MASK (0x3FF << I40E_VF_ATQH_ATQH_SHIFT) 150#define I40E_VF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT)
155#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ 151#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
156#define I40E_VF_ATQLEN_MAX_INDEX 127 152#define I40E_VF_ATQLEN_MAX_INDEX 127
157#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0 153#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0
158#define I40E_VF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN_ATQLEN_SHIFT) 154#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)
159#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 155#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28
160#define I40E_VF_ATQLEN_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN_ATQVFE_SHIFT) 156#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT)
161#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 157#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29
162#define I40E_VF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN_ATQOVFL_SHIFT) 158#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT)
163#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 159#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30
164#define I40E_VF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN_ATQCRIT_SHIFT) 160#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
165#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 161#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
166#define I40E_VF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN_ATQENABLE_SHIFT) 162#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
167#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ 163#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
168#define I40E_VF_ATQT_MAX_INDEX 127 164#define I40E_VF_ATQT_MAX_INDEX 127
169#define I40E_VF_ATQT_ATQT_SHIFT 0 165#define I40E_VF_ATQT_ATQT_SHIFT 0
170#define I40E_VF_ATQT_ATQT_MASK (0x3FF << I40E_VF_ATQT_ATQT_SHIFT) 166#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)
171#define I40E_PRT_L2TAGSEN 0x001C0B20 167#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */
172#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 168#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0
173#define I40E_PRT_L2TAGSEN_ENABLE_MASK (0xFF << I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 169#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
174#define I40E_PFCM_LAN_ERRDATA 0x0010C080 170#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */
175#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0 171#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0
176#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT) 172#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)
177#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4 173#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4
178#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT) 174#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)
179#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8 175#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8
180#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK (0xFFF << I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT) 176#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)
181#define I40E_PFCM_LAN_ERRINFO 0x0010C000 177#define I40E_PFCM_LAN_ERRINFO 0x0010C000 /* Reset: PFR */
182#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0 178#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0
183#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT) 179#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)
184#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4 180#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4
185#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT) 181#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT)
186#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8 182#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8
187#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT) 183#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT)
188#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16 184#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16
189#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT) 185#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
190#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24 186#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24
191#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT) 187#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
192#define I40E_PFCM_LANCTXCTL(_pf) (0x0010C300 + ((_pf) * 4))/* _pf=0..15 */ 188#define I40E_PFCM_LANCTXCTL 0x0010C300 /* Reset: CORER */
193#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0 189#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0
194#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK (0xFFF << I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT) 190#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
195#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12 191#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12
196#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK (0x7 << I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT) 192#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT)
197#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15 193#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15
198#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK (0x3 << I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT) 194#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
199#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17 195#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17
200#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK (0x3 << I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT) 196#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
201#define I40E_PFCM_LANCTXDATA(_i, _pf) (0x0010C100 + ((_i) * 4) + ((_pf) * 16))/* _i=0...3 _pf=0..15 */ 197#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */
202#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3 198#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3
203#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0 199#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0
204#define I40E_PFCM_LANCTXDATA_DATA_MASK (0xFFFFFFFF << I40E_PFCM_LANCTXDATA_DATA_SHIFT) 200#define I40E_PFCM_LANCTXDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT)
205#define I40E_PFCM_LANCTXSTAT(_pf) (0x0010C380 + ((_pf) * 4))/* _pf=0..15 */ 201#define I40E_PFCM_LANCTXSTAT 0x0010C380 /* Reset: CORER */
206#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0 202#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0
207#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT) 203#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
208#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1 204#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
209#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT) 205#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)
210#define I40E_PFCM_PE_ERRDATA 0x00138D00 206#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
211#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
212#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
213#define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
214#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT)
215#define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8
216#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT)
217#define I40E_PFCM_PE_ERRINFO 0x00138C80
218#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
219#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
220#define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
221#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT)
222#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
223#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
224#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
225#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
226#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
227#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
228#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */
229#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127 207#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127
230#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0 208#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0
231#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT) 209#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)
232#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4 210#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4
233#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT) 211#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)
234#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8 212#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8
235#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT) 213#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)
236#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ 214#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
237#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127 215#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127
238#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0 216#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0
239#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT) 217#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)
240#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4 218#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4
241#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT) 219#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT)
242#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8 220#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8
243#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT) 221#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT)
244#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16 222#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16
245#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) 223#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
246#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 224#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
247#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) 225#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
248#define I40E_GLDCB_GENC 0x00083044 226#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */
249#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 227#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
250#define I40E_GLDCB_GENC_PCIRTT_MASK (0xFFFF << I40E_GLDCB_GENC_PCIRTT_SHIFT) 228#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)
251#define I40E_GLDCB_RUPTI 0x00122618 229#define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */
252#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0 230#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0
253#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK (0xFFFFFFFF << I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT) 231#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)
254#define I40E_PRTDCB_FCCFG 0x001E4640 232#define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */
255#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 233#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3
256#define I40E_PRTDCB_FCCFG_TFCE_MASK (0x3 << I40E_PRTDCB_FCCFG_TFCE_SHIFT) 234#define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
257#define I40E_PRTDCB_FCRTV 0x001E4600 235#define I40E_PRTDCB_FCRTV 0x001E4600 /* Reset: GLOBR */
258#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0 236#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0
259#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK (0xFFFF << I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT) 237#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)
260#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ 238#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */
261#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3 239#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3
262#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0 240#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0
263#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT) 241#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
264#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16 242#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16
265#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT) 243#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
266#define I40E_PRTDCB_GENC 0x00083000 244#define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */
267#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0 245#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0
268#define I40E_PRTDCB_GENC_RESERVED_1_MASK (0x3 << I40E_PRTDCB_GENC_RESERVED_1_SHIFT) 246#define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
269#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2 247#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2
270#define I40E_PRTDCB_GENC_NUMTC_MASK (0xF << I40E_PRTDCB_GENC_NUMTC_SHIFT) 248#define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT)
271#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6 249#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6
272#define I40E_PRTDCB_GENC_FCOEUP_MASK (0x7 << I40E_PRTDCB_GENC_FCOEUP_SHIFT) 250#define I40E_PRTDCB_GENC_FCOEUP_MASK I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT)
273#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9 251#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9
274#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK (0x1 << I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT) 252#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
275#define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 253#define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16
276#define I40E_PRTDCB_GENC_PFCLDA_MASK (0xFFFF << I40E_PRTDCB_GENC_PFCLDA_SHIFT) 254#define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
277#define I40E_PRTDCB_GENS 0x00083020 255#define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */
278#define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 256#define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
279#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK (0x7 << I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 257#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
280#define I40E_PRTDCB_MFLCN 0x001E2400 258#define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */
281#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0 259#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0
282#define I40E_PRTDCB_MFLCN_PMCF_MASK (0x1 << I40E_PRTDCB_MFLCN_PMCF_SHIFT) 260#define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
283#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1 261#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1
284#define I40E_PRTDCB_MFLCN_DPF_MASK (0x1 << I40E_PRTDCB_MFLCN_DPF_SHIFT) 262#define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT)
285#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2 263#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2
286#define I40E_PRTDCB_MFLCN_RPFCM_MASK (0x1 << I40E_PRTDCB_MFLCN_RPFCM_SHIFT) 264#define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT)
287#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3 265#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3
288#define I40E_PRTDCB_MFLCN_RFCE_MASK (0x1 << I40E_PRTDCB_MFLCN_RFCE_SHIFT) 266#define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT)
289#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4 267#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4
290#define I40E_PRTDCB_MFLCN_RPFCE_MASK (0xFF << I40E_PRTDCB_MFLCN_RPFCE_SHIFT) 268#define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
291#define I40E_PRTDCB_RETSC 0x001223E0 269#define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */
292#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0 270#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0
293#define I40E_PRTDCB_RETSC_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) 271#define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
294#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1 272#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1
295#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) 273#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)
296#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2 274#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2
297#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK (0xF << I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) 275#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
298#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8 276#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8
299#define I40E_PRTDCB_RETSC_LLTC_MASK (0xFF << I40E_PRTDCB_RETSC_LLTC_SHIFT) 277#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
300#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ 278#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
301#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 279#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7
302#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 280#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0
303#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK (0x7F << I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 281#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
304#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 282#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
305#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK (0x1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 283#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
306#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 284#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
307#define I40E_PRTDCB_RETSTCC_ETSTC_MASK (0x1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) 285#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
308#define I40E_PRTDCB_RPPMC 0x001223A0 286#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */
309#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 287#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
310#define I40E_PRTDCB_RPPMC_LANRPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 288#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
311#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 289#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8
312#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 290#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
313#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 291#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
314#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK (0xFF << I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 292#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
315#define I40E_PRTDCB_RUP 0x001C0B00 293#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */
316#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0 294#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0
317#define I40E_PRTDCB_RUP_NOVLANUP_MASK (0x7 << I40E_PRTDCB_RUP_NOVLANUP_SHIFT) 295#define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
318#define I40E_PRTDCB_RUP2TC 0x001C09A0 296#define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */
319#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0 297#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0
320#define I40E_PRTDCB_RUP2TC_UP0TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP0TC_SHIFT) 298#define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
321#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3 299#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3
322#define I40E_PRTDCB_RUP2TC_UP1TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP1TC_SHIFT) 300#define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)
323#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6 301#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6
324#define I40E_PRTDCB_RUP2TC_UP2TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP2TC_SHIFT) 302#define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)
325#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9 303#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9
326#define I40E_PRTDCB_RUP2TC_UP3TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP3TC_SHIFT) 304#define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)
327#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 305#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12
328#define I40E_PRTDCB_RUP2TC_UP4TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 306#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)
329#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 307#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15
330#define I40E_PRTDCB_RUP2TC_UP5TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 308#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)
331#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 309#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18
332#define I40E_PRTDCB_RUP2TC_UP6TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 310#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
333#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 311#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
334#define I40E_PRTDCB_RUP2TC_UP7TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) 312#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
335#define I40E_PRTDCB_TC2PFC 0x001C0980 313#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */
336#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 314#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
337#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK (0xFF << I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 315#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
338#define I40E_PRTDCB_TCPMC 0x000A21A0 316#define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
317#define I40E_PRTDCB_TCMSTC_MAX_INDEX 7
318#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0
319#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)
320#define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */
339#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0 321#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0
340#define I40E_PRTDCB_TCPMC_CPM_MASK (0x1FFF << I40E_PRTDCB_TCPMC_CPM_SHIFT) 322#define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)
341#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13 323#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13
342#define I40E_PRTDCB_TCPMC_LLTC_MASK (0xFF << I40E_PRTDCB_TCPMC_LLTC_SHIFT) 324#define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)
343#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30 325#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30
344#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) 326#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
345#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ 327#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
346#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7 328#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7
347#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0 329#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0
348#define I40E_PRTDCB_TCWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TCWSTC_MSTC_SHIFT) 330#define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
349#define I40E_PRTDCB_TDPMC 0x000A0180 331#define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */
350#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0 332#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0
351#define I40E_PRTDCB_TDPMC_DPM_MASK (0xFF << I40E_PRTDCB_TDPMC_DPM_SHIFT) 333#define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)
352#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30 334#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30
353#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) 335#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
354#define I40E_PRTDCB_TDPUC 0x00044100 336#define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */
355#define I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT 0
356#define I40E_PRTDCB_TDPUC_MAX_TXFRAME_MASK (0xFFFF << I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT)
357#define I40E_PRTDCB_TETSC_TCB 0x000AE060
358#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0 337#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0
359#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT) 338#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
360#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8 339#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8
361#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT) 340#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
362#define I40E_PRTDCB_TETSC_TPB 0x00098060 341#define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */
363#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0 342#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0
364#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT) 343#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
365#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8 344#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8
366#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT) 345#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
367#define I40E_PRTDCB_TFCS 0x001E4560 346#define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */
368#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0 347#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0
369#define I40E_PRTDCB_TFCS_TXOFF_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF_SHIFT) 348#define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT)
370#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8 349#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
371#define I40E_PRTDCB_TFCS_TXOFF0_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF0_SHIFT) 350#define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT)
372#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9 351#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9
373#define I40E_PRTDCB_TFCS_TXOFF1_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF1_SHIFT) 352#define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT)
374#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10 353#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10
375#define I40E_PRTDCB_TFCS_TXOFF2_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF2_SHIFT) 354#define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT)
376#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11 355#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11
377#define I40E_PRTDCB_TFCS_TXOFF3_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF3_SHIFT) 356#define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT)
378#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12 357#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12
379#define I40E_PRTDCB_TFCS_TXOFF4_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF4_SHIFT) 358#define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT)
380#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13 359#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13
381#define I40E_PRTDCB_TFCS_TXOFF5_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF5_SHIFT) 360#define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT)
382#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14 361#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14
383#define I40E_PRTDCB_TFCS_TXOFF6_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF6_SHIFT) 362#define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
384#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15 363#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15
385#define I40E_PRTDCB_TFCS_TXOFF7_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF7_SHIFT) 364#define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
386#define I40E_PRTDCB_TFWSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ 365#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */
387#define I40E_PRTDCB_TFWSTC_MAX_INDEX 7
388#define I40E_PRTDCB_TFWSTC_MSTC_SHIFT 0
389#define I40E_PRTDCB_TFWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TFWSTC_MSTC_SHIFT)
390#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */
391#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7 366#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7
392#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 367#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0
393#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK (0x3FFF << I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) 368#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
394#define I40E_GLFCOE_RCTL 0x00269B94 369#define I40E_GLFCOE_RCTL 0x00269B94 /* Reset: CORER */
395#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0 370#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0
396#define I40E_GLFCOE_RCTL_FCOEVER_MASK (0xF << I40E_GLFCOE_RCTL_FCOEVER_SHIFT) 371#define I40E_GLFCOE_RCTL_FCOEVER_MASK I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT)
397#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4 372#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4
398#define I40E_GLFCOE_RCTL_SAVBAD_MASK (0x1 << I40E_GLFCOE_RCTL_SAVBAD_SHIFT) 373#define I40E_GLFCOE_RCTL_SAVBAD_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_SAVBAD_SHIFT)
399#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5 374#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5
400#define I40E_GLFCOE_RCTL_ICRC_MASK (0x1 << I40E_GLFCOE_RCTL_ICRC_SHIFT) 375#define I40E_GLFCOE_RCTL_ICRC_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT)
401#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16 376#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16
402#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK (0x3FFF << I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 377#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
403#define I40E_GL_FWSTS 0x00083048 378#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */
404#define I40E_GL_FWSTS_FWS0B_SHIFT 0 379#define I40E_GL_FWSTS_FWS0B_SHIFT 0
405#define I40E_GL_FWSTS_FWS0B_MASK (0xFF << I40E_GL_FWSTS_FWS0B_SHIFT) 380#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)
406#define I40E_GL_FWSTS_FWRI_SHIFT 9 381#define I40E_GL_FWSTS_FWRI_SHIFT 9
407#define I40E_GL_FWSTS_FWRI_MASK (0x1 << I40E_GL_FWSTS_FWRI_SHIFT) 382#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)
408#define I40E_GL_FWSTS_FWS1B_SHIFT 16 383#define I40E_GL_FWSTS_FWS1B_SHIFT 16
409#define I40E_GL_FWSTS_FWS1B_MASK (0xFF << I40E_GL_FWSTS_FWS1B_SHIFT) 384#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
410#define I40E_GLGEN_CLKSTAT 0x000B8184 385#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */
411#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 386#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0
412#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK (0x1 << I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 387#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
413#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 388#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4
414#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK (0x3 << I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 389#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
415#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 390#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8
416#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 391#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)
417#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 392#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12
418#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT) 393#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT)
419#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16 394#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16
420#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT) 395#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)
421#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20 396#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20
422#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT) 397#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)
423#define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ 398#define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
424#define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 399#define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29
425#define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 400#define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0
426#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK (0x3 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 401#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
427#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 402#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3
428#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 403#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
429#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4 404#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4
430#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 405#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
431#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5 406#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5
432#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 407#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
433#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6 408#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6
434#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 409#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
435#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 410#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7
436#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK (0x7 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 411#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
437#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10 412#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10
438#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT) 413#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT)
439#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 414#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11
440#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT) 415#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)
441#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 416#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12
442#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK (0xF << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 417#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
443#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17 418#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17
444#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK (0x3 << I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT) 419#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
445#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 420#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19
446#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 421#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
447#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 422#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
448#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 423#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
449#define I40E_GLGEN_GPIO_SET 0x00088184 424#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */
450#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 425#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
451#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK (0x1F << I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) 426#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
452#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 427#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5
453#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK (0x1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 428#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
454#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 429#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6
455#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK (0x1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 430#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
456#define I40E_GLGEN_GPIO_STAT 0x0008817C 431#define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */
457#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0 432#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0
458#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT) 433#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)
459#define I40E_GLGEN_GPIO_TRANSIT 0x00088180 434#define I40E_GLGEN_GPIO_TRANSIT 0x00088180 /* Reset: POR */
460#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0 435#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0
461#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT) 436#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)
462#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ 437#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
463#define I40E_GLGEN_I2CCMD_MAX_INDEX 3 438#define I40E_GLGEN_I2CCMD_MAX_INDEX 3
464#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0 439#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0
465#define I40E_GLGEN_I2CCMD_DATA_MASK (0xFFFF << I40E_GLGEN_I2CCMD_DATA_SHIFT) 440#define I40E_GLGEN_I2CCMD_DATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT)
466#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16 441#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16
467#define I40E_GLGEN_I2CCMD_REGADD_MASK (0xFF << I40E_GLGEN_I2CCMD_REGADD_SHIFT) 442#define I40E_GLGEN_I2CCMD_REGADD_MASK I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT)
468#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24 443#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24
469#define I40E_GLGEN_I2CCMD_PHYADD_MASK (0x7 << I40E_GLGEN_I2CCMD_PHYADD_SHIFT) 444#define I40E_GLGEN_I2CCMD_PHYADD_MASK I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT)
470#define I40E_GLGEN_I2CCMD_OP_SHIFT 27 445#define I40E_GLGEN_I2CCMD_OP_SHIFT 27
471#define I40E_GLGEN_I2CCMD_OP_MASK (0x1 << I40E_GLGEN_I2CCMD_OP_SHIFT) 446#define I40E_GLGEN_I2CCMD_OP_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_OP_SHIFT)
472#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28 447#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28
473#define I40E_GLGEN_I2CCMD_RESET_MASK (0x1 << I40E_GLGEN_I2CCMD_RESET_SHIFT) 448#define I40E_GLGEN_I2CCMD_RESET_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_RESET_SHIFT)
474#define I40E_GLGEN_I2CCMD_R_SHIFT 29 449#define I40E_GLGEN_I2CCMD_R_SHIFT 29
475#define I40E_GLGEN_I2CCMD_R_MASK (0x1 << I40E_GLGEN_I2CCMD_R_SHIFT) 450#define I40E_GLGEN_I2CCMD_R_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT)
476#define I40E_GLGEN_I2CCMD_E_SHIFT 31 451#define I40E_GLGEN_I2CCMD_E_SHIFT 31
477#define I40E_GLGEN_I2CCMD_E_MASK (0x1 << I40E_GLGEN_I2CCMD_E_SHIFT) 452#define I40E_GLGEN_I2CCMD_E_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT)
478#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ 453#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
479#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3 454#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3
480#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0 455#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0
481#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK (0x1F << I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT) 456#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)
482#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5 457#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5
483#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK (0x7 << I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT) 458#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT)
484#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8 459#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8
485#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT) 460#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT)
486#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9 461#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9
487#define I40E_GLGEN_I2CPARAMS_CLK_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_SHIFT) 462#define I40E_GLGEN_I2CPARAMS_CLK_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_SHIFT)
488#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10 463#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10
489#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT) 464#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT)
490#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11 465#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11
491#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT) 466#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT)
492#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12 467#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12
493#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT) 468#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT)
494#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13 469#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13
495#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT) 470#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT)
496#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14 471#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14
497#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT) 472#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT)
498#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15 473#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15
499#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT) 474#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)
500#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31 475#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31
501#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT) 476#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)
502#define I40E_GLGEN_LED_CTL 0x00088178 477#define I40E_GLGEN_LED_CTL 0x00088178 /* Reset: POR */
503#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0 478#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0
504#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK (0x1 << I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT) 479#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)
505#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ 480#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
506#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3 481#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3
507#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0 482#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0
508#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK (0x1FFFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT) 483#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)
509#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 484#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17
510#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK (0x1 << I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) 485#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
511#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 486#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
512#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK (0x3FFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) 487#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
513#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ 488#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
514#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 489#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3
515#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 490#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
516#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT) 491#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)
517#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1 492#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1
518#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT) 493#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)
519#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5 494#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5
520#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT) 495#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT)
521#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10 496#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10
522#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT) 497#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT)
523#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15 498#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15
524#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT) 499#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT)
525#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20 500#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20
526#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT) 501#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT)
527#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25 502#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25
528#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT) 503#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)
529#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31 504#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31
530#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT) 505#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)
531#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ 506#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
532#define I40E_GLGEN_MSCA_MAX_INDEX 3 507#define I40E_GLGEN_MSCA_MAX_INDEX 3
533#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 508#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0
534#define I40E_GLGEN_MSCA_MDIADD_MASK (0xFFFF << I40E_GLGEN_MSCA_MDIADD_SHIFT) 509#define I40E_GLGEN_MSCA_MDIADD_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT)
535#define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 510#define I40E_GLGEN_MSCA_DEVADD_SHIFT 16
536#define I40E_GLGEN_MSCA_DEVADD_MASK (0x1F << I40E_GLGEN_MSCA_DEVADD_SHIFT) 511#define I40E_GLGEN_MSCA_DEVADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT)
537#define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 512#define I40E_GLGEN_MSCA_PHYADD_SHIFT 21
538#define I40E_GLGEN_MSCA_PHYADD_MASK (0x1F << I40E_GLGEN_MSCA_PHYADD_SHIFT) 513#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)
539#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 514#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26
540#define I40E_GLGEN_MSCA_OPCODE_MASK (0x3 << I40E_GLGEN_MSCA_OPCODE_SHIFT) 515#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)
541#define I40E_GLGEN_MSCA_STCODE_SHIFT 28 516#define I40E_GLGEN_MSCA_STCODE_SHIFT 28
542#define I40E_GLGEN_MSCA_STCODE_MASK (0x3 << I40E_GLGEN_MSCA_STCODE_SHIFT) 517#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)
543#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 518#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
544#define I40E_GLGEN_MSCA_MDICMD_MASK (0x1 << I40E_GLGEN_MSCA_MDICMD_SHIFT) 519#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
545#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 520#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
546#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK (0x1 << I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 521#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
547#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ 522#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
548#define I40E_GLGEN_MSRWD_MAX_INDEX 3 523#define I40E_GLGEN_MSRWD_MAX_INDEX 3
549#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 524#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
550#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 525#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
551#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 526#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
552#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 527#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
553#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 528#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */
554#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 529#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
555#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK (0x1F << I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) 530#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
556#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 531#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
557#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK (0xFF << I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) 532#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
558#define I40E_GLGEN_PE_ENA 0x000B81A0 533#define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */
559#define I40E_GLGEN_PE_ENA_PE_ENA_SHIFT 0
560#define I40E_GLGEN_PE_ENA_PE_ENA_MASK (0x1 << I40E_GLGEN_PE_ENA_PE_ENA_SHIFT)
561#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT 1
562#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_MASK (0x3 << I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT)
563#define I40E_GLGEN_RSTAT 0x000B8188
564#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 534#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
565#define I40E_GLGEN_RSTAT_DEVSTATE_MASK (0x3 << I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 535#define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
566#define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 536#define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2
567#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK (0x3 << I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 537#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)
568#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4 538#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4
569#define I40E_GLGEN_RSTAT_CORERCNT_MASK (0x3 << I40E_GLGEN_RSTAT_CORERCNT_SHIFT) 539#define I40E_GLGEN_RSTAT_CORERCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT)
570#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6 540#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6
571#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT) 541#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT)
572#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8 542#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8
573#define I40E_GLGEN_RSTAT_EMPRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_EMPRCNT_SHIFT) 543#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)
574#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10 544#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10
575#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK (0x3F << I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT) 545#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)
576#define I40E_GLGEN_RSTCTL 0x000B8180 546#define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */
577#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 547#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0
578#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK (0x3F << I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 548#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
579#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 549#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
580#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) 550#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
581#define I40E_GLGEN_RSTENA_EMP 0x000B818C 551#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR */
582#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0 552#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0
583#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT) 553#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)
584#define I40E_GLGEN_RTRIG 0x000B8190 554#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */
585#define I40E_GLGEN_RTRIG_CORER_SHIFT 0 555#define I40E_GLGEN_RTRIG_CORER_SHIFT 0
586#define I40E_GLGEN_RTRIG_CORER_MASK (0x1 << I40E_GLGEN_RTRIG_CORER_SHIFT) 556#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
587#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 557#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1
588#define I40E_GLGEN_RTRIG_GLOBR_MASK (0x1 << I40E_GLGEN_RTRIG_GLOBR_SHIFT) 558#define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT)
589#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2 559#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2
590#define I40E_GLGEN_RTRIG_EMPFWR_MASK (0x1 << I40E_GLGEN_RTRIG_EMPFWR_SHIFT) 560#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT)
591#define I40E_GLGEN_STAT 0x000B612C 561#define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
592#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0 562#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0
593#define I40E_GLGEN_STAT_HWRSVD0_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD0_SHIFT) 563#define I40E_GLGEN_STAT_HWRSVD0_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT)
594#define I40E_GLGEN_STAT_DCBEN_SHIFT 2 564#define I40E_GLGEN_STAT_DCBEN_SHIFT 2
595#define I40E_GLGEN_STAT_DCBEN_MASK (0x1 << I40E_GLGEN_STAT_DCBEN_SHIFT) 565#define I40E_GLGEN_STAT_DCBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_DCBEN_SHIFT)
596#define I40E_GLGEN_STAT_VTEN_SHIFT 3 566#define I40E_GLGEN_STAT_VTEN_SHIFT 3
597#define I40E_GLGEN_STAT_VTEN_MASK (0x1 << I40E_GLGEN_STAT_VTEN_SHIFT) 567#define I40E_GLGEN_STAT_VTEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_VTEN_SHIFT)
598#define I40E_GLGEN_STAT_FCOEN_SHIFT 4 568#define I40E_GLGEN_STAT_FCOEN_SHIFT 4
599#define I40E_GLGEN_STAT_FCOEN_MASK (0x1 << I40E_GLGEN_STAT_FCOEN_SHIFT) 569#define I40E_GLGEN_STAT_FCOEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_FCOEN_SHIFT)
600#define I40E_GLGEN_STAT_EVBEN_SHIFT 5 570#define I40E_GLGEN_STAT_EVBEN_SHIFT 5
601#define I40E_GLGEN_STAT_EVBEN_MASK (0x1 << I40E_GLGEN_STAT_EVBEN_SHIFT) 571#define I40E_GLGEN_STAT_EVBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT)
602#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6 572#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6
603#define I40E_GLGEN_STAT_HWRSVD1_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD1_SHIFT) 573#define I40E_GLGEN_STAT_HWRSVD1_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT)
604#define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ 574#define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
605#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3 575#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3
606#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0 576#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0
607#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK (0xFFFFFFFF << I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT) 577#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)
608#define I40E_GLVFGEN_TIMER 0x000881BC 578#define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */
609#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0 579#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0
610#define I40E_GLVFGEN_TIMER_GTIME_MASK (0xFFFFFFFF << I40E_GLVFGEN_TIMER_GTIME_SHIFT) 580#define I40E_GLVFGEN_TIMER_GTIME_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT)
611#define I40E_PFGEN_CTRL 0x00092400 581#define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */
612#define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 582#define I40E_PFGEN_CTRL_PFSWR_SHIFT 0
613#define I40E_PFGEN_CTRL_PFSWR_MASK (0x1 << I40E_PFGEN_CTRL_PFSWR_SHIFT) 583#define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT)
614#define I40E_PFGEN_DRUN 0x00092500 584#define I40E_PFGEN_DRUN 0x00092500 /* Reset: CORER */
615#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0 585#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0
616#define I40E_PFGEN_DRUN_DRVUNLD_MASK (0x1 << I40E_PFGEN_DRUN_DRVUNLD_SHIFT) 586#define I40E_PFGEN_DRUN_DRVUNLD_MASK I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT)
617#define I40E_PFGEN_PORTNUM 0x001C0480 587#define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */
618#define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 588#define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0
619#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 589#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
620#define I40E_PFGEN_STATE 0x00088000 590#define I40E_PFGEN_STATE 0x00088000 /* Reset: CORER */
621#define I40E_PFGEN_STATE_PFPEEN_SHIFT 0 591#define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0
622#define I40E_PFGEN_STATE_PFPEEN_MASK (0x1 << I40E_PFGEN_STATE_PFPEEN_SHIFT) 592#define I40E_PFGEN_STATE_RESERVED_0_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT)
623#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1 593#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1
624#define I40E_PFGEN_STATE_PFFCEN_MASK (0x1 << I40E_PFGEN_STATE_PFFCEN_SHIFT) 594#define I40E_PFGEN_STATE_PFFCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFFCEN_SHIFT)
625#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2 595#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2
626#define I40E_PFGEN_STATE_PFLINKEN_MASK (0x1 << I40E_PFGEN_STATE_PFLINKEN_SHIFT) 596#define I40E_PFGEN_STATE_PFLINKEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT)
627#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3 597#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3
628#define I40E_PFGEN_STATE_PFSCEN_MASK (0x1 << I40E_PFGEN_STATE_PFSCEN_SHIFT) 598#define I40E_PFGEN_STATE_PFSCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT)
629#define I40E_PRTGEN_CNF 0x000B8120 599#define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */
630#define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 600#define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0
631#define I40E_PRTGEN_CNF_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 601#define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
632#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1 602#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1
633#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT) 603#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)
634#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2 604#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2
635#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT) 605#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)
636#define I40E_PRTGEN_CNF2 0x000B8160 606#define I40E_PRTGEN_CNF2 0x000B8160 /* Reset: POR */
637#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0 607#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0
638#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK (0x1 << I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT) 608#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)
639#define I40E_PRTGEN_STATUS 0x000B8100 609#define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */
640#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0 610#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0
641#define I40E_PRTGEN_STATUS_PORT_VALID_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_VALID_SHIFT) 611#define I40E_PRTGEN_STATUS_PORT_VALID_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)
642#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1 612#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1
643#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT) 613#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)
644#define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ 614#define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
645#define I40E_VFGEN_RSTAT1_MAX_INDEX 127 615#define I40E_VFGEN_RSTAT1_MAX_INDEX 127
646#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0 616#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0
647#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT) 617#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)
648#define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ 618#define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
649#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127 619#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127
650#define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 620#define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0
651#define I40E_VPGEN_VFRSTAT_VFRD_MASK (0x1 << I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 621#define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
652#define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ 622#define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
653#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127 623#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127
654#define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 624#define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0
655#define I40E_VPGEN_VFRTRIG_VFSWR_MASK (0x1 << I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 625#define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
656#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ 626#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
657#define I40E_VSIGEN_RSTAT_MAX_INDEX 383 627#define I40E_VSIGEN_RSTAT_MAX_INDEX 383
658#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0 628#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0
659#define I40E_VSIGEN_RSTAT_VMRD_MASK (0x1 << I40E_VSIGEN_RSTAT_VMRD_SHIFT) 629#define I40E_VSIGEN_RSTAT_VMRD_MASK I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT)
660#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ 630#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
661#define I40E_VSIGEN_RTRIG_MAX_INDEX 383 631#define I40E_VSIGEN_RTRIG_MAX_INDEX 383
662#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0 632#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0
663#define I40E_VSIGEN_RTRIG_VMSWR_MASK (0x1 << I40E_VSIGEN_RTRIG_VMSWR_SHIFT) 633#define I40E_VSIGEN_RTRIG_VMSWR_MASK I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT)
664#define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) 634#define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
665#define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15
666#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
667#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
668#define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */
669#define I40E_GLHMC_CEQPART_MAX_INDEX 15
670#define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0
671#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT)
672#define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16
673#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT)
674#define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */
675#define I40E_GLHMC_DBCQPART_MAX_INDEX 15
676#define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0
677#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT)
678#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16
679#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT)
680#define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */
681#define I40E_GLHMC_DBQPPART_MAX_INDEX 15
682#define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0
683#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT)
684#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16
685#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT)
686#define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */
687#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15 635#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15
688#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 636#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0
689#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 637#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
690#define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ 638#define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
691#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15 639#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15
692#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0 640#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0
693#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK (0xFFFFF << I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT) 641#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)
694#define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 642#define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */
695#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0 643#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0
696#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK (0xF << I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT) 644#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)
697#define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ 645#define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
698#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15 646#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15
699#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 647#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0
700#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 648#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
701#define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ 649#define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
702#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15 650#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15
703#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0 651#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0
704#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK (0x7FFFFF << I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT) 652#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)
705#define I40E_GLHMC_FCOEFMAX 0x000C20D0 653#define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */
706#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 654#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0
707#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK (0xFFFF << I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 655#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
708#define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 656#define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */
709#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0 657#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0
710#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK (0xF << I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT) 658#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)
711#define I40E_GLHMC_FCOEMAX 0x000C2014 659#define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */
712#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0 660#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0
713#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK (0x1FFF << I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT) 661#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)
714#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ 662#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
715#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15 663#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15
716#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0 664#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0
717#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT) 665#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)
718#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ 666#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
719#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15 667#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15
720#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0 668#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0
721#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT) 669#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)
722#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29 670#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29
723#define I40E_GLHMC_FSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_FSIAVCNT_RSVD_SHIFT) 671#define I40E_GLHMC_FSIAVCNT_RSVD_MASK I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)
724#define I40E_GLHMC_FSIAVMAX 0x000C2068 672#define I40E_GLHMC_FSIAVMAX 0x000C2068 /* Reset: CORER */
725#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0 673#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0
726#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK (0x1FFFF << I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT) 674#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)
727#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 675#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 /* Reset: CORER */
728#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0 676#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0
729#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK (0xF << I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT) 677#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)
730#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ 678#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
731#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15 679#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15
732#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0 680#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0
733#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT) 681#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)
734#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ 682#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
735#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15 683#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15
736#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0 684#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0
737#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK (0x1FFFFFFF << I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT) 685#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)
738#define I40E_GLHMC_FSIMCMAX 0x000C2060 686#define I40E_GLHMC_FSIMCMAX 0x000C2060 /* Reset: CORER */
739#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0 687#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0
740#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK (0x3FFF << I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT) 688#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)
741#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c 689#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c /* Reset: CORER */
742#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0 690#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0
743#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK (0xF << I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT) 691#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)
744#define I40E_GLHMC_LANQMAX 0x000C2008 692#define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */
745#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0 693#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0
746#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK (0x7FF << I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT) 694#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)
747#define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ 695#define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
748#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15 696#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15
749#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 697#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0
750#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 698#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
751#define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ 699#define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
752#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15 700#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15
753#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0 701#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0
754#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK (0x7FF << I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT) 702#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)
755#define I40E_GLHMC_LANRXOBJSZ 0x000C200c 703#define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */
756#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0 704#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0
757#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK (0xF << I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT) 705#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)
758#define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ 706#define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
759#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15 707#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15
760#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 708#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0
761#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 709#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
762#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24 710#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24
763#define I40E_GLHMC_LANTXBASE_RSVD_MASK (0xFF << I40E_GLHMC_LANTXBASE_RSVD_SHIFT) 711#define I40E_GLHMC_LANTXBASE_RSVD_MASK I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT)
764#define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ 712#define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
765#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15 713#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15
766#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0 714#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0
767#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK (0x7FF << I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT) 715#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)
768#define I40E_GLHMC_LANTXOBJSZ 0x000C2004 716#define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */
769#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0 717#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0
770#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK (0xF << I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT) 718#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)
771#define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */ 719#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
772#define I40E_GLHMC_PEARPBASE_MAX_INDEX 15
773#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0
774#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT)
775#define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */
776#define I40E_GLHMC_PEARPCNT_MAX_INDEX 15
777#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0
778#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT)
779#define I40E_GLHMC_PEARPMAX 0x000C2038
780#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0
781#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK (0x1FFFF << I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT)
782#define I40E_GLHMC_PEARPOBJSZ 0x000C2034
783#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0
784#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK (0x7 << I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT)
785#define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */
786#define I40E_GLHMC_PECQBASE_MAX_INDEX 15
787#define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0
788#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT)
789#define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */
790#define I40E_GLHMC_PECQCNT_MAX_INDEX 15
791#define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0
792#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT)
793#define I40E_GLHMC_PECQOBJSZ 0x000C2020
794#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0
795#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK (0xF << I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT)
796#define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */
797#define I40E_GLHMC_PEHTCNT_MAX_INDEX 15
798#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0
799#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT)
800#define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */
801#define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15
802#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0
803#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT)
804#define I40E_GLHMC_PEHTEOBJSZ 0x000C202c
805#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0
806#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK (0xF << I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT)
807#define I40E_GLHMC_PEHTMAX 0x000C2030
808#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0
809#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK (0x1FFFFF << I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT)
810#define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */
811#define I40E_GLHMC_PEMRBASE_MAX_INDEX 15
812#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0
813#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT)
814#define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */
815#define I40E_GLHMC_PEMRCNT_MAX_INDEX 15
816#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0
817#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT)
818#define I40E_GLHMC_PEMRMAX 0x000C2040
819#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0
820#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK (0x7FFFFF << I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT)
821#define I40E_GLHMC_PEMROBJSZ 0x000C203c
822#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0
823#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK (0xF << I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT)
824#define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */
825#define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15
826#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0
827#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT)
828#define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */
829#define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15
830#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0
831#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT)
832#define I40E_GLHMC_PEPBLMAX 0x000C206c
833#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0
834#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT)
835#define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */
836#define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15
837#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0
838#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT)
839#define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */
840#define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15
841#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0
842#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT)
843#define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */
844#define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15
845#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
846#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
847#define I40E_GLHMC_PEQ1FLCNT(_i) (0x000C5500 + ((_i) * 4)) /* _i=0...15 */
848#define I40E_GLHMC_PEQ1FLCNT_MAX_INDEX 15
849#define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0
850#define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT)
851#define I40E_GLHMC_PEQ1FLMAX 0x000C2058
852#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0
853#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
854#define I40E_GLHMC_PEQ1MAX 0x000C2054
855#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0
856#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
857#define I40E_GLHMC_PEQ1OBJSZ 0x000C2050
858#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0
859#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK (0xF << I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT)
860#define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */
861#define I40E_GLHMC_PEQPBASE_MAX_INDEX 15
862#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0
863#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT)
864#define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */
865#define I40E_GLHMC_PEQPCNT_MAX_INDEX 15
866#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0
867#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT)
868#define I40E_GLHMC_PEQPOBJSZ 0x000C201c
869#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0
870#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK (0xF << I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT)
871#define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */
872#define I40E_GLHMC_PESRQBASE_MAX_INDEX 15
873#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0
874#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT)
875#define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */
876#define I40E_GLHMC_PESRQCNT_MAX_INDEX 15
877#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0
878#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT)
879#define I40E_GLHMC_PESRQMAX 0x000C2028
880#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0
881#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK (0xFFFF << I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT)
882#define I40E_GLHMC_PESRQOBJSZ 0x000C2024
883#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0
884#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK (0xF << I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT)
885#define I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT 4
886#define I40E_GLHMC_PESRQOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT)
887#define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */
888#define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15
889#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0
890#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT)
891#define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */
892#define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15
893#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0
894#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT)
895#define I40E_GLHMC_PETIMERMAX 0x000C2084
896#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0
897#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT)
898#define I40E_GLHMC_PETIMEROBJSZ 0x000C2080
899#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0
900#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK (0xF << I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT)
901#define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */
902#define I40E_GLHMC_PEXFBASE_MAX_INDEX 15
903#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0
904#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT)
905#define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */
906#define I40E_GLHMC_PEXFCNT_MAX_INDEX 15
907#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0
908#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT)
909#define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */
910#define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15
911#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
912#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT)
913#define I40E_GLHMC_PEXFFLCNT(_i) (0x000C5100 + ((_i) * 4)) /* _i=0...15 */
914#define I40E_GLHMC_PEXFFLCNT_MAX_INDEX 15
915#define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT 0
916#define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT)
917#define I40E_GLHMC_PEXFFLMAX 0x000C204c
918#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0
919#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK (0x1FFFFFF << I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
920#define I40E_GLHMC_PEXFMAX 0x000C2048
921#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
922#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
923#define I40E_GLHMC_PEXFOBJSZ 0x000C2044
924#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0
925#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK (0xF << I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT)
926#define I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT 4
927#define I40E_GLHMC_PEXFOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT)
928#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */
929#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15 720#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15
930#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0 721#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0
931#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK (0xF << I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT) 722#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)
932#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ 723#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
933#define I40E_GLHMC_SDPART_MAX_INDEX 15 724#define I40E_GLHMC_SDPART_MAX_INDEX 15
934#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0 725#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0
935#define I40E_GLHMC_SDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_SDPART_PMSDBASE_SHIFT) 726#define I40E_GLHMC_SDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT)
936#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16 727#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16
937#define I40E_GLHMC_SDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_SDPART_PMSDSIZE_SHIFT) 728#define I40E_GLHMC_SDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)
938#define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) 729#define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */
939#define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
940#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
941#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
942#define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */
943#define I40E_GLHMC_VFCEQPART_MAX_INDEX 31
944#define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0
945#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT)
946#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16
947#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT)
948#define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */
949#define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31
950#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0
951#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT)
952#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16
953#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT)
954#define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */
955#define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31
956#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0
957#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT)
958#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16
959#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT)
960#define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */
961#define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31
962#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0
963#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT)
964#define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */
965#define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31
966#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0
967#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT)
968#define I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT 29
969#define I40E_GLHMC_VFFSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT)
970#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */
971#define I40E_GLHMC_VFPDINV_MAX_INDEX 31
972#define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0
973#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK (0xFFF << I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT)
974#define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16
975#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK (0x1FF << I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT)
976#define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */
977#define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31
978#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0
979#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT)
980#define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */
981#define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31
982#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0
983#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT)
984#define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */
985#define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31
986#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0
987#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT)
988#define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */
989#define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31
990#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0
991#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT)
992#define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */
993#define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31
994#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0
995#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT)
996#define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */
997#define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31
998#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0
999#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT)
1000#define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */
1001#define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31
1002#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0
1003#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT)
1004#define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */
1005#define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31
1006#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0
1007#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT)
1008#define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */
1009#define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31
1010#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0
1011#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT)
1012#define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */
1013#define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31
1014#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0
1015#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT)
1016#define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */
1017#define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31
1018#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0
1019#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT)
1020#define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */
1021#define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31
1022#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0
1023#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT)
1024#define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */
1025#define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
1026#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
1027#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
1028#define I40E_GLHMC_VFPEQ1FLCNT(_i) (0x000Cd500 + ((_i) * 4)) /* _i=0...31 */
1029#define I40E_GLHMC_VFPEQ1FLCNT_MAX_INDEX 31
1030#define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0
1031#define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT)
1032#define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */
1033#define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31
1034#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0
1035#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT)
1036#define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */
1037#define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31
1038#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0
1039#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT)
1040#define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */
1041#define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31
1042#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0
1043#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT)
1044#define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */
1045#define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31
1046#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0
1047#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT)
1048#define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */
1049#define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31
1050#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0
1051#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT)
1052#define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */
1053#define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31
1054#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0
1055#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT)
1056#define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */
1057#define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31
1058#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0
1059#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT)
1060#define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */
1061#define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31
1062#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0
1063#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT)
1064#define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */
1065#define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31
1066#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
1067#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT)
1068#define I40E_GLHMC_VFPEXFFLCNT(_i) (0x000Cd100 + ((_i) * 4)) /* _i=0...31 */
1069#define I40E_GLHMC_VFPEXFFLCNT_MAX_INDEX 31
1070#define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT 0
1071#define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT)
1072#define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */
1073#define I40E_GLHMC_VFSDPART_MAX_INDEX 31
1074#define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0
1075#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT)
1076#define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16
1077#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT)
1078#define I40E_PFHMC_ERRORDATA 0x000C0500
1079#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0 730#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0
1080#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK (0x3FFFFFFF << I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT) 731#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)
1081#define I40E_PFHMC_ERRORINFO 0x000C0400 732#define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */
1082#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0 733#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0
1083#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK (0x1F << I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT) 734#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)
1084#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7 735#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7
1085#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK (0x1 << I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT) 736#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT)
1086#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8 737#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8
1087#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK (0xF << I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT) 738#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT)
1088#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16 739#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16
1089#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK (0x1F << I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT) 740#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)
1090#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31 741#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31
1091#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK (0x1 << I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT) 742#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)
1092#define I40E_PFHMC_PDINV 0x000C0300 743#define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
1093#define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 744#define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
1094#define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) 745#define I40E_PFHMC_PDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
1095#define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 746#define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16
1096#define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT) 747#define I40E_PFHMC_PDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
1097#define I40E_PFHMC_SDCMD 0x000C0000 748#define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */
1098#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0 749#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0
1099#define I40E_PFHMC_SDCMD_PMSDIDX_MASK (0xFFF << I40E_PFHMC_SDCMD_PMSDIDX_SHIFT) 750#define I40E_PFHMC_SDCMD_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)
1100#define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 751#define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
1101#define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) 752#define I40E_PFHMC_SDCMD_PMSDWR_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
1102#define I40E_PFHMC_SDDATAHIGH 0x000C0200 753#define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */
1103#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0 754#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0
1104#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK (0xFFFFFFFF << I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT) 755#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)
1105#define I40E_PFHMC_SDDATALOW 0x000C0100 756#define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */
1106#define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 757#define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0
1107#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT) 758#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)
1108#define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 759#define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1
1109#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) 760#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT)
1110#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 761#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2
1111#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK (0x3FF << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) 762#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)
1112#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12 763#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12
1113#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK (0xFFFFF << I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT) 764#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)
1114#define I40E_GL_UFUSE 0x00094008 765#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */
766#define I40E_GL_GP_FUSE_MAX_INDEX 28
767#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0
768#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)
769#define I40E_GL_UFUSE 0x00094008 /* Reset: POR */
1115#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1 770#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1
1116#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK (0x1 << I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT) 771#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)
1117#define I40E_GL_UFUSE_NIC_ID_SHIFT 2 772#define I40E_GL_UFUSE_NIC_ID_SHIFT 2
1118#define I40E_GL_UFUSE_NIC_ID_MASK (0x1 << I40E_GL_UFUSE_NIC_ID_SHIFT) 773#define I40E_GL_UFUSE_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_NIC_ID_SHIFT)
1119#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10 774#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10
1120#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT) 775#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)
1121#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11 776#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11
1122#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT) 777#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)
1123#define I40E_EMPINT_GPIO_ENA 0x00088188 778#define I40E_EMPINT_GPIO_ENA 0x00088188 /* Reset: POR */
1124#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 779#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
1125#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT) 780#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)
1126#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 781#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
1127#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT) 782#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT)
1128#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 783#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
1129#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT) 784#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT)
1130#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 785#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
1131#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT) 786#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT)
1132#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 787#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
1133#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT) 788#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT)
1134#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 789#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
1135#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT) 790#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT)
1136#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 791#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
1137#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT) 792#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT)
1138#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 793#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
1139#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT) 794#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT)
1140#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 795#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
1141#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT) 796#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT)
1142#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 797#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
1143#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT) 798#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT)
1144#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 799#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
1145#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT) 800#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT)
1146#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 801#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
1147#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT) 802#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT)
1148#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 803#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
1149#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT) 804#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT)
1150#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 805#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
1151#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT) 806#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT)
1152#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 807#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
1153#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT) 808#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT)
1154#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 809#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
1155#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT) 810#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT)
1156#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 811#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
1157#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT) 812#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT)
1158#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 813#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
1159#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT) 814#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT)
1160#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 815#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
1161#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT) 816#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT)
1162#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 817#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
1163#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT) 818#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT)
1164#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 819#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
1165#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT) 820#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT)
1166#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 821#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
1167#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT) 822#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT)
1168#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 823#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
1169#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT) 824#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT)
1170#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 825#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
1171#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT) 826#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT)
1172#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 827#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
1173#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT) 828#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT)
1174#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 829#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
1175#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT) 830#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT)
1176#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 831#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
1177#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT) 832#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT)
1178#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 833#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
1179#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT) 834#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT)
1180#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 835#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
1181#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT) 836#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)
1182#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 837#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
1183#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT) 838#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)
1184#define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 839#define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */
1185#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0 840#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0
1186#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT) 841#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)
1187#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 842#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4
1188#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK (0x1 << I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 843#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
1189#define I40E_PFINT_AEQCTL 0x00038700 844#define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */
1190#define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 845#define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0
1191#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT) 846#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)
1192#define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 847#define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11
1193#define I40E_PFINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_AEQCTL_ITR_INDX_SHIFT) 848#define I40E_PFINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT)
1194#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13 849#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13
1195#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT) 850#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT)
1196#define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 851#define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30
1197#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 852#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
1198#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31 853#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31
1199#define I40E_PFINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_AEQCTL_INTEVENT_SHIFT) 854#define I40E_PFINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT)
1200#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ 855#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
1201#define I40E_PFINT_CEQCTL_MAX_INDEX 511 856#define I40E_PFINT_CEQCTL_MAX_INDEX 511
1202#define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 857#define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0
1203#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT) 858#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)
1204#define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 859#define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11
1205#define I40E_PFINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_CEQCTL_ITR_INDX_SHIFT) 860#define I40E_PFINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT)
1206#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13 861#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13
1207#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT) 862#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT)
1208#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 863#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1209#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT) 864#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT)
1210#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 865#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1211#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT) 866#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1212#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 867#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30
1213#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 868#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
1214#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31 869#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31
1215#define I40E_PFINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_CEQCTL_INTEVENT_SHIFT) 870#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
1216#define I40E_PFINT_DYN_CTL0 0x00038480 871#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */
1217#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 872#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0
1218#define I40E_PFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 873#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
1219#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 874#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1
1220#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 875#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT)
1221#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 876#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
1222#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 877#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1223#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 878#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3
1224#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 879#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)
1225#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5 880#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5
1226#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT) 881#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT)
1227#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 882#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1228#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 883#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1229#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 884#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
1230#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 885#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1231#define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 886#define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
1232#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 887#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1233#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ 888#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1234#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511 889#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511
1235#define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 890#define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0
1236#define I40E_PFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 891#define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
1237#define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 892#define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1
1238#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 893#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT)
1239#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 894#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
1240#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 895#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1241#define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 896#define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3
1242#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 897#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)
1243#define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 898#define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5
1244#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT) 899#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)
1245#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 900#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1246#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 901#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1247#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 902#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
1248#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 903#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1249#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 904#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
1250#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT) 905#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1251#define I40E_PFINT_GPIO_ENA 0x00088080 906#define I40E_PFINT_GPIO_ENA 0x00088080 /* Reset: CORER */
1252#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 907#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
1253#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT) 908#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)
1254#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 909#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
1255#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT) 910#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT)
1256#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 911#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
1257#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT) 912#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT)
1258#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 913#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
1259#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT) 914#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT)
1260#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 915#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
1261#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT) 916#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT)
1262#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 917#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
1263#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT) 918#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT)
1264#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 919#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
1265#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT) 920#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT)
1266#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 921#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
1267#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT) 922#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT)
1268#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 923#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
1269#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT) 924#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT)
1270#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 925#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
1271#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT) 926#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT)
1272#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 927#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
1273#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT) 928#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT)
1274#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 929#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
1275#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT) 930#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT)
1276#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 931#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
1277#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT) 932#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT)
1278#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 933#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
1279#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT) 934#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT)
1280#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 935#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
1281#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT) 936#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT)
1282#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 937#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
1283#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT) 938#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT)
1284#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 939#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
1285#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT) 940#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT)
1286#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 941#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
1287#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT) 942#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT)
1288#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 943#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
1289#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT) 944#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT)
1290#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 945#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
1291#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT) 946#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT)
1292#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 947#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
1293#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT) 948#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT)
1294#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 949#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
1295#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT) 950#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT)
1296#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 951#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
1297#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT) 952#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT)
1298#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 953#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
1299#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT) 954#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT)
1300#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 955#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
1301#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT) 956#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT)
1302#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 957#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
1303#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT) 958#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT)
1304#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 959#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
1305#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT) 960#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT)
1306#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 961#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
1307#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT) 962#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT)
1308#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 963#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
1309#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT) 964#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)
1310#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 965#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
1311#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT) 966#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)
1312#define I40E_PFINT_ICR0 0x00038780 967#define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */
1313#define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 968#define I40E_PFINT_ICR0_INTEVENT_SHIFT 0
1314#define I40E_PFINT_ICR0_INTEVENT_MASK (0x1 << I40E_PFINT_ICR0_INTEVENT_SHIFT) 969#define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT)
1315#define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 970#define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1
1316#define I40E_PFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_0_SHIFT) 971#define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT)
1317#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2 972#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2
1318#define I40E_PFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_1_SHIFT) 973#define I40E_PFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_1_SHIFT)
1319#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3 974#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3
1320#define I40E_PFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_2_SHIFT) 975#define I40E_PFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_2_SHIFT)
1321#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4 976#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4
1322#define I40E_PFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_3_SHIFT) 977#define I40E_PFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_3_SHIFT)
1323#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5 978#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5
1324#define I40E_PFINT_ICR0_QUEUE_4_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_4_SHIFT) 979#define I40E_PFINT_ICR0_QUEUE_4_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_4_SHIFT)
1325#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6 980#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6
1326#define I40E_PFINT_ICR0_QUEUE_5_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_5_SHIFT) 981#define I40E_PFINT_ICR0_QUEUE_5_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_5_SHIFT)
1327#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7 982#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7
1328#define I40E_PFINT_ICR0_QUEUE_6_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_6_SHIFT) 983#define I40E_PFINT_ICR0_QUEUE_6_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_6_SHIFT)
1329#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8 984#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8
1330#define I40E_PFINT_ICR0_QUEUE_7_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_7_SHIFT) 985#define I40E_PFINT_ICR0_QUEUE_7_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_7_SHIFT)
1331#define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 986#define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16
1332#define I40E_PFINT_ICR0_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ECC_ERR_SHIFT) 987#define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT)
1333#define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 988#define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19
1334#define I40E_PFINT_ICR0_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_MAL_DETECT_SHIFT) 989#define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT)
1335#define I40E_PFINT_ICR0_GRST_SHIFT 20 990#define I40E_PFINT_ICR0_GRST_SHIFT 20
1336#define I40E_PFINT_ICR0_GRST_MASK (0x1 << I40E_PFINT_ICR0_GRST_SHIFT) 991#define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT)
1337#define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 992#define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21
1338#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 993#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)
1339#define I40E_PFINT_ICR0_GPIO_SHIFT 22 994#define I40E_PFINT_ICR0_GPIO_SHIFT 22
1340#define I40E_PFINT_ICR0_GPIO_MASK (0x1 << I40E_PFINT_ICR0_GPIO_SHIFT) 995#define I40E_PFINT_ICR0_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GPIO_SHIFT)
1341#define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 996#define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23
1342#define I40E_PFINT_ICR0_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_TIMESYNC_SHIFT) 997#define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT)
998#define I40E_PFINT_ICR0_STORM_DETECT_SHIFT 24
999#define I40E_PFINT_ICR0_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_STORM_DETECT_SHIFT)
1343#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 1000#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1344#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 1001#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1345#define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 1002#define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26
1346#define I40E_PFINT_ICR0_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_HMC_ERR_SHIFT) 1003#define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT)
1347#define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 1004#define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28
1348#define I40E_PFINT_ICR0_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_PE_CRITERR_SHIFT) 1005#define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT)
1349#define I40E_PFINT_ICR0_VFLR_SHIFT 29 1006#define I40E_PFINT_ICR0_VFLR_SHIFT 29
1350#define I40E_PFINT_ICR0_VFLR_MASK (0x1 << I40E_PFINT_ICR0_VFLR_SHIFT) 1007#define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT)
1351#define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 1008#define I40E_PFINT_ICR0_ADMINQ_SHIFT 30
1352#define I40E_PFINT_ICR0_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ADMINQ_SHIFT) 1009#define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT)
1353#define I40E_PFINT_ICR0_SWINT_SHIFT 31 1010#define I40E_PFINT_ICR0_SWINT_SHIFT 31
1354#define I40E_PFINT_ICR0_SWINT_MASK (0x1 << I40E_PFINT_ICR0_SWINT_SHIFT) 1011#define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT)
1355#define I40E_PFINT_ICR0_ENA 0x00038800 1012#define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */
1356#define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 1013#define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16
1357#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) 1014#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)
1358#define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 1015#define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19
1359#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) 1016#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT)
1360#define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 1017#define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20
1361#define I40E_PFINT_ICR0_ENA_GRST_MASK (0x1 << I40E_PFINT_ICR0_ENA_GRST_SHIFT) 1018#define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT)
1362#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 1019#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21
1363#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) 1020#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT)
1364#define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 1021#define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22
1365#define I40E_PFINT_ICR0_ENA_GPIO_MASK (0x1 << I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 1022#define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT)
1366#define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 1023#define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23
1367#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 1024#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)
1025#define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT 24
1026#define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT)
1368#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 1027#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1369#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 1028#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1370#define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 1029#define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26
1371#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 1030#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)
1372#define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 1031#define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28
1373#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) 1032#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT)
1374#define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 1033#define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29
1375#define I40E_PFINT_ICR0_ENA_VFLR_MASK (0x1 << I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 1034#define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT)
1376#define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 1035#define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30
1377#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 1036#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
1378#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31 1037#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31
1379#define I40E_PFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_PFINT_ICR0_ENA_RSVD_SHIFT) 1038#define I40E_PFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT)
1380#define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ 1039#define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */
1381#define I40E_PFINT_ITR0_MAX_INDEX 2 1040#define I40E_PFINT_ITR0_MAX_INDEX 2
1382#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0 1041#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0
1383#define I40E_PFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_PFINT_ITR0_INTERVAL_SHIFT) 1042#define I40E_PFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT)
1384#define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) 1043#define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */
1385#define I40E_PFINT_ITRN_MAX_INDEX 2 1044#define I40E_PFINT_ITRN_MAX_INDEX 2
1386#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0 1045#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0
1387#define I40E_PFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_PFINT_ITRN_INTERVAL_SHIFT) 1046#define I40E_PFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT)
1388#define I40E_PFINT_LNKLST0 0x00038500 1047#define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */
1389#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 1048#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1390#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) 1049#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1391#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 1050#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1392#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 1051#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1393#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ 1052#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1394#define I40E_PFINT_LNKLSTN_MAX_INDEX 511 1053#define I40E_PFINT_LNKLSTN_MAX_INDEX 511
1395#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 1054#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1396#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 1055#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1397#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 1056#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1398#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 1057#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1399#define I40E_PFINT_RATE0 0x00038580 1058#define I40E_PFINT_RATE0 0x00038580 /* Reset: PFR */
1400#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0 1059#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0
1401#define I40E_PFINT_RATE0_INTERVAL_MASK (0x3F << I40E_PFINT_RATE0_INTERVAL_SHIFT) 1060#define I40E_PFINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT)
1402#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6 1061#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6
1403#define I40E_PFINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATE0_INTRL_ENA_SHIFT) 1062#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT)
1404#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ 1063#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1405#define I40E_PFINT_RATEN_MAX_INDEX 511 1064#define I40E_PFINT_RATEN_MAX_INDEX 511
1406#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0 1065#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0
1407#define I40E_PFINT_RATEN_INTERVAL_MASK (0x3F << I40E_PFINT_RATEN_INTERVAL_SHIFT) 1066#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
1408#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 1067#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
1409#define I40E_PFINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATEN_INTRL_ENA_SHIFT) 1068#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
1410#define I40E_PFINT_STAT_CTL0 0x00038400 1069#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: PFR */
1411#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1070#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1412#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1071#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1413#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ 1072#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1414#define I40E_QINT_RQCTL_MAX_INDEX 1535 1073#define I40E_QINT_RQCTL_MAX_INDEX 1535
1415#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 1074#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0
1416#define I40E_QINT_RQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 1075#define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
1417#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 1076#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11
1418#define I40E_QINT_RQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_RQCTL_ITR_INDX_SHIFT) 1077#define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT)
1419#define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 1078#define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13
1420#define I40E_QINT_RQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) 1079#define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT)
1421#define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 1080#define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16
1422#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 1081#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)
1423#define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 1082#define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27
1424#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) 1083#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)
1425#define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 1084#define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30
1426#define I40E_QINT_RQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 1085#define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
1427#define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 1086#define I40E_QINT_RQCTL_INTEVENT_SHIFT 31
1428#define I40E_QINT_RQCTL_INTEVENT_MASK (0x1 << I40E_QINT_RQCTL_INTEVENT_SHIFT) 1087#define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT)
1429#define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ 1088#define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1430#define I40E_QINT_TQCTL_MAX_INDEX 1535 1089#define I40E_QINT_TQCTL_MAX_INDEX 1535
1431#define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 1090#define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0
1432#define I40E_QINT_TQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 1091#define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
1433#define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 1092#define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11
1434#define I40E_QINT_TQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_TQCTL_ITR_INDX_SHIFT) 1093#define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT)
1435#define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 1094#define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13
1436#define I40E_QINT_TQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) 1095#define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT)
1437#define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 1096#define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16
1438#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 1097#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)
1439#define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 1098#define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27
1440#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) 1099#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)
1441#define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 1100#define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30
1442#define I40E_QINT_TQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 1101#define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
1443#define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 1102#define I40E_QINT_TQCTL_INTEVENT_SHIFT 31
1444#define I40E_QINT_TQCTL_INTEVENT_MASK (0x1 << I40E_QINT_TQCTL_INTEVENT_SHIFT) 1103#define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT)
1445#define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ 1104#define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1446#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127 1105#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127
1447#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0 1106#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0
1448#define I40E_VFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_SHIFT) 1107#define I40E_VFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT)
1449#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1 1108#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1
1450#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT) 1109#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT)
1451#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 1110#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
1452#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 1111#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1453#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3 1112#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3
1454#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) 1113#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)
1455#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5 1114#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5
1456#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT) 1115#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)
1457#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 1116#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1458#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 1117#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1459#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 1118#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
1460#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 1119#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1461#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 1120#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
1462#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT) 1121#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1463#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ 1122#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1464#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511 1123#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511
1465#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0 1124#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0
1466#define I40E_VFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_SHIFT) 1125#define I40E_VFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT)
1467#define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 1126#define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1
1468#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 1127#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)
1469#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 1128#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
1470#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 1129#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1471#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3 1130#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3
1472#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) 1131#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT)
1473#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5 1132#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5
1474#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT) 1133#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT)
1475#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 1134#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1476#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 1135#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1477#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 1136#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
1478#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 1137#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1479#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 1138#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
1480#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT) 1139#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1481#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ 1140#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1482#define I40E_VFINT_ICR0_MAX_INDEX 127 1141#define I40E_VFINT_ICR0_MAX_INDEX 127
1483#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0 1142#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0
1484#define I40E_VFINT_ICR0_INTEVENT_MASK (0x1 << I40E_VFINT_ICR0_INTEVENT_SHIFT) 1143#define I40E_VFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT)
1485#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1 1144#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1
1486#define I40E_VFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_0_SHIFT) 1145#define I40E_VFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_0_SHIFT)
1487#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2 1146#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2
1488#define I40E_VFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_1_SHIFT) 1147#define I40E_VFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_1_SHIFT)
1489#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3 1148#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3
1490#define I40E_VFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_2_SHIFT) 1149#define I40E_VFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_2_SHIFT)
1491#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4 1150#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4
1492#define I40E_VFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_3_SHIFT) 1151#define I40E_VFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_3_SHIFT)
1493#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 1152#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1494#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 1153#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1495#define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 1154#define I40E_VFINT_ICR0_ADMINQ_SHIFT 30
1496#define I40E_VFINT_ICR0_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ADMINQ_SHIFT) 1155#define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT)
1497#define I40E_VFINT_ICR0_SWINT_SHIFT 31 1156#define I40E_VFINT_ICR0_SWINT_SHIFT 31
1498#define I40E_VFINT_ICR0_SWINT_MASK (0x1 << I40E_VFINT_ICR0_SWINT_SHIFT) 1157#define I40E_VFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT)
1499#define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ 1158#define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1500#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127 1159#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127
1501#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 1160#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1502#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 1161#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1503#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30 1162#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30
1504#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT) 1163#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)
1505#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31 1164#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31
1506#define I40E_VFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA_RSVD_SHIFT) 1165#define I40E_VFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT)
1507#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ 1166#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */
1508#define I40E_VFINT_ITR0_MAX_INDEX 2 1167#define I40E_VFINT_ITR0_MAX_INDEX 2
1509#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0 1168#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0
1510#define I40E_VFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR0_INTERVAL_SHIFT) 1169#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT)
1511#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) 1170#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */
1512#define I40E_VFINT_ITRN_MAX_INDEX 2 1171#define I40E_VFINT_ITRN_MAX_INDEX 2
1513#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 1172#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
1514#define I40E_VFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN_INTERVAL_SHIFT) 1173#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
1515#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ 1174#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1516#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 1175#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127
1517#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1176#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1518#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1177#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1519#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ 1178#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1520#define I40E_VPINT_AEQCTL_MAX_INDEX 127 1179#define I40E_VPINT_AEQCTL_MAX_INDEX 127
1521#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 1180#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0
1522#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) 1181#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)
1523#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 1182#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11
1524#define I40E_VPINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_AEQCTL_ITR_INDX_SHIFT) 1183#define I40E_VPINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT)
1525#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13 1184#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13
1526#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT) 1185#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT)
1527#define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 1186#define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30
1528#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 1187#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
1529#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31 1188#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31
1530#define I40E_VPINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_AEQCTL_INTEVENT_SHIFT) 1189#define I40E_VPINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT)
1531#define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ 1190#define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */
1532#define I40E_VPINT_CEQCTL_MAX_INDEX 511 1191#define I40E_VPINT_CEQCTL_MAX_INDEX 511
1533#define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 1192#define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0
1534#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT) 1193#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)
1535#define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 1194#define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11
1536#define I40E_VPINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_CEQCTL_ITR_INDX_SHIFT) 1195#define I40E_VPINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT)
1537#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13 1196#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13
1538#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT) 1197#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT)
1539#define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 1198#define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1540#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 1199#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)
1541#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 1200#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1542#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 1201#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1543#define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 1202#define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30
1544#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 1203#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
1545#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31 1204#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31
1546#define I40E_VPINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_CEQCTL_INTEVENT_SHIFT) 1205#define I40E_VPINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT)
1547#define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ 1206#define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1548#define I40E_VPINT_LNKLST0_MAX_INDEX 127 1207#define I40E_VPINT_LNKLST0_MAX_INDEX 127
1549#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 1208#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1550#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 1209#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1551#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 1210#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1552#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 1211#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1553#define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ 1212#define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1554#define I40E_VPINT_LNKLSTN_MAX_INDEX 511 1213#define I40E_VPINT_LNKLSTN_MAX_INDEX 511
1555#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 1214#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1556#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 1215#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1557#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 1216#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1558#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 1217#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1559#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ 1218#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1560#define I40E_VPINT_RATE0_MAX_INDEX 127 1219#define I40E_VPINT_RATE0_MAX_INDEX 127
1561#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0 1220#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0
1562#define I40E_VPINT_RATE0_INTERVAL_MASK (0x3F << I40E_VPINT_RATE0_INTERVAL_SHIFT) 1221#define I40E_VPINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT)
1563#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6 1222#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6
1564#define I40E_VPINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATE0_INTRL_ENA_SHIFT) 1223#define I40E_VPINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT)
1565#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ 1224#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1566#define I40E_VPINT_RATEN_MAX_INDEX 511 1225#define I40E_VPINT_RATEN_MAX_INDEX 511
1567#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0 1226#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0
1568#define I40E_VPINT_RATEN_INTERVAL_MASK (0x3F << I40E_VPINT_RATEN_INTERVAL_SHIFT) 1227#define I40E_VPINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT)
1569#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6 1228#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6
1570#define I40E_VPINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATEN_INTRL_ENA_SHIFT) 1229#define I40E_VPINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT)
1571#define I40E_GL_RDPU_CNTRL 0x00051060 1230#define I40E_GL_RDPU_CNTRL 0x00051060 /* Reset: CORER */
1572#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0 1231#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0
1573#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK (0x1 << I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT) 1232#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)
1574#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1 1233#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1
1575#define I40E_GL_RDPU_CNTRL_ECO_MASK (0x7FFFFFFF << I40E_GL_RDPU_CNTRL_ECO_SHIFT) 1234#define I40E_GL_RDPU_CNTRL_ECO_MASK I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT)
1576#define I40E_GLLAN_RCTL_0 0x0012A500 1235#define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */
1577#define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 1236#define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0
1578#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK (0x1 << I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 1237#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
1579#define I40E_GLLAN_TSOMSK_F 0x000442D8 1238#define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */
1580#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0 1239#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0
1581#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK (0xFFF << I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT) 1240#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)
1582#define I40E_GLLAN_TSOMSK_L 0x000442E0 1241#define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */
1583#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0 1242#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0
1584#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK (0xFFF << I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT) 1243#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)
1585#define I40E_GLLAN_TSOMSK_M 0x000442DC 1244#define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */
1586#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0 1245#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0
1587#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK (0xFFF << I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT) 1246#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)
1588#define I40E_GLLAN_TXPRE_QDIS(_i) (0x000E6500 + ((_i) * 4)) /* i=0..11 */ 1247#define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */
1248#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11
1589#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 1249#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0
1590#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK (0x7FF << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 1250#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
1251#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16
1252#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)
1591#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 1253#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30
1592#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 1254#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
1593#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 1255#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
1594#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) 1256#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
1595 1257#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */
1596#define I40E_PFLAN_QALLOC 0x001C0400
1597#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 1258#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
1598#define I40E_PFLAN_QALLOC_FIRSTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 1259#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
1599#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 1260#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
1600#define I40E_PFLAN_QALLOC_LASTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_LASTQ_SHIFT) 1261#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
1601#define I40E_PFLAN_QALLOC_VALID_SHIFT 31 1262#define I40E_PFLAN_QALLOC_VALID_SHIFT 31
1602#define I40E_PFLAN_QALLOC_VALID_MASK (0x1 << I40E_PFLAN_QALLOC_VALID_SHIFT) 1263#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)
1603#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ 1264#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1604#define I40E_QRX_ENA_MAX_INDEX 1535 1265#define I40E_QRX_ENA_MAX_INDEX 1535
1605#define I40E_QRX_ENA_QENA_REQ_SHIFT 0 1266#define I40E_QRX_ENA_QENA_REQ_SHIFT 0
1606#define I40E_QRX_ENA_QENA_REQ_MASK (0x1 << I40E_QRX_ENA_QENA_REQ_SHIFT) 1267#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)
1607#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 1268#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1
1608#define I40E_QRX_ENA_FAST_QDIS_MASK (0x1 << I40E_QRX_ENA_FAST_QDIS_SHIFT) 1269#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)
1609#define I40E_QRX_ENA_QENA_STAT_SHIFT 2 1270#define I40E_QRX_ENA_QENA_STAT_SHIFT 2
1610#define I40E_QRX_ENA_QENA_STAT_MASK (0x1 << I40E_QRX_ENA_QENA_STAT_SHIFT) 1271#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)
1611#define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ 1272#define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1612#define I40E_QRX_TAIL_MAX_INDEX 1535 1273#define I40E_QRX_TAIL_MAX_INDEX 1535
1613#define I40E_QRX_TAIL_TAIL_SHIFT 0 1274#define I40E_QRX_TAIL_TAIL_SHIFT 0
1614#define I40E_QRX_TAIL_TAIL_MASK (0x1FFF << I40E_QRX_TAIL_TAIL_SHIFT) 1275#define I40E_QRX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT)
1615#define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ 1276#define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1616#define I40E_QTX_CTL_MAX_INDEX 1535 1277#define I40E_QTX_CTL_MAX_INDEX 1535
1617#define I40E_QTX_CTL_PFVF_Q_SHIFT 0 1278#define I40E_QTX_CTL_PFVF_Q_SHIFT 0
1618#define I40E_QTX_CTL_PFVF_Q_MASK (0x3 << I40E_QTX_CTL_PFVF_Q_SHIFT) 1279#define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)
1619#define I40E_QTX_CTL_PF_INDX_SHIFT 2 1280#define I40E_QTX_CTL_PF_INDX_SHIFT 2
1620#define I40E_QTX_CTL_PF_INDX_MASK (0xF << I40E_QTX_CTL_PF_INDX_SHIFT) 1281#define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT)
1621#define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 1282#define I40E_QTX_CTL_VFVM_INDX_SHIFT 7
1622#define I40E_QTX_CTL_VFVM_INDX_MASK (0x1FF << I40E_QTX_CTL_VFVM_INDX_SHIFT) 1283#define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)
1623#define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ 1284#define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1624#define I40E_QTX_ENA_MAX_INDEX 1535 1285#define I40E_QTX_ENA_MAX_INDEX 1535
1625#define I40E_QTX_ENA_QENA_REQ_SHIFT 0 1286#define I40E_QTX_ENA_QENA_REQ_SHIFT 0
1626#define I40E_QTX_ENA_QENA_REQ_MASK (0x1 << I40E_QTX_ENA_QENA_REQ_SHIFT) 1287#define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT)
1627#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1 1288#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1
1628#define I40E_QTX_ENA_FAST_QDIS_MASK (0x1 << I40E_QTX_ENA_FAST_QDIS_SHIFT) 1289#define I40E_QTX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT)
1629#define I40E_QTX_ENA_QENA_STAT_SHIFT 2 1290#define I40E_QTX_ENA_QENA_STAT_SHIFT 2
1630#define I40E_QTX_ENA_QENA_STAT_MASK (0x1 << I40E_QTX_ENA_QENA_STAT_SHIFT) 1291#define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT)
1631#define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ 1292#define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1632#define I40E_QTX_HEAD_MAX_INDEX 1535 1293#define I40E_QTX_HEAD_MAX_INDEX 1535
1633#define I40E_QTX_HEAD_HEAD_SHIFT 0 1294#define I40E_QTX_HEAD_HEAD_SHIFT 0
1634#define I40E_QTX_HEAD_HEAD_MASK (0x1FFF << I40E_QTX_HEAD_HEAD_SHIFT) 1295#define I40E_QTX_HEAD_HEAD_MASK I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT)
1635#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16 1296#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16
1636#define I40E_QTX_HEAD_RS_PENDING_MASK (0x1 << I40E_QTX_HEAD_RS_PENDING_SHIFT) 1297#define I40E_QTX_HEAD_RS_PENDING_MASK I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT)
1637#define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ 1298#define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1638#define I40E_QTX_TAIL_MAX_INDEX 1535 1299#define I40E_QTX_TAIL_MAX_INDEX 1535
1639#define I40E_QTX_TAIL_TAIL_SHIFT 0 1300#define I40E_QTX_TAIL_TAIL_SHIFT 0
1640#define I40E_QTX_TAIL_TAIL_MASK (0x1FFF << I40E_QTX_TAIL_TAIL_SHIFT) 1301#define I40E_QTX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT)
1641#define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ 1302#define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1642#define I40E_VPLAN_MAPENA_MAX_INDEX 127 1303#define I40E_VPLAN_MAPENA_MAX_INDEX 127
1643#define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 1304#define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0
1644#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK (0x1 << I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 1305#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
1645#define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ 1306#define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */
1646#define I40E_VPLAN_QTABLE_MAX_INDEX 15 1307#define I40E_VPLAN_QTABLE_MAX_INDEX 15
1647#define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 1308#define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0
1648#define I40E_VPLAN_QTABLE_QINDEX_MASK (0x7FF << I40E_VPLAN_QTABLE_QINDEX_SHIFT) 1309#define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)
1649#define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ 1310#define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
1650#define I40E_VSILAN_QBASE_MAX_INDEX 383 1311#define I40E_VSILAN_QBASE_MAX_INDEX 383
1651#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0 1312#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0
1652#define I40E_VSILAN_QBASE_VSIBASE_MASK (0x7FF << I40E_VSILAN_QBASE_VSIBASE_SHIFT) 1313#define I40E_VSILAN_QBASE_VSIBASE_MASK I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT)
1653#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 1314#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
1654#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK (0x1 << I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 1315#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
1655#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) 1316#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */
1656#define I40E_VSILAN_QTABLE_MAX_INDEX 7 1317#define I40E_VSILAN_QTABLE_MAX_INDEX 7
1657#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0 1318#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0
1658#define I40E_VSILAN_QTABLE_QINDEX_0_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_0_SHIFT) 1319#define I40E_VSILAN_QTABLE_QINDEX_0_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
1659#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16 1320#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16
1660#define I40E_VSILAN_QTABLE_QINDEX_1_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) 1321#define I40E_VSILAN_QTABLE_QINDEX_1_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)
1661#define I40E_PRTGL_SAH 0x001E2140 1322#define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */
1662#define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 1323#define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
1663#define I40E_PRTGL_SAH_FC_SAH_MASK (0xFFFF << I40E_PRTGL_SAH_FC_SAH_SHIFT) 1324#define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
1664#define I40E_PRTGL_SAH_MFS_SHIFT 16 1325#define I40E_PRTGL_SAH_MFS_SHIFT 16
1665#define I40E_PRTGL_SAH_MFS_MASK (0xFFFF << I40E_PRTGL_SAH_MFS_SHIFT) 1326#define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT)
1666#define I40E_PRTGL_SAL 0x001E2120 1327#define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */
1667#define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 1328#define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
1668#define I40E_PRTGL_SAL_FC_SAL_MASK (0xFFFFFFFF << I40E_PRTGL_SAL_FC_SAL_SHIFT) 1329#define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
1669#define I40E_PRTMAC_HLCTLA 0x001E4760 1330#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 /* Reset: GLOBR */
1670#define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT 0
1671#define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT)
1672#define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT 1
1673#define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_MASK (0x1 << I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT)
1674#define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT 2
1675#define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT)
1676#define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT 4
1677#define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT)
1678#define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT 7
1679#define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT)
1680#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP 0x001E3130
1681#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT 0
1682#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT)
1683#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP 0x001E3290
1684#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT 0
1685#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT)
1686#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP 0x001E3310
1687#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT 0
1688#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT)
1689#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP 0x001E3100
1690#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT 0
1691#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT)
1692#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP 0x001E3280
1693#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT 0
1694#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT)
1695#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP 0x001E3300
1696#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT 0
1697#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT)
1698#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0
1699#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0 1331#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0
1700#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT) 1332#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)
1701#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 1333#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */
1702#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0 1334#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0
1703#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT) 1335#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
1704#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 1336#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */
1705#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0 1337#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0
1706#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT) 1338#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
1707#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 1339#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 /* Reset: GLOBR */
1708#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0 1340#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0
1709#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT) 1341#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)
1710#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 1342#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 /* Reset: GLOBR */
1711#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0 1343#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0
1712#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT) 1344#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)
1713#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 1345#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 /* Reset: GLOBR */
1714#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0 1346#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0
1715#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT) 1347#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)
1716#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 1348#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */
1717#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0 1349#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0
1718#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) 1350#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
1719#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 1351#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 /* Reset: GLOBR */
1720#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0 1352#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0
1721#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT) 1353#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)
1722#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 1354#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 /* Reset: GLOBR */
1723#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0 1355#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0
1724#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT) 1356#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)
1725#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE 0x001E3000 1357#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */
1726#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT 0
1727#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT)
1728#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0
1729#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0 1358#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0
1730#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) 1359#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
1731#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) 1360#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1732#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8 1361#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
1733#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0 1362#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0
1734#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT) 1363#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)
1735#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) 1364#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1736#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 1365#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
1737#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0 1366#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0
1738#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) 1367#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
1739#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 1368#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 /* Reset: GLOBR */
1740#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0 1369#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0
1741#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT) 1370#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)
1742#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 1371#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 /* Reset: GLOBR */
1743#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0 1372#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0
1744#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT) 1373#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)
1745#define I40E_PRTMAC_HSECTL1 0x001E3560 1374#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 /* Reset: GLOBR */
1746#define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT 0
1747#define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT)
1748#define I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT 3
1749#define I40E_PRTMAC_HSECTL1_PAD_US_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT)
1750#define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT 4
1751#define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT)
1752#define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT 7
1753#define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT)
1754#define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT 30
1755#define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT)
1756#define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT 31
1757#define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT)
1758#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480
1759#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0 1375#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0
1760#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT) 1376#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)
1761#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2 1377#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2
1762#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT) 1378#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT)
1763#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4 1379#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4
1764#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT) 1380#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT)
1765#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6 1381#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6
1766#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT) 1382#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT)
1767#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8 1383#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8
1768#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT) 1384#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT)
1769#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10 1385#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10
1770#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT) 1386#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT)
1771#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12 1387#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12
1772#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT) 1388#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)
1773#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14 1389#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14
1774#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT) 1390#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)
1775#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 1391#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 /* Reset: GLOBR */
1776#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0 1392#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0
1777#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT) 1393#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)
1778#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2 1394#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2
1779#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT) 1395#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT)
1780#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4 1396#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4
1781#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT) 1397#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT)
1782#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6 1398#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6
1783#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT) 1399#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT)
1784#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8 1400#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8
1785#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT) 1401#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT)
1786#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10 1402#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10
1787#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT) 1403#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT)
1788#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12 1404#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12
1789#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT) 1405#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
1790#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14 1406#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
1791#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT) 1407#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
1792#define I40E_GL_MNG_FWSM 0x000B6134 1408#define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */
1793#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 1 1409#define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0
1794#define I40E_GL_MNG_FWSM_FW_MODES_MASK (0x7 << I40E_GL_MNG_FWSM_FW_MODES_SHIFT) 1410#define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)
1795#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 6 1411#define I40E_GL_MNG_FWSM 0x000B6134 /* Reset: POR */
1796#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK (0x1 << I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT) 1412#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0
1413#define I40E_GL_MNG_FWSM_FW_MODES_MASK I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
1414#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10
1415#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)
1797#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11 1416#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11
1798#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK (0xF << I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT) 1417#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)
1799#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15 1418#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15
1800#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK (0x1 << I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT) 1419#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)
1801#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16 1420#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16
1802#define I40E_GL_MNG_FWSM_RESET_CNT_MASK (0x7 << I40E_GL_MNG_FWSM_RESET_CNT_SHIFT) 1421#define I40E_GL_MNG_FWSM_RESET_CNT_MASK I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT)
1803#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19 1422#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19
1804#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK (0x3F << I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT) 1423#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)
1805#define I40E_GL_MNG_FWSM_RSVD_SHIFT 25
1806#define I40E_GL_MNG_FWSM_RSVD_MASK (0x1 << I40E_GL_MNG_FWSM_RSVD_SHIFT)
1807#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26 1424#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26
1808#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT) 1425#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)
1809#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27 1426#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27
1810#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT) 1427#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT)
1811#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28 1428#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28
1812#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT) 1429#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)
1813#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29 1430#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29
1814#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT) 1431#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)
1815#define I40E_GL_MNG_HWARB_CTRL 0x000B6130 1432#define I40E_GL_MNG_HWARB_CTRL 0x000B6130 /* Reset: POR */
1816#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0 1433#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0
1817#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK (0x1 << I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT) 1434#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)
1818#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ 1435#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */
1819#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31 1436#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31
1820#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0 1437#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0
1821#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK (0xFFFFFFFF << I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT) 1438#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)
1822#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 1439#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 /* Reset: POR */
1823#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0 1440#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0
1824#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK (0xFF << I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT) 1441#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)
1825#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ 1442#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1826#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7 1443#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7
1827#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0 1444#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0
1828#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK (0xFFFF << I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT) 1445#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)
1829#define I40E_PRT_MNG_MANC 0x00256A20 1446#define I40E_PRT_MNG_MANC 0x00256A20 /* Reset: POR */
1830#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0 1447#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0
1831#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT) 1448#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)
1832#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1 1449#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1
1833#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT) 1450#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT)
1834#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17 1451#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17
1835#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT) 1452#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT)
1836#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19 1453#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19
1837#define I40E_PRT_MNG_MANC_RCV_ALL_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_ALL_SHIFT) 1454#define I40E_PRT_MNG_MANC_RCV_ALL_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT)
1838#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25 1455#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25
1839#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT) 1456#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT)
1840#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26 1457#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26
1841#define I40E_PRT_MNG_MANC_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_NET_TYPE_SHIFT) 1458#define I40E_PRT_MNG_MANC_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT)
1842#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28 1459#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28
1843#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT) 1460#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)
1844#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29 1461#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29
1845#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT) 1462#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)
1846#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ 1463#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1847#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7 1464#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7
1848#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0 1465#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0
1849#define I40E_PRT_MNG_MAVTV_VID_MASK (0xFFF << I40E_PRT_MNG_MAVTV_VID_SHIFT) 1466#define I40E_PRT_MNG_MAVTV_VID_MASK I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT)
1850#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) 1467#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1851#define I40E_PRT_MNG_MDEF_MAX_INDEX 7 1468#define I40E_PRT_MNG_MDEF_MAX_INDEX 7
1852#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0 1469#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0
1853#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT) 1470#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)
1854#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4 1471#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4
1855#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT) 1472#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT)
1856#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5 1473#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5
1857#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK (0xFF << I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT) 1474#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT)
1858#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13 1475#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13
1859#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT) 1476#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT)
1860#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17 1477#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17
1861#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT) 1478#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT)
1862#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21 1479#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21
1863#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT) 1480#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT)
1864#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25 1481#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25
1865#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT) 1482#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT)
1866#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26 1483#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26
1867#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT) 1484#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT)
1868#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27 1485#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27
1869#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT) 1486#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT)
1870#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28 1487#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28
1871#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT) 1488#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT)
1872#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29 1489#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29
1873#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT) 1490#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT)
1874#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30 1491#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30
1875#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT) 1492#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)
1876#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31 1493#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31
1877#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT) 1494#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)
1878#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) 1495#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1879#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7 1496#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7
1880#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0 1497#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0
1881#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT) 1498#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)
1882#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4 1499#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4
1883#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT) 1500#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT)
1884#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8 1501#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8
1885#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK (0xFFFF << I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT) 1502#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT)
1886#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24 1503#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24
1887#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT) 1504#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT)
1888#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25 1505#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25
1889#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT) 1506#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT)
1890#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26 1507#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26
1891#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT) 1508#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT)
1892#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27 1509#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27
1893#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT) 1510#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT)
1894#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28 1511#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28
1895#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT) 1512#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT)
1896#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29 1513#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29
1897#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT) 1514#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT)
1898#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30 1515#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30
1899#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT) 1516#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)
1900#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31 1517#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31
1901#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT) 1518#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)
1902#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ 1519#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1903#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3 1520#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3
1904#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0 1521#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0
1905#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT) 1522#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
1906#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16 1523#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16
1907#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT) 1524#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
1908#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ 1525#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1909#define I40E_PRT_MNG_METF_MAX_INDEX 3 1526#define I40E_PRT_MNG_METF_MAX_INDEX 3
1910#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0 1527#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0
1911#define I40E_PRT_MNG_METF_ETYPE_MASK (0xFFFF << I40E_PRT_MNG_METF_ETYPE_SHIFT) 1528#define I40E_PRT_MNG_METF_ETYPE_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT)
1912#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30 1529#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30
1913#define I40E_PRT_MNG_METF_POLARITY_MASK (0x1 << I40E_PRT_MNG_METF_POLARITY_SHIFT) 1530#define I40E_PRT_MNG_METF_POLARITY_MASK I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT)
1914#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ 1531#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1915#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15 1532#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15
1916#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0 1533#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0
1917#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK (0xFFFF << I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT) 1534#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)
1918#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16 1535#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16
1919#define I40E_PRT_MNG_MFUTP_UDP_MASK (0x1 << I40E_PRT_MNG_MFUTP_UDP_SHIFT) 1536#define I40E_PRT_MNG_MFUTP_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_UDP_SHIFT)
1920#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17 1537#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17
1921#define I40E_PRT_MNG_MFUTP_TCP_MASK (0x1 << I40E_PRT_MNG_MFUTP_TCP_SHIFT) 1538#define I40E_PRT_MNG_MFUTP_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT)
1922#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18 1539#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18
1923#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK (0x1 << I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT) 1540#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)
1924#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ 1541#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1925#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3 1542#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3
1926#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0 1543#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0
1927#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT) 1544#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)
1928#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ 1545#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1929#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15 1546#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15
1930#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0 1547#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0
1931#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT) 1548#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)
1932#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ 1549#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1933#define I40E_PRT_MNG_MMAH_MAX_INDEX 3 1550#define I40E_PRT_MNG_MMAH_MAX_INDEX 3
1934#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0 1551#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0
1935#define I40E_PRT_MNG_MMAH_MMAH_MASK (0xFFFF << I40E_PRT_MNG_MMAH_MMAH_SHIFT) 1552#define I40E_PRT_MNG_MMAH_MMAH_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT)
1936#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ 1553#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1937#define I40E_PRT_MNG_MMAL_MAX_INDEX 3 1554#define I40E_PRT_MNG_MMAL_MAX_INDEX 3
1938#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0 1555#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0
1939#define I40E_PRT_MNG_MMAL_MMAL_MASK (0xFFFFFFFF << I40E_PRT_MNG_MMAL_MMAL_SHIFT) 1556#define I40E_PRT_MNG_MMAL_MMAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT)
1940#define I40E_PRT_MNG_MNGONLY 0x00256A60 1557#define I40E_PRT_MNG_MNGONLY 0x00256A60 /* Reset: POR */
1941#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0 1558#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0
1942#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK (0xFF << I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT) 1559#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)
1943#define I40E_PRT_MNG_MSFM 0x00256AA0 1560#define I40E_PRT_MNG_MSFM 0x00256AA0 /* Reset: POR */
1944#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0 1561#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0
1945#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT) 1562#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)
1946#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1 1563#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1
1947#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT) 1564#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT)
1948#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2 1565#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2
1949#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT) 1566#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT)
1950#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3 1567#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3
1951#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT) 1568#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT)
1952#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4 1569#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4
1953#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT) 1570#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT)
1954#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5 1571#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5
1955#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT) 1572#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT)
1956#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6 1573#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6
1957#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT) 1574#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)
1958#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7 1575#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7
1959#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT) 1576#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)
1960#define I40E_MSIX_PBA(_i) (0x00004900 + ((_i) * 4)) /* _i=0...5 */ 1577#define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */
1961#define I40E_MSIX_PBA_MAX_INDEX 5 1578#define I40E_MSIX_PBA_MAX_INDEX 5
1962#define I40E_MSIX_PBA_PENBIT_SHIFT 0 1579#define I40E_MSIX_PBA_PENBIT_SHIFT 0
1963#define I40E_MSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_MSIX_PBA_PENBIT_SHIFT) 1580#define I40E_MSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT)
1964#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ 1581#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1965#define I40E_MSIX_TADD_MAX_INDEX 128 1582#define I40E_MSIX_TADD_MAX_INDEX 128
1966#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0 1583#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0
1967#define I40E_MSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_MSIX_TADD_MSIXTADD10_SHIFT) 1584#define I40E_MSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT)
1968#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2 1585#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2
1969#define I40E_MSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_MSIX_TADD_MSIXTADD_SHIFT) 1586#define I40E_MSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT)
1970#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ 1587#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1971#define I40E_MSIX_TMSG_MAX_INDEX 128 1588#define I40E_MSIX_TMSG_MAX_INDEX 128
1972#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0 1589#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0
1973#define I40E_MSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_MSIX_TMSG_MSIXTMSG_SHIFT) 1590#define I40E_MSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT)
1974#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ 1591#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1975#define I40E_MSIX_TUADD_MAX_INDEX 128 1592#define I40E_MSIX_TUADD_MAX_INDEX 128
1976#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0 1593#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0
1977#define I40E_MSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_MSIX_TUADD_MSIXTUADD_SHIFT) 1594#define I40E_MSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT)
1978#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ 1595#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1979#define I40E_MSIX_TVCTRL_MAX_INDEX 128 1596#define I40E_MSIX_TVCTRL_MAX_INDEX 128
1980#define I40E_MSIX_TVCTRL_MASK_SHIFT 0 1597#define I40E_MSIX_TVCTRL_MASK_SHIFT 0
1981#define I40E_MSIX_TVCTRL_MASK_MASK (0x1 << I40E_MSIX_TVCTRL_MASK_SHIFT) 1598#define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT)
1982#define I40E_VFMSIX_PBA1(_i) (0x00004944 + ((_i) * 4)) /* _i=0...19 */ 1599#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
1983#define I40E_VFMSIX_PBA1_MAX_INDEX 19 1600#define I40E_VFMSIX_PBA1_MAX_INDEX 19
1984#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 1601#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
1985#define I40E_VFMSIX_PBA1_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA1_PENBIT_SHIFT) 1602#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
1986#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ 1603#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1987#define I40E_VFMSIX_TADD1_MAX_INDEX 639 1604#define I40E_VFMSIX_TADD1_MAX_INDEX 639
1988#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 1605#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
1989#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) 1606#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
1990#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 1607#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2
1991#define I40E_VFMSIX_TADD1_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) 1608#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
1992#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ 1609#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1993#define I40E_VFMSIX_TMSG1_MAX_INDEX 639 1610#define I40E_VFMSIX_TMSG1_MAX_INDEX 639
1994#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 1611#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
1995#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) 1612#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
1996#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ 1613#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1997#define I40E_VFMSIX_TUADD1_MAX_INDEX 639 1614#define I40E_VFMSIX_TUADD1_MAX_INDEX 639
1998#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 1615#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
1999#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) 1616#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
2000#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ 1617#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
2001#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 1618#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639
2002#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 1619#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
2003#define I40E_VFMSIX_TVCTRL1_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL1_MASK_SHIFT) 1620#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
2004#define I40E_GLNVM_FLA 0x000B6108 1621#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
2005#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0 1622#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0
2006#define I40E_GLNVM_FLA_FL_SCK_MASK (0x1 << I40E_GLNVM_FLA_FL_SCK_SHIFT) 1623#define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT)
2007#define I40E_GLNVM_FLA_FL_CE_SHIFT 1 1624#define I40E_GLNVM_FLA_FL_CE_SHIFT 1
2008#define I40E_GLNVM_FLA_FL_CE_MASK (0x1 << I40E_GLNVM_FLA_FL_CE_SHIFT) 1625#define I40E_GLNVM_FLA_FL_CE_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_CE_SHIFT)
2009#define I40E_GLNVM_FLA_FL_SI_SHIFT 2 1626#define I40E_GLNVM_FLA_FL_SI_SHIFT 2
2010#define I40E_GLNVM_FLA_FL_SI_MASK (0x1 << I40E_GLNVM_FLA_FL_SI_SHIFT) 1627#define I40E_GLNVM_FLA_FL_SI_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SI_SHIFT)
2011#define I40E_GLNVM_FLA_FL_SO_SHIFT 3 1628#define I40E_GLNVM_FLA_FL_SO_SHIFT 3
2012#define I40E_GLNVM_FLA_FL_SO_MASK (0x1 << I40E_GLNVM_FLA_FL_SO_SHIFT) 1629#define I40E_GLNVM_FLA_FL_SO_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SO_SHIFT)
2013#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4 1630#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4
2014#define I40E_GLNVM_FLA_FL_REQ_MASK (0x1 << I40E_GLNVM_FLA_FL_REQ_SHIFT) 1631#define I40E_GLNVM_FLA_FL_REQ_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_REQ_SHIFT)
2015#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5 1632#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5
2016#define I40E_GLNVM_FLA_FL_GNT_MASK (0x1 << I40E_GLNVM_FLA_FL_GNT_SHIFT) 1633#define I40E_GLNVM_FLA_FL_GNT_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_GNT_SHIFT)
2017#define I40E_GLNVM_FLA_LOCKED_SHIFT 6 1634#define I40E_GLNVM_FLA_LOCKED_SHIFT 6
2018#define I40E_GLNVM_FLA_LOCKED_MASK (0x1 << I40E_GLNVM_FLA_LOCKED_SHIFT) 1635#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
2019#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18 1636#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18
2020#define I40E_GLNVM_FLA_FL_SADDR_MASK (0x7FF << I40E_GLNVM_FLA_FL_SADDR_SHIFT) 1637#define I40E_GLNVM_FLA_FL_SADDR_MASK I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT)
2021#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30 1638#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30
2022#define I40E_GLNVM_FLA_FL_BUSY_MASK (0x1 << I40E_GLNVM_FLA_FL_BUSY_SHIFT) 1639#define I40E_GLNVM_FLA_FL_BUSY_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT)
2023#define I40E_GLNVM_FLA_FL_DER_SHIFT 31 1640#define I40E_GLNVM_FLA_FL_DER_SHIFT 31
2024#define I40E_GLNVM_FLA_FL_DER_MASK (0x1 << I40E_GLNVM_FLA_FL_DER_SHIFT) 1641#define I40E_GLNVM_FLA_FL_DER_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT)
2025#define I40E_GLNVM_FLASHID 0x000B6104 1642#define I40E_GLNVM_FLASHID 0x000B6104 /* Reset: POR */
2026#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0 1643#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0
2027#define I40E_GLNVM_FLASHID_FLASHID_MASK (0xFFFFFF << I40E_GLNVM_FLASHID_FLASHID_SHIFT) 1644#define I40E_GLNVM_FLASHID_FLASHID_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT)
2028#define I40E_GLNVM_GENS 0x000B6100 1645#define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31
1646#define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT)
1647#define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */
2029#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0 1648#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0
2030#define I40E_GLNVM_GENS_NVM_PRES_MASK (0x1 << I40E_GLNVM_GENS_NVM_PRES_SHIFT) 1649#define I40E_GLNVM_GENS_NVM_PRES_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT)
2031#define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 1650#define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5
2032#define I40E_GLNVM_GENS_SR_SIZE_MASK (0x7 << I40E_GLNVM_GENS_SR_SIZE_SHIFT) 1651#define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT)
2033#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8 1652#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8
2034#define I40E_GLNVM_GENS_BANK1VAL_MASK (0x1 << I40E_GLNVM_GENS_BANK1VAL_SHIFT) 1653#define I40E_GLNVM_GENS_BANK1VAL_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_BANK1VAL_SHIFT)
2035#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23 1654#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23
2036#define I40E_GLNVM_GENS_ALT_PRST_MASK (0x1 << I40E_GLNVM_GENS_ALT_PRST_SHIFT) 1655#define I40E_GLNVM_GENS_ALT_PRST_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT)
2037#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25 1656#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25
2038#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK (0x1 << I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT) 1657#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)
2039#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ 1658#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */
2040#define I40E_GLNVM_PROTCSR_MAX_INDEX 59 1659#define I40E_GLNVM_PROTCSR_MAX_INDEX 59
2041#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0 1660#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0
2042#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK (0xFFFFFF << I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT) 1661#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)
2043#define I40E_GLNVM_SRCTL 0x000B6110 1662#define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */
2044#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0 1663#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0
2045#define I40E_GLNVM_SRCTL_SRBUSY_MASK (0x1 << I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 1664#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
2046#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 1665#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14
2047#define I40E_GLNVM_SRCTL_ADDR_MASK (0x7FFF << I40E_GLNVM_SRCTL_ADDR_SHIFT) 1666#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)
2048#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 1667#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29
2049#define I40E_GLNVM_SRCTL_WRITE_MASK (0x1 << I40E_GLNVM_SRCTL_WRITE_SHIFT) 1668#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT)
2050#define I40E_GLNVM_SRCTL_START_SHIFT 30 1669#define I40E_GLNVM_SRCTL_START_SHIFT 30
2051#define I40E_GLNVM_SRCTL_START_MASK (0x1 << I40E_GLNVM_SRCTL_START_SHIFT) 1670#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
2052#define I40E_GLNVM_SRCTL_DONE_SHIFT 31 1671#define I40E_GLNVM_SRCTL_DONE_SHIFT 31
2053#define I40E_GLNVM_SRCTL_DONE_MASK (0x1 << I40E_GLNVM_SRCTL_DONE_SHIFT) 1672#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)
2054#define I40E_GLNVM_SRDATA 0x000B6114 1673#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */
2055#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 1674#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
2056#define I40E_GLNVM_SRDATA_WRDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_WRDATA_SHIFT) 1675#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
2057#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 1676#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
2058#define I40E_GLNVM_SRDATA_RDDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_RDDATA_SHIFT) 1677#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
2059#define I40E_GLNVM_ULD 0x000B6008 1678#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
2060#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 1679#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0
2061#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) 1680#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
2062#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1 1681#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1
2063#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT) 1682#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT)
2064#define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2 1683#define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2
2065#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT) 1684#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT)
2066#define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 1685#define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3
2067#define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 1686#define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT)
2068#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 1687#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4
2069#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 1688#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT)
2070#define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5 1689#define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5
2071#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT) 1690#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT)
2072#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6 1691#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6
2073#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT) 1692#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT)
2074#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7 1693#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7
2075#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT) 1694#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT)
2076#define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8 1695#define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8
2077#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT) 1696#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT)
2078#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9 1697#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9
2079#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT) 1698#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT)
2080 1699#define I40E_GLPCI_BYTCTH 0x0009C484 /* Reset: PCIR */
2081#define I40E_GLPCI_BYTCTH 0x0009C484
2082#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0 1700#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0
2083#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT) 1701#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)
2084#define I40E_GLPCI_BYTCTL 0x0009C488 1702#define I40E_GLPCI_BYTCTL 0x0009C488 /* Reset: PCIR */
2085#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0 1703#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0
2086#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT) 1704#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)
2087#define I40E_GLPCI_CAPCTRL 0x000BE4A4 1705#define I40E_GLPCI_CAPCTRL 0x000BE4A4 /* Reset: PCIR */
2088#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0 1706#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0
2089#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK (0x1 << I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT) 1707#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)
2090#define I40E_GLPCI_CAPSUP 0x000BE4A8 1708#define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */
2091#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0 1709#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0
2092#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK (0x1 << I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT) 1710#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)
2093#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2 1711#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2
2094#define I40E_GLPCI_CAPSUP_LTR_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_LTR_EN_SHIFT) 1712#define I40E_GLPCI_CAPSUP_LTR_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT)
2095#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3 1713#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3
2096#define I40E_GLPCI_CAPSUP_TPH_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_TPH_EN_SHIFT) 1714#define I40E_GLPCI_CAPSUP_TPH_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT)
2097#define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 1715#define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4
2098#define I40E_GLPCI_CAPSUP_ARI_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 1716#define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)
2099#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5 1717#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5
2100#define I40E_GLPCI_CAPSUP_IOV_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IOV_EN_SHIFT) 1718#define I40E_GLPCI_CAPSUP_IOV_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT)
2101#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6 1719#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6
2102#define I40E_GLPCI_CAPSUP_ACS_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ACS_EN_SHIFT) 1720#define I40E_GLPCI_CAPSUP_ACS_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT)
2103#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7 1721#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7
2104#define I40E_GLPCI_CAPSUP_SEC_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_SEC_EN_SHIFT) 1722#define I40E_GLPCI_CAPSUP_SEC_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT)
2105#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16 1723#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16
2106#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT) 1724#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT)
2107#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17 1725#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17
2108#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT) 1726#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT)
2109#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18 1727#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18
2110#define I40E_GLPCI_CAPSUP_IDO_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IDO_EN_SHIFT) 1728#define I40E_GLPCI_CAPSUP_IDO_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT)
2111#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19 1729#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19
2112#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK (0x1 << I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT) 1730#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT)
2113#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20 1731#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20
2114#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT) 1732#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT)
2115#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30 1733#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30
2116#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT) 1734#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)
2117#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31 1735#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31
2118#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT) 1736#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)
2119#define I40E_GLPCI_CNF 0x000BE4C0 1737#define I40E_GLPCI_CNF 0x000BE4C0 /* Reset: POR */
2120#define I40E_GLPCI_CNF_FLEX10_SHIFT 1 1738#define I40E_GLPCI_CNF_FLEX10_SHIFT 1
2121#define I40E_GLPCI_CNF_FLEX10_MASK (0x1 << I40E_GLPCI_CNF_FLEX10_SHIFT) 1739#define I40E_GLPCI_CNF_FLEX10_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT)
2122#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2 1740#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2
2123#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK (0x1 << I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT) 1741#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)
2124#define I40E_GLPCI_CNF2 0x000BE494 1742#define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */
2125#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0 1743#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0
2126#define I40E_GLPCI_CNF2_RO_DIS_MASK (0x1 << I40E_GLPCI_CNF2_RO_DIS_SHIFT) 1744#define I40E_GLPCI_CNF2_RO_DIS_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT)
2127#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1 1745#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1
2128#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK (0x1 << I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT) 1746#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT)
2129#define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 1747#define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2
2130#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 1748#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
2131#define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 1749#define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13
2132#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 1750#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
2133#define I40E_GLPCI_DREVID 0x0009C480 1751#define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */
2134#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0 1752#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0
2135#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK (0xFF << I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT) 1753#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)
2136#define I40E_GLPCI_GSCL_1 0x0009C48C 1754#define I40E_GLPCI_GSCL_1 0x0009C48C /* Reset: PCIR */
2137#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0 1755#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0
2138#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT) 1756#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)
2139#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1 1757#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1
2140#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT) 1758#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT)
2141#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2 1759#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2
2142#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT) 1760#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT)
2143#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3 1761#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3
2144#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT) 1762#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT)
2145#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4 1763#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4
2146#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT) 1764#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT)
2147#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5 1765#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5
2148#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT) 1766#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT)
2149#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6 1767#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6
2150#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT) 1768#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT)
2151#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7 1769#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7
2152#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT) 1770#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT)
2153#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8 1771#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8
2154#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT) 1772#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT)
2155#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9 1773#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9
2156#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT) 1774#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT)
2157#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14 1775#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14
2158#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT) 1776#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT)
2159#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15 1777#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15
2160#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT) 1778#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT)
2161#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28 1779#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28
2162#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT) 1780#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT)
2163#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29 1781#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29
2164#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT) 1782#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT)
2165#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30 1783#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30
2166#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT) 1784#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)
2167#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31 1785#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31
2168#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT) 1786#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)
2169#define I40E_GLPCI_GSCL_2 0x0009C490 1787#define I40E_GLPCI_GSCL_2 0x0009C490 /* Reset: PCIR */
2170#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0 1788#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0
2171#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT) 1789#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)
2172#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8 1790#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8
2173#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT) 1791#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT)
2174#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16 1792#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16
2175#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT) 1793#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)
2176#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24 1794#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24
2177#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT) 1795#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)
2178#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ 1796#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
2179#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3 1797#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3
2180#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0 1798#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0
2181#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT) 1799#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
2182#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16 1800#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16
2183#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT) 1801#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
2184#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ 1802#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
2185#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 1803#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3
2186#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 1804#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
2187#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK (0xFFFFFFFF << I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) 1805#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
2188#define I40E_GLPCI_LATCT 0x0009C4B4 1806#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCIR */
2189#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0 1807#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0
2190#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK (0xFFFFFFFF << I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT) 1808#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)
2191#define I40E_GLPCI_LBARCTRL 0x000BE484 1809#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
2192#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 1810#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0
2193#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK (0x1 << I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) 1811#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
2194#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1 1812#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1
2195#define I40E_GLPCI_LBARCTRL_BAR32_MASK (0x1 << I40E_GLPCI_LBARCTRL_BAR32_SHIFT) 1813#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT)
2196#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3 1814#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3
2197#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK (0x1 << I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT) 1815#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT)
2198#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4 1816#define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4
2199#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK (0x3 << I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT) 1817#define I40E_GLPCI_LBARCTRL_RSVD_4_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT)
2200#define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 1818#define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6
2201#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 1819#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)
2202#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10 1820#define I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT 10
2203#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK (0x1 << I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT) 1821#define I40E_GLPCI_LBARCTRL_RSVD_10_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT)
2204#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11 1822#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11
2205#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT) 1823#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)
2206#define I40E_GLPCI_LINKCAP 0x000BE4AC 1824#define I40E_GLPCI_LINKCAP 0x000BE4AC /* Reset: PCIR */
2207#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0 1825#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0
2208#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK (0x3F << I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT) 1826#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)
2209#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6 1827#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6
2210#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK (0x7 << I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT) 1828#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)
2211#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9 1829#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9
2212#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK (0xF << I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT) 1830#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)
2213#define I40E_GLPCI_PCIERR 0x000BE4FC 1831#define I40E_GLPCI_PCIERR 0x000BE4FC /* Reset: PCIR */
2214#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0 1832#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
2215#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK (0xFFFFFFFF << I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT) 1833#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
2216#define I40E_GLPCI_PCITEST2 0x000BE4BC 1834#define I40E_GLPCI_PKTCT 0x0009C4BC /* Reset: PCIR */
2217#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT 0
2218#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_MASK (0x1 << I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT)
2219#define I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT 1
2220#define I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK (0x1 << I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT)
2221
2222#define I40E_GLPCI_PKTCT 0x0009C4BC
2223#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0 1835#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
2224#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK (0xFFFFFFFF << I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT) 1836#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
2225#define I40E_GLPCI_PMSUP 0x000BE4B0 1837#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 /* Reset: PCIR */
1838#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0
1839#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
1840#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16
1841#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)
1842#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 /* Reset: PCIR */
1843#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0
1844#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
1845#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16
1846#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
1847#define I40E_GLPCI_PMSUP 0x000BE4B0 /* Reset: PCIR */
2226#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0 1848#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0
2227#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT) 1849#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)
2228#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2 1850#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2
2229#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT) 1851#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT)
2230#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5 1852#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5
2231#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT) 1853#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT)
2232#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8 1854#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8
2233#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT) 1855#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT)
2234#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11 1856#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11
2235#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT) 1857#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT)
2236#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14 1858#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14
2237#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK (0x1 << I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT) 1859#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)
2238#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15 1860#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15
2239#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT) 1861#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)
2240#define I40E_GLPCI_PWRDATA 0x000BE490 1862#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC /* Reset: PCIR */
1863#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0
1864#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)
1865#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8
1866#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)
1867#define I40E_GLPCI_PWRDATA 0x000BE490 /* Reset: PCIR */
2241#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0 1868#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0
2242#define I40E_GLPCI_PWRDATA_D0_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D0_POWER_SHIFT) 1869#define I40E_GLPCI_PWRDATA_D0_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)
2243#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8 1870#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8
2244#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT) 1871#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT)
2245#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16 1872#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16
2246#define I40E_GLPCI_PWRDATA_D3_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D3_POWER_SHIFT) 1873#define I40E_GLPCI_PWRDATA_D3_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)
2247#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24 1874#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24
2248#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK (0x3 << I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT) 1875#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)
2249#define I40E_GLPCI_REVID 0x000BE4B4 1876#define I40E_GLPCI_REVID 0x000BE4B4 /* Reset: PCIR */
2250#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0 1877#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0
2251#define I40E_GLPCI_REVID_NVM_REVID_MASK (0xFF << I40E_GLPCI_REVID_NVM_REVID_SHIFT) 1878#define I40E_GLPCI_REVID_NVM_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT)
2252#define I40E_GLPCI_SERH 0x000BE49C 1879#define I40E_GLPCI_SERH 0x000BE49C /* Reset: PCIR */
2253#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0 1880#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0
2254#define I40E_GLPCI_SERH_SER_NUM_H_MASK (0xFFFF << I40E_GLPCI_SERH_SER_NUM_H_SHIFT) 1881#define I40E_GLPCI_SERH_SER_NUM_H_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT)
2255#define I40E_GLPCI_SERL 0x000BE498 1882#define I40E_GLPCI_SERL 0x000BE498 /* Reset: PCIR */
2256#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0 1883#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0
2257#define I40E_GLPCI_SERL_SER_NUM_L_MASK (0xFFFFFFFF << I40E_GLPCI_SERL_SER_NUM_L_SHIFT) 1884#define I40E_GLPCI_SERL_SER_NUM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT)
2258#define I40E_GLPCI_SUBSYSID 0x000BE48C 1885#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 /* Reset: PCIR */
2259#define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT 0 1886#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0
2260#define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT) 1887#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
2261#define I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT 16 1888#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC /* Reset: PCIR */
2262#define I40E_GLPCI_SUBSYSID_SUB_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT) 1889#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0
2263#define I40E_GLPCI_UPADD 0x000BE4F8 1890#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)
1891#define I40E_GLPCI_SUBVENID 0x000BE48C /* Reset: PCIR */
1892#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0
1893#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT)
1894#define I40E_GLPCI_UPADD 0x000BE4F8 /* Reset: PCIR */
2264#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1 1895#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1
2265#define I40E_GLPCI_UPADD_ADDRESS_MASK (0x7FFFFFFF << I40E_GLPCI_UPADD_ADDRESS_SHIFT) 1896#define I40E_GLPCI_UPADD_ADDRESS_MASK I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT)
2266#define I40E_GLPCI_VFSUP 0x000BE4B8 1897#define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */
1898#define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0
1899#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT)
1900#define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */
2267#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0 1901#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0
2268#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK (0x1 << I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) 1902#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
2269#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 1903#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
2270#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK (0x1 << I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) 1904#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
2271#define I40E_PF_FUNC_RID 0x0009C000 1905#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */
2272#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 1906#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
2273#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK (0x7 << I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) 1907#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
2274#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3 1908#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3
2275#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK (0x1F << I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT) 1909#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)
2276#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8 1910#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8
2277#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK (0xFF << I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT) 1911#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)
2278#define I40E_PF_PCI_CIAA 0x0009C080 1912#define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */
2279#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0 1913#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0
2280#define I40E_PF_PCI_CIAA_ADDRESS_MASK (0xFFF << I40E_PF_PCI_CIAA_ADDRESS_SHIFT) 1914#define I40E_PF_PCI_CIAA_ADDRESS_MASK I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT)
2281#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 1915#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12
2282#define I40E_PF_PCI_CIAA_VF_NUM_MASK (0x7F << I40E_PF_PCI_CIAA_VF_NUM_SHIFT) 1916#define I40E_PF_PCI_CIAA_VF_NUM_MASK I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT)
2283#define I40E_PF_PCI_CIAD 0x0009C100 1917#define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */
2284#define I40E_PF_PCI_CIAD_DATA_SHIFT 0 1918#define I40E_PF_PCI_CIAD_DATA_SHIFT 0
2285#define I40E_PF_PCI_CIAD_DATA_MASK (0xFFFFFFFF << I40E_PF_PCI_CIAD_DATA_SHIFT) 1919#define I40E_PF_PCI_CIAD_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT)
2286#define I40E_PFPCI_CLASS 0x000BE400 1920#define I40E_PFPCI_CLASS 0x000BE400 /* Reset: PCIR */
2287#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0 1921#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0
2288#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK (0x1 << I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT) 1922#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)
2289#define I40E_PFPCI_CNF 0x000BE000 1923#define I40E_PFPCI_CLASS_RESERVED_1_SHIFT 1
1924#define I40E_PFPCI_CLASS_RESERVED_1_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT)
1925#define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT 2
1926#define I40E_PFPCI_CLASS_PF_IS_LAN_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT)
1927#define I40E_PFPCI_CNF 0x000BE000 /* Reset: PCIR */
2290#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2 1928#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2
2291#define I40E_PFPCI_CNF_MSI_EN_MASK (0x1 << I40E_PFPCI_CNF_MSI_EN_SHIFT) 1929#define I40E_PFPCI_CNF_MSI_EN_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT)
2292#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3 1930#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3
2293#define I40E_PFPCI_CNF_EXROM_DIS_MASK (0x1 << I40E_PFPCI_CNF_EXROM_DIS_SHIFT) 1931#define I40E_PFPCI_CNF_EXROM_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_EXROM_DIS_SHIFT)
2294#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4 1932#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4
2295#define I40E_PFPCI_CNF_IO_BAR_MASK (0x1 << I40E_PFPCI_CNF_IO_BAR_SHIFT) 1933#define I40E_PFPCI_CNF_IO_BAR_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT)
2296#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5 1934#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5
2297#define I40E_PFPCI_CNF_INT_PIN_MASK (0x3 << I40E_PFPCI_CNF_INT_PIN_SHIFT) 1935#define I40E_PFPCI_CNF_INT_PIN_MASK I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT)
2298#define I40E_PFPCI_FACTPS 0x0009C180 1936#define I40E_PFPCI_DEVID 0x000BE080 /* Reset: PCIR */
1937#define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0
1938#define I40E_PFPCI_DEVID_PF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)
1939#define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16
1940#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
1941#define I40E_PFPCI_FACTPS 0x0009C180 /* Reset: FLR */
2299#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0 1942#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0
2300#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK (0x3 << I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT) 1943#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
2301#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3 1944#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3
2302#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK (0x1 << I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT) 1945#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)
2303#define I40E_PFPCI_FUNC 0x000BE200 1946#define I40E_PFPCI_FUNC 0x000BE200 /* Reset: POR */
2304#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0 1947#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0
2305#define I40E_PFPCI_FUNC_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_FUNC_DIS_SHIFT) 1948#define I40E_PFPCI_FUNC_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)
2306#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1 1949#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1
2307#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT) 1950#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)
2308#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2 1951#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2
2309#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK (0x1 << I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT) 1952#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)
2310#define I40E_PFPCI_FUNC2 0x000BE180 1953#define I40E_PFPCI_FUNC2 0x000BE180 /* Reset: PCIR */
2311#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0 1954#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0
2312#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT) 1955#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)
2313#define I40E_PFPCI_ICAUSE 0x0009C200 1956#define I40E_PFPCI_ICAUSE 0x0009C200 /* Reset: PFR */
2314#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0 1957#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0
2315#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK (0xFFFFFFFF << I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT) 1958#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)
2316#define I40E_PFPCI_IENA 0x0009C280 1959#define I40E_PFPCI_IENA 0x0009C280 /* Reset: PFR */
2317#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0 1960#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0
2318#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK (0xFFFFFFFF << I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT) 1961#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)
2319#define I40E_PFPCI_PFDEVID 0x000BE080 1962#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 /* Reset: PCIR */
2320#define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT 0 1963#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
2321#define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT) 1964#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)
2322#define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT 16 1965#define I40E_PFPCI_PM 0x000BE300 /* Reset: POR */
2323#define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT)
2324#define I40E_PFPCI_PM 0x000BE300
2325#define I40E_PFPCI_PM_PME_EN_SHIFT 0 1966#define I40E_PFPCI_PM_PME_EN_SHIFT 0
2326#define I40E_PFPCI_PM_PME_EN_MASK (0x1 << I40E_PFPCI_PM_PME_EN_SHIFT) 1967#define I40E_PFPCI_PM_PME_EN_MASK I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT)
2327#define I40E_PFPCI_STATUS1 0x000BE280 1968#define I40E_PFPCI_STATUS1 0x000BE280 /* Reset: POR */
2328#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0 1969#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0
2329#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK (0x1 << I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT) 1970#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)
2330#define I40E_PFPCI_VFDEVID 0x000BE100 1971#define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */
2331#define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT 0 1972#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0
2332#define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT) 1973#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)
2333#define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT 16 1974#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16
2334#define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT) 1975#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
2335#define I40E_PFPCI_VMINDEX 0x0009C300 1976#define I40E_PFPCI_VF_FLUSH_DONE 0x0000E400 /* Reset: PCIR */
1977#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1978#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
1979#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */
1980#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127
1981#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0
1982#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)
1983#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 /* Reset: PCIR */
1984#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1985#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
1986#define I40E_PFPCI_VMINDEX 0x0009C300 /* Reset: PCIR */
2336#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0 1987#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0
2337#define I40E_PFPCI_VMINDEX_VMINDEX_MASK (0x1FF << I40E_PFPCI_VMINDEX_VMINDEX_SHIFT) 1988#define I40E_PFPCI_VMINDEX_VMINDEX_MASK I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)
2338#define I40E_PFPCI_VMPEND 0x0009C380 1989#define I40E_PFPCI_VMPEND 0x0009C380 /* Reset: PCIR */
2339#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0 1990#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0
2340#define I40E_PFPCI_VMPEND_PENDING_MASK (0x1 << I40E_PFPCI_VMPEND_PENDING_SHIFT) 1991#define I40E_PFPCI_VMPEND_PENDING_MASK I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT)
2341#define I40E_GLPE_CPUSTATUS0 0x0000D040 1992#define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */
2342#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0
2343#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
2344#define I40E_GLPE_CPUSTATUS1 0x0000D044
2345#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0
2346#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT)
2347#define I40E_GLPE_CPUSTATUS2 0x0000D048
2348#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0
2349#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT)
2350#define I40E_GLPE_PFFLMOBJCTRL(_i) (0x0000D480 + ((_i) * 4)) /* _i=0...15 */
2351#define I40E_GLPE_PFFLMOBJCTRL_MAX_INDEX 15
2352#define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
2353#define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
2354#define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
2355#define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
2356#define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */
2357#define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31
2358#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
2359#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
2360#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
2361#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
2362#define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */
2363#define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
2364#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
2365#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
2366#define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */
2367#define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
2368#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
2369#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT)
2370#define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */
2371#define I40E_GLPE_VFUDACTRL_MAX_INDEX 31
2372#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0
2373#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT)
2374#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1
2375#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT)
2376#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2
2377#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT)
2378#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3
2379#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT)
2380#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
2381#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT)
2382#define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */
2383#define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31
2384#define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0
2385#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT)
2386#define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31
2387#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK (0x1 << I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT)
2388#define I40E_PFPE_AEQALLOC 0x00131180
2389#define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0
2390#define I40E_PFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_PFPE_AEQALLOC_AECOUNT_SHIFT)
2391#define I40E_PFPE_CCQPHIGH 0x00008200
2392#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
2393#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
2394#define I40E_PFPE_CCQPLOW 0x00008180
2395#define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0
2396#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT)
2397#define I40E_PFPE_CCQPSTATUS 0x00008100
2398#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
2399#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
2400#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
2401#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
2402#define I40E_PFPE_CQACK 0x00131100
2403#define I40E_PFPE_CQACK_PECQID_SHIFT 0
2404#define I40E_PFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_PFPE_CQACK_PECQID_SHIFT)
2405#define I40E_PFPE_CQARM 0x00131080
2406#define I40E_PFPE_CQARM_PECQID_SHIFT 0
2407#define I40E_PFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_PFPE_CQARM_PECQID_SHIFT)
2408#define I40E_PFPE_CQPDB 0x00008000
2409#define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0
2410#define I40E_PFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_PFPE_CQPDB_WQHEAD_SHIFT)
2411#define I40E_PFPE_CQPERRCODES 0x00008880
2412#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
2413#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
2414#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
2415#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
2416#define I40E_PFPE_CQPTAIL 0x00008080
2417#define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0
2418#define I40E_PFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
2419#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
2420#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
2421#define I40E_PFPE_FLMQ1ALLOCERR 0x00008980
2422#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
2423#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
2424#define I40E_PFPE_FLMXMITALLOCERR 0x00008900
2425#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
2426#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT)
2427#define I40E_PFPE_IPCONFIG0 0x00008280
2428#define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0
2429#define I40E_PFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
2430#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
2431#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
2432
2433#define I40E_PFPE_MRTEIDXMASK 0x00008600
2434#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
2435#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
2436#define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680
2437#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
2438#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
2439#define I40E_PFPE_TCPNOWTIMER 0x00008580
2440#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
2441#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
2442#define I40E_PFPE_UDACTRL 0x00008700
2443#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0
2444#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT)
2445#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1
2446#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT)
2447#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2
2448#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT)
2449#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3
2450#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT)
2451#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
2452#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT)
2453#define I40E_PFPE_UDAUCFBQPN 0x00008780
2454#define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0
2455#define I40E_PFPE_UDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_PFPE_UDAUCFBQPN_QPN_SHIFT)
2456#define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31
2457#define I40E_PFPE_UDAUCFBQPN_VALID_MASK (0x1 << I40E_PFPE_UDAUCFBQPN_VALID_SHIFT)
2458#define I40E_PFPE_WQEALLOC 0x00138C00
2459#define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0
2460#define I40E_PFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_PFPE_WQEALLOC_PEQPID_SHIFT)
2461#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
2462#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
2463#define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */
2464#define I40E_VFPE_AEQALLOC_MAX_INDEX 127
2465#define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0
2466#define I40E_VFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC_AECOUNT_SHIFT)
2467#define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */
2468#define I40E_VFPE_CCQPHIGH_MAX_INDEX 127
2469#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
2470#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
2471#define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */
2472#define I40E_VFPE_CCQPLOW_MAX_INDEX 127
2473#define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0
2474#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT)
2475#define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */
2476#define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127
2477#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
2478#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
2479#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
2480#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
2481#define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */
2482#define I40E_VFPE_CQACK_MAX_INDEX 127
2483#define I40E_VFPE_CQACK_PECQID_SHIFT 0
2484#define I40E_VFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK_PECQID_SHIFT)
2485#define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */
2486#define I40E_VFPE_CQARM_MAX_INDEX 127
2487#define I40E_VFPE_CQARM_PECQID_SHIFT 0
2488#define I40E_VFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM_PECQID_SHIFT)
2489#define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */
2490#define I40E_VFPE_CQPDB_MAX_INDEX 127
2491#define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0
2492#define I40E_VFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB_WQHEAD_SHIFT)
2493#define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */
2494#define I40E_VFPE_CQPERRCODES_MAX_INDEX 127
2495#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
2496#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
2497#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
2498#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
2499#define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */
2500#define I40E_VFPE_CQPTAIL_MAX_INDEX 127
2501#define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0
2502#define I40E_VFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL_WQTAIL_SHIFT)
2503#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
2504#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
2505#define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */
2506#define I40E_VFPE_IPCONFIG0_MAX_INDEX 127
2507#define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0
2508#define I40E_VFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
2509#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
2510#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
2511#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */
2512#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127
2513#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
2514#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
2515#define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4))
2516#define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127
2517#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
2518#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
2519#define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */
2520#define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127
2521#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
2522#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
2523#define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */
2524#define I40E_VFPE_WQEALLOC_MAX_INDEX 127
2525#define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0
2526#define I40E_VFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC_PEQPID_SHIFT)
2527#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
2528#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
2529#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */
2530#define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15
2531#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
2532#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
2533#define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */
2534#define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15
2535#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
2536#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
2537#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */
2538#define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15
2539#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
2540#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
2541#define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8))
2542#define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15
2543#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
2544#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
2545#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8))
2546#define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15
2547#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
2548#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
2549#define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8))
2550#define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15
2551#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
2552#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
2553#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8))
2554#define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15
2555#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
2556#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
2557#define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */
2558#define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15
2559#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
2560#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
2561#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */
2562#define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15
2563#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
2564#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
2565#define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */
2566#define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15
2567#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
2568#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
2569#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */
2570#define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15
2571#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
2572#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
2573#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */
2574#define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15
2575#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
2576#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
2577#define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */
2578#define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15
2579#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
2580#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
2581#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */
2582#define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15
2583#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
2584#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
2585#define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8))
2586#define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15
2587#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
2588#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
2589#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8))
2590#define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15
2591#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
2592#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
2593#define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8))
2594#define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15
2595#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
2596#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
2597#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8))
2598#define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15
2599#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
2600#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
2601#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */
2602#define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15
2603#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
2604#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
2605#define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */
2606#define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15
2607#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
2608#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
2609#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */
2610#define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15
2611#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
2612#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
2613#define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */
2614#define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15
2615#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
2616#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
2617#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */
2618#define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15
2619#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
2620#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
2621#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */
2622#define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15
2623#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
2624#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
2625#define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */
2626#define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15
2627#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
2628#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
2629#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */
2630#define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15
2631#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
2632#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
2633#define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8))
2634#define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15
2635#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
2636#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
2637#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8))
2638#define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15
2639#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
2640#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
2641#define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8))
2642#define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15
2643#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
2644#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
2645#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8))
2646#define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15
2647#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
2648#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
2649#define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */
2650#define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15
2651#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
2652#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
2653#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */
2654#define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15
2655#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
2656#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
2657#define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */
2658#define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15
2659#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
2660#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
2661#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */
2662#define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15
2663#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
2664#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
2665#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */
2666#define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15
2667#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
2668#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
2669#define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */
2670#define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15
2671#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
2672#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
2673#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */
2674#define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15
2675#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
2676#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
2677#define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8))
2678#define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15
2679#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
2680#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
2681#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8))
2682#define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15
2683#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
2684#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
2685#define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8))
2686#define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15
2687#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
2688#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
2689#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8))
2690#define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15
2691#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
2692#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
2693#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */
2694#define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15
2695#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
2696#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
2697#define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */
2698#define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15
2699#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
2700#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
2701#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */
2702#define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15
2703#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
2704#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
2705#define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */
2706#define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15
2707#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
2708#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
2709#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */
2710#define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15
2711#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
2712#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
2713#define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */
2714#define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15
2715#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
2716#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
2717#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */
2718#define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15
2719#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
2720#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
2721#define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */
2722#define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15
2723#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
2724#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
2725#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */
2726#define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15
2727#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
2728#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
2729#define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */
2730#define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15
2731#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
2732#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
2733#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */
2734#define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15
2735#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
2736#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
2737#define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */
2738#define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15
2739#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
2740#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
2741#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */
2742#define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15
2743#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
2744#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
2745#define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */
2746#define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15
2747#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
2748#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
2749#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */
2750#define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15
2751#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
2752#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
2753#define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */
2754#define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15
2755#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
2756#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
2757#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */
2758#define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15
2759#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
2760#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
2761#define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */
2762#define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15
2763#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
2764#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
2765#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */
2766#define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15
2767#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
2768#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
2769#define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */
2770#define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15
2771#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0
2772#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT)
2773#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */
2774#define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15
2775#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0
2776#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT)
2777#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */
2778#define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15
2779#define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0
2780#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT)
2781#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */
2782#define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15
2783#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0
2784#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT)
2785#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */
2786#define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15
2787#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
2788#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
2789#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4))
2790#define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15
2791#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
2792#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
2793#define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */
2794#define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15
2795#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
2796#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
2797#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */
2798#define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15
2799#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
2800#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
2801#define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */
2802#define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15
2803#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
2804#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
2805#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */
2806#define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15
2807#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
2808#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
2809#define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */
2810#define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15
2811#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
2812#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
2813#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */
2814#define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15
2815#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
2816#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
2817#define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */
2818#define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15
2819#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
2820#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
2821#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */
2822#define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15
2823#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
2824#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
2825#define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014
2826#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0
2827#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT)
2828#define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010
2829#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0
2830#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT)
2831#define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C
2832#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0
2833#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT)
2834#define I40E_GLPES_RDMARXOOODDPLO 0x0001E018
2835#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0
2836#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT)
2837#define I40E_GLPES_RDMARXOOONOMARK 0x0001E004
2838#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0
2839#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT)
2840#define I40E_GLPES_RDMARXUNALIGN 0x0001E000
2841#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0
2842#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT)
2843#define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044
2844#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0
2845#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT)
2846#define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040
2847#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0
2848#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT)
2849#define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C
2850#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0
2851#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT)
2852#define I40E_GLPES_TCPRXONEHOLELO 0x0001E028
2853#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0
2854#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT)
2855#define I40E_GLPES_TCPRXPUREACKHI 0x0001E024
2856#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0
2857#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT)
2858#define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020
2859#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0
2860#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT)
2861#define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C
2862#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0
2863#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT)
2864#define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038
2865#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0
2866#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT)
2867#define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034
2868#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0
2869#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT)
2870#define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030
2871#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0
2872#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT)
2873#define I40E_GLPES_TCPRXUNEXPERR 0x0001E008
2874#define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT 0
2875#define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_MASK (0xFFFFFF << I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT)
2876#define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C
2877#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0
2878#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT)
2879#define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048
2880#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0
2881#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT)
2882#define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054
2883#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0
2884#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT)
2885#define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050
2886#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0
2887#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT)
2888#define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C
2889#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0
2890#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT)
2891#define I40E_GLPES_TCPTXTOUTSLO 0x0001E058
2892#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0
2893#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT)
2894#define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */
2895#define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31
2896#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
2897#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
2898#define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 4)) /* _i=0...31 */
2899#define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31
2900#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
2901#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
2902#define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 4)) /* _i=0...31 */
2903#define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31
2904#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
2905#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
2906#define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 4))
2907#define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31
2908#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
2909#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
2910#define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 4))
2911#define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31
2912#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
2913#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
2914#define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 4))
2915#define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31
2916#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
2917#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
2918#define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 4))
2919#define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31
2920#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
2921#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
2922#define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 4)) /* _i=0...31 */
2923#define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31
2924#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
2925#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
2926#define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 4)) /* _i=0...31 */
2927#define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31
2928#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
2929#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
2930#define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 4)) /* _i=0...31 */
2931#define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31
2932#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
2933#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
2934#define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 4)) /* _i=0...31 */
2935#define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31
2936#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
2937#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
2938#define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */
2939#define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31
2940#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
2941#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
2942#define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 4)) /* _i=0...31 */
2943#define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31
2944#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
2945#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
2946#define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 4)) /* _i=0...31 */
2947#define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31
2948#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
2949#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
2950#define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 4))
2951#define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31
2952#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
2953#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
2954#define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 4))
2955#define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31
2956#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
2957#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
2958#define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 4))
2959#define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31
2960#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
2961#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
2962#define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 4))
2963#define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31
2964#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
2965#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
2966#define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */
2967#define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31
2968#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
2969#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
2970#define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 4)) /* _i=0...31 */
2971#define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31
2972#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
2973#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
2974#define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 4)) /* _i=0...31 */
2975#define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31
2976#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
2977#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
2978#define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 4)) /* _i=0...31 */
2979#define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31
2980#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
2981#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
2982#define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 4)) /* _i=0...31 */
2983#define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31
2984#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
2985#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
2986#define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */
2987#define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31
2988#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
2989#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
2990#define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 4)) /* _i=0...31 */
2991#define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31
2992#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
2993#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
2994#define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 4)) /* _i=0...31 */
2995#define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31
2996#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
2997#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
2998#define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 4))
2999#define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31
3000#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
3001#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
3002#define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 4))
3003#define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31
3004#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
3005#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
3006#define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 4))
3007#define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31
3008#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
3009#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
3010#define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 4))
3011#define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31
3012#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
3013#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
3014#define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 4)) /* _i=0...31 */
3015#define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31
3016#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
3017#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
3018#define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 4)) /* _i=0...31 */
3019#define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31
3020#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
3021#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
3022#define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 4)) /* _i=0...31 */
3023#define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31
3024#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
3025#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
3026#define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 4)) /* _i=0...31 */
3027#define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31
3028#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
3029#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
3030#define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */
3031#define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31
3032#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
3033#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
3034#define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 4)) /* _i=0...31 */
3035#define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31
3036#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
3037#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
3038#define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 4)) /* _i=0...31 */
3039#define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31
3040#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
3041#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
3042#define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 4))
3043#define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31
3044#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
3045#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
3046#define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 4))
3047#define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31
3048#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
3049#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
3050#define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 4))
3051#define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31
3052#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
3053#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
3054#define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 4))
3055#define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31
3056#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
3057#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
3058#define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */
3059#define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31
3060#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
3061#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
3062#define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 4)) /* _i=0...31 */
3063#define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31
3064#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
3065#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
3066#define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 4)) /* _i=0...31 */
3067#define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31
3068#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
3069#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
3070#define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 4)) /* _i=0...31 */
3071#define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31
3072#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
3073#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
3074#define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 4)) /* _i=0...31 */
3075#define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31
3076#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
3077#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
3078#define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 4)) /* _i=0...31 */
3079#define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31
3080#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
3081#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
3082#define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 4)) /* _i=0...31 */
3083#define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31
3084#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
3085#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
3086#define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 4)) /* _i=0...31 */
3087#define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31
3088#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
3089#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
3090#define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 4)) /* _i=0...31 */
3091#define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31
3092#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
3093#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
3094#define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 4)) /* _i=0...31 */
3095#define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31
3096#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
3097#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
3098#define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 4)) /* _i=0...31 */
3099#define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31
3100#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
3101#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
3102#define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 4)) /* _i=0...31 */
3103#define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31
3104#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
3105#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
3106#define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 4)) /* _i=0...31 */
3107#define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31
3108#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
3109#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
3110#define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 4)) /* _i=0...31 */
3111#define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31
3112#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
3113#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
3114#define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 4)) /* _i=0...31 */
3115#define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31
3116#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
3117#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
3118#define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 4)) /* _i=0...31 */
3119#define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31
3120#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
3121#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
3122#define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 4)) /* _i=0...31 */
3123#define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31
3124#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
3125#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
3126#define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 4)) /* _i=0...31 */
3127#define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31
3128#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
3129#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
3130#define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 4)) /* _i=0...31 */
3131#define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31
3132#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
3133#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
3134#define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 4)) /* _i=0...31 */
3135#define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31
3136#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0
3137#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT)
3138#define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 4)) /* _i=0...31 */
3139#define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31
3140#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0
3141#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT)
3142#define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */
3143#define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31
3144#define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0
3145#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT)
3146#define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */
3147#define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31
3148#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0
3149#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT)
3150#define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */
3151#define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31
3152#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
3153#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
3154#define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4))
3155#define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31
3156#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
3157#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
3158#define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 4)) /* _i=0...31 */
3159#define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31
3160#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
3161#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
3162#define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 4)) /* _i=0...31 */
3163#define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31
3164#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
3165#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
3166#define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 4)) /* _i=0...31 */
3167#define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31
3168#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
3169#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
3170#define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 4)) /* _i=0...31 */
3171#define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31
3172#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
3173#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
3174#define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 4)) /* _i=0...31 */
3175#define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31
3176#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
3177#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
3178#define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 4)) /* _i=0...31 */
3179#define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31
3180#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
3181#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
3182#define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 4)) /* _i=0...31 */
3183#define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31
3184#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
3185#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
3186#define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 4)) /* _i=0...31 */
3187#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31
3188#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
3189#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
3190#define I40E_PRTPM_EEE_STAT 0x001E4320
3191#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29 1993#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29
3192#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK (0x1 << I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT) 1994#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
3193#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 1995#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30
3194#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 1996#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
3195#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 1997#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
3196#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 1998#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
3197#define I40E_PRTPM_EEEC 0x001E4380 1999#define I40E_PRTPM_EEEC 0x001E4380 /* Reset: GLOBR */
3198#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16 2000#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16
3199#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK (0x3F << I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT) 2001#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)
3200#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24 2002#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24
3201#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK (0x3 << I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT) 2003#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)
3202#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26 2004#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26
3203#define I40E_PRTPM_EEEC_TEEE_DLY_MASK (0x3F << I40E_PRTPM_EEEC_TEEE_DLY_SHIFT) 2005#define I40E_PRTPM_EEEC_TEEE_DLY_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)
3204#define I40E_PRTPM_EEEFWD 0x001E4400 2006#define I40E_PRTPM_EEEFWD 0x001E4400 /* Reset: GLOBR */
3205#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31 2007#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31
3206#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK (0x1 << I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT) 2008#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)
3207#define I40E_PRTPM_EEER 0x001E4360 2009#define I40E_PRTPM_EEER 0x001E4360 /* Reset: GLOBR */
3208#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0 2010#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0
3209#define I40E_PRTPM_EEER_TW_SYSTEM_MASK (0xFFFF << I40E_PRTPM_EEER_TW_SYSTEM_SHIFT) 2011#define I40E_PRTPM_EEER_TW_SYSTEM_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)
3210#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16 2012#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16
3211#define I40E_PRTPM_EEER_TX_LPI_EN_MASK (0x1 << I40E_PRTPM_EEER_TX_LPI_EN_SHIFT) 2013#define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
3212#define I40E_PRTPM_EEETXC 0x001E43E0 2014#define I40E_PRTPM_EEETXC 0x001E43E0 /* Reset: GLOBR */
3213#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0 2015#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0
3214#define I40E_PRTPM_EEETXC_TW_PHY_MASK (0xFFFF << I40E_PRTPM_EEETXC_TW_PHY_SHIFT) 2016#define I40E_PRTPM_EEETXC_TW_PHY_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT)
3215#define I40E_PRTPM_GC 0x000B8140 2017#define I40E_PRTPM_GC 0x000B8140 /* Reset: POR */
3216#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0 2018#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0
3217#define I40E_PRTPM_GC_EMP_LINK_ON_MASK (0x1 << I40E_PRTPM_GC_EMP_LINK_ON_SHIFT) 2019#define I40E_PRTPM_GC_EMP_LINK_ON_MASK I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)
3218#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1 2020#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1
3219#define I40E_PRTPM_GC_MNG_VETO_MASK (0x1 << I40E_PRTPM_GC_MNG_VETO_SHIFT) 2021#define I40E_PRTPM_GC_MNG_VETO_MASK I40E_MASK(0x1, I40E_PRTPM_GC_MNG_VETO_SHIFT)
3220#define I40E_PRTPM_GC_RATD_SHIFT 2 2022#define I40E_PRTPM_GC_RATD_SHIFT 2
3221#define I40E_PRTPM_GC_RATD_MASK (0x1 << I40E_PRTPM_GC_RATD_SHIFT) 2023#define I40E_PRTPM_GC_RATD_MASK I40E_MASK(0x1, I40E_PRTPM_GC_RATD_SHIFT)
3222#define I40E_PRTPM_GC_LCDMP_SHIFT 3 2024#define I40E_PRTPM_GC_LCDMP_SHIFT 3
3223#define I40E_PRTPM_GC_LCDMP_MASK (0x1 << I40E_PRTPM_GC_LCDMP_SHIFT) 2025#define I40E_PRTPM_GC_LCDMP_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT)
3224#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31 2026#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
3225#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK (0x1 << I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT) 2027#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
3226#define I40E_PRTPM_RLPIC 0x001E43A0 2028#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */
3227#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0 2029#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
3228#define I40E_PRTPM_RLPIC_ERLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_RLPIC_ERLPIC_SHIFT) 2030#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
3229#define I40E_PRTPM_TLPIC 0x001E43C0 2031#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */
3230#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0 2032#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
3231#define I40E_PRTPM_TLPIC_ETLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_TLPIC_ETLPIC_SHIFT) 2033#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
3232#define I40E_GLRPB_DPSS 0x000AC828 2034#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */
3233#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0 2035#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
3234#define I40E_GLRPB_DPSS_DPS_TCN_MASK (0xFFFFF << I40E_GLRPB_DPSS_DPS_TCN_SHIFT) 2036#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
3235#define I40E_GLRPB_GHW 0x000AC830 2037#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */
3236#define I40E_GLRPB_GHW_GHW_SHIFT 0 2038#define I40E_GLRPB_GHW_GHW_SHIFT 0
3237#define I40E_GLRPB_GHW_GHW_MASK (0xFFFFF << I40E_GLRPB_GHW_GHW_SHIFT) 2039#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)
3238#define I40E_GLRPB_GLW 0x000AC834 2040#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */
3239#define I40E_GLRPB_GLW_GLW_SHIFT 0 2041#define I40E_GLRPB_GLW_GLW_SHIFT 0
3240#define I40E_GLRPB_GLW_GLW_MASK (0xFFFFF << I40E_GLRPB_GLW_GLW_SHIFT) 2042#define I40E_GLRPB_GLW_GLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT)
3241#define I40E_GLRPB_PHW 0x000AC844 2043#define I40E_GLRPB_PHW 0x000AC844 /* Reset: CORER */
3242#define I40E_GLRPB_PHW_PHW_SHIFT 0 2044#define I40E_GLRPB_PHW_PHW_SHIFT 0
3243#define I40E_GLRPB_PHW_PHW_MASK (0xFFFFF << I40E_GLRPB_PHW_PHW_SHIFT) 2045#define I40E_GLRPB_PHW_PHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT)
3244#define I40E_GLRPB_PLW 0x000AC848 2046#define I40E_GLRPB_PLW 0x000AC848 /* Reset: CORER */
3245#define I40E_GLRPB_PLW_PLW_SHIFT 0 2047#define I40E_GLRPB_PLW_PLW_SHIFT 0
3246#define I40E_GLRPB_PLW_PLW_MASK (0xFFFFF << I40E_GLRPB_PLW_PLW_SHIFT) 2048#define I40E_GLRPB_PLW_PLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT)
3247#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ 2049#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3248#define I40E_PRTRPB_DHW_MAX_INDEX 7 2050#define I40E_PRTRPB_DHW_MAX_INDEX 7
3249#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0 2051#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0
3250#define I40E_PRTRPB_DHW_DHW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) 2052#define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
3251#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ 2053#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3252#define I40E_PRTRPB_DLW_MAX_INDEX 7 2054#define I40E_PRTRPB_DLW_MAX_INDEX 7
3253#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0 2055#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0
3254#define I40E_PRTRPB_DLW_DLW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) 2056#define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
3255#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ 2057#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3256#define I40E_PRTRPB_DPS_MAX_INDEX 7 2058#define I40E_PRTRPB_DPS_MAX_INDEX 7
3257#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0 2059#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0
3258#define I40E_PRTRPB_DPS_DPS_TCN_MASK (0xFFFFF << I40E_PRTRPB_DPS_DPS_TCN_SHIFT) 2060#define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
3259#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ 2061#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3260#define I40E_PRTRPB_SHT_MAX_INDEX 7 2062#define I40E_PRTRPB_SHT_MAX_INDEX 7
3261#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0 2063#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0
3262#define I40E_PRTRPB_SHT_SHT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) 2064#define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
3263#define I40E_PRTRPB_SHW 0x000AC580 2065#define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */
3264#define I40E_PRTRPB_SHW_SHW_SHIFT 0 2066#define I40E_PRTRPB_SHW_SHW_SHIFT 0
3265#define I40E_PRTRPB_SHW_SHW_MASK (0xFFFFF << I40E_PRTRPB_SHW_SHW_SHIFT) 2067#define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)
3266#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ 2068#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3267#define I40E_PRTRPB_SLT_MAX_INDEX 7 2069#define I40E_PRTRPB_SLT_MAX_INDEX 7
3268#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0 2070#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0
3269#define I40E_PRTRPB_SLT_SLT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) 2071#define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
3270#define I40E_PRTRPB_SLW 0x000AC6A0 2072#define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */
3271#define I40E_PRTRPB_SLW_SLW_SHIFT 0 2073#define I40E_PRTRPB_SLW_SLW_SHIFT 0
3272#define I40E_PRTRPB_SLW_SLW_MASK (0xFFFFF << I40E_PRTRPB_SLW_SLW_SHIFT) 2074#define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)
3273#define I40E_PRTRPB_SPS 0x000AC7C0 2075#define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */
3274#define I40E_PRTRPB_SPS_SPS_SHIFT 0 2076#define I40E_PRTRPB_SPS_SPS_SHIFT 0
3275#define I40E_PRTRPB_SPS_SPS_MASK (0xFFFFF << I40E_PRTRPB_SPS_SPS_SHIFT) 2077#define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)
3276#define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */ 2078#define I40E_GLQF_CTL 0x00269BA4 /* Reset: CORER */
3277#define I40E_GLQF_APBVT_MAX_INDEX 2047
3278#define I40E_GLQF_APBVT_APBVT_SHIFT 0
3279#define I40E_GLQF_APBVT_APBVT_MASK (0xFFFFFFFF << I40E_GLQF_APBVT_APBVT_SHIFT)
3280#define I40E_GLQF_CTL 0x00269BA4
3281#define I40E_GLQF_CTL_HTOEP_SHIFT 1 2079#define I40E_GLQF_CTL_HTOEP_SHIFT 1
3282#define I40E_GLQF_CTL_HTOEP_MASK (0x1 << I40E_GLQF_CTL_HTOEP_SHIFT) 2080#define I40E_GLQF_CTL_HTOEP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT)
3283#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2 2081#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2
3284#define I40E_GLQF_CTL_HTOEP_FCOE_MASK (0x1 << I40E_GLQF_CTL_HTOEP_FCOE_SHIFT) 2082#define I40E_GLQF_CTL_HTOEP_FCOE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)
3285#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3 2083#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3
3286#define I40E_GLQF_CTL_PCNT_ALLOC_MASK (0x7 << I40E_GLQF_CTL_PCNT_ALLOC_SHIFT) 2084#define I40E_GLQF_CTL_PCNT_ALLOC_MASK I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)
2085#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT 6
2086#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT)
3287#define I40E_GLQF_CTL_RSVD_SHIFT 7 2087#define I40E_GLQF_CTL_RSVD_SHIFT 7
3288#define I40E_GLQF_CTL_RSVD_MASK (0x1 << I40E_GLQF_CTL_RSVD_SHIFT) 2088#define I40E_GLQF_CTL_RSVD_MASK I40E_MASK(0x1, I40E_GLQF_CTL_RSVD_SHIFT)
3289#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8 2089#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8
3290#define I40E_GLQF_CTL_MAXPEBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXPEBLEN_SHIFT) 2090#define I40E_GLQF_CTL_MAXPEBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT)
3291#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11 2091#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11
3292#define I40E_GLQF_CTL_MAXFCBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFCBLEN_SHIFT) 2092#define I40E_GLQF_CTL_MAXFCBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT)
3293#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14 2093#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14
3294#define I40E_GLQF_CTL_MAXFDBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFDBLEN_SHIFT) 2094#define I40E_GLQF_CTL_MAXFDBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT)
3295#define I40E_GLQF_CTL_FDBEST_SHIFT 17 2095#define I40E_GLQF_CTL_FDBEST_SHIFT 17
3296#define I40E_GLQF_CTL_FDBEST_MASK (0xFF << I40E_GLQF_CTL_FDBEST_SHIFT) 2096#define I40E_GLQF_CTL_FDBEST_MASK I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT)
3297#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25 2097#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25
3298#define I40E_GLQF_CTL_PROGPRIO_MASK (0x1 << I40E_GLQF_CTL_PROGPRIO_SHIFT) 2098#define I40E_GLQF_CTL_PROGPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_PROGPRIO_SHIFT)
3299#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26 2099#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26
3300#define I40E_GLQF_CTL_INVALPRIO_MASK (0x1 << I40E_GLQF_CTL_INVALPRIO_SHIFT) 2100#define I40E_GLQF_CTL_INVALPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT)
3301#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27 2101#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27
3302#define I40E_GLQF_CTL_IGNORE_IP_MASK (0x1 << I40E_GLQF_CTL_IGNORE_IP_SHIFT) 2102#define I40E_GLQF_CTL_IGNORE_IP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT)
3303#define I40E_GLQF_FDCNT_0 0x00269BAC 2103#define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */
3304#define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 2104#define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0
3305#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) 2105#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
3306#define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 2106#define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13
3307#define I40E_GLQF_FDCNT_0_BESTCNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 2107#define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
3308#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ 2108#define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
2109#define I40E_GLQF_HKEY_MAX_INDEX 12
2110#define I40E_GLQF_HKEY_KEY_0_SHIFT 0
2111#define I40E_GLQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT)
2112#define I40E_GLQF_HKEY_KEY_1_SHIFT 8
2113#define I40E_GLQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT)
2114#define I40E_GLQF_HKEY_KEY_2_SHIFT 16
2115#define I40E_GLQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT)
2116#define I40E_GLQF_HKEY_KEY_3_SHIFT 24
2117#define I40E_GLQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT)
2118#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
3309#define I40E_GLQF_HSYM_MAX_INDEX 63 2119#define I40E_GLQF_HSYM_MAX_INDEX 63
3310#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0 2120#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0
3311#define I40E_GLQF_HSYM_SYMH_ENA_MASK (0x1 << I40E_GLQF_HSYM_SYMH_ENA_SHIFT) 2121#define I40E_GLQF_HSYM_SYMH_ENA_MASK I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT)
3312#define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ 2122#define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */
3313#define I40E_GLQF_PCNT_MAX_INDEX 511 2123#define I40E_GLQF_PCNT_MAX_INDEX 511
3314#define I40E_GLQF_PCNT_PCNT_SHIFT 0 2124#define I40E_GLQF_PCNT_PCNT_SHIFT 0
3315#define I40E_GLQF_PCNT_PCNT_MASK (0xFFFFFFFF << I40E_GLQF_PCNT_PCNT_SHIFT) 2125#define I40E_GLQF_PCNT_PCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT)
3316#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ 2126#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
3317#define I40E_GLQF_SWAP_MAX_INDEX 1 2127#define I40E_GLQF_SWAP_MAX_INDEX 1
3318#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0 2128#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0
3319#define I40E_GLQF_SWAP_OFF0_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT) 2129#define I40E_GLQF_SWAP_OFF0_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)
3320#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6 2130#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6
3321#define I40E_GLQF_SWAP_OFF0_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC1_SHIFT) 2131#define I40E_GLQF_SWAP_OFF0_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT)
3322#define I40E_GLQF_SWAP_FLEN0_SHIFT 12 2132#define I40E_GLQF_SWAP_FLEN0_SHIFT 12
3323#define I40E_GLQF_SWAP_FLEN0_MASK (0xF << I40E_GLQF_SWAP_FLEN0_SHIFT) 2133#define I40E_GLQF_SWAP_FLEN0_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT)
3324#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16 2134#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16
3325#define I40E_GLQF_SWAP_OFF1_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC0_SHIFT) 2135#define I40E_GLQF_SWAP_OFF1_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT)
3326#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22 2136#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22
3327#define I40E_GLQF_SWAP_OFF1_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC1_SHIFT) 2137#define I40E_GLQF_SWAP_OFF1_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)
3328#define I40E_GLQF_SWAP_FLEN1_SHIFT 28 2138#define I40E_GLQF_SWAP_FLEN1_SHIFT 28
3329#define I40E_GLQF_SWAP_FLEN1_MASK (0xF << I40E_GLQF_SWAP_FLEN1_SHIFT) 2139#define I40E_GLQF_SWAP_FLEN1_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT)
3330#define I40E_PFQF_CTL_0 0x001C0AC0 2140#define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */
3331#define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 2141#define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0
3332#define I40E_PFQF_CTL_0_PEHSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) 2142#define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
3333#define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 2143#define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5
3334#define I40E_PFQF_CTL_0_PEDSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) 2144#define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT)
3335#define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 2145#define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10
3336#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) 2146#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT)
3337#define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 2147#define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14
3338#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) 2148#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT)
3339#define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 2149#define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16
3340#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK (0x1 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) 2150#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT)
3341#define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 2151#define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17
3342#define I40E_PFQF_CTL_0_FD_ENA_MASK (0x1 << I40E_PFQF_CTL_0_FD_ENA_SHIFT) 2152#define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT)
3343#define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 2153#define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18
3344#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK (0x1 << I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 2154#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)
3345#define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 2155#define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19
3346#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK (0x1 << I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 2156#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)
3347#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20 2157#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20
3348#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT) 2158#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)
3349#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24 2159#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24
3350#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT) 2160#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)
3351#define I40E_PFQF_CTL_1 0x00245D80 2161#define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */
3352#define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 2162#define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0
3353#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK (0x1 << I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 2163#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
3354#define I40E_PFQF_FDALLOC 0x00246280 2164#define I40E_PFQF_FDALLOC 0x00246280 /* Reset: CORER */
3355#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0 2165#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0
3356#define I40E_PFQF_FDALLOC_FDALLOC_MASK (0xFF << I40E_PFQF_FDALLOC_FDALLOC_SHIFT) 2166#define I40E_PFQF_FDALLOC_FDALLOC_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT)
3357#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8 2167#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8
3358#define I40E_PFQF_FDALLOC_FDBEST_MASK (0xFF << I40E_PFQF_FDALLOC_FDBEST_SHIFT) 2168#define I40E_PFQF_FDALLOC_FDBEST_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT)
3359#define I40E_PFQF_FDSTAT 0x00246380 2169#define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */
3360#define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 2170#define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0
3361#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 2171#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
3362#define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 2172#define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16
3363#define I40E_PFQF_FDSTAT_BEST_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 2173#define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
3364#define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ 2174#define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */
3365#define I40E_PFQF_HENA_MAX_INDEX 1 2175#define I40E_PFQF_HENA_MAX_INDEX 1
3366#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0 2176#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0
3367#define I40E_PFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_PFQF_HENA_PTYPE_ENA_SHIFT) 2177#define I40E_PFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT)
3368#define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ 2178#define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */
3369#define I40E_PFQF_HKEY_MAX_INDEX 12 2179#define I40E_PFQF_HKEY_MAX_INDEX 12
3370#define I40E_PFQF_HKEY_KEY_0_SHIFT 0 2180#define I40E_PFQF_HKEY_KEY_0_SHIFT 0
3371#define I40E_PFQF_HKEY_KEY_0_MASK (0xFF << I40E_PFQF_HKEY_KEY_0_SHIFT) 2181#define I40E_PFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT)
3372#define I40E_PFQF_HKEY_KEY_1_SHIFT 8 2182#define I40E_PFQF_HKEY_KEY_1_SHIFT 8
3373#define I40E_PFQF_HKEY_KEY_1_MASK (0xFF << I40E_PFQF_HKEY_KEY_1_SHIFT) 2183#define I40E_PFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_1_SHIFT)
3374#define I40E_PFQF_HKEY_KEY_2_SHIFT 16 2184#define I40E_PFQF_HKEY_KEY_2_SHIFT 16
3375#define I40E_PFQF_HKEY_KEY_2_MASK (0xFF << I40E_PFQF_HKEY_KEY_2_SHIFT) 2185#define I40E_PFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT)
3376#define I40E_PFQF_HKEY_KEY_3_SHIFT 24 2186#define I40E_PFQF_HKEY_KEY_3_SHIFT 24
3377#define I40E_PFQF_HKEY_KEY_3_MASK (0xFF << I40E_PFQF_HKEY_KEY_3_SHIFT) 2187#define I40E_PFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT)
3378#define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ 2188#define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */
3379#define I40E_PFQF_HLUT_MAX_INDEX 127 2189#define I40E_PFQF_HLUT_MAX_INDEX 127
3380#define I40E_PFQF_HLUT_LUT0_SHIFT 0 2190#define I40E_PFQF_HLUT_LUT0_SHIFT 0
3381#define I40E_PFQF_HLUT_LUT0_MASK (0x3F << I40E_PFQF_HLUT_LUT0_SHIFT) 2191#define I40E_PFQF_HLUT_LUT0_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT)
3382#define I40E_PFQF_HLUT_LUT1_SHIFT 8 2192#define I40E_PFQF_HLUT_LUT1_SHIFT 8
3383#define I40E_PFQF_HLUT_LUT1_MASK (0x3F << I40E_PFQF_HLUT_LUT1_SHIFT) 2193#define I40E_PFQF_HLUT_LUT1_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT1_SHIFT)
3384#define I40E_PFQF_HLUT_LUT2_SHIFT 16 2194#define I40E_PFQF_HLUT_LUT2_SHIFT 16
3385#define I40E_PFQF_HLUT_LUT2_MASK (0x3F << I40E_PFQF_HLUT_LUT2_SHIFT) 2195#define I40E_PFQF_HLUT_LUT2_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT)
3386#define I40E_PFQF_HLUT_LUT3_SHIFT 24 2196#define I40E_PFQF_HLUT_LUT3_SHIFT 24
3387#define I40E_PFQF_HLUT_LUT3_MASK (0x3F << I40E_PFQF_HLUT_LUT3_SHIFT) 2197#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)
3388#define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */ 2198#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */
3389#define I40E_PFQF_HREGION_MAX_INDEX 7
3390#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
3391#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
3392#define I40E_PFQF_HREGION_REGION_0_SHIFT 1
3393#define I40E_PFQF_HREGION_REGION_0_MASK (0x7 << I40E_PFQF_HREGION_REGION_0_SHIFT)
3394#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
3395#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
3396#define I40E_PFQF_HREGION_REGION_1_SHIFT 5
3397#define I40E_PFQF_HREGION_REGION_1_MASK (0x7 << I40E_PFQF_HREGION_REGION_1_SHIFT)
3398#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
3399#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
3400#define I40E_PFQF_HREGION_REGION_2_SHIFT 9
3401#define I40E_PFQF_HREGION_REGION_2_MASK (0x7 << I40E_PFQF_HREGION_REGION_2_SHIFT)
3402#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
3403#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
3404#define I40E_PFQF_HREGION_REGION_3_SHIFT 13
3405#define I40E_PFQF_HREGION_REGION_3_MASK (0x7 << I40E_PFQF_HREGION_REGION_3_SHIFT)
3406#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
3407#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
3408#define I40E_PFQF_HREGION_REGION_4_SHIFT 17
3409#define I40E_PFQF_HREGION_REGION_4_MASK (0x7 << I40E_PFQF_HREGION_REGION_4_SHIFT)
3410#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
3411#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
3412#define I40E_PFQF_HREGION_REGION_5_SHIFT 21
3413#define I40E_PFQF_HREGION_REGION_5_MASK (0x7 << I40E_PFQF_HREGION_REGION_5_SHIFT)
3414#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
3415#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
3416#define I40E_PFQF_HREGION_REGION_6_SHIFT 25
3417#define I40E_PFQF_HREGION_REGION_6_MASK (0x7 << I40E_PFQF_HREGION_REGION_6_SHIFT)
3418#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
3419#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
3420#define I40E_PFQF_HREGION_REGION_7_SHIFT 29
3421#define I40E_PFQF_HREGION_REGION_7_MASK (0x7 << I40E_PFQF_HREGION_REGION_7_SHIFT)
3422#define I40E_PRTQF_CTL_0 0x00256E60
3423#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0 2199#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0
3424#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK (0x1 << I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT) 2200#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)
3425#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ 2201#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */
3426#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63 2202#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63
3427#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0 2203#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0
3428#define I40E_PRTQF_FD_FLXINSET_INSET_MASK (0xFF << I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) 2204#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
3429#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ 2205#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
3430#define I40E_PRTQF_FD_MSK_MAX_INDEX 63 2206#define I40E_PRTQF_FD_MSK_MAX_INDEX 63
3431#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0 2207#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0
3432#define I40E_PRTQF_FD_MSK_MASK_MASK (0xFFFF << I40E_PRTQF_FD_MSK_MASK_SHIFT) 2208#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)
3433#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16 2209#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16
3434#define I40E_PRTQF_FD_MSK_OFFSET_MASK (0x3F << I40E_PRTQF_FD_MSK_OFFSET_SHIFT) 2210#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)
3435#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ 2211#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */
3436#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8 2212#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8
3437#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 2213#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0
3438#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK (0x1F << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 2214#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
3439#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 2215#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5
3440#define I40E_PRTQF_FLX_PIT_FSIZE_MASK (0x1F << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 2216#define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
3441#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 2217#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10
3442#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK (0x3F << I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 2218#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
3443#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) 2219#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */
3444#define I40E_VFQF_HENA1_MAX_INDEX 1 2220#define I40E_VFQF_HENA1_MAX_INDEX 1
3445#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0 2221#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0
3446#define I40E_VFQF_HENA1_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA1_PTYPE_ENA_SHIFT) 2222#define I40E_VFQF_HENA1_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT)
3447#define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ 2223#define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */
3448#define I40E_VFQF_HKEY1_MAX_INDEX 12 2224#define I40E_VFQF_HKEY1_MAX_INDEX 12
3449#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0 2225#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0
3450#define I40E_VFQF_HKEY1_KEY_0_MASK (0xFF << I40E_VFQF_HKEY1_KEY_0_SHIFT) 2226#define I40E_VFQF_HKEY1_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT)
3451#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8 2227#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8
3452#define I40E_VFQF_HKEY1_KEY_1_MASK (0xFF << I40E_VFQF_HKEY1_KEY_1_SHIFT) 2228#define I40E_VFQF_HKEY1_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_1_SHIFT)
3453#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16 2229#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16
3454#define I40E_VFQF_HKEY1_KEY_2_MASK (0xFF << I40E_VFQF_HKEY1_KEY_2_SHIFT) 2230#define I40E_VFQF_HKEY1_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT)
3455#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24 2231#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24
3456#define I40E_VFQF_HKEY1_KEY_3_MASK (0xFF << I40E_VFQF_HKEY1_KEY_3_SHIFT) 2232#define I40E_VFQF_HKEY1_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT)
3457#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ 2233#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
3458#define I40E_VFQF_HLUT1_MAX_INDEX 15 2234#define I40E_VFQF_HLUT1_MAX_INDEX 15
3459#define I40E_VFQF_HLUT1_LUT0_SHIFT 0 2235#define I40E_VFQF_HLUT1_LUT0_SHIFT 0
3460#define I40E_VFQF_HLUT1_LUT0_MASK (0xF << I40E_VFQF_HLUT1_LUT0_SHIFT) 2236#define I40E_VFQF_HLUT1_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT)
3461#define I40E_VFQF_HLUT1_LUT1_SHIFT 8 2237#define I40E_VFQF_HLUT1_LUT1_SHIFT 8
3462#define I40E_VFQF_HLUT1_LUT1_MASK (0xF << I40E_VFQF_HLUT1_LUT1_SHIFT) 2238#define I40E_VFQF_HLUT1_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT1_SHIFT)
3463#define I40E_VFQF_HLUT1_LUT2_SHIFT 16 2239#define I40E_VFQF_HLUT1_LUT2_SHIFT 16
3464#define I40E_VFQF_HLUT1_LUT2_MASK (0xF << I40E_VFQF_HLUT1_LUT2_SHIFT) 2240#define I40E_VFQF_HLUT1_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT)
3465#define I40E_VFQF_HLUT1_LUT3_SHIFT 24 2241#define I40E_VFQF_HLUT1_LUT3_SHIFT 24
3466#define I40E_VFQF_HLUT1_LUT3_MASK (0xF << I40E_VFQF_HLUT1_LUT3_SHIFT) 2242#define I40E_VFQF_HLUT1_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT)
3467#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) 2243#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */
3468#define I40E_VFQF_HREGION1_MAX_INDEX 7 2244#define I40E_VFQF_HREGION1_MAX_INDEX 7
3469#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0 2245#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0
3470#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT) 2246#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT)
3471#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1 2247#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1
3472#define I40E_VFQF_HREGION1_REGION_0_MASK (0x7 << I40E_VFQF_HREGION1_REGION_0_SHIFT) 2248#define I40E_VFQF_HREGION1_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_0_SHIFT)
3473#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4 2249#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4
3474#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT) 2250#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT)
3475#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5 2251#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5
3476#define I40E_VFQF_HREGION1_REGION_1_MASK (0x7 << I40E_VFQF_HREGION1_REGION_1_SHIFT) 2252#define I40E_VFQF_HREGION1_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_1_SHIFT)
3477#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8 2253#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8
3478#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT) 2254#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT)
3479#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9 2255#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9
3480#define I40E_VFQF_HREGION1_REGION_2_MASK (0x7 << I40E_VFQF_HREGION1_REGION_2_SHIFT) 2256#define I40E_VFQF_HREGION1_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_2_SHIFT)
3481#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12 2257#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12
3482#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT) 2258#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT)
3483#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13 2259#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13
3484#define I40E_VFQF_HREGION1_REGION_3_MASK (0x7 << I40E_VFQF_HREGION1_REGION_3_SHIFT) 2260#define I40E_VFQF_HREGION1_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_3_SHIFT)
3485#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16 2261#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16
3486#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT) 2262#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT)
3487#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17 2263#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17
3488#define I40E_VFQF_HREGION1_REGION_4_MASK (0x7 << I40E_VFQF_HREGION1_REGION_4_SHIFT) 2264#define I40E_VFQF_HREGION1_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_4_SHIFT)
3489#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20 2265#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20
3490#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT) 2266#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT)
3491#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21 2267#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21
3492#define I40E_VFQF_HREGION1_REGION_5_MASK (0x7 << I40E_VFQF_HREGION1_REGION_5_SHIFT) 2268#define I40E_VFQF_HREGION1_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_5_SHIFT)
3493#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24 2269#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24
3494#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT) 2270#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT)
3495#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25 2271#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25
3496#define I40E_VFQF_HREGION1_REGION_6_MASK (0x7 << I40E_VFQF_HREGION1_REGION_6_SHIFT) 2272#define I40E_VFQF_HREGION1_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_6_SHIFT)
3497#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28 2273#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28
3498#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT) 2274#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT)
3499#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29 2275#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29
3500#define I40E_VFQF_HREGION1_REGION_7_MASK (0x7 << I40E_VFQF_HREGION1_REGION_7_SHIFT) 2276#define I40E_VFQF_HREGION1_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT)
3501#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ 2277#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
3502#define I40E_VPQF_CTL_MAX_INDEX 127 2278#define I40E_VPQF_CTL_MAX_INDEX 127
3503#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0 2279#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0
3504#define I40E_VPQF_CTL_PEHSIZE_MASK (0x1F << I40E_VPQF_CTL_PEHSIZE_SHIFT) 2280#define I40E_VPQF_CTL_PEHSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT)
3505#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5 2281#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5
3506#define I40E_VPQF_CTL_PEDSIZE_MASK (0x1F << I40E_VPQF_CTL_PEDSIZE_SHIFT) 2282#define I40E_VPQF_CTL_PEDSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEDSIZE_SHIFT)
3507#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10 2283#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10
3508#define I40E_VPQF_CTL_FCHSIZE_MASK (0xF << I40E_VPQF_CTL_FCHSIZE_SHIFT) 2284#define I40E_VPQF_CTL_FCHSIZE_MASK I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT)
3509#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14 2285#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14
3510#define I40E_VPQF_CTL_FCDSIZE_MASK (0x3 << I40E_VPQF_CTL_FCDSIZE_SHIFT) 2286#define I40E_VPQF_CTL_FCDSIZE_MASK I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT)
3511#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ 2287#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
3512#define I40E_VSIQF_CTL_MAX_INDEX 383 2288#define I40E_VSIQF_CTL_MAX_INDEX 383
3513#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0 2289#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0
3514#define I40E_VSIQF_CTL_FCOE_ENA_MASK (0x1 << I40E_VSIQF_CTL_FCOE_ENA_SHIFT) 2290#define I40E_VSIQF_CTL_FCOE_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_FCOE_ENA_SHIFT)
3515#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1 2291#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1
3516#define I40E_VSIQF_CTL_PETCP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PETCP_ENA_SHIFT) 2292#define I40E_VSIQF_CTL_PETCP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PETCP_ENA_SHIFT)
3517#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2 2293#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2
3518#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT) 2294#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT)
3519#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3 2295#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3
3520#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT) 2296#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT)
3521#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4 2297#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4
3522#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT) 2298#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT)
3523#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5 2299#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5
3524#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT) 2300#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)
3525#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) 2301#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */
3526#define I40E_VSIQF_TCREGION_MAX_INDEX 3 2302#define I40E_VSIQF_TCREGION_MAX_INDEX 3
3527#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0 2303#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0
3528#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT) 2304#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)
3529#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9 2305#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9
3530#define I40E_VSIQF_TCREGION_TC_SIZE_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE_SHIFT) 2306#define I40E_VSIQF_TCREGION_TC_SIZE_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE_SHIFT)
3531#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16 2307#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16
3532#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT) 2308#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT)
3533#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25 2309#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25
3534#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT) 2310#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT)
3535#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ 2311#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3536#define I40E_GL_FCOECRC_MAX_INDEX 143 2312#define I40E_GL_FCOECRC_MAX_INDEX 143
3537#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0 2313#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0
3538#define I40E_GL_FCOECRC_FCOECRC_MASK (0xFFFFFFFF << I40E_GL_FCOECRC_FCOECRC_SHIFT) 2314#define I40E_GL_FCOECRC_FCOECRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT)
3539#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ 2315#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3540#define I40E_GL_FCOEDDPC_MAX_INDEX 143 2316#define I40E_GL_FCOEDDPC_MAX_INDEX 143
3541#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0 2317#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0
3542#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK (0xFFFFFFFF << I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT) 2318#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)
3543/* _i=0...143 */ 2319#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3544#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */
3545#define I40E_GL_FCOEDIFEC_MAX_INDEX 143 2320#define I40E_GL_FCOEDIFEC_MAX_INDEX 143
3546#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0 2321#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0
3547#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT) 2322#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT)
3548#define I40E_GL_FCOEDIFRC(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ 2323#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3549#define I40E_GL_FCOEDIFRC_MAX_INDEX 143
3550#define I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT 0
3551#define I40E_GL_FCOEDIFRC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT)
3552#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */
3553#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143 2324#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143
3554#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0 2325#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0
3555#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT) 2326#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT)
3556#define I40E_GL_FCOEDIXAC(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ 2327#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3557#define I40E_GL_FCOEDIXAC_MAX_INDEX 143
3558#define I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT 0
3559#define I40E_GL_FCOEDIXAC_FCOEDIXAC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT)
3560#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */
3561#define I40E_GL_FCOEDIXEC_MAX_INDEX 143 2328#define I40E_GL_FCOEDIXEC_MAX_INDEX 143
3562#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0 2329#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0
3563#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT) 2330#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT)
3564#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ 2331#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3565#define I40E_GL_FCOEDIXVC_MAX_INDEX 143 2332#define I40E_GL_FCOEDIXVC_MAX_INDEX 143
3566#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0 2333#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0
3567#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT) 2334#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT)
3568#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ 2335#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3569#define I40E_GL_FCOEDWRCH_MAX_INDEX 143 2336#define I40E_GL_FCOEDWRCH_MAX_INDEX 143
3570#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0 2337#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0
3571#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK (0xFFFF << I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT) 2338#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT)
3572#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ 2339#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3573#define I40E_GL_FCOEDWRCL_MAX_INDEX 143 2340#define I40E_GL_FCOEDWRCL_MAX_INDEX 143
3574#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0 2341#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0
3575#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT) 2342#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT)
3576#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ 2343#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3577#define I40E_GL_FCOEDWTCH_MAX_INDEX 143 2344#define I40E_GL_FCOEDWTCH_MAX_INDEX 143
3578#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0 2345#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0
3579#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK (0xFFFF << I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT) 2346#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT)
3580#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ 2347#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3581#define I40E_GL_FCOEDWTCL_MAX_INDEX 143 2348#define I40E_GL_FCOEDWTCL_MAX_INDEX 143
3582#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0 2349#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0
3583#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT) 2350#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT)
3584#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ 2351#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3585#define I40E_GL_FCOELAST_MAX_INDEX 143 2352#define I40E_GL_FCOELAST_MAX_INDEX 143
3586#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0 2353#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0
3587#define I40E_GL_FCOELAST_FCOELAST_MASK (0xFFFFFFFF << I40E_GL_FCOELAST_FCOELAST_SHIFT) 2354#define I40E_GL_FCOELAST_FCOELAST_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT)
3588#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ 2355#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3589#define I40E_GL_FCOEPRC_MAX_INDEX 143 2356#define I40E_GL_FCOEPRC_MAX_INDEX 143
3590#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0 2357#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0
3591#define I40E_GL_FCOEPRC_FCOEPRC_MASK (0xFFFFFFFF << I40E_GL_FCOEPRC_FCOEPRC_SHIFT) 2358#define I40E_GL_FCOEPRC_FCOEPRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT)
3592#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ 2359#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3593#define I40E_GL_FCOEPTC_MAX_INDEX 143 2360#define I40E_GL_FCOEPTC_MAX_INDEX 143
3594#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0 2361#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0
3595#define I40E_GL_FCOEPTC_FCOEPTC_MASK (0xFFFFFFFF << I40E_GL_FCOEPTC_FCOEPTC_SHIFT) 2362#define I40E_GL_FCOEPTC_FCOEPTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT)
3596#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ 2363#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
3597#define I40E_GL_FCOERPDC_MAX_INDEX 143 2364#define I40E_GL_FCOERPDC_MAX_INDEX 143
3598#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0 2365#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0
3599#define I40E_GL_FCOERPDC_FCOERPDC_MASK (0xFFFFFFFF << I40E_GL_FCOERPDC_FCOERPDC_SHIFT) 2366#define I40E_GL_FCOERPDC_FCOERPDC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT)
3600#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ 2367#define I40E_GL_RXERR1_L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2368#define I40E_GL_RXERR1_L_MAX_INDEX 143
2369#define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0
2370#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT)
2371#define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2372#define I40E_GL_RXERR2_L_MAX_INDEX 143
2373#define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0
2374#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
2375#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3601#define I40E_GLPRT_BPRCH_MAX_INDEX 3 2376#define I40E_GLPRT_BPRCH_MAX_INDEX 3
3602#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0 2377#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0
3603#define I40E_GLPRT_BPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPRCH_UPRCH_SHIFT) 2378#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_UPRCH_SHIFT)
3604#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ 2379#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3605#define I40E_GLPRT_BPRCL_MAX_INDEX 3 2380#define I40E_GLPRT_BPRCL_MAX_INDEX 3
3606#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0 2381#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0
3607#define I40E_GLPRT_BPRCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPRCL_UPRCH_SHIFT) 2382#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_UPRCH_SHIFT)
3608#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ 2383#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3609#define I40E_GLPRT_BPTCH_MAX_INDEX 3 2384#define I40E_GLPRT_BPTCH_MAX_INDEX 3
3610#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0 2385#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0
3611#define I40E_GLPRT_BPTCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPTCH_UPRCH_SHIFT) 2386#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_UPRCH_SHIFT)
3612#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ 2387#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3613#define I40E_GLPRT_BPTCL_MAX_INDEX 3 2388#define I40E_GLPRT_BPTCL_MAX_INDEX 3
3614#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0 2389#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0
3615#define I40E_GLPRT_BPTCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPTCL_UPRCH_SHIFT) 2390#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_UPRCH_SHIFT)
3616#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ 2391#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3617#define I40E_GLPRT_CRCERRS_MAX_INDEX 3 2392#define I40E_GLPRT_CRCERRS_MAX_INDEX 3
3618#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 2393#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0
3619#define I40E_GLPRT_CRCERRS_CRCERRS_MASK (0xFFFFFFFF << I40E_GLPRT_CRCERRS_CRCERRS_SHIFT) 2394#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT)
3620#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ 2395#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3621#define I40E_GLPRT_GORCH_MAX_INDEX 3 2396#define I40E_GLPRT_GORCH_MAX_INDEX 3
3622#define I40E_GLPRT_GORCH_GORCH_SHIFT 0 2397#define I40E_GLPRT_GORCH_GORCH_SHIFT 0
3623#define I40E_GLPRT_GORCH_GORCH_MASK (0xFFFF << I40E_GLPRT_GORCH_GORCH_SHIFT) 2398#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT)
3624#define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ 2399#define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3625#define I40E_GLPRT_GORCL_MAX_INDEX 3 2400#define I40E_GLPRT_GORCL_MAX_INDEX 3
3626#define I40E_GLPRT_GORCL_GORCL_SHIFT 0 2401#define I40E_GLPRT_GORCL_GORCL_SHIFT 0
3627#define I40E_GLPRT_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLPRT_GORCL_GORCL_SHIFT) 2402#define I40E_GLPRT_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT)
3628#define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ 2403#define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3629#define I40E_GLPRT_GOTCH_MAX_INDEX 3 2404#define I40E_GLPRT_GOTCH_MAX_INDEX 3
3630#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0 2405#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0
3631#define I40E_GLPRT_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLPRT_GOTCH_GOTCH_SHIFT) 2406#define I40E_GLPRT_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT)
3632#define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ 2407#define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3633#define I40E_GLPRT_GOTCL_MAX_INDEX 3 2408#define I40E_GLPRT_GOTCL_MAX_INDEX 3
3634#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0 2409#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0
3635#define I40E_GLPRT_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLPRT_GOTCL_GOTCL_SHIFT) 2410#define I40E_GLPRT_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT)
3636#define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ 2411#define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3637#define I40E_GLPRT_ILLERRC_MAX_INDEX 3 2412#define I40E_GLPRT_ILLERRC_MAX_INDEX 3
3638#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0 2413#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0
3639#define I40E_GLPRT_ILLERRC_ILLERRC_MASK (0xFFFFFFFF << I40E_GLPRT_ILLERRC_ILLERRC_SHIFT) 2414#define I40E_GLPRT_ILLERRC_ILLERRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT)
3640#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ 2415#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3641#define I40E_GLPRT_LDPC_MAX_INDEX 3 2416#define I40E_GLPRT_LDPC_MAX_INDEX 3
3642#define I40E_GLPRT_LDPC_LDPC_SHIFT 0 2417#define I40E_GLPRT_LDPC_LDPC_SHIFT 0
3643#define I40E_GLPRT_LDPC_LDPC_MASK (0xFFFFFFFF << I40E_GLPRT_LDPC_LDPC_SHIFT) 2418#define I40E_GLPRT_LDPC_LDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT)
3644#define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ 2419#define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3645#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3 2420#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3
3646#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0 2421#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0
3647#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT) 2422#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT)
3648#define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ 2423#define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3649#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3 2424#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3
3650#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0 2425#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0
3651#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT) 2426#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT)
3652#define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ 2427#define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3653#define I40E_GLPRT_LXONRXC_MAX_INDEX 3 2428#define I40E_GLPRT_LXONRXC_MAX_INDEX 3
3654#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0 2429#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0
3655#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT) 2430#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT)
3656#define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ 2431#define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3657#define I40E_GLPRT_LXONTXC_MAX_INDEX 3 2432#define I40E_GLPRT_LXONTXC_MAX_INDEX 3
3658#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0 2433#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0
3659#define I40E_GLPRT_LXONTXC_LXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXONTXC_LXONTXC_SHIFT) 2434#define I40E_GLPRT_LXONTXC_LXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT)
3660#define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ 2435#define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3661#define I40E_GLPRT_MLFC_MAX_INDEX 3 2436#define I40E_GLPRT_MLFC_MAX_INDEX 3
3662#define I40E_GLPRT_MLFC_MLFC_SHIFT 0 2437#define I40E_GLPRT_MLFC_MLFC_SHIFT 0
3663#define I40E_GLPRT_MLFC_MLFC_MASK (0xFFFFFFFF << I40E_GLPRT_MLFC_MLFC_SHIFT) 2438#define I40E_GLPRT_MLFC_MLFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT)
3664#define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ 2439#define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3665#define I40E_GLPRT_MPRCH_MAX_INDEX 3 2440#define I40E_GLPRT_MPRCH_MAX_INDEX 3
3666#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0 2441#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0
3667#define I40E_GLPRT_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLPRT_MPRCH_MPRCH_SHIFT) 2442#define I40E_GLPRT_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT)
3668#define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ 2443#define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3669#define I40E_GLPRT_MPRCL_MAX_INDEX 3 2444#define I40E_GLPRT_MPRCL_MAX_INDEX 3
3670#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0 2445#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0
3671#define I40E_GLPRT_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPRCL_MPRCL_SHIFT) 2446#define I40E_GLPRT_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT)
3672#define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ 2447#define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3673#define I40E_GLPRT_MPTCH_MAX_INDEX 3 2448#define I40E_GLPRT_MPTCH_MAX_INDEX 3
3674#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0 2449#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0
3675#define I40E_GLPRT_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLPRT_MPTCH_MPTCH_SHIFT) 2450#define I40E_GLPRT_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT)
3676#define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ 2451#define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3677#define I40E_GLPRT_MPTCL_MAX_INDEX 3 2452#define I40E_GLPRT_MPTCL_MAX_INDEX 3
3678#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0 2453#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0
3679#define I40E_GLPRT_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPTCL_MPTCL_SHIFT) 2454#define I40E_GLPRT_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT)
3680#define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ 2455#define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3681#define I40E_GLPRT_MRFC_MAX_INDEX 3 2456#define I40E_GLPRT_MRFC_MAX_INDEX 3
3682#define I40E_GLPRT_MRFC_MRFC_SHIFT 0 2457#define I40E_GLPRT_MRFC_MRFC_SHIFT 0
3683#define I40E_GLPRT_MRFC_MRFC_MASK (0xFFFFFFFF << I40E_GLPRT_MRFC_MRFC_SHIFT) 2458#define I40E_GLPRT_MRFC_MRFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT)
3684#define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ 2459#define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3685#define I40E_GLPRT_PRC1023H_MAX_INDEX 3 2460#define I40E_GLPRT_PRC1023H_MAX_INDEX 3
3686#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0 2461#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0
3687#define I40E_GLPRT_PRC1023H_PRC1023H_MASK (0xFFFF << I40E_GLPRT_PRC1023H_PRC1023H_SHIFT) 2462#define I40E_GLPRT_PRC1023H_PRC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT)
3688#define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ 2463#define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3689#define I40E_GLPRT_PRC1023L_MAX_INDEX 3 2464#define I40E_GLPRT_PRC1023L_MAX_INDEX 3
3690#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0 2465#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0
3691#define I40E_GLPRT_PRC1023L_PRC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1023L_PRC1023L_SHIFT) 2466#define I40E_GLPRT_PRC1023L_PRC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT)
3692#define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ 2467#define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3693#define I40E_GLPRT_PRC127H_MAX_INDEX 3 2468#define I40E_GLPRT_PRC127H_MAX_INDEX 3
3694#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0 2469#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0
3695#define I40E_GLPRT_PRC127H_PRC127H_MASK (0xFFFF << I40E_GLPRT_PRC127H_PRC127H_SHIFT) 2470#define I40E_GLPRT_PRC127H_PRC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT)
3696#define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ 2471#define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3697#define I40E_GLPRT_PRC127L_MAX_INDEX 3 2472#define I40E_GLPRT_PRC127L_MAX_INDEX 3
3698#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0 2473#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0
3699#define I40E_GLPRT_PRC127L_PRC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC127L_PRC127L_SHIFT) 2474#define I40E_GLPRT_PRC127L_PRC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT)
3700#define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ 2475#define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3701#define I40E_GLPRT_PRC1522H_MAX_INDEX 3 2476#define I40E_GLPRT_PRC1522H_MAX_INDEX 3
3702#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0 2477#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0
3703#define I40E_GLPRT_PRC1522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC1522H_PRC1522H_SHIFT) 2478#define I40E_GLPRT_PRC1522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT)
3704#define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ 2479#define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3705#define I40E_GLPRT_PRC1522L_MAX_INDEX 3 2480#define I40E_GLPRT_PRC1522L_MAX_INDEX 3
3706#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0 2481#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0
3707#define I40E_GLPRT_PRC1522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1522L_PRC1522L_SHIFT) 2482#define I40E_GLPRT_PRC1522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT)
3708#define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ 2483#define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3709#define I40E_GLPRT_PRC255H_MAX_INDEX 3 2484#define I40E_GLPRT_PRC255H_MAX_INDEX 3
3710#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0 2485#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0
3711#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK (0xFFFF << I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT) 2486#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT)
3712#define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ 2487#define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3713#define I40E_GLPRT_PRC255L_MAX_INDEX 3 2488#define I40E_GLPRT_PRC255L_MAX_INDEX 3
3714#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0 2489#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0
3715#define I40E_GLPRT_PRC255L_PRC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC255L_PRC255L_SHIFT) 2490#define I40E_GLPRT_PRC255L_PRC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT)
3716#define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ 2491#define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3717#define I40E_GLPRT_PRC511H_MAX_INDEX 3 2492#define I40E_GLPRT_PRC511H_MAX_INDEX 3
3718#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0 2493#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0
3719#define I40E_GLPRT_PRC511H_PRC511H_MASK (0xFFFF << I40E_GLPRT_PRC511H_PRC511H_SHIFT) 2494#define I40E_GLPRT_PRC511H_PRC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT)
3720#define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ 2495#define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3721#define I40E_GLPRT_PRC511L_MAX_INDEX 3 2496#define I40E_GLPRT_PRC511L_MAX_INDEX 3
3722#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0 2497#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0
3723#define I40E_GLPRT_PRC511L_PRC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC511L_PRC511L_SHIFT) 2498#define I40E_GLPRT_PRC511L_PRC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT)
3724#define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ 2499#define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3725#define I40E_GLPRT_PRC64H_MAX_INDEX 3 2500#define I40E_GLPRT_PRC64H_MAX_INDEX 3
3726#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0 2501#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0
3727#define I40E_GLPRT_PRC64H_PRC64H_MASK (0xFFFF << I40E_GLPRT_PRC64H_PRC64H_SHIFT) 2502#define I40E_GLPRT_PRC64H_PRC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT)
3728#define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ 2503#define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3729#define I40E_GLPRT_PRC64L_MAX_INDEX 3 2504#define I40E_GLPRT_PRC64L_MAX_INDEX 3
3730#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0 2505#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0
3731#define I40E_GLPRT_PRC64L_PRC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC64L_PRC64L_SHIFT) 2506#define I40E_GLPRT_PRC64L_PRC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT)
3732#define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ 2507#define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3733#define I40E_GLPRT_PRC9522H_MAX_INDEX 3 2508#define I40E_GLPRT_PRC9522H_MAX_INDEX 3
3734#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0 2509#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0
3735#define I40E_GLPRT_PRC9522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC9522H_PRC1522H_SHIFT) 2510#define I40E_GLPRT_PRC9522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT)
3736#define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ 2511#define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3737#define I40E_GLPRT_PRC9522L_MAX_INDEX 3 2512#define I40E_GLPRT_PRC9522L_MAX_INDEX 3
3738#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0 2513#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0
3739#define I40E_GLPRT_PRC9522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC9522L_PRC1522L_SHIFT) 2514#define I40E_GLPRT_PRC9522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT)
3740#define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ 2515#define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3741#define I40E_GLPRT_PTC1023H_MAX_INDEX 3 2516#define I40E_GLPRT_PTC1023H_MAX_INDEX 3
3742#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0 2517#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0
3743#define I40E_GLPRT_PTC1023H_PTC1023H_MASK (0xFFFF << I40E_GLPRT_PTC1023H_PTC1023H_SHIFT) 2518#define I40E_GLPRT_PTC1023H_PTC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT)
3744#define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ 2519#define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3745#define I40E_GLPRT_PTC1023L_MAX_INDEX 3 2520#define I40E_GLPRT_PTC1023L_MAX_INDEX 3
3746#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0 2521#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0
3747#define I40E_GLPRT_PTC1023L_PTC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1023L_PTC1023L_SHIFT) 2522#define I40E_GLPRT_PTC1023L_PTC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT)
3748#define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ 2523#define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3749#define I40E_GLPRT_PTC127H_MAX_INDEX 3 2524#define I40E_GLPRT_PTC127H_MAX_INDEX 3
3750#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0 2525#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0
3751#define I40E_GLPRT_PTC127H_PTC127H_MASK (0xFFFF << I40E_GLPRT_PTC127H_PTC127H_SHIFT) 2526#define I40E_GLPRT_PTC127H_PTC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT)
3752#define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ 2527#define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3753#define I40E_GLPRT_PTC127L_MAX_INDEX 3 2528#define I40E_GLPRT_PTC127L_MAX_INDEX 3
3754#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0 2529#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0
3755#define I40E_GLPRT_PTC127L_PTC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC127L_PTC127L_SHIFT) 2530#define I40E_GLPRT_PTC127L_PTC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT)
3756#define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ 2531#define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3757#define I40E_GLPRT_PTC1522H_MAX_INDEX 3 2532#define I40E_GLPRT_PTC1522H_MAX_INDEX 3
3758#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0 2533#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0
3759#define I40E_GLPRT_PTC1522H_PTC1522H_MASK (0xFFFF << I40E_GLPRT_PTC1522H_PTC1522H_SHIFT) 2534#define I40E_GLPRT_PTC1522H_PTC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT)
3760#define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ 2535#define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3761#define I40E_GLPRT_PTC1522L_MAX_INDEX 3 2536#define I40E_GLPRT_PTC1522L_MAX_INDEX 3
3762#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0 2537#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0
3763#define I40E_GLPRT_PTC1522L_PTC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1522L_PTC1522L_SHIFT) 2538#define I40E_GLPRT_PTC1522L_PTC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT)
3764#define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ 2539#define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3765#define I40E_GLPRT_PTC255H_MAX_INDEX 3 2540#define I40E_GLPRT_PTC255H_MAX_INDEX 3
3766#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0 2541#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0
3767#define I40E_GLPRT_PTC255H_PTC255H_MASK (0xFFFF << I40E_GLPRT_PTC255H_PTC255H_SHIFT) 2542#define I40E_GLPRT_PTC255H_PTC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT)
3768#define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ 2543#define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3769#define I40E_GLPRT_PTC255L_MAX_INDEX 3 2544#define I40E_GLPRT_PTC255L_MAX_INDEX 3
3770#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0 2545#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0
3771#define I40E_GLPRT_PTC255L_PTC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC255L_PTC255L_SHIFT) 2546#define I40E_GLPRT_PTC255L_PTC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT)
3772#define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ 2547#define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3773#define I40E_GLPRT_PTC511H_MAX_INDEX 3 2548#define I40E_GLPRT_PTC511H_MAX_INDEX 3
3774#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0 2549#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0
3775#define I40E_GLPRT_PTC511H_PTC511H_MASK (0xFFFF << I40E_GLPRT_PTC511H_PTC511H_SHIFT) 2550#define I40E_GLPRT_PTC511H_PTC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT)
3776#define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ 2551#define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3777#define I40E_GLPRT_PTC511L_MAX_INDEX 3 2552#define I40E_GLPRT_PTC511L_MAX_INDEX 3
3778#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0 2553#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0
3779#define I40E_GLPRT_PTC511L_PTC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC511L_PTC511L_SHIFT) 2554#define I40E_GLPRT_PTC511L_PTC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT)
3780#define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ 2555#define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3781#define I40E_GLPRT_PTC64H_MAX_INDEX 3 2556#define I40E_GLPRT_PTC64H_MAX_INDEX 3
3782#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0 2557#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0
3783#define I40E_GLPRT_PTC64H_PTC64H_MASK (0xFFFF << I40E_GLPRT_PTC64H_PTC64H_SHIFT) 2558#define I40E_GLPRT_PTC64H_PTC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT)
3784#define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ 2559#define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3785#define I40E_GLPRT_PTC64L_MAX_INDEX 3 2560#define I40E_GLPRT_PTC64L_MAX_INDEX 3
3786#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0 2561#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0
3787#define I40E_GLPRT_PTC64L_PTC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC64L_PTC64L_SHIFT) 2562#define I40E_GLPRT_PTC64L_PTC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT)
3788#define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ 2563#define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3789#define I40E_GLPRT_PTC9522H_MAX_INDEX 3 2564#define I40E_GLPRT_PTC9522H_MAX_INDEX 3
3790#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0 2565#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0
3791#define I40E_GLPRT_PTC9522H_PTC9522H_MASK (0xFFFF << I40E_GLPRT_PTC9522H_PTC9522H_SHIFT) 2566#define I40E_GLPRT_PTC9522H_PTC9522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT)
3792#define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ 2567#define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3793#define I40E_GLPRT_PTC9522L_MAX_INDEX 3 2568#define I40E_GLPRT_PTC9522L_MAX_INDEX 3
3794#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0 2569#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0
3795#define I40E_GLPRT_PTC9522L_PTC9522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC9522L_PTC9522L_SHIFT) 2570#define I40E_GLPRT_PTC9522L_PTC9522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT)
3796#define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) 2571#define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3797#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3 2572#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3
3798#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0 2573#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0
3799#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT) 2574#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT)
3800#define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) 2575#define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3801#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3 2576#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3
3802#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0 2577#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0
3803#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT) 2578#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT)
3804#define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) 2579#define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3805#define I40E_GLPRT_PXONRXC_MAX_INDEX 3 2580#define I40E_GLPRT_PXONRXC_MAX_INDEX 3
3806#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0 2581#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0
3807#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT) 2582#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT)
3808#define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) 2583#define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3809#define I40E_GLPRT_PXONTXC_MAX_INDEX 3 2584#define I40E_GLPRT_PXONTXC_MAX_INDEX 3
3810#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0 2585#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0
3811#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT) 2586#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT)
3812#define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ 2587#define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3813#define I40E_GLPRT_RDPC_MAX_INDEX 3 2588#define I40E_GLPRT_RDPC_MAX_INDEX 3
3814#define I40E_GLPRT_RDPC_RDPC_SHIFT 0 2589#define I40E_GLPRT_RDPC_RDPC_SHIFT 0
3815#define I40E_GLPRT_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLPRT_RDPC_RDPC_SHIFT) 2590#define I40E_GLPRT_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT)
3816#define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ 2591#define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3817#define I40E_GLPRT_RFC_MAX_INDEX 3 2592#define I40E_GLPRT_RFC_MAX_INDEX 3
3818#define I40E_GLPRT_RFC_RFC_SHIFT 0 2593#define I40E_GLPRT_RFC_RFC_SHIFT 0
3819#define I40E_GLPRT_RFC_RFC_MASK (0xFFFFFFFF << I40E_GLPRT_RFC_RFC_SHIFT) 2594#define I40E_GLPRT_RFC_RFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT)
3820#define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ 2595#define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3821#define I40E_GLPRT_RJC_MAX_INDEX 3 2596#define I40E_GLPRT_RJC_MAX_INDEX 3
3822#define I40E_GLPRT_RJC_RJC_SHIFT 0 2597#define I40E_GLPRT_RJC_RJC_SHIFT 0
3823#define I40E_GLPRT_RJC_RJC_MASK (0xFFFFFFFF << I40E_GLPRT_RJC_RJC_SHIFT) 2598#define I40E_GLPRT_RJC_RJC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT)
3824#define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ 2599#define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3825#define I40E_GLPRT_RLEC_MAX_INDEX 3 2600#define I40E_GLPRT_RLEC_MAX_INDEX 3
3826#define I40E_GLPRT_RLEC_RLEC_SHIFT 0 2601#define I40E_GLPRT_RLEC_RLEC_SHIFT 0
3827#define I40E_GLPRT_RLEC_RLEC_MASK (0xFFFFFFFF << I40E_GLPRT_RLEC_RLEC_SHIFT) 2602#define I40E_GLPRT_RLEC_RLEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT)
3828#define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ 2603#define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3829#define I40E_GLPRT_ROC_MAX_INDEX 3 2604#define I40E_GLPRT_ROC_MAX_INDEX 3
3830#define I40E_GLPRT_ROC_ROC_SHIFT 0 2605#define I40E_GLPRT_ROC_ROC_SHIFT 0
3831#define I40E_GLPRT_ROC_ROC_MASK (0xFFFFFFFF << I40E_GLPRT_ROC_ROC_SHIFT) 2606#define I40E_GLPRT_ROC_ROC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT)
3832#define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ 2607#define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3833#define I40E_GLPRT_RUC_MAX_INDEX 3 2608#define I40E_GLPRT_RUC_MAX_INDEX 3
3834#define I40E_GLPRT_RUC_RUC_SHIFT 0 2609#define I40E_GLPRT_RUC_RUC_SHIFT 0
3835#define I40E_GLPRT_RUC_RUC_MASK (0xFFFFFFFF << I40E_GLPRT_RUC_RUC_SHIFT) 2610#define I40E_GLPRT_RUC_RUC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT)
3836#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ 2611#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3837#define I40E_GLPRT_RUPP_MAX_INDEX 3 2612#define I40E_GLPRT_RUPP_MAX_INDEX 3
3838#define I40E_GLPRT_RUPP_RUPP_SHIFT 0 2613#define I40E_GLPRT_RUPP_RUPP_SHIFT 0
3839#define I40E_GLPRT_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLPRT_RUPP_RUPP_SHIFT) 2614#define I40E_GLPRT_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT)
3840#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) 2615#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
3841#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3 2616#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3
3842#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0 2617#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0
3843#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK (0xFFFFFFFF << I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT) 2618#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT)
3844#define I40E_GLPRT_STDC(_i) (0x00300640 + ((_i) * 8)) /* _i=0...3 */ 2619#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3845#define I40E_GLPRT_STDC_MAX_INDEX 3
3846#define I40E_GLPRT_STDC_STDC_SHIFT 0
3847#define I40E_GLPRT_STDC_STDC_MASK (0xFFFFFFFF << I40E_GLPRT_STDC_STDC_SHIFT)
3848#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */
3849#define I40E_GLPRT_TDOLD_MAX_INDEX 3 2620#define I40E_GLPRT_TDOLD_MAX_INDEX 3
3850#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 2621#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0
3851#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK (0xFFFFFFFF << I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) 2622#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
3852#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ 2623#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3853#define I40E_GLPRT_TDPC_MAX_INDEX 3 2624#define I40E_GLPRT_TDPC_MAX_INDEX 3
3854#define I40E_GLPRT_TDPC_TDPC_SHIFT 0 2625#define I40E_GLPRT_TDPC_TDPC_SHIFT 0
3855#define I40E_GLPRT_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLPRT_TDPC_TDPC_SHIFT) 2626#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDPC_TDPC_SHIFT)
3856#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ 2627#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3857#define I40E_GLPRT_UPRCH_MAX_INDEX 3 2628#define I40E_GLPRT_UPRCH_MAX_INDEX 3
3858#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 2629#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
3859#define I40E_GLPRT_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_UPRCH_UPRCH_SHIFT) 2630#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT)
3860#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ 2631#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3861#define I40E_GLPRT_UPRCL_MAX_INDEX 3 2632#define I40E_GLPRT_UPRCL_MAX_INDEX 3
3862#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0 2633#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0
3863#define I40E_GLPRT_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_UPRCL_UPRCL_SHIFT) 2634#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT)
3864#define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ 2635#define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3865#define I40E_GLPRT_UPTCH_MAX_INDEX 3 2636#define I40E_GLPRT_UPTCH_MAX_INDEX 3
3866#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0 2637#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0
3867#define I40E_GLPRT_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLPRT_UPTCH_UPTCH_SHIFT) 2638#define I40E_GLPRT_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT)
3868#define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ 2639#define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
3869#define I40E_GLPRT_UPTCL_MAX_INDEX 3 2640#define I40E_GLPRT_UPTCL_MAX_INDEX 3
3870#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0 2641#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0
3871#define I40E_GLPRT_UPTCL_VUPTCH_MASK (0xFFFFFFFF << I40E_GLPRT_UPTCL_VUPTCH_SHIFT) 2642#define I40E_GLPRT_UPTCL_VUPTCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT)
3872#define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ 2643#define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3873#define I40E_GLSW_BPRCH_MAX_INDEX 15 2644#define I40E_GLSW_BPRCH_MAX_INDEX 15
3874#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0 2645#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0
3875#define I40E_GLSW_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLSW_BPRCH_BPRCH_SHIFT) 2646#define I40E_GLSW_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT)
3876#define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ 2647#define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3877#define I40E_GLSW_BPRCL_MAX_INDEX 15 2648#define I40E_GLSW_BPRCL_MAX_INDEX 15
3878#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0 2649#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0
3879#define I40E_GLSW_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLSW_BPRCL_BPRCL_SHIFT) 2650#define I40E_GLSW_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT)
3880#define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ 2651#define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3881#define I40E_GLSW_BPTCH_MAX_INDEX 15 2652#define I40E_GLSW_BPTCH_MAX_INDEX 15
3882#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0 2653#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0
3883#define I40E_GLSW_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLSW_BPTCH_BPTCH_SHIFT) 2654#define I40E_GLSW_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT)
3884#define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ 2655#define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3885#define I40E_GLSW_BPTCL_MAX_INDEX 15 2656#define I40E_GLSW_BPTCL_MAX_INDEX 15
3886#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0 2657#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0
3887#define I40E_GLSW_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLSW_BPTCL_BPTCL_SHIFT) 2658#define I40E_GLSW_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT)
3888#define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ 2659#define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3889#define I40E_GLSW_GORCH_MAX_INDEX 15 2660#define I40E_GLSW_GORCH_MAX_INDEX 15
3890#define I40E_GLSW_GORCH_GORCH_SHIFT 0 2661#define I40E_GLSW_GORCH_GORCH_SHIFT 0
3891#define I40E_GLSW_GORCH_GORCH_MASK (0xFFFF << I40E_GLSW_GORCH_GORCH_SHIFT) 2662#define I40E_GLSW_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT)
3892#define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ 2663#define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3893#define I40E_GLSW_GORCL_MAX_INDEX 15 2664#define I40E_GLSW_GORCL_MAX_INDEX 15
3894#define I40E_GLSW_GORCL_GORCL_SHIFT 0 2665#define I40E_GLSW_GORCL_GORCL_SHIFT 0
3895#define I40E_GLSW_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLSW_GORCL_GORCL_SHIFT) 2666#define I40E_GLSW_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT)
3896#define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ 2667#define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3897#define I40E_GLSW_GOTCH_MAX_INDEX 15 2668#define I40E_GLSW_GOTCH_MAX_INDEX 15
3898#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0 2669#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0
3899#define I40E_GLSW_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLSW_GOTCH_GOTCH_SHIFT) 2670#define I40E_GLSW_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT)
3900#define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ 2671#define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3901#define I40E_GLSW_GOTCL_MAX_INDEX 15 2672#define I40E_GLSW_GOTCL_MAX_INDEX 15
3902#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0 2673#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0
3903#define I40E_GLSW_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLSW_GOTCL_GOTCL_SHIFT) 2674#define I40E_GLSW_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT)
3904#define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ 2675#define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3905#define I40E_GLSW_MPRCH_MAX_INDEX 15 2676#define I40E_GLSW_MPRCH_MAX_INDEX 15
3906#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0 2677#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0
3907#define I40E_GLSW_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLSW_MPRCH_MPRCH_SHIFT) 2678#define I40E_GLSW_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT)
3908#define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ 2679#define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3909#define I40E_GLSW_MPRCL_MAX_INDEX 15 2680#define I40E_GLSW_MPRCL_MAX_INDEX 15
3910#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0 2681#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0
3911#define I40E_GLSW_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLSW_MPRCL_MPRCL_SHIFT) 2682#define I40E_GLSW_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT)
3912#define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ 2683#define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3913#define I40E_GLSW_MPTCH_MAX_INDEX 15 2684#define I40E_GLSW_MPTCH_MAX_INDEX 15
3914#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0 2685#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0
3915#define I40E_GLSW_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLSW_MPTCH_MPTCH_SHIFT) 2686#define I40E_GLSW_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT)
3916#define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ 2687#define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3917#define I40E_GLSW_MPTCL_MAX_INDEX 15 2688#define I40E_GLSW_MPTCL_MAX_INDEX 15
3918#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0 2689#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0
3919#define I40E_GLSW_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLSW_MPTCL_MPTCL_SHIFT) 2690#define I40E_GLSW_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT)
3920#define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ 2691#define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3921#define I40E_GLSW_RUPP_MAX_INDEX 15 2692#define I40E_GLSW_RUPP_MAX_INDEX 15
3922#define I40E_GLSW_RUPP_RUPP_SHIFT 0 2693#define I40E_GLSW_RUPP_RUPP_SHIFT 0
3923#define I40E_GLSW_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLSW_RUPP_RUPP_SHIFT) 2694#define I40E_GLSW_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT)
3924#define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ 2695#define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3925#define I40E_GLSW_TDPC_MAX_INDEX 15 2696#define I40E_GLSW_TDPC_MAX_INDEX 15
3926#define I40E_GLSW_TDPC_TDPC_SHIFT 0 2697#define I40E_GLSW_TDPC_TDPC_SHIFT 0
3927#define I40E_GLSW_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLSW_TDPC_TDPC_SHIFT) 2698#define I40E_GLSW_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT)
3928#define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ 2699#define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3929#define I40E_GLSW_UPRCH_MAX_INDEX 15 2700#define I40E_GLSW_UPRCH_MAX_INDEX 15
3930#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0 2701#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0
3931#define I40E_GLSW_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLSW_UPRCH_UPRCH_SHIFT) 2702#define I40E_GLSW_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT)
3932#define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ 2703#define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3933#define I40E_GLSW_UPRCL_MAX_INDEX 15 2704#define I40E_GLSW_UPRCL_MAX_INDEX 15
3934#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0 2705#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0
3935#define I40E_GLSW_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLSW_UPRCL_UPRCL_SHIFT) 2706#define I40E_GLSW_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT)
3936#define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ 2707#define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3937#define I40E_GLSW_UPTCH_MAX_INDEX 15 2708#define I40E_GLSW_UPTCH_MAX_INDEX 15
3938#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0 2709#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0
3939#define I40E_GLSW_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLSW_UPTCH_UPTCH_SHIFT) 2710#define I40E_GLSW_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT)
3940#define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ 2711#define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
3941#define I40E_GLSW_UPTCL_MAX_INDEX 15 2712#define I40E_GLSW_UPTCL_MAX_INDEX 15
3942#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0 2713#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0
3943#define I40E_GLSW_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLSW_UPTCL_UPTCL_SHIFT) 2714#define I40E_GLSW_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT)
3944#define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ 2715#define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3945#define I40E_GLV_BPRCH_MAX_INDEX 383 2716#define I40E_GLV_BPRCH_MAX_INDEX 383
3946#define I40E_GLV_BPRCH_BPRCH_SHIFT 0 2717#define I40E_GLV_BPRCH_BPRCH_SHIFT 0
3947#define I40E_GLV_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLV_BPRCH_BPRCH_SHIFT) 2718#define I40E_GLV_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT)
3948#define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ 2719#define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3949#define I40E_GLV_BPRCL_MAX_INDEX 383 2720#define I40E_GLV_BPRCL_MAX_INDEX 383
3950#define I40E_GLV_BPRCL_BPRCL_SHIFT 0 2721#define I40E_GLV_BPRCL_BPRCL_SHIFT 0
3951#define I40E_GLV_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLV_BPRCL_BPRCL_SHIFT) 2722#define I40E_GLV_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT)
3952#define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ 2723#define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3953#define I40E_GLV_BPTCH_MAX_INDEX 383 2724#define I40E_GLV_BPTCH_MAX_INDEX 383
3954#define I40E_GLV_BPTCH_BPTCH_SHIFT 0 2725#define I40E_GLV_BPTCH_BPTCH_SHIFT 0
3955#define I40E_GLV_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLV_BPTCH_BPTCH_SHIFT) 2726#define I40E_GLV_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT)
3956#define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ 2727#define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3957#define I40E_GLV_BPTCL_MAX_INDEX 383 2728#define I40E_GLV_BPTCL_MAX_INDEX 383
3958#define I40E_GLV_BPTCL_BPTCL_SHIFT 0 2729#define I40E_GLV_BPTCL_BPTCL_SHIFT 0
3959#define I40E_GLV_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLV_BPTCL_BPTCL_SHIFT) 2730#define I40E_GLV_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT)
3960#define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ 2731#define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3961#define I40E_GLV_GORCH_MAX_INDEX 383 2732#define I40E_GLV_GORCH_MAX_INDEX 383
3962#define I40E_GLV_GORCH_GORCH_SHIFT 0 2733#define I40E_GLV_GORCH_GORCH_SHIFT 0
3963#define I40E_GLV_GORCH_GORCH_MASK (0xFFFF << I40E_GLV_GORCH_GORCH_SHIFT) 2734#define I40E_GLV_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT)
3964#define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ 2735#define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3965#define I40E_GLV_GORCL_MAX_INDEX 383 2736#define I40E_GLV_GORCL_MAX_INDEX 383
3966#define I40E_GLV_GORCL_GORCL_SHIFT 0 2737#define I40E_GLV_GORCL_GORCL_SHIFT 0
3967#define I40E_GLV_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLV_GORCL_GORCL_SHIFT) 2738#define I40E_GLV_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT)
3968#define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ 2739#define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3969#define I40E_GLV_GOTCH_MAX_INDEX 383 2740#define I40E_GLV_GOTCH_MAX_INDEX 383
3970#define I40E_GLV_GOTCH_GOTCH_SHIFT 0 2741#define I40E_GLV_GOTCH_GOTCH_SHIFT 0
3971#define I40E_GLV_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLV_GOTCH_GOTCH_SHIFT) 2742#define I40E_GLV_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT)
3972#define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ 2743#define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3973#define I40E_GLV_GOTCL_MAX_INDEX 383 2744#define I40E_GLV_GOTCL_MAX_INDEX 383
3974#define I40E_GLV_GOTCL_GOTCL_SHIFT 0 2745#define I40E_GLV_GOTCL_GOTCL_SHIFT 0
3975#define I40E_GLV_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLV_GOTCL_GOTCL_SHIFT) 2746#define I40E_GLV_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT)
3976#define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ 2747#define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3977#define I40E_GLV_MPRCH_MAX_INDEX 383 2748#define I40E_GLV_MPRCH_MAX_INDEX 383
3978#define I40E_GLV_MPRCH_MPRCH_SHIFT 0 2749#define I40E_GLV_MPRCH_MPRCH_SHIFT 0
3979#define I40E_GLV_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLV_MPRCH_MPRCH_SHIFT) 2750#define I40E_GLV_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT)
3980#define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ 2751#define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3981#define I40E_GLV_MPRCL_MAX_INDEX 383 2752#define I40E_GLV_MPRCL_MAX_INDEX 383
3982#define I40E_GLV_MPRCL_MPRCL_SHIFT 0 2753#define I40E_GLV_MPRCL_MPRCL_SHIFT 0
3983#define I40E_GLV_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLV_MPRCL_MPRCL_SHIFT) 2754#define I40E_GLV_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT)
3984#define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ 2755#define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3985#define I40E_GLV_MPTCH_MAX_INDEX 383 2756#define I40E_GLV_MPTCH_MAX_INDEX 383
3986#define I40E_GLV_MPTCH_MPTCH_SHIFT 0 2757#define I40E_GLV_MPTCH_MPTCH_SHIFT 0
3987#define I40E_GLV_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLV_MPTCH_MPTCH_SHIFT) 2758#define I40E_GLV_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT)
3988#define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ 2759#define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3989#define I40E_GLV_MPTCL_MAX_INDEX 383 2760#define I40E_GLV_MPTCL_MAX_INDEX 383
3990#define I40E_GLV_MPTCL_MPTCL_SHIFT 0 2761#define I40E_GLV_MPTCL_MPTCL_SHIFT 0
3991#define I40E_GLV_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLV_MPTCL_MPTCL_SHIFT) 2762#define I40E_GLV_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT)
3992#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ 2763#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3993#define I40E_GLV_RDPC_MAX_INDEX 383 2764#define I40E_GLV_RDPC_MAX_INDEX 383
3994#define I40E_GLV_RDPC_RDPC_SHIFT 0 2765#define I40E_GLV_RDPC_RDPC_SHIFT 0
3995#define I40E_GLV_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLV_RDPC_RDPC_SHIFT) 2766#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT)
3996#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ 2767#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
3997#define I40E_GLV_RUPP_MAX_INDEX 383 2768#define I40E_GLV_RUPP_MAX_INDEX 383
3998#define I40E_GLV_RUPP_RUPP_SHIFT 0 2769#define I40E_GLV_RUPP_RUPP_SHIFT 0
3999#define I40E_GLV_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLV_RUPP_RUPP_SHIFT) 2770#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT)
4000#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 8)) /* _i=0...383 */ 2771#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
4001#define I40E_GLV_TEPC_MAX_INDEX 383 2772#define I40E_GLV_TEPC_MAX_INDEX 383
4002#define I40E_GLV_TEPC_TEPC_SHIFT 0 2773#define I40E_GLV_TEPC_TEPC_SHIFT 0
4003#define I40E_GLV_TEPC_TEPC_MASK (0xFFFFFFFF << I40E_GLV_TEPC_TEPC_SHIFT) 2774#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT)
4004#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ 2775#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4005#define I40E_GLV_UPRCH_MAX_INDEX 383 2776#define I40E_GLV_UPRCH_MAX_INDEX 383
4006#define I40E_GLV_UPRCH_UPRCH_SHIFT 0 2777#define I40E_GLV_UPRCH_UPRCH_SHIFT 0
4007#define I40E_GLV_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLV_UPRCH_UPRCH_SHIFT) 2778#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT)
4008#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ 2779#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4009#define I40E_GLV_UPRCL_MAX_INDEX 383 2780#define I40E_GLV_UPRCL_MAX_INDEX 383
4010#define I40E_GLV_UPRCL_UPRCL_SHIFT 0 2781#define I40E_GLV_UPRCL_UPRCL_SHIFT 0
4011#define I40E_GLV_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLV_UPRCL_UPRCL_SHIFT) 2782#define I40E_GLV_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT)
4012#define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ 2783#define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4013#define I40E_GLV_UPTCH_MAX_INDEX 383 2784#define I40E_GLV_UPTCH_MAX_INDEX 383
4014#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0 2785#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0
4015#define I40E_GLV_UPTCH_GLVUPTCH_MASK (0xFFFF << I40E_GLV_UPTCH_GLVUPTCH_SHIFT) 2786#define I40E_GLV_UPTCH_GLVUPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT)
4016#define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ 2787#define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
4017#define I40E_GLV_UPTCL_MAX_INDEX 383 2788#define I40E_GLV_UPTCL_MAX_INDEX 383
4018#define I40E_GLV_UPTCL_UPTCL_SHIFT 0 2789#define I40E_GLV_UPTCL_UPTCL_SHIFT 0
4019#define I40E_GLV_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLV_UPTCL_UPTCL_SHIFT) 2790#define I40E_GLV_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT)
4020#define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2791#define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4021#define I40E_GLVEBTC_RBCH_MAX_INDEX 7 2792#define I40E_GLVEBTC_RBCH_MAX_INDEX 7
4022#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0 2793#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0
4023#define I40E_GLVEBTC_RBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_RBCH_TCBCH_SHIFT) 2794#define I40E_GLVEBTC_RBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT)
4024#define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2795#define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4025#define I40E_GLVEBTC_RBCL_MAX_INDEX 7 2796#define I40E_GLVEBTC_RBCL_MAX_INDEX 7
4026#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0 2797#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0
4027#define I40E_GLVEBTC_RBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RBCL_TCBCL_SHIFT) 2798#define I40E_GLVEBTC_RBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT)
4028#define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2799#define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4029#define I40E_GLVEBTC_RPCH_MAX_INDEX 7 2800#define I40E_GLVEBTC_RPCH_MAX_INDEX 7
4030#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0 2801#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0
4031#define I40E_GLVEBTC_RPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_RPCH_TCPCH_SHIFT) 2802#define I40E_GLVEBTC_RPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT)
4032#define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2803#define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4033#define I40E_GLVEBTC_RPCL_MAX_INDEX 7 2804#define I40E_GLVEBTC_RPCL_MAX_INDEX 7
4034#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0 2805#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0
4035#define I40E_GLVEBTC_RPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RPCL_TCPCL_SHIFT) 2806#define I40E_GLVEBTC_RPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT)
4036#define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2807#define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4037#define I40E_GLVEBTC_TBCH_MAX_INDEX 7 2808#define I40E_GLVEBTC_TBCH_MAX_INDEX 7
4038#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0 2809#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0
4039#define I40E_GLVEBTC_TBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_TBCH_TCBCH_SHIFT) 2810#define I40E_GLVEBTC_TBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT)
4040#define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2811#define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4041#define I40E_GLVEBTC_TBCL_MAX_INDEX 7 2812#define I40E_GLVEBTC_TBCL_MAX_INDEX 7
4042#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0 2813#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0
4043#define I40E_GLVEBTC_TBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TBCL_TCBCL_SHIFT) 2814#define I40E_GLVEBTC_TBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT)
4044#define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2815#define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4045#define I40E_GLVEBTC_TPCH_MAX_INDEX 7 2816#define I40E_GLVEBTC_TPCH_MAX_INDEX 7
4046#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0 2817#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0
4047#define I40E_GLVEBTC_TPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_TPCH_TCPCH_SHIFT) 2818#define I40E_GLVEBTC_TPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT)
4048#define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ 2819#define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
4049#define I40E_GLVEBTC_TPCL_MAX_INDEX 7 2820#define I40E_GLVEBTC_TPCL_MAX_INDEX 7
4050#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0 2821#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0
4051#define I40E_GLVEBTC_TPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TPCL_TCPCL_SHIFT) 2822#define I40E_GLVEBTC_TPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT)
4052#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ 2823#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4053#define I40E_GLVEBVL_BPCH_MAX_INDEX 127 2824#define I40E_GLVEBVL_BPCH_MAX_INDEX 127
4054#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0 2825#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0
4055#define I40E_GLVEBVL_BPCH_VLBPCH_MASK (0xFFFF << I40E_GLVEBVL_BPCH_VLBPCH_SHIFT) 2826#define I40E_GLVEBVL_BPCH_VLBPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT)
4056#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ 2827#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4057#define I40E_GLVEBVL_BPCL_MAX_INDEX 127 2828#define I40E_GLVEBVL_BPCL_MAX_INDEX 127
4058#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0 2829#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0
4059#define I40E_GLVEBVL_BPCL_VLBPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_BPCL_VLBPCL_SHIFT) 2830#define I40E_GLVEBVL_BPCL_VLBPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT)
4060#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ 2831#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4061#define I40E_GLVEBVL_GORCH_MAX_INDEX 127 2832#define I40E_GLVEBVL_GORCH_MAX_INDEX 127
4062#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0 2833#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0
4063#define I40E_GLVEBVL_GORCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GORCH_VLBCH_SHIFT) 2834#define I40E_GLVEBVL_GORCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT)
4064#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ 2835#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4065#define I40E_GLVEBVL_GORCL_MAX_INDEX 127 2836#define I40E_GLVEBVL_GORCL_MAX_INDEX 127
4066#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0 2837#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0
4067#define I40E_GLVEBVL_GORCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GORCL_VLBCL_SHIFT) 2838#define I40E_GLVEBVL_GORCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT)
4068#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ 2839#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4069#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127 2840#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127
4070#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0 2841#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0
4071#define I40E_GLVEBVL_GOTCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GOTCH_VLBCH_SHIFT) 2842#define I40E_GLVEBVL_GOTCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT)
4072#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ 2843#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4073#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127 2844#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127
4074#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0 2845#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0
4075#define I40E_GLVEBVL_GOTCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GOTCL_VLBCL_SHIFT) 2846#define I40E_GLVEBVL_GOTCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT)
4076#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ 2847#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4077#define I40E_GLVEBVL_MPCH_MAX_INDEX 127 2848#define I40E_GLVEBVL_MPCH_MAX_INDEX 127
4078#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0 2849#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0
4079#define I40E_GLVEBVL_MPCH_VLMPCH_MASK (0xFFFF << I40E_GLVEBVL_MPCH_VLMPCH_SHIFT) 2850#define I40E_GLVEBVL_MPCH_VLMPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT)
4080#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ 2851#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4081#define I40E_GLVEBVL_MPCL_MAX_INDEX 127 2852#define I40E_GLVEBVL_MPCL_MAX_INDEX 127
4082#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0 2853#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0
4083#define I40E_GLVEBVL_MPCL_VLMPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_MPCL_VLMPCL_SHIFT) 2854#define I40E_GLVEBVL_MPCL_VLMPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT)
4084#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ 2855#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4085#define I40E_GLVEBVL_UPCH_MAX_INDEX 127 2856#define I40E_GLVEBVL_UPCH_MAX_INDEX 127
4086#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0 2857#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0
4087#define I40E_GLVEBVL_UPCH_VLUPCH_MASK (0xFFFF << I40E_GLVEBVL_UPCH_VLUPCH_SHIFT) 2858#define I40E_GLVEBVL_UPCH_VLUPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT)
4088#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ 2859#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
4089#define I40E_GLVEBVL_UPCL_MAX_INDEX 127 2860#define I40E_GLVEBVL_UPCL_MAX_INDEX 127
4090#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0 2861#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0
4091#define I40E_GLVEBVL_UPCL_VLUPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_UPCL_VLUPCL_SHIFT) 2862#define I40E_GLVEBVL_UPCL_VLUPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT)
4092#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C 2863#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C /* Reset: CORER */
4093#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0 2864#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0
4094#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK (0xFFFF << I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT) 2865#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT)
4095#define I40E_GL_MTG_FLU_MSK_L 0x00269F44 2866#define I40E_GL_SWR_DEF_ACT(_i) (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */
4096#define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT 0 2867#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 35
4097#define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_MASK (0xFFFFFFFF << I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT)
4098#define I40E_GL_SWR_DEF_ACT(_i) (0x0026CF00 + ((_i) * 4)) /* _i=0...25 */
4099#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 25
4100#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0 2868#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0
4101#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT) 2869#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT)
4102#define I40E_GL_SWR_DEF_ACT_EN 0x0026CF84 2870#define I40E_GL_SWR_DEF_ACT_EN(_i) (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
2871#define I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX 1
4103#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0 2872#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0
4104#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT) 2873#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT)
4105#define I40E_PRT_MSCCNT 0x00256BA0 2874#define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */
4106#define I40E_PRT_MSCCNT_CCOUNT_SHIFT 0
4107#define I40E_PRT_MSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_MSCCNT_CCOUNT_SHIFT)
4108#define I40E_PRT_SCSTS 0x00256C20
4109#define I40E_PRT_SCSTS_BSCA_SHIFT 0
4110#define I40E_PRT_SCSTS_BSCA_MASK (0x1 << I40E_PRT_SCSTS_BSCA_SHIFT)
4111#define I40E_PRT_SCSTS_BSCAP_SHIFT 1
4112#define I40E_PRT_SCSTS_BSCAP_MASK (0x1 << I40E_PRT_SCSTS_BSCAP_SHIFT)
4113#define I40E_PRT_SCSTS_MSCA_SHIFT 2
4114#define I40E_PRT_SCSTS_MSCA_MASK (0x1 << I40E_PRT_SCSTS_MSCA_SHIFT)
4115#define I40E_PRT_SCSTS_MSCAP_SHIFT 3
4116#define I40E_PRT_SCSTS_MSCAP_MASK (0x1 << I40E_PRT_SCSTS_MSCAP_SHIFT)
4117#define I40E_PRT_SWT_BSCCNT 0x00256C60
4118#define I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT 0
4119#define I40E_PRT_SWT_BSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT)
4120#define I40E_PRTTSYN_ADJ 0x001E4280
4121#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0 2875#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0
4122#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK (0x7FFFFFFF << I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT) 2876#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT)
4123#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31 2877#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31
4124#define I40E_PRTTSYN_ADJ_SIGN_MASK (0x1 << I40E_PRTTSYN_ADJ_SIGN_SHIFT) 2878#define I40E_PRTTSYN_ADJ_SIGN_MASK I40E_MASK(0x1, I40E_PRTTSYN_ADJ_SIGN_SHIFT)
4125#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ 2879#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4126#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1 2880#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1
4127#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0 2881#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0
4128#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 2882#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
4129#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1 2883#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1
4130#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK (0x3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 2884#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
4131#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3 2885#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3
4132#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT) 2886#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT)
4133#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8 2887#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8
4134#define I40E_PRTTSYN_AUX_0_PULSEW_MASK (0xF << I40E_PRTTSYN_AUX_0_PULSEW_SHIFT) 2888#define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
4135#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 2889#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
4136#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK (0x3 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT) 2890#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
4137#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ 2891#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4138#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1 2892#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1
4139#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 2893#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0
4140#define I40E_PRTTSYN_AUX_1_INSTNT_MASK (0x1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 2894#define I40E_PRTTSYN_AUX_1_INSTNT_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
4141#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1 2895#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1
4142#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK (0x1 << I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT) 2896#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT)
4143#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ 2897#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4144#define I40E_PRTTSYN_CLKO_MAX_INDEX 1 2898#define I40E_PRTTSYN_CLKO_MAX_INDEX 1
4145#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0 2899#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0
4146#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK (0xFFFFFFFF << I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT) 2900#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT)
4147#define I40E_PRTTSYN_CTL0 0x001E4200 2901#define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */
4148#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0 2902#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0
4149#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK (0x1 << I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT) 2903#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT)
4150#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 2904#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1
4151#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 2905#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)
4152#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2 2906#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2
4153#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT) 2907#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)
4154#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3 2908#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3
4155#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT) 2909#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT)
4156#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 2910#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8
4157#define I40E_PRTTSYN_CTL0_PF_ID_MASK (0xF << I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 2911#define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT)
4158#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12 2912#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12
4159#define I40E_PRTTSYN_CTL0_TSYNACT_MASK (0x3 << I40E_PRTTSYN_CTL0_TSYNACT_SHIFT) 2913#define I40E_PRTTSYN_CTL0_TSYNACT_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT)
4160#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 2914#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31
4161#define I40E_PRTTSYN_CTL0_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 2915#define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)
4162#define I40E_PRTTSYN_CTL1 0x00085020 2916#define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */
4163#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 2917#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0
4164#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 2918#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)
4165#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8 2919#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8
4166#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT) 2920#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT)
4167#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 2921#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16
4168#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 2922#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)
4169#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20 2923#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20
4170#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT) 2924#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT)
4171#define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 2925#define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24
4172#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK (0x3 << I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 2926#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
4173#define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 2927#define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26
4174#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK (0x3 << I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 2928#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
4175#define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 2929#define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31
4176#define I40E_PRTTSYN_CTL1_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 2930#define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
4177#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ 2931#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4178#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1 2932#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1
4179#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0 2933#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0
4180#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT) 2934#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT)
4181#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ 2935#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4182#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1 2936#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1
4183#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0 2937#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0
4184#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT) 2938#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT)
4185#define I40E_PRTTSYN_INC_H 0x001E4060 2939#define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */
4186#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0 2940#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0
4187#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK (0x3F << I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT) 2941#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT)
4188#define I40E_PRTTSYN_INC_L 0x001E4040 2942#define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */
4189#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0 2943#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0
4190#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT) 2944#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT)
4191#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ 2945#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
4192#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3 2946#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3
4193#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0 2947#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0
4194#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT) 2948#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT)
4195#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ 2949#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
4196#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3 2950#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3
4197#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0 2951#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0
4198#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT) 2952#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT)
4199#define I40E_PRTTSYN_STAT_0 0x001E4220 2953#define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */
4200#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0 2954#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0
4201#define I40E_PRTTSYN_STAT_0_EVENT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT0_SHIFT) 2955#define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)
4202#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1 2956#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1
4203#define I40E_PRTTSYN_STAT_0_EVENT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT1_SHIFT) 2957#define I40E_PRTTSYN_STAT_0_EVENT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT1_SHIFT)
4204#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2 2958#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2
4205#define I40E_PRTTSYN_STAT_0_TGT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT0_SHIFT) 2959#define I40E_PRTTSYN_STAT_0_TGT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT0_SHIFT)
4206#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3 2960#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3
4207#define I40E_PRTTSYN_STAT_0_TGT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT1_SHIFT) 2961#define I40E_PRTTSYN_STAT_0_TGT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT1_SHIFT)
4208#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 2962#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4
4209#define I40E_PRTTSYN_STAT_0_TXTIME_MASK (0x1 << I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 2963#define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)
4210#define I40E_PRTTSYN_STAT_1 0x00085140 2964#define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */
4211#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0 2965#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0
4212#define I40E_PRTTSYN_STAT_1_RXT0_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT0_SHIFT) 2966#define I40E_PRTTSYN_STAT_1_RXT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT0_SHIFT)
4213#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1 2967#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1
4214#define I40E_PRTTSYN_STAT_1_RXT1_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT1_SHIFT) 2968#define I40E_PRTTSYN_STAT_1_RXT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT1_SHIFT)
4215#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2 2969#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2
4216#define I40E_PRTTSYN_STAT_1_RXT2_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT2_SHIFT) 2970#define I40E_PRTTSYN_STAT_1_RXT2_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT2_SHIFT)
4217#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3 2971#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3
4218#define I40E_PRTTSYN_STAT_1_RXT3_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT3_SHIFT) 2972#define I40E_PRTTSYN_STAT_1_RXT3_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT3_SHIFT)
4219#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ 2973#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4220#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1 2974#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1
4221#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0 2975#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0
4222#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT) 2976#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT)
4223#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ 2977#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
4224#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1 2978#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1
4225#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0 2979#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0
4226#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT) 2980#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT)
4227#define I40E_PRTTSYN_TIME_H 0x001E4120 2981#define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */
4228#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0 2982#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0
4229#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT) 2983#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT)
4230#define I40E_PRTTSYN_TIME_L 0x001E4100 2984#define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */
4231#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0 2985#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0
4232#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT) 2986#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT)
4233#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 2987#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */
4234#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0 2988#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0
4235#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT) 2989#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT)
4236#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 2990#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */
4237#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 2991#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0
4238#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) 2992#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
4239#define I40E_GLSCD_QUANTA 0x000B2080 2993#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */
4240#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0 2994#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0
4241#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK (0x7 << I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT) 2995#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7, I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)
4242#define I40E_GL_MDET_RX 0x0012A510 2996#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */
4243#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 2997#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
4244#define I40E_GL_MDET_RX_FUNCTION_MASK (0xFF << I40E_GL_MDET_RX_FUNCTION_SHIFT) 2998#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
4245#define I40E_GL_MDET_RX_EVENT_SHIFT 8 2999#define I40E_GL_MDET_RX_EVENT_SHIFT 8
4246#define I40E_GL_MDET_RX_EVENT_MASK (0x1FF << I40E_GL_MDET_RX_EVENT_SHIFT) 3000#define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT)
4247#define I40E_GL_MDET_RX_QUEUE_SHIFT 17 3001#define I40E_GL_MDET_RX_QUEUE_SHIFT 17
4248#define I40E_GL_MDET_RX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_RX_QUEUE_SHIFT) 3002#define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT)
4249#define I40E_GL_MDET_RX_VALID_SHIFT 31 3003#define I40E_GL_MDET_RX_VALID_SHIFT 31
4250#define I40E_GL_MDET_RX_VALID_MASK (0x1 << I40E_GL_MDET_RX_VALID_SHIFT) 3004#define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT)
4251#define I40E_GL_MDET_TX 0x000E6480 3005#define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */
4252#define I40E_GL_MDET_TX_FUNCTION_SHIFT 0 3006#define I40E_GL_MDET_TX_QUEUE_SHIFT 0
4253#define I40E_GL_MDET_TX_FUNCTION_MASK (0xFF << I40E_GL_MDET_TX_FUNCTION_SHIFT) 3007#define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT)
4254#define I40E_GL_MDET_TX_EVENT_SHIFT 8 3008#define I40E_GL_MDET_TX_VF_NUM_SHIFT 12
4255#define I40E_GL_MDET_TX_EVENT_MASK (0x1FF << I40E_GL_MDET_TX_EVENT_SHIFT) 3009#define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT)
4256#define I40E_GL_MDET_TX_QUEUE_SHIFT 17 3010#define I40E_GL_MDET_TX_PF_NUM_SHIFT 21
4257#define I40E_GL_MDET_TX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_TX_QUEUE_SHIFT) 3011#define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT)
3012#define I40E_GL_MDET_TX_EVENT_SHIFT 25
3013#define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT)
4258#define I40E_GL_MDET_TX_VALID_SHIFT 31 3014#define I40E_GL_MDET_TX_VALID_SHIFT 31
4259#define I40E_GL_MDET_TX_VALID_MASK (0x1 << I40E_GL_MDET_TX_VALID_SHIFT) 3015#define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT)
4260#define I40E_PF_MDET_RX 0x0012A400 3016#define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */
4261#define I40E_PF_MDET_RX_VALID_SHIFT 0 3017#define I40E_PF_MDET_RX_VALID_SHIFT 0
4262#define I40E_PF_MDET_RX_VALID_MASK (0x1 << I40E_PF_MDET_RX_VALID_SHIFT) 3018#define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT)
4263#define I40E_PF_MDET_TX 0x000E6400 3019#define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */
4264#define I40E_PF_MDET_TX_VALID_SHIFT 0 3020#define I40E_PF_MDET_TX_VALID_SHIFT 0
4265#define I40E_PF_MDET_TX_VALID_MASK (0x1 << I40E_PF_MDET_TX_VALID_SHIFT) 3021#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT)
4266#define I40E_PF_VT_PFALLOC 0x001C0500 3022#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */
4267#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 3023#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0
4268#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 3024#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)
4269#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 3025#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
4270#define I40E_PF_VT_PFALLOC_LASTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 3026#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
4271#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 3027#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
4272#define I40E_PF_VT_PFALLOC_VALID_MASK (0x1 << I40E_PF_VT_PFALLOC_VALID_SHIFT) 3028#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)
4273#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ 3029#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
4274#define I40E_VP_MDET_RX_MAX_INDEX 127 3030#define I40E_VP_MDET_RX_MAX_INDEX 127
4275#define I40E_VP_MDET_RX_VALID_SHIFT 0 3031#define I40E_VP_MDET_RX_VALID_SHIFT 0
4276#define I40E_VP_MDET_RX_VALID_MASK (0x1 << I40E_VP_MDET_RX_VALID_SHIFT) 3032#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)
4277#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ 3033#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
4278#define I40E_VP_MDET_TX_MAX_INDEX 127 3034#define I40E_VP_MDET_TX_MAX_INDEX 127
4279#define I40E_VP_MDET_TX_VALID_SHIFT 0 3035#define I40E_VP_MDET_TX_VALID_SHIFT 0
4280#define I40E_VP_MDET_TX_VALID_MASK (0x1 << I40E_VP_MDET_TX_VALID_SHIFT) 3036#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)
4281#define I40E_GLPM_WUMC 0x0006C800 3037#define I40E_GLPM_WUMC 0x0006C800 /* Reset: POR */
4282#define I40E_GLPM_WUMC_NOTCO_SHIFT 0 3038#define I40E_GLPM_WUMC_NOTCO_SHIFT 0
4283#define I40E_GLPM_WUMC_NOTCO_MASK (0x1 << I40E_GLPM_WUMC_NOTCO_SHIFT) 3039#define I40E_GLPM_WUMC_NOTCO_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_NOTCO_SHIFT)
4284#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1 3040#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1
4285#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK (0x1 << I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT) 3041#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT)
4286#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2 3042#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2
4287#define I40E_GLPM_WUMC_ROL_MODE_MASK (0x1 << I40E_GLPM_WUMC_ROL_MODE_SHIFT) 3043#define I40E_GLPM_WUMC_ROL_MODE_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_ROL_MODE_SHIFT)
4288#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3 3044#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3
4289#define I40E_GLPM_WUMC_RESERVED_4_MASK (0x1FFF << I40E_GLPM_WUMC_RESERVED_4_SHIFT) 3045#define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)
4290#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16 3046#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16
4291#define I40E_GLPM_WUMC_MNG_WU_PF_MASK (0xFFFF << I40E_GLPM_WUMC_MNG_WU_PF_SHIFT) 3047#define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
4292#define I40E_PFPM_APM 0x000B8080 3048#define I40E_PFPM_APM 0x000B8080 /* Reset: POR */
4293#define I40E_PFPM_APM_APME_SHIFT 0 3049#define I40E_PFPM_APM_APME_SHIFT 0
4294#define I40E_PFPM_APM_APME_MASK (0x1 << I40E_PFPM_APM_APME_SHIFT) 3050#define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT)
4295#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ 3051#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */
4296#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7 3052#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7
4297#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0 3053#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0
4298#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK (0xFF << I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT) 3054#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
4299#define I40E_PFPM_WUC 0x0006B200 3055#define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */
4300#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5 3056#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5
4301#define I40E_PFPM_WUC_EN_APM_D0_MASK (0x1 << I40E_PFPM_WUC_EN_APM_D0_SHIFT) 3057#define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT)
4302#define I40E_PFPM_WUFC 0x0006B400 3058#define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */
4303#define I40E_PFPM_WUFC_LNKC_SHIFT 0 3059#define I40E_PFPM_WUFC_LNKC_SHIFT 0
4304#define I40E_PFPM_WUFC_LNKC_MASK (0x1 << I40E_PFPM_WUFC_LNKC_SHIFT) 3060#define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT)
4305#define I40E_PFPM_WUFC_MAG_SHIFT 1 3061#define I40E_PFPM_WUFC_MAG_SHIFT 1
4306#define I40E_PFPM_WUFC_MAG_MASK (0x1 << I40E_PFPM_WUFC_MAG_SHIFT) 3062#define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT)
4307#define I40E_PFPM_WUFC_MNG_SHIFT 3 3063#define I40E_PFPM_WUFC_MNG_SHIFT 3
4308#define I40E_PFPM_WUFC_MNG_MASK (0x1 << I40E_PFPM_WUFC_MNG_SHIFT) 3064#define I40E_PFPM_WUFC_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MNG_SHIFT)
4309#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4 3065#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4
4310#define I40E_PFPM_WUFC_FLX0_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX0_ACT_SHIFT) 3066#define I40E_PFPM_WUFC_FLX0_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_ACT_SHIFT)
4311#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5 3067#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5
4312#define I40E_PFPM_WUFC_FLX1_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX1_ACT_SHIFT) 3068#define I40E_PFPM_WUFC_FLX1_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_ACT_SHIFT)
4313#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6 3069#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6
4314#define I40E_PFPM_WUFC_FLX2_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX2_ACT_SHIFT) 3070#define I40E_PFPM_WUFC_FLX2_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_ACT_SHIFT)
4315#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7 3071#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7
4316#define I40E_PFPM_WUFC_FLX3_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX3_ACT_SHIFT) 3072#define I40E_PFPM_WUFC_FLX3_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_ACT_SHIFT)
4317#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8 3073#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8
4318#define I40E_PFPM_WUFC_FLX4_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX4_ACT_SHIFT) 3074#define I40E_PFPM_WUFC_FLX4_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_ACT_SHIFT)
4319#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9 3075#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9
4320#define I40E_PFPM_WUFC_FLX5_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX5_ACT_SHIFT) 3076#define I40E_PFPM_WUFC_FLX5_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_ACT_SHIFT)
4321#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10 3077#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10
4322#define I40E_PFPM_WUFC_FLX6_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX6_ACT_SHIFT) 3078#define I40E_PFPM_WUFC_FLX6_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_ACT_SHIFT)
4323#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11 3079#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11
4324#define I40E_PFPM_WUFC_FLX7_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX7_ACT_SHIFT) 3080#define I40E_PFPM_WUFC_FLX7_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_ACT_SHIFT)
4325#define I40E_PFPM_WUFC_FLX0_SHIFT 16 3081#define I40E_PFPM_WUFC_FLX0_SHIFT 16
4326#define I40E_PFPM_WUFC_FLX0_MASK (0x1 << I40E_PFPM_WUFC_FLX0_SHIFT) 3082#define I40E_PFPM_WUFC_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_SHIFT)
4327#define I40E_PFPM_WUFC_FLX1_SHIFT 17 3083#define I40E_PFPM_WUFC_FLX1_SHIFT 17
4328#define I40E_PFPM_WUFC_FLX1_MASK (0x1 << I40E_PFPM_WUFC_FLX1_SHIFT) 3084#define I40E_PFPM_WUFC_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_SHIFT)
4329#define I40E_PFPM_WUFC_FLX2_SHIFT 18 3085#define I40E_PFPM_WUFC_FLX2_SHIFT 18
4330#define I40E_PFPM_WUFC_FLX2_MASK (0x1 << I40E_PFPM_WUFC_FLX2_SHIFT) 3086#define I40E_PFPM_WUFC_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_SHIFT)
4331#define I40E_PFPM_WUFC_FLX3_SHIFT 19 3087#define I40E_PFPM_WUFC_FLX3_SHIFT 19
4332#define I40E_PFPM_WUFC_FLX3_MASK (0x1 << I40E_PFPM_WUFC_FLX3_SHIFT) 3088#define I40E_PFPM_WUFC_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_SHIFT)
4333#define I40E_PFPM_WUFC_FLX4_SHIFT 20 3089#define I40E_PFPM_WUFC_FLX4_SHIFT 20
4334#define I40E_PFPM_WUFC_FLX4_MASK (0x1 << I40E_PFPM_WUFC_FLX4_SHIFT) 3090#define I40E_PFPM_WUFC_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_SHIFT)
4335#define I40E_PFPM_WUFC_FLX5_SHIFT 21 3091#define I40E_PFPM_WUFC_FLX5_SHIFT 21
4336#define I40E_PFPM_WUFC_FLX5_MASK (0x1 << I40E_PFPM_WUFC_FLX5_SHIFT) 3092#define I40E_PFPM_WUFC_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_SHIFT)
4337#define I40E_PFPM_WUFC_FLX6_SHIFT 22 3093#define I40E_PFPM_WUFC_FLX6_SHIFT 22
4338#define I40E_PFPM_WUFC_FLX6_MASK (0x1 << I40E_PFPM_WUFC_FLX6_SHIFT) 3094#define I40E_PFPM_WUFC_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_SHIFT)
4339#define I40E_PFPM_WUFC_FLX7_SHIFT 23 3095#define I40E_PFPM_WUFC_FLX7_SHIFT 23
4340#define I40E_PFPM_WUFC_FLX7_MASK (0x1 << I40E_PFPM_WUFC_FLX7_SHIFT) 3096#define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT)
4341#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31 3097#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31
4342#define I40E_PFPM_WUFC_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUFC_FW_RST_WK_SHIFT) 3098#define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT)
4343#define I40E_PFPM_WUS 0x0006B600 3099#define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */
4344#define I40E_PFPM_WUS_LNKC_SHIFT 0 3100#define I40E_PFPM_WUS_LNKC_SHIFT 0
4345#define I40E_PFPM_WUS_LNKC_MASK (0x1 << I40E_PFPM_WUS_LNKC_SHIFT) 3101#define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT)
4346#define I40E_PFPM_WUS_MAG_SHIFT 1 3102#define I40E_PFPM_WUS_MAG_SHIFT 1
4347#define I40E_PFPM_WUS_MAG_MASK (0x1 << I40E_PFPM_WUS_MAG_SHIFT) 3103#define I40E_PFPM_WUS_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MAG_SHIFT)
4348#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2 3104#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2
4349#define I40E_PFPM_WUS_PME_STATUS_MASK (0x1 << I40E_PFPM_WUS_PME_STATUS_SHIFT) 3105#define I40E_PFPM_WUS_PME_STATUS_MASK I40E_MASK(0x1, I40E_PFPM_WUS_PME_STATUS_SHIFT)
4350#define I40E_PFPM_WUS_MNG_SHIFT 3 3106#define I40E_PFPM_WUS_MNG_SHIFT 3
4351#define I40E_PFPM_WUS_MNG_MASK (0x1 << I40E_PFPM_WUS_MNG_SHIFT) 3107#define I40E_PFPM_WUS_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MNG_SHIFT)
4352#define I40E_PFPM_WUS_FLX0_SHIFT 16 3108#define I40E_PFPM_WUS_FLX0_SHIFT 16
4353#define I40E_PFPM_WUS_FLX0_MASK (0x1 << I40E_PFPM_WUS_FLX0_SHIFT) 3109#define I40E_PFPM_WUS_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX0_SHIFT)
4354#define I40E_PFPM_WUS_FLX1_SHIFT 17 3110#define I40E_PFPM_WUS_FLX1_SHIFT 17
4355#define I40E_PFPM_WUS_FLX1_MASK (0x1 << I40E_PFPM_WUS_FLX1_SHIFT) 3111#define I40E_PFPM_WUS_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX1_SHIFT)
4356#define I40E_PFPM_WUS_FLX2_SHIFT 18 3112#define I40E_PFPM_WUS_FLX2_SHIFT 18
4357#define I40E_PFPM_WUS_FLX2_MASK (0x1 << I40E_PFPM_WUS_FLX2_SHIFT) 3113#define I40E_PFPM_WUS_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX2_SHIFT)
4358#define I40E_PFPM_WUS_FLX3_SHIFT 19 3114#define I40E_PFPM_WUS_FLX3_SHIFT 19
4359#define I40E_PFPM_WUS_FLX3_MASK (0x1 << I40E_PFPM_WUS_FLX3_SHIFT) 3115#define I40E_PFPM_WUS_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX3_SHIFT)
4360#define I40E_PFPM_WUS_FLX4_SHIFT 20 3116#define I40E_PFPM_WUS_FLX4_SHIFT 20
4361#define I40E_PFPM_WUS_FLX4_MASK (0x1 << I40E_PFPM_WUS_FLX4_SHIFT) 3117#define I40E_PFPM_WUS_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX4_SHIFT)
4362#define I40E_PFPM_WUS_FLX5_SHIFT 21 3118#define I40E_PFPM_WUS_FLX5_SHIFT 21
4363#define I40E_PFPM_WUS_FLX5_MASK (0x1 << I40E_PFPM_WUS_FLX5_SHIFT) 3119#define I40E_PFPM_WUS_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX5_SHIFT)
4364#define I40E_PFPM_WUS_FLX6_SHIFT 22 3120#define I40E_PFPM_WUS_FLX6_SHIFT 22
4365#define I40E_PFPM_WUS_FLX6_MASK (0x1 << I40E_PFPM_WUS_FLX6_SHIFT) 3121#define I40E_PFPM_WUS_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX6_SHIFT)
4366#define I40E_PFPM_WUS_FLX7_SHIFT 23 3122#define I40E_PFPM_WUS_FLX7_SHIFT 23
4367#define I40E_PFPM_WUS_FLX7_MASK (0x1 << I40E_PFPM_WUS_FLX7_SHIFT) 3123#define I40E_PFPM_WUS_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX7_SHIFT)
4368#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31 3124#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31
4369#define I40E_PFPM_WUS_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUS_FW_RST_WK_SHIFT) 3125#define I40E_PFPM_WUS_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FW_RST_WK_SHIFT)
4370#define I40E_PRTPM_FHFHR 0x0006C000 3126#define I40E_PRTPM_FHFHR 0x0006C000 /* Reset: POR */
4371#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0 3127#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0
4372#define I40E_PRTPM_FHFHR_UNICAST_MASK (0x1 << I40E_PRTPM_FHFHR_UNICAST_SHIFT) 3128#define I40E_PRTPM_FHFHR_UNICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_UNICAST_SHIFT)
4373#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1 3129#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1
4374#define I40E_PRTPM_FHFHR_MULTICAST_MASK (0x1 << I40E_PRTPM_FHFHR_MULTICAST_SHIFT) 3130#define I40E_PRTPM_FHFHR_MULTICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_MULTICAST_SHIFT)
4375#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ 3131#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
4376#define I40E_PRTPM_SAH_MAX_INDEX 3 3132#define I40E_PRTPM_SAH_MAX_INDEX 3
4377#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0 3133#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0
4378#define I40E_PRTPM_SAH_PFPM_SAH_MASK (0xFFFF << I40E_PRTPM_SAH_PFPM_SAH_SHIFT) 3134#define I40E_PRTPM_SAH_PFPM_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT)
4379#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26 3135#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26
4380#define I40E_PRTPM_SAH_PF_NUM_MASK (0xF << I40E_PRTPM_SAH_PF_NUM_SHIFT) 3136#define I40E_PRTPM_SAH_PF_NUM_MASK I40E_MASK(0xF, I40E_PRTPM_SAH_PF_NUM_SHIFT)
4381#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30 3137#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30
4382#define I40E_PRTPM_SAH_MC_MAG_EN_MASK (0x1 << I40E_PRTPM_SAH_MC_MAG_EN_SHIFT) 3138#define I40E_PRTPM_SAH_MC_MAG_EN_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT)
4383#define I40E_PRTPM_SAH_AV_SHIFT 31 3139#define I40E_PRTPM_SAH_AV_SHIFT 31
4384#define I40E_PRTPM_SAH_AV_MASK (0x1 << I40E_PRTPM_SAH_AV_SHIFT) 3140#define I40E_PRTPM_SAH_AV_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_AV_SHIFT)
4385#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ 3141#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
4386#define I40E_PRTPM_SAL_MAX_INDEX 3 3142#define I40E_PRTPM_SAL_MAX_INDEX 3
4387#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0 3143#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0
4388#define I40E_PRTPM_SAL_PFPM_SAL_MASK (0xFFFFFFFF << I40E_PRTPM_SAL_PFPM_SAL_SHIFT) 3144#define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT)
4389#define I40E_VF_ARQBAH1 0x00006000 3145#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
4390#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 3146#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
4391#define I40E_VF_ARQBAH1_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH1_ARQBAH_SHIFT) 3147#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
4392#define I40E_VF_ARQBAL1 0x00006C00 3148#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
4393#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 3149#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0
4394#define I40E_VF_ARQBAL1_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL1_ARQBAL_SHIFT) 3150#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)
4395#define I40E_VF_ARQH1 0x00007400 3151#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */
4396#define I40E_VF_ARQH1_ARQH_SHIFT 0 3152#define I40E_VF_ARQH1_ARQH_SHIFT 0
4397#define I40E_VF_ARQH1_ARQH_MASK (0x3FF << I40E_VF_ARQH1_ARQH_SHIFT) 3153#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)
4398#define I40E_VF_ARQLEN1 0x00008000 3154#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
4399#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 3155#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0
4400#define I40E_VF_ARQLEN1_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN1_ARQLEN_SHIFT) 3156#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
4401#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 3157#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28
4402#define I40E_VF_ARQLEN1_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN1_ARQVFE_SHIFT) 3158#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)
4403#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 3159#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29
4404#define I40E_VF_ARQLEN1_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 3160#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)
4405#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 3161#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
4406#define I40E_VF_ARQLEN1_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 3162#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
4407#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 3163#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
4408#define I40E_VF_ARQLEN1_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN1_ARQENABLE_SHIFT) 3164#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
4409#define I40E_VF_ARQT1 0x00007000 3165#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
4410#define I40E_VF_ARQT1_ARQT_SHIFT 0 3166#define I40E_VF_ARQT1_ARQT_SHIFT 0
4411#define I40E_VF_ARQT1_ARQT_MASK (0x3FF << I40E_VF_ARQT1_ARQT_SHIFT) 3167#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
4412#define I40E_VF_ATQBAH1 0x00007800 3168#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
4413#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 3169#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
4414#define I40E_VF_ATQBAH1_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH1_ATQBAH_SHIFT) 3170#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
4415#define I40E_VF_ATQBAL1 0x00007C00 3171#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
4416#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 3172#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
4417#define I40E_VF_ATQBAL1_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL1_ATQBAL_SHIFT) 3173#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
4418#define I40E_VF_ATQH1 0x00006400 3174#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
4419#define I40E_VF_ATQH1_ATQH_SHIFT 0 3175#define I40E_VF_ATQH1_ATQH_SHIFT 0
4420#define I40E_VF_ATQH1_ATQH_MASK (0x3FF << I40E_VF_ATQH1_ATQH_SHIFT) 3176#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
4421#define I40E_VF_ATQLEN1 0x00006800 3177#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
4422#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 3178#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0
4423#define I40E_VF_ATQLEN1_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN1_ATQLEN_SHIFT) 3179#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
4424#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 3180#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28
4425#define I40E_VF_ATQLEN1_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN1_ATQVFE_SHIFT) 3181#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)
4426#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 3182#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29
4427#define I40E_VF_ATQLEN1_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 3183#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)
4428#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 3184#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
4429#define I40E_VF_ATQLEN1_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 3185#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
4430#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 3186#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
4431#define I40E_VF_ATQLEN1_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN1_ATQENABLE_SHIFT) 3187#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
4432#define I40E_VF_ATQT1 0x00008400 3188#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
4433#define I40E_VF_ATQT1_ATQT_SHIFT 0 3189#define I40E_VF_ATQT1_ATQT_SHIFT 0
4434#define I40E_VF_ATQT1_ATQT_MASK (0x3FF << I40E_VF_ATQT1_ATQT_SHIFT) 3190#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
4435#define I40E_VFGEN_RSTAT 0x00008800 3191#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
4436#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 3192#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
4437#define I40E_VFGEN_RSTAT_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 3193#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
4438#define I40E_VFINT_DYN_CTL01 0x00005C00 3194#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
4439#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 3195#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0
4440#define I40E_VFINT_DYN_CTL01_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_SHIFT) 3196#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
4441#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 3197#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1
4442#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) 3198#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
4443#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 3199#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
4444#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) 3200#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
4445#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 3201#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
4446#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) 3202#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
4447#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 3203#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5
4448#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) 3204#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)
4449#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 3205#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
4450#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) 3206#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
4451#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 3207#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
4452#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) 3208#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
4453#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 3209#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31
4454#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) 3210#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
4455#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) 3211#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
4456#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 3212#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15
4457#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 3213#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0
4458#define I40E_VFINT_DYN_CTLN1_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) 3214#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
4459#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 3215#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
4460#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) 3216#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
4461#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 3217#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
4462#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) 3218#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
4463#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 3219#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
4464#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) 3220#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
4465#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 3221#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
4466#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) 3222#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
4467#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 3223#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
4468#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) 3224#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
4469#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 3225#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
4470#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) 3226#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
4471#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 3227#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31
4472#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) 3228#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
4473#define I40E_VFINT_ICR0_ENA1 0x00005000 3229#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
4474#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 3230#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
4475#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) 3231#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
4476#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 3232#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
4477#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) 3233#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
4478#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 3234#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31
4479#define I40E_VFINT_ICR0_ENA1_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) 3235#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
4480#define I40E_VFINT_ICR01 0x00004800 3236#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */
4481#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 3237#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0
4482#define I40E_VFINT_ICR01_INTEVENT_MASK (0x1 << I40E_VFINT_ICR01_INTEVENT_SHIFT) 3238#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)
4483#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 3239#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1
4484#define I40E_VFINT_ICR01_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_0_SHIFT) 3240#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT)
4485#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 3241#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2
4486#define I40E_VFINT_ICR01_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_1_SHIFT) 3242#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT)
4487#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 3243#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3
4488#define I40E_VFINT_ICR01_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_2_SHIFT) 3244#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT)
4489#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 3245#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4
4490#define I40E_VFINT_ICR01_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_3_SHIFT) 3246#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT)
4491#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 3247#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
4492#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) 3248#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
4493#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 3249#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30
4494#define I40E_VFINT_ICR01_ADMINQ_MASK (0x1 << I40E_VFINT_ICR01_ADMINQ_SHIFT) 3250#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)
4495#define I40E_VFINT_ICR01_SWINT_SHIFT 31 3251#define I40E_VFINT_ICR01_SWINT_SHIFT 31
4496#define I40E_VFINT_ICR01_SWINT_MASK (0x1 << I40E_VFINT_ICR01_SWINT_SHIFT) 3252#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)
4497#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ 3253#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
4498#define I40E_VFINT_ITR01_MAX_INDEX 2 3254#define I40E_VFINT_ITR01_MAX_INDEX 2
4499#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 3255#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0
4500#define I40E_VFINT_ITR01_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR01_INTERVAL_SHIFT) 3256#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)
4501#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) 3257#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
4502#define I40E_VFINT_ITRN1_MAX_INDEX 2 3258#define I40E_VFINT_ITRN1_MAX_INDEX 2
4503#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 3259#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
4504#define I40E_VFINT_ITRN1_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN1_INTERVAL_SHIFT) 3260#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
4505#define I40E_VFINT_STAT_CTL01 0x00005400 3261#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: VFR */
4506#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 3262#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
4507#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) 3263#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
4508#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ 3264#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
4509#define I40E_QRX_TAIL1_MAX_INDEX 15 3265#define I40E_QRX_TAIL1_MAX_INDEX 15
4510#define I40E_QRX_TAIL1_TAIL_SHIFT 0 3266#define I40E_QRX_TAIL1_TAIL_SHIFT 0
4511#define I40E_QRX_TAIL1_TAIL_MASK (0x1FFF << I40E_QRX_TAIL1_TAIL_SHIFT) 3267#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)
4512#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ 3268#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
4513#define I40E_QTX_TAIL1_MAX_INDEX 15 3269#define I40E_QTX_TAIL1_MAX_INDEX 15
4514#define I40E_QTX_TAIL1_TAIL_SHIFT 0 3270#define I40E_QTX_TAIL1_TAIL_SHIFT 0
4515#define I40E_QTX_TAIL1_TAIL_MASK (0x1FFF << I40E_QTX_TAIL1_TAIL_SHIFT) 3271#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)
4516#define I40E_VFMSIX_PBA 0x00002000 3272#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */
4517#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 3273#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
4518#define I40E_VFMSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA_PENBIT_SHIFT) 3274#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)
4519#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ 3275#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4520#define I40E_VFMSIX_TADD_MAX_INDEX 16 3276#define I40E_VFMSIX_TADD_MAX_INDEX 16
4521#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 3277#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
4522#define I40E_VFMSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) 3278#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
4523#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 3279#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2
4524#define I40E_VFMSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD_MSIXTADD_SHIFT) 3280#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
4525#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ 3281#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4526#define I40E_VFMSIX_TMSG_MAX_INDEX 16 3282#define I40E_VFMSIX_TMSG_MAX_INDEX 16
4527#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 3283#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
4528#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) 3284#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
4529#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ 3285#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4530#define I40E_VFMSIX_TUADD_MAX_INDEX 16 3286#define I40E_VFMSIX_TUADD_MAX_INDEX 16
4531#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 3287#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
4532#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) 3288#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
4533#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ 3289#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
4534#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 3290#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16
4535#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 3291#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
4536#define I40E_VFMSIX_TVCTRL_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL_MASK_SHIFT) 3292#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)
4537#define I40E_VFCM_PE_ERRDATA 0x0000DC00 3293#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */
4538#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 3294#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
4539#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) 3295#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
4540#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 3296#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
4541#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) 3297#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
4542#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 3298#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8
4543#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) 3299#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
4544#define I40E_VFCM_PE_ERRINFO 0x0000D800 3300#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */
4545#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 3301#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
4546#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) 3302#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
4547#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 3303#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
4548#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) 3304#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)
4549#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 3305#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
4550#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) 3306#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
4551#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 3307#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
4552#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) 3308#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
4553#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 3309#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
4554#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) 3310#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
4555#define I40E_VFPE_AEQALLOC1 0x0000A400 3311#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
4556#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
4557#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
4558#define I40E_VFPE_CCQPHIGH1 0x00009800
4559#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
4560#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
4561#define I40E_VFPE_CCQPLOW1 0x0000AC00
4562#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
4563#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
4564#define I40E_VFPE_CCQPSTATUS1 0x0000B800
4565#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
4566#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
4567#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
4568#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
4569#define I40E_VFPE_CQACK1 0x0000B000
4570#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
4571#define I40E_VFPE_CQACK1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK1_PECQID_SHIFT)
4572#define I40E_VFPE_CQARM1 0x0000B400
4573#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
4574#define I40E_VFPE_CQARM1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM1_PECQID_SHIFT)
4575#define I40E_VFPE_CQPDB1 0x0000BC00
4576#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
4577#define I40E_VFPE_CQPDB1_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
4578#define I40E_VFPE_CQPERRCODES1 0x00009C00
4579#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
4580#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
4581#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
4582#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
4583#define I40E_VFPE_CQPTAIL1 0x0000A000
4584#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
4585#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
4586#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
4587#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
4588#define I40E_VFPE_IPCONFIG01 0x00008C00
4589#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
4590#define I40E_VFPE_IPCONFIG01_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
4591#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
4592#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
4593#define I40E_VFPE_MRTEIDXMASK1 0x00009000
4594#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
4595#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
4596#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400
4597#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
4598#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
4599#define I40E_VFPE_TCPNOWTIMER1 0x0000A800
4600#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
4601#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
4602#define I40E_VFPE_WQEALLOC1 0x0000C000
4603#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
4604#define I40E_VFPE_WQEALLOC1_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
4605#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
4606#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
4607#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */
4608#define I40E_VFQF_HENA_MAX_INDEX 1 3312#define I40E_VFQF_HENA_MAX_INDEX 1
4609#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 3313#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0
4610#define I40E_VFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA_PTYPE_ENA_SHIFT) 3314#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
4611#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ 3315#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
4612#define I40E_VFQF_HKEY_MAX_INDEX 12 3316#define I40E_VFQF_HKEY_MAX_INDEX 12
4613#define I40E_VFQF_HKEY_KEY_0_SHIFT 0 3317#define I40E_VFQF_HKEY_KEY_0_SHIFT 0
4614#define I40E_VFQF_HKEY_KEY_0_MASK (0xFF << I40E_VFQF_HKEY_KEY_0_SHIFT) 3318#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)
4615#define I40E_VFQF_HKEY_KEY_1_SHIFT 8 3319#define I40E_VFQF_HKEY_KEY_1_SHIFT 8
4616#define I40E_VFQF_HKEY_KEY_1_MASK (0xFF << I40E_VFQF_HKEY_KEY_1_SHIFT) 3320#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)
4617#define I40E_VFQF_HKEY_KEY_2_SHIFT 16 3321#define I40E_VFQF_HKEY_KEY_2_SHIFT 16
4618#define I40E_VFQF_HKEY_KEY_2_MASK (0xFF << I40E_VFQF_HKEY_KEY_2_SHIFT) 3322#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)
4619#define I40E_VFQF_HKEY_KEY_3_SHIFT 24 3323#define I40E_VFQF_HKEY_KEY_3_SHIFT 24
4620#define I40E_VFQF_HKEY_KEY_3_MASK (0xFF << I40E_VFQF_HKEY_KEY_3_SHIFT) 3324#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)
4621#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ 3325#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
4622#define I40E_VFQF_HLUT_MAX_INDEX 15 3326#define I40E_VFQF_HLUT_MAX_INDEX 15
4623#define I40E_VFQF_HLUT_LUT0_SHIFT 0 3327#define I40E_VFQF_HLUT_LUT0_SHIFT 0
4624#define I40E_VFQF_HLUT_LUT0_MASK (0xF << I40E_VFQF_HLUT_LUT0_SHIFT) 3328#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)
4625#define I40E_VFQF_HLUT_LUT1_SHIFT 8 3329#define I40E_VFQF_HLUT_LUT1_SHIFT 8
4626#define I40E_VFQF_HLUT_LUT1_MASK (0xF << I40E_VFQF_HLUT_LUT1_SHIFT) 3330#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)
4627#define I40E_VFQF_HLUT_LUT2_SHIFT 16 3331#define I40E_VFQF_HLUT_LUT2_SHIFT 16
4628#define I40E_VFQF_HLUT_LUT2_MASK (0xF << I40E_VFQF_HLUT_LUT2_SHIFT) 3332#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)
4629#define I40E_VFQF_HLUT_LUT3_SHIFT 24 3333#define I40E_VFQF_HLUT_LUT3_SHIFT 24
4630#define I40E_VFQF_HLUT_LUT3_MASK (0xF << I40E_VFQF_HLUT_LUT3_SHIFT) 3334#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)
4631#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ 3335#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
4632#define I40E_VFQF_HREGION_MAX_INDEX 7 3336#define I40E_VFQF_HREGION_MAX_INDEX 7
4633#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 3337#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
4634#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) 3338#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
4635#define I40E_VFQF_HREGION_REGION_0_SHIFT 1 3339#define I40E_VFQF_HREGION_REGION_0_SHIFT 1
4636#define I40E_VFQF_HREGION_REGION_0_MASK (0x7 << I40E_VFQF_HREGION_REGION_0_SHIFT) 3340#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)
4637#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 3341#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
4638#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) 3342#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
4639#define I40E_VFQF_HREGION_REGION_1_SHIFT 5 3343#define I40E_VFQF_HREGION_REGION_1_SHIFT 5
4640#define I40E_VFQF_HREGION_REGION_1_MASK (0x7 << I40E_VFQF_HREGION_REGION_1_SHIFT) 3344#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)
4641#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 3345#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
4642#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) 3346#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
4643#define I40E_VFQF_HREGION_REGION_2_SHIFT 9 3347#define I40E_VFQF_HREGION_REGION_2_SHIFT 9
4644#define I40E_VFQF_HREGION_REGION_2_MASK (0x7 << I40E_VFQF_HREGION_REGION_2_SHIFT) 3348#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)
4645#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 3349#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
4646#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) 3350#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
4647#define I40E_VFQF_HREGION_REGION_3_SHIFT 13 3351#define I40E_VFQF_HREGION_REGION_3_SHIFT 13
4648#define I40E_VFQF_HREGION_REGION_3_MASK (0x7 << I40E_VFQF_HREGION_REGION_3_SHIFT) 3352#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)
4649#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 3353#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
4650#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) 3354#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
4651#define I40E_VFQF_HREGION_REGION_4_SHIFT 17 3355#define I40E_VFQF_HREGION_REGION_4_SHIFT 17
4652#define I40E_VFQF_HREGION_REGION_4_MASK (0x7 << I40E_VFQF_HREGION_REGION_4_SHIFT) 3356#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)
4653#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 3357#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
4654#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) 3358#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
4655#define I40E_VFQF_HREGION_REGION_5_SHIFT 21 3359#define I40E_VFQF_HREGION_REGION_5_SHIFT 21
4656#define I40E_VFQF_HREGION_REGION_5_MASK (0x7 << I40E_VFQF_HREGION_REGION_5_SHIFT) 3360#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)
4657#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 3361#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
4658#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 3362#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
4659#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 3363#define I40E_VFQF_HREGION_REGION_6_SHIFT 25
4660#define I40E_VFQF_HREGION_REGION_6_MASK (0x7 << I40E_VFQF_HREGION_REGION_6_SHIFT) 3364#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)
4661#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 3365#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
4662#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 3366#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
4663#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 3367#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
4664#define I40E_VFQF_HREGION_REGION_7_MASK (0x7 << I40E_VFQF_HREGION_REGION_7_SHIFT) 3368#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
4665#define I40E_RCU_PST_FOC_ACCESS_STATUS 0x00270110
4666#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT 0
4667#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT)
4668#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT 8
4669#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT)
4670#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT 16
4671#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT)
4672#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT 24
4673#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_MASK (0x7 << I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT)
4674#endif 3369#endif
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h
index d3cf5a69de54..9c835786e8a1 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h
@@ -50,6 +50,9 @@
50 (d) == I40E_DEV_ID_QSFP_B || \ 50 (d) == I40E_DEV_ID_QSFP_B || \
51 (d) == I40E_DEV_ID_QSFP_C) 51 (d) == I40E_DEV_ID_QSFP_C)
52 52
53/* I40E_MASK is a macro used on 32 bit registers */
54#define I40E_MASK(mask, shift) (mask << shift)
55
53#define I40E_MAX_VSI_QP 16 56#define I40E_MAX_VSI_QP 16
54#define I40E_MAX_VF_VSI 3 57#define I40E_MAX_VF_VSI 3
55#define I40E_MAX_CHAINED_RX_BUFFERS 5 58#define I40E_MAX_CHAINED_RX_BUFFERS 5
@@ -1162,4 +1165,7 @@ enum i40e_reset_type {
1162 I40E_RESET_GLOBR = 2, 1165 I40E_RESET_GLOBR = 2,
1163 I40E_RESET_EMPR = 3, 1166 I40E_RESET_EMPR = 3,
1164}; 1167};
1168
1169/* RSS Hash Table Size */
1170#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1165#endif /* _I40E_TYPE_H_ */ 1171#endif /* _I40E_TYPE_H_ */
diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c
index 60407a9df0c1..e70e4cdb0eb2 100644
--- a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c
+++ b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c
@@ -632,7 +632,7 @@ static int i40evf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key)
632 u32 hlut_val; 632 u32 hlut_val;
633 int i, j; 633 int i, j;
634 634
635 for (i = 0, j = 0; i < I40E_VFQF_HLUT_MAX_INDEX; i++) { 635 for (i = 0, j = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) {
636 hlut_val = rd32(hw, I40E_VFQF_HLUT(i)); 636 hlut_val = rd32(hw, I40E_VFQF_HLUT(i));
637 indir[j++] = hlut_val & 0xff; 637 indir[j++] = hlut_val & 0xff;
638 indir[j++] = (hlut_val >> 8) & 0xff; 638 indir[j++] = (hlut_val >> 8) & 0xff;
@@ -659,7 +659,7 @@ static int i40evf_set_rxfh(struct net_device *netdev, const u32 *indir,
659 u32 hlut_val; 659 u32 hlut_val;
660 int i, j; 660 int i, j;
661 661
662 for (i = 0, j = 0; i < I40E_VFQF_HLUT_MAX_INDEX + 1; i++) { 662 for (i = 0, j = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) {
663 hlut_val = indir[j++]; 663 hlut_val = indir[j++];
664 hlut_val |= indir[j++] << 8; 664 hlut_val |= indir[j++] << 8;
665 hlut_val |= indir[j++] << 16; 665 hlut_val |= indir[j++] << 16;
diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/i40evf/i40evf_main.c
index 7fc5f3b5d6bf..2fdccce1b872 100644
--- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c
+++ b/drivers/net/ethernet/intel/i40evf/i40evf_main.c
@@ -36,7 +36,7 @@ char i40evf_driver_name[] = "i40evf";
36static const char i40evf_driver_string[] = 36static const char i40evf_driver_string[] =
37 "Intel(R) XL710 X710 Virtual Function Network Driver"; 37 "Intel(R) XL710 X710 Virtual Function Network Driver";
38 38
39#define DRV_VERSION "0.9.34" 39#define DRV_VERSION "0.9.35"
40const char i40evf_driver_version[] = DRV_VERSION; 40const char i40evf_driver_version[] = DRV_VERSION;
41static const char i40evf_copyright[] = 41static const char i40evf_copyright[] =
42 "Copyright (c) 2013 - 2014 Intel Corporation."; 42 "Copyright (c) 2013 - 2014 Intel Corporation.";
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 22:32:12 -0400