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authorMika Kuoppala <mika.kuoppala@linux.intel.com>2014-07-09 07:55:56 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-07-12 05:13:47 -0400
commit542a6b205b184ec90e2108aaebaf8ba16128baec (patch)
treeaf5ef3cb1b973090ef2797c9fb4573107bba227f
parentd4ef41ce151988411dec8b089636d9ecbd1da559 (diff)
drm/i915/chv: calculate rc6 residency correctly
The register to read cz count is different from vlv. Also the counts returned from CCK_CTL1 for BSW are (ticks in 30ns - 1). czcount_30ns of value 1 is a special case for 320Mhz. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80703 Suggested-by: Deepak S <deepak.s@linux.intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Tested-by: Guo Jinxian <jinxianx.guo@intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
-rw-r--r--drivers/gpu/drm/i915/i915_sysfs.c39
2 files changed, 32 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0ebe0f49db28..503da23b6c3f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2281,7 +2281,7 @@ enum punit_power_well {
2281/* Same as Haswell, but 72064 bytes now. */ 2281/* Same as Haswell, but 72064 bytes now. */
2282#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) 2282#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2283 2283
2284 2284#define CHV_CLK_CTL1 0x101100
2285#define VLV_CLK_CTL2 0x101104 2285#define VLV_CLK_CTL2 0x101104
2286#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 2286#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2287 2287
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index b15c8cee103b..ae7fd8fc27f0 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -47,22 +47,45 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
47 47
48 intel_runtime_pm_get(dev_priv); 48 intel_runtime_pm_get(dev_priv);
49 49
50 /* On VLV, residency time is in CZ units rather than 1.28us */ 50 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
51 if (IS_VALLEYVIEW(dev)) { 51 if (IS_VALLEYVIEW(dev)) {
52 u32 clkctl2; 52 u32 reg, czcount_30ns;
53 53
54 clkctl2 = I915_READ(VLV_CLK_CTL2) >> 54 if (IS_CHERRYVIEW(dev))
55 CLK_CTL2_CZCOUNT_30NS_SHIFT; 55 reg = CHV_CLK_CTL1;
56 if (!clkctl2) { 56 else
57 WARN(!clkctl2, "bogus CZ count value"); 57 reg = VLV_CLK_CTL2;
58
59 czcount_30ns = I915_READ(reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
60
61 if (!czcount_30ns) {
62 WARN(!czcount_30ns, "bogus CZ count value");
58 ret = 0; 63 ret = 0;
59 goto out; 64 goto out;
60 } 65 }
61 units = DIV_ROUND_UP_ULL(30ULL * bias, (u64)clkctl2); 66
67 units = 0;
68 div = 1000000ULL;
69
70 if (IS_CHERRYVIEW(dev)) {
71 /* Special case for 320Mhz */
72 if (czcount_30ns == 1) {
73 div = 10000000ULL;
74 units = 3125ULL;
75 } else {
76 /* chv counts are one less */
77 czcount_30ns += 1;
78 }
79 }
80
81 if (units == 0)
82 units = DIV_ROUND_UP_ULL(30ULL * bias,
83 (u64)czcount_30ns);
84
62 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) 85 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
63 units <<= 8; 86 units <<= 8;
64 87
65 div = 1000000ULL * bias; 88 div = div * bias;
66 } 89 }
67 90
68 raw_time = I915_READ(reg) * units; 91 raw_time = I915_READ(reg) * units;